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1. general description the 74LVC821A is a 10-bit d-type flip-flop featuring separate d-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. a clock input (pin cp) and an output enable input (pin oe ) are common to all flip-flops. th e ten flip-flops store the state of their individual d-inputs that meet the set-up and hold times requirements on the low-to-high cp transition. when pin oe is low, the contents of the ten flip-flops are available at the outputs. when pin oe is high, the outputs go to the high -impedance off-state. operation of the oe inputs does not affect the state of the flip-flops. inputs can be driven from either 3.3 v or 5 v devices. when disabled, up to 5.5 v can be applied to the outputs. these features allow the use of these device s as translators in mixed 3.3 v and 5 v applications. 2. features and benefits ? 5 v tolerant inputs and outputs; for interfacing with 5 v logic ? wide supply voltage range from 1.2 v to 3.6 v ? cmos low power consumption ? direct interface with ttl levels ? flow-through pinout architecture ? 10-bit positive edge-triggered register ? independent register and 3-state buffer operation ? complies with jedec standard: ? jesd8-7a (1.65 v to 1.95 v) ? jesd8-5a (2.3 v to 2.7 v) ? jesd8-c/jesd36 (2.7 v to 3.6 v) ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-b exceeds 200 v ? cdm jesd22-c101e exceeds 1000 v ? specified from ? 40 ? c to +85 ? c and ? 40 ? c to +125 ? c. 74LVC821A 10-bit d-type flip-flop with 5 v tolerant inputs/outputs; positive-edge trigger; 3-state rev. 4 ? 23 november 2012 product data sheet
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 2 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74LVC821Ad ? 40 ? c to +125 ? c so24 plastic small outl ine package; 24 leads; body width 7.5 mm sot137-1 74LVC821Adb ? 40 ? c to +125 ? c ssop24 plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 74LVC821Apw ? 40 ? c to +125 ? c tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 74LVC821Abq ? 40 ? c to +125 ? c dhvqfn24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 ? 5.5 ? 0.85 mm sot815-1 fig 1. logic symbol fig 2. iec logic symbol 001aaa677 d0 d1 d2 d3 d4 d5 d6 d9 oe cp q0 q1 q2 q3 q4 q5 q6 q9 13 1 14 17 18 19 20 21 22 23 11 8 7 d7 d8 q7 q8 15 16 10 9 6 5 4 3 2 001aaa678 14 17 18 19 20 21 22 13 c1 1 en 1d 23 11 8 7 6 5 4 3 2 16 9 15 10
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 3 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state fig 3. functional diagram 001aaa679 3-state outputs ff0 to ff9 q0 q3 q4 q5 q6 q7 q8 q9 14 15 16 17 18 19 20 23 d0 d3 d4 d5 d6 d7 d8 d9 cp oe 11 13 1 10 9 8 7 6 5 q1 q2 21 22 d1 d2 4 3 2
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 4 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state fig 4. logic diagram 001aaa681 q4 d4 q3 d3 q2 d2 q1 d1 q0 d0 d ff1 q cp cp d ff2 q cp d ff3 q cp d ff4 q cp d ff5 q cp d ff6 q cp d ff7 q cp d ff10 q cp oe q5 d5 q6 d6 q9 d9 d ff8 q cp d ff9 q cp q7 d7 q8 d8
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 5 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 5. pinning information 5.1 pinning 5.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 5. pin configuration so24 and (t)ssop24 fig 6. pin configuration dhvqfn24 821a oe v cc d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 d8 q8 d9 q9 gnd cp 001aaa676 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 001aaa680 821a transparent top view q9 d8 d9 q8 d7 q7 d6 q6 d5 q5 d4 q4 d3 q3 d2 q2 d1 q1 d0 q0 gnd cp oe v cc 11 14 10 15 9 16 8 17 7 18 6 19 5 20 4 21 3 22 2 23 12 13 1 24 terminal 1 index area gnd (1) table 2. pin description symbol pin description oe 1 output enable input (active low) cp 13 clock input (low-to-high, edge-triggered) d[0:9] 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 data input q[0:9] 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 3-state flip-flop output gnd 12 ground (0 v) v cc 24 supply voltage
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 6 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 6. functional description [1] h = high voltage level h = high voltage level one set-up time before the low-to-high cp transition l = low voltage level l = low voltage level one set-up time before the low-to-high cp transition z = high-impedance off-state ? = low-to-high clock transition x = don?t care nc = no change 7. limiting values [1] the minimum input voltage ratings may be excee ded if the input current ratings are observed. [2] the output voltage ratings may be exceeded if the output current ratings are observed. [3] for so24 package: above 70 ? c derate linearly with 8 mw/k. for ssop24 and tssop24 packages: above 60 ? c derate linearly with 5.5 mw/k. for dhvqfn24 package: above 60 ? c derate linearly with 4.5 mw/k. table 3. function table [1] operating mode input internal flip-flops output oe cp dn qn load and read register l ? ill l ? hhh load register and disable outputs h ? ilz h ? hhz hold l h or l x nc nc table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v i ik input clamping current v i <0 v ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o >v cc or v o <0 v - ? 50 ma v o output voltage high or low state [2] ? 0.5 v cc + 0.5 v 3-state [2] ? 0.5 +6.5 v i o output current v o =0 v tov cc - ? 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [3] -500 mw
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 7 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 8. recommended operating conditions 9. static characteristics table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 1.65 - 3.6 v functional 1.2 - - v v i input voltage 0 - 5.5 v v o output voltage high or low state 0 - v cc v 3-state 0 - 5.5 v t amb ambient temperature in free air ? 40 - +125 ?c ? t/ ? v input transition rise and fall rate v cc = 1.65 v to 2.7 v 0 - 20 ns/v v cc = 2.7 v to 3.6 v 0 - 10 ns/v table 6. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max v ih high-level input voltage v cc = 1.2 v 1.08 - - 1.08 - v v cc = 1.65 v to 1.95 v 0.65 ? v cc - - 0.65 ? v cc -v v cc = 2.3 v to 2.7 v 1.7 - - 1.7 - v v cc = 2.7 v to 3.6 v 2.0 - - 2.0 - v v il low-level input voltage v cc = 1.2 v - - 0.12 - 0.12 v v cc = 1.65 v to 1.95 v - - 0.35 ? v cc -0 . 3 5 ? v cc v v cc = 2.3 v to 2.7 v - - 0.7 - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il i o = ? 100 ? a; v cc =1.65vto3.6v v cc ? 0.2 - - v cc ? 0.3 - v i o = ? 4ma; v cc = 1.65 v 1.2 - - 1.05 - v i o = ? 8ma; v cc = 2.3 v 1.8 - - 1.65 - v i o = ? 12 ma; v cc = 2.7 v 2.2 - - 2.05 - v i o = ? 18 ma; v cc = 3.0 v 2.4 - - 2.25 - v i o = ? 24 ma; v cc = 3.0 v 2.2 - - 2.0 - v v ol low-level output voltage v i =v ih or v il i o = 100 ? a; v cc = 1.65 v to 3.6 v - - 0.2 - 0.3 v i o =4ma; v cc = 1.65 v - - 0.45 - 0.65 v i o =8ma; v cc = 2.3 v - - 0.6 - 0.8 v i o =12ma; v cc = 2.7 v - - 0.4 - 0.6 v i o =24ma; v cc = 3.0 v - - 0.55 - 0.8 v i i input leakage current v cc = 3.6 v; v i =5.5vorgnd - ? 0.1 ? 5- ? 20 ? a
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 8 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state [1] all typical values are measured at v cc = 3.3 v (unless stated otherwise) and t amb =25 ? c. 10. dynamic characteristics i oz off-state output current v i =v ih or v il ; v cc = 3.6 v; v o =5.5vorgnd; -0.1 ? 5- ? 20 ? a i off power-off leakage current v cc = 0 v; v i or v o = 5.5 v - 0.1 ? 10 - ? 20 ? a i cc supply current v cc = 3.6 v; v i =v cc or gnd; i o =0a -0.110-40 ? a ? i cc additional supply current per input pin; v cc = 2.7 v to 3.6 v; v i =v cc ? 0.6 v; i o =0a - 5 500 - 5000 ? a c i input capacitance v cc = 0 v to 3.6 v; v i =gndtov cc -5 . 0---p f table 6. static characteristics ...continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v). for test circuit see figure 10 . symbol parameter conditions t amb = ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max t pd propagation delay cp to qn; see figure 7 [2] v cc = 1.2 v - 18 - - - ns v cc = 1.65 v to 1.95 v 2.4 8.6 17.1 2.3 19.7 ns v cc = 2.3 v to 2.7 v 1.8 4.5 8.8 1.6 10.1 ns v cc = 2.7 v 1.5 4.1 8.5 2.2 11.0 ns v cc = 3.0 v to 3.6 v 1.5 3.8 7.3 2.0 9.5 ns t en enable time oe to qn; see figure 9 [2] v cc = 1.2 v - 20 - - - ns v cc = 1.65 v 1.8 7.7 17.4 1.6 20.1 ns v cc = 2.3 v to 2.7 v 1.5 4.3 9.6 1.3 11.0 ns v cc = 2.7 v 1.3 4.4 8.8 2.4 11.0 ns v cc = 3.0 v to 3.6 v 1.5 3.5 7.6 1.5 9.5 ns t dis disable time oe to qn; see figure 9 [2] v cc = 1.2 v - 9.0 - - - ns v cc = 1.65 v 2.5 4.4 10.4 1.8 12.0 ns v cc = 2.3 v to 2.7 v 1.0 2.4 5.9 0.6 6.8 ns v cc = 2.7 v 1.5 3.3 6.8 2.2 8.5 ns v cc = 3.0 v to 3.6 v 1.5 3.0 6.2 1.9 8.0 ns
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 9 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state [1] typical values are measured at t amb =25 ? c and v cc = 1.2 v, 1.8 v, 2.5 v, 2.7 v and 3.3 v respectively. [2] t pd is the same as t plh and t phl . t en is the same as t pzl and t pzh . t dis is the same as t plz and t phz . [3] skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. [4] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in volts n = number of inputs switching ? (c l ? v cc 2 ? f o ) = sum of the outputs t w pulse width clock high or low; see figure 7 v cc = 1.65 v to 1.95 v 5.0 - - 5.0 - ns v cc = 2.3 v to 2.7 v 4.0 - - 4.0 - ns v cc = 2.7 v 3.3 - - 3.3 - ns v cc = 3.0 v to 3.6 v 3.3 1.7 - 3.3 - ns t su set-up time dn to cp; see figure 8 v cc = 1.65 v to 1.95 v 3.5 - - 3.5 - ns v cc = 2.3 v to 2.7 v 2.0 - - 2.0 - ns v cc = 2.7 v 0.9 - - 0.9 - ns v cc = 3.0 v to 3.6 v 1.9 0.6 - 1.9 - ns t h hold time dn to cp; see figure 8 v cc = 1.65 v to 1.95 v 3.0 - - 3.0 - ns v cc = 2.3 v to 2.7 v 2.0 - - 2.0 - ns v cc = 2.7 v 1.5 - - 1.5 - ns v cc = 3.0 v to 3.6 v 1.5 0.0 - 1.5 - ns f max maximum frequency see figure 7 v cc = 1.65 v to 1.95 v 100 - - 80 - mhz v cc = 2.3 v to 2.7 v 125 - - 100 - mhz v cc = 2.7 v 150 - - 120 - mhz v cc = 3.0 v to 3.6 v 150 200 - 120 - mhz t sk(o) output skew time v cc = 3.0 v to 3.6 v [3] - - 1.0 - 1.5 ns c pd power dissipation capacitance per input; v i =gndtov cc [4] v cc = 1.65 v to 1.95 v - 12.5 - - - pf v cc = 2.3 v to 2.7 v - 14.7 - - - pf v cc = 3.0 v to 3.6 v - 16.6 - - - pf table 7. dynamic characteristics ...continued voltages are referenced to gnd (ground = 0 v). for test circuit see figure 10 . symbol parameter conditions t amb = ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 10 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 11. waveforms measurement points are given in table 8 . v ol and v oh are the typical output voltage levels that occur with the output load. fig 7. clock (cp) to output (qn) propagation delays, the clock pulse width, and the maximum frequency mna894 cp input qn output t phl t plh t w 1/f max v m v oh v i gnd v ol v m measurement points are given in table 8 . v ol and v oh are the typical output voltage levels that occur with the output load. the shaded areas indicate when the input is permi tted to change for predicable output performance. fig 8. data set-up and hold times fo r the dn input to the cp input mna202 gnd gnd t h t h t su t su v m v m v m v i v oh v ol v i qn output cp input dn input
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 11 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state measurement points are given in table 8 . v ol and v oh are the typical output voltage levels that occur with the output load. fig 9. 3-state enable and disable times mgu775 t plz t phz outputs disabled outputs enabled v y v x outputs enabled qn output low-to-off off-to-low qn output high-to-off off-to-high oe input v i v ol v oh v cc v m v m gnd gnd t pzl t pzh v m v m table 8. measurement points supply voltage input output v cc v i v m v m v x v y 1.2 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 1.65 v to 1.95 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 2.3 v to 2.7 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 2.7 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v 3.0 v to 3.6 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 12 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state test data is given in table 9 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 10. load circuitry for switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae331 v ext v cc v i v o dut c l r t r l r l g table 9. test data supply voltage input load v ext v i t r , t f c l r l t plh , t phl t plz , t pzl t phz , t pzh 1.2 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 1.65 v to 1.95 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 2.3 v to 2.7 v v cc ? 2 ns 30 pf 500 ? open 2 ? v cc gnd 2.7v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd 3.0vto3.6v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 13 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 12. package outline fig 11. package outline sot 137-1 (so24) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 99-12-27 03-02-19
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 14 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state fig 12. package outline sot 340-1 (ssop24) unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 0.8 0.4 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot340-1 mo-150 99-12-27 03-02-19 x w m ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 a max. 2
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 15 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state fig 13. package outline sot 355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 11 2 24 13 pin 1 index tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 16 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state fig 14. package outline sot 815-1 (dhvqfn24) references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. sot815-1 - - - - - - - - - 03-04-29 sot815-1 0 2.5 5 mm scale b y y 1 c c ac c b v m w m e 1 e 2 terminal 1 index area terminal 1 index area x unit a (1) max. a 1 bc e e h l e 1 ywv mm 1 0.05 0.00 0.30 0.18 0.5 4.5 e 2 1.5 0.2 2.25 1.95 d h 4.25 3.95 0.05 0.05 y 1 0.1 0.1 dimensions (mm are the original dimensions) 0.5 0.3 d (1) 5.6 5.4 e (1) 3.6 3.4 d e b a e dhvqfn24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm a a 1 c detail x e h l d h 2 23 11 14 13 12 1 24
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 17 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74LVC821A v.4 20121123 product data sheet - 74LVC821A v.3 modifications: ? the format of this data sheet has been redesigne d to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? ta b l e 4 , table 5 , table 6 , ta b l e 7 , and table 8 : values added for lower voltage ranges. 74LVC821A v.3 20040511 product specification - 74LVC821A v.2 74LVC821A v.2 20040415 product specification - 74LVC821A v.1 74LVC821A v.1 19980925 product specification - -
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 18 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74LVC821A all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 23 november 2012 19 of 20 nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74LVC821A 10-bit d-type flip-flop; 5 v tolerance; positive-edge trigger; 3-state ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 23 november 2012 document identifier: 74LVC821A please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 recommended operating conditions. . . . . . . . 7 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 18 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16 contact information. . . . . . . . . . . . . . . . . . . . . 19 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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