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12 lvds/24 cmos output clock generator with integrated 2.8 ghz vco data sheet ad9522 - 0 features low phase noise, phase - locked loop (pll) on - chip voltage controlled oscillator (vco) tunes from 2.53 ghz to 2. 9 5 ghz supports e xternal 3.3 v / 5 v vco/vcxo to 2.4 ghz 1 differential or 2 single - ended reference inputs accepts cmos, lvpecl , or lvds re ferences to 250 mhz accepts 16. 62 mhz to 33.3 mhz crystal for reference input optional reference clock doubler reference monitoring capability revertive a uto matic and manual reference s witchover/ holdover modes g litch - free switchover between references aut omatic recover y from holdover digital or analog lock detect, selectable optional z ero delay operation twelve 800 m hz lvds outputs divided into 4 groups each group of 3 has a 1 - to - 32 divider with phase delay additive output jitter as low as 2 42 f s rms chan nel - to - channel skew grouped outputs < 6 0 ps each lvds output can be configure d as 2 cmos outputs (for f out 250 mhz) automatic synchronization of all outputs on power - up manual synchronization of outputs as needed spi - and i2c - compatible serial control port 64- lead lfcsp non volatile eeprom stores configuration settings applications low j itter, low phase noise clock distribution clock generation and translation for sonet, 10ge, 1 0g fc, and other 10 gb p s protocols forward error corr ection (g.710) clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers ate and h igh performan ce instrumentation broadband infrastructure s general description the ad9522 - 0 1 provides a multi output clock distribution f unction with subpicosecond jitter performance, along with an on - chip pll and vco. the on - chip vco tunes from 2.53 ghz to 2. 9 5 ghz . a n external 3.3 v /5 v vco/vcxo of up to 2.4 ghz can also be used. functional block dia gram optional ref1 ref2 clk lf switchover and monitor pll divider and muxes zero delay cp vco status monitor spi/i 2 c control port and digital logic eeprom ad9522 out0 out1 out2 div/ out3 out4 out5 div/ out6 out7 out8 div/ out9 out10 out11 div/ lvds/ cmos refin refin 07219-001 figure 1. the ad9522 serial interface supports both spi and i2c ? ports. an in - package eeprom can be programmed thro ugh the serial interface and store user - defined register setting s for power - up and chip reset. the ad9522 features 12 lvds outputs in four g roups . any of the 800 mhz lvds outputs can be reconfigured as two 250 mhz cmos outputs . each group of outputs has a divider that al lows both the divide ratio (from 1 to 32) and the phase (coarse delay ) to be se t . the ad9522 is available in a 64 - lead lfcsp and can be operated from a singl e 3.3 v supply. the external vco can have an operating voltage up to 5.5 v. the ad9522 is specified for operation over the standard industrial range of ? 40c to +85c. the ad9520 - 0 is an equivalent part to the ad9522 - 0 featuring lvpecl/cmos drivers instead of lvds/cmos drivers. 1 the ad9522 is used throughout this data sheet to refer to all the members of the ad9522 family. however, when ad9522 - 0 is used, it is referring to that specific member of the ad9522 family. rev. a document feedback information furnished by analog devices is b elieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. n o license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel : 781.329.4700 ? 2008 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com
ad9522- 0 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 4 specifications ..................................................................................... 5 power supply requirements ....................................................... 5 pll characteristics ...................................................................... 5 clock inputs .................................................................................. 8 clock outputs ............................................................................... 8 timing characteristics ................................................................ 9 timing diagrams ..................................................................... 9 clock output additive phase noise (distribution only; vco divider not used) ...................................................................... 10 clock output absolute p hase noise (internal vco used) .. 11 clock output absolute time jitter (clock generation using internal vco) ............................................................................. 11 clock output absolu te time jitter (clock cleanup using internal vco) ............................................................................. 11 clock output absolute time jitter (clock generation using external vcxo) ......................................................................... 12 clock output additive time jitter (vco divider not used) ....................................................................................................... 12 clock output additive time jitter (vco divider used) ..... 13 serial cont rol port spi mode ................................................ 13 serial control port i2c mode ................................................ 14 pd , sync , and reset p ins ..................................................... 15 serial port setup pins: sp1, sp0 ............................................... 15 ld, status, and refmon pins ............................................ 15 power dissipation ....................................................................... 16 absolute maximum ratings .......................................................... 17 thermal resistance .................................................................... 17 esd caution ................................................................................ 17 pin configuration and function descriptions ........................... 18 typical performance characteristics ........................................... 21 test circuits ..................................................................................... 26 terminology .................................................................................... 27 detailed block diagram ................................................................ 28 theory of operation ...................................................................... 29 operational configurations ...................................................... 29 mode 0: internal vco and cl ock distribution ................. 29 mode 1: clock distribution or external vco < 1600 mhz .................................................................................................. 31 mode 2: high frequency clock distribution clk or ex ternal vco > 1600 mhz .................................................. 33 phase - locked loop (pll) .................................................... 35 configuration of the pll ...................................................... 35 phase frequency detector (pfd) ........................................ 35 charge pump (cp) ................................................................. 35 on - chip vco ........................................................................ 36 pll external loop filter ....................................................... 36 pll reference inputs ............................................................. 36 reference switchover ............................................................. 37 reference divider r ............................................................... 37 vco/vcxo feedback divider n: p, a, b .......................... 37 digital lock detect (dld) ................................................... 39 analog lock detect (ald) ................................................... 39 current source digital lock detect (csdld) .................. 39 external vcxo/vco clock input (clk/ clk ) ................ 40 holdover .................................................................................. 40 external/manual holdover mode ........................................ 40 automatic/internal holdover mode .................................... 40 frequency status monitors ................................................... 42 vco calibratio n .................................................................... 42 zero delay operation ................................................................ 45 internal zero delay mode ..................................................... 45 externa l zero delay mode .................................................... 45 clock distribution ..................................................................... 46 operation modes ................................................................... 46 cl ock frequency division ..................................................... 47 vco divider ........................................................................... 47 channel dividers ................................................................... 47 syn chronizing the outputs sync function ................... 49 lvds output drivers ............................................................ 50 cmos output drivers .......................................................... 51 reset modes ................................................................................ 51 power - on reset ...................................................................... 51 hardware reset via the reset pin ..................................... 51 soft reset via the serial port ................................................. 51 soft reset to settings in eeprom when eeprom pin = 0 via the serial port ......................................................................... 51 rev. a | page 2 of 84
data sheet ad9522- 0 power - down modes ................................................................... 51 chip power - down via pd ..................................................... 51 pll power - down .................................................................... 52 distribution power - down ..................................................... 52 individual clock output power - down ................................ 52 individual clock channel power - down ............................. 52 serial control port .......................................................................... 53 spi/i2c port selection ................................................................ 53 i2c serial port operation ........................................................... 53 i 2 c bus characteristics ........................................................... 53 data transfer process ............................................................. 54 data transfer format ............................................................. 55 i2c serial port timing ............................................................ 55 spi serial port operation ........................................................... 56 pin descriptions ...................................................................... 56 spi mode operation ............................................................... 56 communication cycle instructi on plus data .................. 56 write ......................................................................................... 56 read .......................................................................................... 56 spi instruction word (16 bits) .................................................. 57 spi msb/lsb first transfers ..................................................... 57 eeprom operations ..................................................................... 60 writing t o the eeprom ............................................................ 60 reading from the eeprom ...................................................... 60 programming the eeprom buffer segment .......................... 61 register section definition group ....................................... 61 io_update (operational code 0x80) .............................. 61 end - of - data (operational code 0xff ) ............................... 61 pseudo - end - of - data (operational code 0xfe) ................. 61 thermal performance ..................................................................... 63 register map .................................................................................... 64 register map descriptions ............................................................. 68 applications information ............................................................... 82 frequency planning using the ad9522 .................................. 82 using the ad9522 outputs for adc clock applications ..... 82 lvds clock dist ribution ........................................................... 82 cmos clock distribution ......................................................... 83 outline dimensions ........................................................................ 84 ord ering guide ........................................................................... 84 rev. a | page 3 of 84
ad9522- 0 data sheet revision history 3 /15 rev. 0 to rev. a changes to features section ............................................................ 1 changes to table 1 and table 2 ....................................................... 5 change to input frequency parameter, table 3 ........................... 8 changes to table 4 ............................................................................ 8 changes to sdio , sdo (outputs) parameter, test conditions/comments column, table 13 .................................. 13 changes to table 17 ........................................................................ 15 change to vcp supply parameter, table 18 ............................... 1 6 change to junction temperature parameter, table 19 .............. 17 changes to pin 4 description column, table 21 and pin 22 descri ption column, table 21 ...................................................... 18 delete d figure 13; renumbered sequentially ............................. 21 added test circuits section .......................................................... 26 moved figure 33 and figure 34 .................................................... 26 changes to figure 33 and figure 34 ............................................. 26 changes to mode 0: internal vco and clock distribution section .............................................................................................. 29 deleted configur ation and register setting s section ............... 29 changes to figure 36 ...................................................................... 30 changes to figure 37 ...................................................................... 32 changes to figure 38 ...................................................................... 34 changes to configuration of the pll section and charge pump (cp) section .................................................................................... 35 changes to on - chip vco section, figure 40, and pll reference inputs s ection ............................................................... 36 added figure 42 and figure 43; renumbered sequentially ..... 36 changes to reference switchover section ................................... 37 changes to prescaler section, a and b counters section, r and n divider delays, and table 29 .................................................... 38 changes to current source digital lock detect (cs dld) section .............................................................................................. 39 changes to external vcxo/vco clock input (clk/ clk ) and holdover section ............................................................................ 40 changes to frequency status monitors section and vco calibration section ......................................................................... 42 changes to figure 49 caption ...................................................... 43 added table 31; renumbered sequentially ................................ 44 changes to zero delay operation section and internal zero delay mode section ....................................................................... 45 changes to clock distribution section ....................................... 46 added channel divider maximum frequency section ............ 47 changes to duty cycle and duty - cycle correction section and table 37 ............................................................................................ 48 changes to synchronizing the outputs sync function section .............................................................................................. 49 changes to cmos output drivers section, power - on reset section, hardware reset via the reset pin section, and soft reset via the serial port section ................................................... 51 changes to pi n descriptions section and spi mode operation section .............................................................................................. 56 changes to spi instruction word (16 bits) section .................. 57 changes to figure 6 6 , figure 67 caption, and figure 6 8 .......... 58 changes to eeprom operation section .................................... 60 changes to table 49 ....................................................................... 64 changes to table 50 and ta ble 51 ................................................ 68 changes to table 53 ....................................................................... 69 changes to table 55 ....................................................................... 77 changes to table 58 ....................................................................... 8 1 change to frequency planning using the ad9522 section ..... 82 updated outline dimensions ....................................................... 84 10 /08 revision 0 : initial version rev. a | page 4 of 84
data sheet ad9522- 0 specifications typical (typ) is given for vs = 3.3 v 5%; vs vcp 5.25 v; t a = 25c; rset = 4.12 k?; cprset = 5.1 k? , unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. power supply requir e ments table 1 . parameter min typ max unit test conditions/comments vs 3.135 3.3 3.465 v 3.3 v 5% vcp vs 5.25 v this supply is usually at the same voltage as vs; set vcp = 5.0 v 5% only if connecting a 5 v external vco/vcxo rset pin resistor 4.12 k? sets internal bias ing cur rents; connect to ground cprset pin resistor 5.1 k? sets internal cp current range, nominally 4.8 ma (cp_lsb = 600 a); actual current can be calculated by cp_lsb = 3.06/cprset; connect to ground bypass pin capacitor 220 nf bypass for interna l ldo regulator; necessary for l do stability; connect to ground pll characteristics table 2 . parameter min typ max unit test conditions/comments vco ( on - chip ) frequency range 2530 2950 mhz vco gain (k vco ) 52 mhz/v see figure 8 tuning voltage (v t ) 0.5 v cp ? 0.5 v v cp vs when using internal vco frequency pushing (open - loop) 1 mhz/v phase noise at 1 khz offset ? 6 0 dbc/hz lvds output; f vco = 2750 mhz ; f out = 685 mhz phase noise at 100 khz offset ? 1 18 dbc/hz lvds output; f vco = 275 0 mhz; f out = 685 mhz phase noise at 1 mhz offset ? 1 35 dbc/hz lvds output; f vco = 275 0 mhz; f out = 685 mhz reference inputs differential mode (refin, refin ) differential mode (can accommodate single - ended input by ac grounding the unused com plementary input) input frequency 0 250 mhz frequencies below about 1 mhz must be dc - coupled; be careful to match v cm (self - bias voltage) input sensitivity 280 mv p -p pll figure of merit (fom) increases with increasing slew rate (see figure 12 ); the input sensitivity is sufficient for ac - coupled lvds and lvpecl signals self - bias voltage, refin 1.3 5 1.60 1.75 v self - bias voltage of refin 1 self - bias voltage, refin 1.30 1.50 1.60 v self - bias voltage of refin 1 input resistance, refin 4.0 4.8 5.9 k? self - biased 1 input resistance, refin 4.4 5.3 6.4 k? self - biased 1 dual single - ended mode (ref1, ref2) two single - ended cmos - compatible inputs input frequency (ac - coupled) with dc offset off ) 1 0 250 mhz s lew rate must be > 50 v/s input frequency (ac - coupled with dc offset on ) 250 mhz slew rate must be > 50 v/s , and input amplitude sensitivity spec ification must be met ; see input sensitivity input frequency (dc - coupled) 0 250 mhz slew rate > 50 v/s; cmos levels input sensitivity (ac - coupled with dc offset off ) 0.55 3.28 v p - p v ih must not exceed vs input sensitivity (ac - coupled with dc offset on) 1.5 2.78 v p -p vih must not exceed vs input logic high , dc offset off 2.0 v input logic low , dc offset off 0.8 v input current ?100 +100 a input capacitance 2 p f each pin, refin (ref1 ) / refin ( ref2) pulse width high/low 1.8 ns amount of time a square wave is high/low determines the allowable input duty cycle rev. a | page 5 of 84
ad9522- 0 data sheet parameter min typ max unit test conditions/comments crystal oscillator crystal resonator frequency range 16.6 2 33.33 mhz maximum crystal motional resistance 30 ? phase/frequency detector (pfd) pfd input frequency 100 mhz antibacklash pulse width = 1.3 ns, 2.9 ns 45 mhz antibacklash pulse width = 6.0 ns ref erence input clock doubler frequency 0.004 50 mhz antibacklash pulse width = 1.3 ns, 2.9 ns antibacklash pulse width 1.3 ns register 0x017 [ 1:0 ] = 01b 2.9 ns register 0x017 [ 1:0 ] = 00b; register 0x017 [ 1:0 ] = 11b 6.0 ns register 0x017 [ 1:0 ] = 10b charge pump (cp) i cp sink/source programmable high value 4.8 ma with cprset = 5.1 k? ; h igher i cp is possible by changing cprset low value 0.60 ma with cprset = 5.1 k ?; l ower i cp is possible by changing cprset absolute accuracy 2.5 % charge pump voltage set to v cp /2 cprset range 2.7 10 k? i cp high impedance mode leakage 1 na sink - and - source current matching 1 % 0.5 v < v cp < vcp ? 0.5 v; v cp is the voltage on the cp (charge pump) pin; vcp is the voltage on the vcp power supply pin i cp vs. v cp 1.5 % 0.5 v < v cp < vcp ? 0.5 v i cp vs. temperature 2 % v cp = vcp/2 v prescaler (part of n divider) prescaler input frequency p = 1 fd 300 mhz p = 2 fd 600 mhz p = 3 fd 900 mhz p = 2 dm (2/3) 2 00 mhz p = 4 dm (4/5) 1000 mhz p = 8 dm (8/9) 2400 mhz p = 16 dm (16/17) 3000 mhz p = 32 dm ( 32/33) 3000 mhz prescaler output frequency 300 mhz a, b counter input frequency (prescaler input frequency divided by p) pll n divider delay register 0x0 19 [ 2:0 ] ; see table 53 000 off 001 385 ps 010 504 ps 011 623 ps 100 743 ps 101 866 ps 110 989 ps 111 1112 ps pll r divider delay register 0x019 [ 5:3 ] ; see table 53 000 off 001 365 ps 010 486 ps 011 608 ps 100 730 ps 101 852 ps 110 976 ps 111 1101 ps rev. a | page 6 of 84
data sheet ad9522- 0 parameter min typ max unit test conditions/comments phase offset in zero delay ref refers to refin (ref1)/ refin (ref2) phase offset (ref - to - lvds clock output pins) in internal zero delay mode 1890 2348 3026 ps when n delay and r delay are bypass ed phase offset (ref - to - lvds clock output pins) in internal zero delay mode 900 1217 1695 ps when n delay = s etting 111 and r del ay is bypassed phase offset (ref - to - clk input pins) in external zero delay mode 318 677 1085 ps when n de lay and r delay are bypass ed phase offset (ref - to - clk input pins) in external zero delay mode ? 329 + 33 + 360 ps when n delay = s etting 011 and r delay is bypassed noise characteristics in - band phase noise of the charge pump/ phase frequency detector (in - band means within the lbw of the pll) the pll in - band phase noise floor is estimated by measuring the in - band phase noise at the output of the vco and subtracting 20 log(n) (where n is the value of the n divider) at 500 khz pfd frequency ?165 dbc/hz at 1 mhz pfd frequency ?162 dbc/hz at 10 mhz pfd frequency ?152 dbc/hz at 50 mhz pfd frequency ?144 dbc/hz pll figure of merit (fom) ?222 dbc/hz reference slew rate > 0. 5 v/ns; fom + 10 log(f pfd ) is an approximation of the pfd/cp in - band phase noise (in the flat region) inside the pll loop bandwidth; when running closed -lo op, the phase noise, as observed at the vco output, is increased by 20 log(n) ; pll figure of merit decreases with decreasing slew rate; see figure 12 pll digital lock detect window 2 signal available at the ld, status, and refmon pins when selected by appropriate register settings ; l ock detect window settings can be varied by changing the cprset resistor lock threshold (coincidence of edges) selected by register 0x017 [ 1:0 ] and register 0x018 [ 4 ] ( t his is the threshold to go from unlock to lock) low range (abp 1.3 ns, 2.9 ns) 3.5 ns register 0x017 [ 1:0 ] = 00b, 01b, 11b; register 0x018 [ 4 ] = 1b high range (abp 1.3 ns, 2.9 ns) 7.5 ns register 0x017 [ 1:0 ] = 00b, 01b, 11b; register 0x018 [ 4 ] = 0b high ra nge (abp 6 .0 ns) 3.5 ns register 0x017 [ 1:0 ] = 10b; register 0x018 [ 4 ] = 0b unlock threshold (hysteresis) 2 selected by register 0x017[1:0] and register 0x018[4] (t his is the threshold to go from lock to unlock ) low range (abp 1.3 ns, 2.9 ns) 7 ns register 0x017 [ 1:0 ] = 00b, 01b, 11b; register 0x018 [ 4 ] = 1b high range (abp 1.3 ns, 2.9 ns) 15 ns register 0x017 [ 1:0 ] = 00b, 01b, 11b; register 0x018 [ 4 ] = 0b high range (abp 6 .0 ns) 11 ns register 0x017 [ 1:0 ] = 10b; register 0x018 [ 4 ] = 0b 1 the refin and refin self - bias points are offset slightly to avoid chatter on an open input condition. 2 for reliable operation of the digital lock detect, the period of the pfd frequency must be great er than the unlock - after - lock time. rev. a | page 7 of 84
ad9522- 0 data sheet clock input s table 3 . parameter min typ max unit test conditions/comments clock inputs (clk, clk ) differential input input frequency 0 1 2.4 ghz high frequency dis tribution (vco divider) 0 1 2 ghz distribution only (vco divider bypassed); this is the frequency range supported by the channel divider , see the channel divider maximum frequency se ction input sensitivity, differential 150 mv p -p measured at 2.4 ghz ; j itter performance is improved with slew rates > 1 v/ns input level, differential 2 v p -p larger voltage swings can turn on the protection diodes and can degrade jitter performance input common - mode voltage, v cm 1.3 1.57 1. 8 v self - biased; enables ac coupling input common - mode range, v cmr 1.3 1.8 v wit h 200 mv p - p signal applied; dc - coupled input sensitivity, single - ended 150 mv p - p clk ac - coupled; clk ac - byp assed to rf ground input resistance 3.9 4.7 5.7 k? self - biased input capacitance 2 pf 1 below about 1 mhz, the input must be dc - coupled. take care to match v cm . clock outputs table 4 . parameter min typ max unit test conditions/comments lvds clock outputs termination = 100 ? across differential pair out0, out1, out2, out3, out4, out5 , out6, out7, out8, out9, out10, out11 differential (out, out ) output frequency 800 mhz the ad9522 outputs toggle at h igher frequencie s, bu t the output amplitude may not meet the v od spec ification output differential voltage, v od 247 360 454 mv v oh ? v ol for each leg of a differential pair for default amplitude setting with the driver not toggling; the peak -to - peak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2 these values (see figure 20) delta v od 25 mv absolute difference between voltage swing of normal pin and inverted pin, output driver static output offset voltage, v os 1.125 1.25 1.375 v (v oh + v ol )/2 across a differential pair del ta v os 25 mv this is the absolute value of the difference between v os when the normal output is high vs. when the complementary output is high short - circuit current, i sa , i sb 14 24 ma output shorted to gnd tristate leakage current p er output <1 na o utput in tristate with 100 ? across differential pair cmos clock outputs out0a, out0b, out1a, out1b, out2a, out2b, out3a, out3b, out4a, out4b, out5a, out5b, out6a, out6b, out7a, out7b, out8a, out8b, out9a, out9b, out10a, out10b, out11a, out11b single - ended; termination = 10 pf output frequency 250 mhz see figure 21 output voltage high, v oh vs ? 0.1 v at 1 ma load output voltage low, v ol 0.1 v at 1 ma load output voltage high, v oh 2.7 v a t 10 ma load output voltage low, v ol 0.5 v at 10 ma load rev. a | page 8 of 84
data sheet ad9522- 0 timing characteristi cs table 5 . parameter min typ max unit test conditions/comments lvds output rise/fall times termination = 10 0 ? across differential pair o utput rise time, t rp 150 350 ps 20% to 80%, measured differentially output fall time, t fp 150 350 ps 80% to 20%, measured differentially propagation delay, t lvds , clk - to - lvds out put for a ll divide v alues 1866 2313 2812 ps high frequency clock dis tribution configuration 1808 2245 2740 p s clock distribution configuration variation with temperature 1 ps/c output skew , lvds outputs 1 termination = 100 ? across differential pair lvds outputs that share the same divider 7 60 p s lvds outputs on different dividers 19 162 ps all lvds outputs across multiple parts 432 ps cmos output rise/fall times termination = open output r ise time, t rc 625 835 p s 20% to 80%; c load = 10 pf output fall time, t fc 625 800 p s 80% to 20%; c load = 10 pf propagation delay, t cmos , clk - to - cmos output clock distribution configuration for all divide values 1913 2400 2950 ps variation with te mperature 2 ps/c output skew, cmos outputs 1 cmos outputs that share the same divider 10 55 p s all cmos outputs on different dividers 27 230 p s all cmos outputs across multiple parts 5 00 ps output skew , lvds - to - cmos out put 1 all settings identical ; different logic type outputs that s hare the same div ider ? 31 + 152 + 495 p s lvds to cmos on the same part outputs that a re on d ifferent d ivide r s ? 193 + 160 + 495 p s lvds to cmos on the same part 1 the output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. timing diagrams clk t cmos t clk t lvds 07219-060 figure 2 . clk/ clk t o clock output timing, div = 1 differential lvds 80% 20% t rp t fp 07219-061 figure 3. lvds timing, differential single-ended cmos 10pf load 80% 20% t rc t fc 07219-063 figure 4 . cmos timing, single - ended, 10 pf load rev. a | page 9 of 84
ad9522- 0 data sheet clock output additiv e phase noise (distr ibution o nly; vco divider not used) table 6 . parameter min typ max unit test conditions/comments clk - to - lvds additive phase nois e distribution section only; does not include pll and vco clk = 1 .6 ghz, output = 800 m hz input slew rate > 1 v/ns divider = 2 at 10 hz offset ?10 0 dbc/hz at 100 hz offset ?11 0 dbc/hz at 1 khz offset ?117 dbc/hz at 10 khz offset ?1 26 dbc/hz at 100 khz offset ?1 34 dbc/hz at 1 mhz offset ?1 37 dbc/hz at 10 mhz offset ?147 dbc/hz at 100 mhz offset ?1 48 dbc/hz clk = 1 gh z, output = 200 mhz input slew rate > 1 v/ns divider = 5 at 10 hz offset ?1 11 dbc/hz at 100 hz offset ?1 23 dbc/hz at 1 khz offset ?1 32 dbc/hz at 10 khz offset ?1 41 dbc/hz at 100 khz offset ?1 46 dbc/hz at 1 mhz offset ?150 d bc/hz >10 mhz offset ?156 dbc/hz clk - to - cmos additive phase noise distribution section only; does not include pll and vco clk = 1 ghz, output = 5 0 0 mhz input slew rate > 1 v/ns divider = 2 at 10 hz offset ?1 02 dbc/hz at 100 hz off set ?1 14 dbc/hz at 1 khz offset ?1 22 dbc/hz at 10 khz offset ?1 29 dbc/hz at 100 khz offset ?13 5 dbc/hz at 1 mhz offset ?1 4 0 dbc/hz >10 mhz offset ?15 0 dbc/hz clk = 1 ghz, output = 50 mhz input slew rate > 1 v/ns divider = 20 at 10 hz offset ?12 5 dbc/hz at 100 hz offset ?13 6 dbc/hz at 1 khz offset ?1 44 dbc/hz at 10 khz offset ?1 52 dbc/hz at 100 khz offset ?157 dbc/hz at 1 mhz offset ?160 dbc/hz >10 mhz offset ?164 dbc/hz rev. a | page 10 of 84
data sheet ad9522- 0 clock output abso lute phase noise (internal vco used) table 7 . parameter min typ max unit test conditions/comments lvds absolute phase noise inter nal vco; vco divider = 4 ; lvds o utput and for loop bandwidths < 1 khz vco = 2950 m hz ; output = 7 37.5 m hz at 1 khz offset ? 5 9 dbc/hz at 10 khz offset ? 9 0 dbc/hz at 100 khz offset ? 115 dbc/hz at 1 mhz offset ? 133 dbc/hz at 10 mhz offset ? 146 dbc/hz at 40 mhz offset ? 1 49 dbc/hz vco = 2750 m hz ; output = 685 m hz at 1 khz offset ? 6 0 dbc/hz at 10 kh z offset ? 9 2 dbc/hz at 100 khz offset ? 1 18 dbc/hz at 1 mhz offset ? 135 dbc/hz at 10 mhz offset ? 148 dbc/hz at 40 mhz offset ? 151 dbc/hz vco = 2550 m hz ; output = 632.5 m hz at 1 khz offset ? 64 dbc/hz at 10 khz offset ? 9 5 dbc/h z at 100 khz offset ? 120 dbc/hz at 1 mhz offset ? 1 3 7 dbc/hz at 10 mhz offset ? 1 4 8 dbc/hz at 40 mhz offset ? 151 dbc/hz clock output a b solute time jitter ( clock generation usi ng internal vco) table 8 . parameter min typ max unit test conditions/comments lvds output absolute time jitter application example based on a typical setup where the reference source is clean, so a wider pll loop bandwidth is used ; r eference = 15.36 mhz; r div = 1 vco = 2949 m hz ; lvds = 245.76 mhz; pll lbw = 55 khz 187 f s rms int egration bandwidth = 200 khz to 10 mhz 352 fs rms int egration bandwidth = 12 khz to 20 mhz vco = 2580 m hz ; lvds = 122.88 mhz; pll lbw = 55 khz 1 6 6 fs rms inte gration bandwidth = 200 khz to 10 mhz 321 fs rms int egration bandwidth = 12 khz to 20 mhz vco = 2580 m hz ; lvds = 61.44 mhz; pll lbw = 55 khz 218 fs rms int egration bandwidth = 200 khz to 10 mhz 3 78 fs rms int egration bandwidth = 12 khz to 20 mhz clock output a b solute time jitter (c lock cleanup using intern al vco ) table 9 . parameter min typ max unit test conditions/comments lvds output absolute time jitter application example based on a typical setup where the reference source is jittery, so a narrower pll loop bandwidth is used; reference = 1 9 . 44 mhz; r div = 162 vco = 2799 m hz ; lvds = 155.52 mhz; pll lbw = 1.8 k hz 617 fs rms integration bandwidth = 12 khz to 20 mhz vco = 2580 m hz ; lvds = 122.88 mhz; pll lbw = 1.8 k hz 514 fs rms int egration bandwidth = 12 khz to 20 mhz rev. a | page 11 of 84
ad9522- 0 data sheet clock output a b solute time jitter (c lock generation using external vcxo ) table 10. parameter min typ max unit test conditions/comments lvds output absolute time jitter application example based on a typica l setup using an external 245.76 mhz vcxo (toyocom tco -2112) ; r eference = 15.36 mhz; r div = 1 lvds = 245.76 mhz; pll lbw = 125 hz 87 fs rms int egration bandwidth = 200 khz to 5 mhz 108 fs rms inte gration bandwidth = 200 khz to 10 mhz 1 46 fs rms int egration bandwidth = 12 khz to 20 mhz lvds = 122.88 mhz; pll lbw = 125 hz 120 fs rms integration bandwidth = 200 khz to 5 mhz 1 51 fs rms inte gration bandwidth = 200 khz to 10 mhz 207 fs rms int egration bandwidth = 12 khz to 20 mhz lvds = 6 1.44 mhz; pll lbw = 125 hz 1 57 fs rms int egration bandwidth = 200 khz to 5 mhz 210 fs rms inte gration bandwidth = 200 khz to 10 mhz 2 95 fs rms int egration bandwidth = 12 khz to 20 mhz clock output additiv e time jitter (vco d ivider not used) tab le 11. parameter min typ max unit test conditions/comments lvds output additive time jitter distribution s ection only; does not include pll and vco ; m easured at rising ed ge of clock signal clk = 622.08 mhz 69 fs rms inte gration bandwidth = 12 khz to 20 mhz any lvds o utput = 622.08 mhz divide ratio = 1 clk = 622.08 mhz 116 fs rms integrat ion bandwidth = 12 khz to 20 mhz any lvds o utput = 155.52 mhz divide ratio = 4 clk = 1 00 mhz 263 fs rms c alculated from snr of adc method any lvds output = 100 mhz broadband jitter divide ratio = 1 clk = 5 00 mhz 2 42 fs rms calculated from snr of adc met hod any lvds o utput = 100 mhz broadband jitter divide ratio = 5 cmos output addit ive time jitter distribution s ection only; does not include pll and vco clk = 2 00 mhz 289 fs rms calculated from snr of adc method any cmos output p air = 100 mhz broadband j itter divide ratio = 2 rev. a | page 12 of 84
data sheet ad9522- 0 clock output additiv e time ji tter (vco divider us ed) table 12. parameter min typ max unit test conditions/comments lvds output additive time jitter distribution section only; does not include pll and vco ; u ses rising edge of c lock signal clk = 500 mhz; vco div = 5; lvds = 100 mhz; bypass channel divider; duty - cycle correction = on 248 fs rms calculated from snr of adc method ( broadband jitter ) cmos output additive time jitter distribution section only; does not include pll and vco ; uses rising e dge of clock signal clk = 200 mhz; vco div = 2; cmos = 100 mhz; bypass channel divider; duty - cycle correction = off 290 fs rms calculated from snr of adc method ( broadband jitter ) clk = 2 00 m hz; vco d iv = 1 ; cmos = 100 mhz; bypass channel divider ; dut y - cycle correction = off 288 fs rms cal culated from snr of adc method (broadband jitter) serial control port spi mode table 13. parameter min typ max unit test conditions/comments cs (input ) cs has an internal 30 k? pull - up resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 3 a input logic 0 current ? 110 a the minus sign indicates that current is flowing out of the ad9522 , which is due to the internal pull - up resistor input capacitance 2 pf sclk (input) in spi mode sclk has an internal 30 k? pu ll- down resistor in spi mode, but not in i 2 c mode input log ic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 110 a input logic 0 current 1 a input capacitance 2 pf sdio ( when an input in bidirectional mode ) input logic 1 voltage 2.0 v input logic 0 voltage 0 .8 v input logic 1 current 1 a input logic 0 current 1 a input capacitance 2 pf sdio, sdo (outputs) output logic 1 voltage 2.7 v at 1 ma current; maximum recommended current: 5 ma output logic 0 voltage 0.4 v at 1 ma current tim ing clock rate (sclk, 1/t sclk ) 25 mhz pulse width high, t hi gh 16 ns pulse width low, t l o w 16 ns sdio to sclk setup, t ds 4 ns sclk to sdio hold, t dh 0 ns sclk to valid sdio and sdo, t dv 1 1 ns cs to sclk set up and hold, t s , t c 2 ns cs minimum pulse width high, t pwh 3 ns rev. a | page 13 of 84
ad9522- 0 data sheet serial control port i2c mode table 14. parameter min typ max unit test conditions/comments sda, scl ( when input ting data ) input logic 1 voltage 0.7 vs v input logic 0 voltage 0.3 vs v input current with an input voltage betwe en 0.1 vs and 0.9 vs ? 10 + 10 a hysteresis of schmitt trigger inpu ts 0.015 vs v pulse w idth of spikes that must be suppressed by the input fi lter , t sp ike 50 ns sda ( when outputting data ) output logic 0 voltage at 3 ma sink current 0.4 v output fall ti me from vi h min to v i l max with a bus cap acitance from 10 pf to 400 pf 20 + 0.1 c b 250 ns c b = capacitance of one bus li ne in pf timing note that a ll i 2 c timing values refer to vih min (0.3 vs) and vil max levels (0.7 vs) clock rate (scl, f i2c ) 400 k hz bus free time b etween a stop and s tart c ondition , t idle 1.3 s set u p ti me for a r epeated s tart c ondition , t s et ; st r 0.6 s hold time (re peated) s tart c ondition ( after this p eriod, the first clock pulse is g enerated ) , t hl d; st r 0.6 s set u p time for s top c ondition, t s et ; st p 0.6 s l ow p eriod of the scl c lock , t lo w 1.3 s h igh p eriod of the scl c lock , t high 0.6 s scl, sda rise time, t rise 20 + 0.1 c b 300 ns c b = capacitance of one bus line in pf scl, sda fall time, t fal l 20 + 0.1 c b 300 ns c b = capacitance of one bus line in pf data setup time, t s et ; dat 120 ns this is a m inor deviati on from the original i2c specification of 100 ns minimum data hold time, t hl d; dat 140 880 ns this is a minor deviation from the original i2c specification of 0 ns minimum 1 capacitive l oad for each bus li ne, c b 400 pf 1 according to the o riginal i 2 c specification, an i 2 c master m ust also provide a minimum hold time of 300 ns for the sda signal to bridge the undefined region of the scl falling edge. rev. a | page 14 of 84
data sheet ad9522- 0 pd , sync , and reset pins table 1 5 . parameter min typ max unit test conditions/comments input characteristics each of t hese pins ha s a n 30 k? internal pull - up resistor logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 1 a logic 0 current ? 110 a the minus sign indicates that current is flowing out of the ad9522 , which is due to the internal pull - up resistor capacitance 2 pf reset timing pulse width low 50 ns reset i nactive to s tart of register programming 100 ns sync timing pulse width low 1.3 ns high speed clock is clk input signal serial port setup pi ns : sp1, sp0 table 16. parameter min typ max unit test conditions/comments sp1, sp0 these pins do not have internal pull -up /pull - down resistor s logic level 0 0.25 vs v vs is the voltage on the vs pin logic level ? 0.4 vs 0.65 vs v user can float these pins to obtain logic level ?; if floating this pin, connect a capacitor to ground logic level 1 0.8 vs v ld, status, and refmon pins table 17. parameter min typ max unit test conditions/comments output characteristics when selected as a digital output (cmos); there are other modes in which these pins are not cmos digital out puts; see table 53 , register 0x017, register 0x01a, and register 0x01b output voltage high, v oh 2.7 v at 1 ma current; maximum recommended current: 5 ma output voltage low, v ol 0.4 v at 1 ma current maximu m toggle rate 100 mhz applies when mux is set to any divider or counter output, or pfd up/down pulse ; a lso applies in analog lock detect mode ; u sually debug mode only ; note that spurs can couple to output when any of these pins are toggling analog lock detect capacitance 3 pf on - chip capacitance; used to calculate rc time constant for analog lock detect read back ; use a pull - up resistor ref1 , ref2 , and vco frequency status monitor normal range 1.02 m hz frequency above which the monitor i ndicate s the presence of the reference extended range 8 khz frequency above which the monitor indicate s the presence of the reference ld pin comparator trip point 1.6 v hysteresis 260 mv rev. a | page 15 of 84
ad9522- 0 data sheet power dissipation table 18. parameter min typ max unit test conditions/comments power dissipation , chip does not include power dissipated in external resistors ; a ll lvds outputs terminated with 10 0 ? across differential pair; a ll cmos outputs have 10 pf capacitive loadin g power - on de fault 0.88 1.0 w no clock; no programming; default register values pll locked; o ne lvds output en abled 0.54 0.63 w f ref = 25 mhz ; f out = 250 mhz ; vco = 2 7 5 0 m hz ; vco d ivider = 2; o ne lvds output and output divider enabled ; z ero delay off ; i cp = 4.8 ma pll locked; o ne cmos output e nabled 0.55 0.66 w f ref = 25 mhz; f out = 62.5 mhz ; vco = 2750 m hz ; vco d i vider = 2; o ne cmos output and output divider enabled ; zero delay off; i cp = 4.8 ma distribution only mode ; vco divider o n ; one lvds o utput e nabled 0.36 0.43 w f clk = 2 .4 g hz; f out = 20 0 mhz ; vco d ivider = 2; o ne lvds output and output divider enabled ; zero delay off distribution only mode; vco divider off; one lvds output enabled 0.33 0.4 w f clk = 2 .4 ghz ; f out = 200 mhz; vco divid er bypassed; one lvds output and output divider enabled; zero delay off max imum power, full operation 1. 1 1.3 w pll on; internal vco = 2750 m hz; vco divider = 2; all channel dividers on; 12 lvds outputs at 125 mhz; zero delay on pd po wer - down 35 50 mw pd pin pulled low ; d oes not include power dissipated in termination resistor s pd power - down, m ax imum s leep 27 43 mw pd pin pulled low ; pll power - down , register 0x 0 10[ 1:0 ] = 01b ; po wer - down sync, register 0x230 [ 2 ] = 1b ; power - down distribution reference , register 0x230[1] = 1b v cp s upply 2.3 8 mw pll operating; ty pical closed - loop configuration power deltas , individual functions p ower delta when a function is enabled/disabled vco divider on/o ff 33 43 mw vco divider not used refin ( d ifferential) o ff 25 31 mw delta between r ef erence input off and differential reference input mode ref1, ref2 ( single - end ed) on/off 16 22 mw delta between reference inputs off and one single - end ed reference enabled ; d ouble this number if both ref 1 and ref 2 are powered up vco on/off 60 95 mw internal vco disabled ; clk input selected pll dividers and phase detector on/of f 54 67 mw pll off to pll on, normal operation; no reference enabled lvds channel 118 146 mw n o lvds output on to one lvds output on ; c hannel divider set to 1 lvds driver 11 15 mw second lvds output turned on , same channel cmos channel 120 154 mw n o cmos output on to one cmos output on ; c hannel divider set to 1 ; f out = 62. 5 mhz and 10 pf of capacitive loading cmos driver on/off 16 30 mw additional cmos outputs within the same channel turned on channel divider enabled 33 40 mw delta between d ivider bypassed (divide -by - 1) and divide -by - 2 to divide -by -32 zero delay block on/off 30 35 mw rev. a | page 16 of 84
data sheet ad9522- 0 absolute maximum rat ings table 19. parameter or pin with respect to rating vs gnd ?0.3 v to +3.6 v v cp , cp gnd ?0.3 v to +5.8 v refin, refin gnd ?0.3 v to vs + 0.3 v rset , lf , bypass g nd ?0.3 v to vs + 0.3 v cprset gnd ?0.3 v to vs + 0.3 v clk, clk gnd ?0.3 v to vs + 0.3 v clk clk ?1.2 v to +1.2 v sclk /scl , sdio /sda , sdo, cs gnd ?0.3 v to vs + 0.3 v out0, out0 , out1, out1 , out2, out2 , out3, out3 , out4, out4 , out5, out5 , out6, out6 , out7, out7 , out8, out8 , out9, out9 , out10, out10 , out11, out11 gnd ?0.3 v to vs + 0.3 v sync , reset , pd gnd ?0.3 v to vs + 0.3 v refmon, status, ld gnd ?0.3 v to vs + 0.3 v sp0, sp1, eeprom gnd ?0.3 v to vs + 0.3 v junction temperature 1 1 2 5c storage temperatu re range ?65c to +150c lead temperature (10 sec) 300c 1 see the specifications section for operating temperature range (t a ) . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any othe r conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal impedance measurements wer e taken on a jedec jesd 51- 5 2s2p test board in s till air in accordance with jedec jesd 51 - 2 . see the thermal performance section for more details. table 20. package type ja unit 64- lead lfcsp (cp -64-4) 22 c/w esd caution rev. a | page 17 of 84
ad9522- 0 data sheet pin configuration an d function descripti ons notes 1. exposed die pad must be connected to gnd. pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 sdio/sda sdo gnd sp1 sp0 eeprom reset pd out9 (out9a) out9 (out9b) vs out10 (out10a) out10 (out10b) out11 (out11a) out11 (out11b) vs 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 refin (ref1) refin (ref2) cprset vs vs gnd rset vs out0 (out0a) out0 (out0b) vs out1 (out1a) out1 (out1b) out2 (out2a) out2 (out2b) vs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vs refmon ld vcp cp status ref_sel sync lf bypass vs vs clk clk cs sclk/scl out3 (out3a) out3 (out3b) vs out4 (out4a) out4 (out4b) out5 (out5a) out5 (out5b) vs vs out8 (out8b) out8 (out8a) out7 (out7b) out7 (out7a) vs out6 (out6b) out6 (out6a) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad9522 top view (not to scale) 07219-003 figure 5 . pin configuration table 21 . pin function descriptions pin no. input/ output pin typ e mnemonic description 1, 11, 12, 27, 32, 35, 40, 41, 46, 49, 54, 57, 60, 61 i power vs 3.3 v power pins. 2 o 3.3 v cmos refmon reference monitor (output). this pin has multiple selectable outputs. 3 o 3.3 v cmos ld lock detect (output). this pin has multiple selectable outputs. 4 i power v cp power supply for charge pump (cp); vs vc p 5.25 v. vcp must still b e connected to 3.3 v if the pll is not used. 5 o loop f ilter cp charge pump (output). this pin connects to an external loop filter. this pin can be left unconnected if the pll is not used. 6 o 3.3 v cmos status programmable status output . 7 i 3.3 v cmos ref_sel reference se lect. it selects ref1 (low) or ref2 (high). this pin has an internal 30 k? pull - down resistor. 8 i 3.3 v cmos sync manual synchronizations and manual holdover. this pin initiates a manual synchronization and is used for manual holdover. active low. this pin has an internal 30 k? pull - up resistor. 9 i loop f ilter lf loop filter (input). it connects internally to the vco control voltage node. 10 o loop f ilter bypass this pin is for bypassing the ldo to ground with a 220 nf capacitor. this pin can be left unconnected if the pll is not used. 13 i differential clock input clk along with clk , this pin is the differential input for the clo ck distribution section. 14 i differential clock input clk along with clk, this pin is the differential input for the clock distribution section. if a single - ended input is connected to the clk pin, connect a 0.1 f bypass capacitor fr om this pin to ground. rev. a | page 18 of 84
data sheet ad9522- 0 pin no. input/ output pin typ e mnemonic description 15 i 3.3 v cmos cs serial control port chip select; active low. this pin has an internal 30 k? pull - up resistor. 16 i 3.3 v cmos sclk/scl serial control port clock signal. this pin has an internal 30 k? pull - down resistor in spi mode but is high impedance in i2c mode. 17 i/o 3.3 v cmos sdio/sda serial control port bidirectional serial data in/out. 18 o 3.3 v cmos sdo serial control port unidirectional serial data out. 19, 59 i gnd gnd ground pins. 20 i three - l evel logic sp1 select spi or i2c as the serial interface port and select the i2c slave address in i2c mode. three - level logic. this pin is internally biased for the open logic level. 21 i three - level logic sp0 select spi or i2c as the serial interface po rt and select the i2c slave address in i2c mode. three - level logic. this pin is internally biased for the open logic level. 22 i 3.3 v cmos eeprom setting this pin high selects the register values stored in the internal eeprom to be loaded at reset and/ or power - up. setting this pin low causes the ad9522 to load the hard - coded default register va lues at power - up/reset. this pin has an internal 30 k? pull - down resistor. note that t o guarantee the proper loading of eeprom during startup, a high - low - high pulse on the reset pin occurs after the power supply stabilizes. 23 i 3.3 v c mos reset chip reset , active low. this pin has an internal 30 k? pull - up resistor. 24 i 3.3 v cmos pd chip power - down , active low. this pin has an internal 30 k? pull - up resistor. 25 o lvds or cmos out9 (out9a) clock o utput . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 26 o lvds or cmos out9 (out9b) clock output . this pin can be configured as one side of a differential lvds o utput or as a singl e - ended cmos output. 28 o lvds or cmos out10 (out10a) clock output . this pin can be configured as one s i de of a d ifferential lvds o utput or as a single - e nded cmos o utput. 29 o lvds or cmos out10 (out10b) clock output . this pin can be c onfigured as one side of a differential lvds o utput or as a single - ended cmos output. 30 o lvds or cmos out11 (out11a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 31 o lvds or cmo s out11 (out11b) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 33 o lvds or cmos out6 (out6a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 34 o lvds or cmos out6 (out6b) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 36 o lvds or cmos out7 (out7a) clock out put . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 37 o lvds or cmos out7 (out7b) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 38 o lvds or cmos out8 (out8a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 39 o lvds or cmos out8 (out8b) clock output . this pin can be config ured as one side of a differential lvds o utput or as a single - ended cmos output. 42 o lvds or cmos out5 (out5b) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 43 o lvds or cmos out5 (out5a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 44 o lvds or cmos out4 (out4b) clock output . this pin can be configured as one side of a dif ferential lvds o utput or as a single - ended cmos output. 45 o lvds or cmos out4 (out4a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. rev. a | page 19 of 84
ad9522- 0 data sheet pin no. input/ output pin typ e mnemonic description 47 o lvds or cmos out3 (out3b ) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 48 o lvds or cmos out3 (out3a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ende d cmos output. 50 o lvds or cmos out2 (out2b) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 51 o lvds or cmos out2 (out2a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 52 o lvds or cmos out1 (out1b) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 53 o lvd s or cmos out1 (out1a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 55 o lvds or cmos out0 (out0b) clock output . this pin can be configured as one side of a differe ntial lvds o utput or as a single - ended cmos output. 56 o lvds or cmos out0 (out0a) clock output . this pin can be configured as one side of a differential lvds o utput or as a single - ended cmos output. 58 o current set resistor rset clock distribution c urrent set resistor. connect a 4.12 k ? resistor from this pin to gnd. 62 o current set resistor cprset charge pump current set resistor. connect a 5.1 k ? resistor from this pin to gnd. this resistor can be omitted if the pll is not used. 63 i reference i nput refin (ref 2) along with refin, this is the differential input for the pll reference. alternatively, this pin is a single - ended input for ref2. 64 i reference i nput refin (ref1) along with refin , this is the differential input for the pll referen ce. alternatively, this pin is a single - ended input for ref1. epad gnd gnd the e xposed die pad must be connected to gnd. rev. a | page 20 of 84
data sheet ad9522- 0 typical performance characteristics 275 250 225 200 175 150 125 100 75 0 200 400 600 800 1000 current (ma) frequency (mhz) 3 channels?6 lvds 3 channels?3 lvds 2 channels?2 lvds 1 channel?1 lvds 07219-108 figure 6. total current vs. freque n cy , clk - to - output (pll o ff) , channel and vco divider bypassed, lvds o utputs terminated 100 ? across differential pair 240 220 200 180 160 140 120 100 80 0 50 100 150 200 250 current (ma) frequency (mhz) 2 channels?8 cmos 2 channels?2 cmos 1 channel?2 cmos 1 channel?1 cmos 07219-109 figure 7. total current vs. frequency, clk - to - output (pll o ff), c hannel and vco divid er bypassed, cmos outputs with 10 pf l oad 65 40 45 50 55 60 2.55 2.95 2.85 2.75 2.65 k vco (mhz/v) vco frequency (ghz) 07219-010 figure 8. k vco vs. vco frequency 5 4 3 2 1 0 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 current from cp pin (ma) voltage on cp pin (v) pump up pump down 07219-111 figure 9. charge pump characteristics at vcp = 3.3 v 5 4 3 2 1 0 0 5.0 4.0 3.0 4.5 3.5 2.5 2.0 1.5 1.0 0.5 current from cp pin (ma) voltage on cp pin (v) pump down pump up 07219-112 figure 10 . charge pump characteristics at vcp = 5.0 v ?140 ?145 ?150 ?155 ?160 ?165 ?170 0.1 1 100 10 pfd phase noise referred to pfd input (dbc/hz) pfd frequency (mhz) 07219-013 figure 11 . pfd phase noise referred to pfd i nput vs. pfd frequency rev. a | page 21 of 8 4
ad9522- 0 data sheet ?208 ?210 ?212 ?214 ?216 ?218 ?220 ?222 ?224 0 0.4 0.8 1.2 0.2 0.6 1.0 1.4 pll figure of merit (dbc/hz) input slew rate (v/ns) differential input single-ended input 07219-114 figure 12 . pll figure of merit (fom) vs. slew rate at refin/ refin 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 power (dbm) 100 145 140 135 130 125 120 115 110 105 frequency (mhz) 07219-116 figure 13 . pfd/cp spurs; 122.88 mhz; pfd = 15.36 mhz ; lbw = 127 khz; i cp = 3.0 ma; f vco = 2580 m hz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 power (dbm) 122.38 122.58 122.78 122.98 123.18 123.38 frequency (mhz) 07219-117 figure 1 output spectrum, lvds 12288 mhz pfd = 16 mhz lbw = 12 khz i cp = 0 ma f vco = 280 m hz 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh (v) 10k 1k 100 resistive load (?) vs_drv = 3.135v vs_drv = 2.35v vs_drv = 3.3v vs_drv = 2.5v 07219-118 figure 15 . cmos output v oh (s tatic) vs . r load (to ground) 07219-014 0.4 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 differential output (v) time (ns) figure 16 lvds output (diffe rential) at 100 mhz output terminated 100 across differential pair 0.4 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 3.0 2.5 2.0 1.5 1.0 0.5 differential swing (v p-p) time (ns) 07219-015 figure 17 . lvds differe ntial v oltage swing at 800 mhz output terminated 100 across differential pair rev. a | page 22 of 84
data sheet ad9522-0 rev. a | page 23 of 84 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 080 60 100 40 20 70 50 90 30 10 amplitude (v) time (ns) 07219-018 figure 18. cmos output with 10 pf load at 25 mhz 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 010 987654321 amplitude (v) time (ns) 2pf load 10pf load 07219-019 figure 19. cmos output with 2 pf and 10 pf load at 250 mhz 1600 1400 1200 1000 800 600 400 200 0 0 1000 600 800 400 200 differential swing (mv p-p) frequency (ghz) 7ma setting default 3.5ma setting 07219-123 figure 20. lvds differential voltage swing vs. frequency output terminated 100 across differential pair 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0700 2pf 10pf 20pf 600 500 400 300 200 100 amplitude (v) frequency (mhz) 07219-124 figure 21. cmos output swing vs. frequency and capacitive load ? 50 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 1k 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-023 figure 22. internal vco phase noise (absolute), lvds output at 633 mhz ? 50 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 1k 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-024 figure 23. internal vco phase noise (absolute), lvds output at 685 mhz
ad9522- 0 data sheet ?50 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 1k 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-025 figure 24 . internal vco phase noise ( absolute) , lvds output at 737 mhz ?100 ?110 ?120 ?130 ?140 ?150 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-128 figure 25 . additive (residual) phase noise , clk - to - lvds at 245.76 mhz , d ivide - by - 1 ?100 ?110 ?120 ?130 ?140 ?160 ?150 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-129 figure 26 . additive (res idual) phase noise , clk - to - lvds at 200 mhz , d ivide - by - 5 ?100 ?110 ?120 ?130 ?140 ?150 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-130 figure 27 . additive (residual) phase noise , clk - to - lvds at 8 00 mhz, d ivide - by - 1 ?110 ?120 ?130 ?140 ?150 ?170 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-131 figure 28 . additive (residual) phase noise , clk - to - cmos at 5 0 mhz, divide- by - 20 ?100 ?110 ?120 ?130 ?140 ?150 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-132 figure 29 . additive (residual) phase noise , clk - to - cmos at 250 mhz, divide - by - 4 rev. a | page 24 of 84
data sheet ad9522- 0 ?100 ?160 ?150 ?140 ?130 ?120 ?110 1k 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07219-033 figure 30 . phase noise (absolute) clock generation; i nternal vco at 2580 m hz ; pfd = 15.36 mhz; l bw = 40 khz; lvds output = 122.88 mhz ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1k 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) integrated rms jitter (12khz to 20mhz): 617fs integrated rms jitter (20khz to 80mhz): 450fs (extrapolated) 07219-034 figure 31 . phase noise (absolute) clock cleanup; internal vco at 2799 m hz ; pfd = 120 k hz; lbw = 1 .92 khz; lvds output = 155.52 mhz 1k 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 integrated rms jitter (12khz to 20mhz): 146fs 07219-135 figure 32 . phase noise (abs olute), e xternal vcxo (toyocom tco - 2112) at 245.76 mhz; pfd = 15.36 mhz; lbw = 250 hz ; lvds o utput = 245.76 mhz rev. a | page 25 of 84
ad9522- 0 data sheet test circuits c1 62pf c3 33pf c2 240nf c12 220nf bypass capacitor for ldo r1 820? r2 390? lf cp bypass 07219-234 figure 33 . pll loop filter used for clock generation plot (see figure 30 ) c1 1.5nf c3 2.2nf c2 4.7f c12 220nf bypass capacitor for ldo r1 2.1k? r2 3k? lf cp bypass 07219-235 figure 34 . pll loop filter used for clock cleanup plot (see figure 31 ) rev. a | page 26 of 84
data sheet ad9522- 0 terminology phase jitter and phase noise an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can cont ribute to phase jitter, one major cause is random noise, which is characterized statistically as gaussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous p ower spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in d ecibels ) of the power contained within a 1 hz bandwidth wit h respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. it is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz ). this is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of adcs , da cs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as ti me jitter. when observing a sine wave, the time of successive zero crossings var ies . in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the gaussian distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal - to - noise ratio ( snr ) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given converter. additive phase noise additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the var ious oscillators and clock sources, each of which contribute s its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contributors to phase noise, the total is the square roo t of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is s ubtracted. this makes it possible to predict the degree to which the device i mpact s the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute s its own time jitter to the total. in many ca ses, the time jitter of the external oscillators and clock sources dominates the system time jitter. rev. a | page 27 of 84
ad9522- 0 data sheet detailed block diagr am programmable n delay refin clk clk ref1 ref2 buf amp ad9522 status status r divider clock doubler status programmable r delay reference switchover ref_sel cprset vcp vs gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) phase frequency detector lock detect charge pump pll reference hold 0 1 divide by 1, 2, 3, 4, 5, or 6 pd sync refin reset eeprom digital logic eeprom divide by 1 to 32 out0 out0 out1 out1 out2 out2 divide by 1 to 32 out3 out3 out4 out4 out5 out5 divide by 1 to 32 out6 out6 out7 out7 out8 out8 divide by 1 to 32 out9 out9 out10 out10 out11 out11 zero delay block lvds/lvcmos output sp1 sp0 spi interface i 2 c interface sclk/scl sdio/sda sdo cs serial port decode optional 07219-028 figure 35 . rev. a | page 28 of 84
data sheet ad9522- 0 theory of operation operational configur ations t he ad9522 can be configured in several ways . these configurations must be set up by loading the control registers ( see table 49 to table 60) . each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. after the desired configuration is programmed, the user can store these values in the o n - board eeprom to allow the part to power up in the desired configuration without user intervention. mode 0: internal vco and clock distribution when using the internal vco and pll, the vco divider must be employed to ensure in most cases that the input f requency to the channel dividers does not exceed its specified maximum frequency (see table 3 ). the exceptions to this are vco direct mode and cases where the vco frequency is 2000 mhz. the channel divider maxim um input frequency is 2000 mhz provided that the user does not choose a divide - by - 17 or a divide - by - 3. if divide - by - 3 or divide - by - 17 is desired, the maximum channel divider input frequency is 1600 mhz. the internal pll uses an external loop filter to set the loop bandwidth. the external loop filter is also crucial to the loop stability. the internal pll uses an external loop filter to set the loop bandwidth. the external loop filter is also crucial to the loop stability. when using the internal vco, it i s necessary to calibrate the vco (register 0x018[0] = 1b) to ensure optimal performance. for internal vco and clock distribution applications, use the register settings shown in table 22. table 22 . settings when using internal vco register description 0x010[1:0] = 00b pll normal operation (pll on) 0x010 to 0x01e pll settings; select and enable a reference input; set r, n (p, a, b), pfd polarity, and i cp according to the intended loop confi guration 0x1e1[1] = 1b vco selected as the source 0x01c[2:0] enable reference inputs 0x1e0[2:0] set vco divider 0x1e1[0] = 0b use the vco divider as the source for the distribution section 0x018[0] = 0 b 0x232[0] = 1 b reset vco calibration and issue io _update (not necessary for the first time after power - up , but must be done subsequently) 0x018[0] = 1 b 0x232[0] = 1 b initiate vco calibration, i ssue io_update rev. a | page 29 of 84
ad9522- 0 data sheet programmable n delay refin clk clk ref1 ref2 buf amp ad9522 r divider clock doubler status programmable r delay reference switchover ref_sel cprset vcp vs gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) phase frequency detector lock detect charge pump pll reference hold 0 1 divide by 1, 2, 3, 4, 5, or 6 pd sync refin reset eeprom digital logic eeprom divide by 1 to 32 out0 out0 out1 out1 out2 out2 divide by 1 to 32 out3 out3 out4 out4 out5 out5 divide by 1 to 32 out6 out6 out7 out7 out8 out8 divide by 1 to 32 out9 out9 out10 out10 out11 out11 zero delay block lvds/cmos output status status sp1 sp0 spi interface i 2 c interface sclk/scl sdio/sda sdo cs serial port decode optional 07219-030 figure 36 . internal vco and clock distribution (mode 0) rev. a | page 30 of 84
data sheet ad9522- 0 mo de 1: clock distribution or external vco < 1600 mhz when the external clock source to be distributed or the external vco/vcxo is <1600 mhz, a configuration that bypasses the vco divider can be used. this is the only difference from mode 2. bypassing the v co divider limits the frequency of the clock source to <1600 mhz (due to the maximum input frequency allowed at the channel dividers). for clock distribution applications where the external clock is <1600 mhz, use the register settings shown in table 23 . table 23 . settings for clock distribution < 1600 mhz register description 0x010[1:0] = 01b pll asynchronous power - down (pll off ) 0x1e1[0] = 1b bypass the vco divider as the source for the distribution section 0x1e1[1] = 0b clk selected as the source when using the internal pll with an external vco < 1600 mhz, the pll must be turned on. table 24 . settings for using internal pll with external vco < 1600 mhz regis ter description 0x1e1[0] = 1b bypass the vco divider as the source for the distribution section 0x010[1:0] = 00b pll normal operation (pll on) along with other appropriate pll settings in register 0x010 to register 0x01e an external vco/vcxo requires an external loop filter that must be connected between cp and the tuning pin of the vco/ vcxo. this loop filter determines the loop bandwidth and stability of the pll. make sure to select the proper pfd polarity for the vco/vcxo being used. table 25 . setting the pfd polarity register description 0x010[7] = 0 b pfd polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1 b pfd polarity negative (higher control voltage produces lower frequency) rev. a | page 31 of 84
ad9522- 0 data sheet 07219-031 programmable n delay refin clk clk ref1 ref2 buf amp ad9522 r divider clock doubler status programmable r delay reference switchover ref_sel cprset vcp vs gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) phase frequency detector lock detect charge pump pll reference hold 0 1 divide by 1, 2, 3, 4, 5, or 6 pd sync refin reset eeprom digital logic eeprom divide by 1 to 32 out0 out0 out1 out1 out2 out2 divide by 1 to 32 out3 out3 out4 out4 out5 out5 divide by 1 to 32 out6 out6 out7 out7 out8 out8 divide by 1 to 32 out9 out9 out10 out10 out11 out11 zero delay block lvds/cmos outputs status status sp1 sp0 spi interface i 2 c interface sclk/scl sdio/sda sdo cs serial port decode optional figure 37 . clock distribution or external vco < 1600 mhz (mode 1 ) rev. a | page 32 of 84
data sheet ad9522- 0 mode 2: high frequency clock distribution clk or external vco > 1600 mh z the ad9522 power - up default configuration has the pll powered off and the routing of the input set so that the clk/ clk input is connected to the distribution section t hrough the vco divider ( divide - by - 1/ divide - by - 2 / divide - by - 3 /divide - b y - 4 / divide - by - 5 /divide - by - 6) . this is a distribution - only mode that allows for an external input up to 2400 mhz (see table 3 ) . t he maximum frequency that can be applied to the channel dividers is 1600 mhz ; there fore, higher input frequencies must be divided down before reaching the channel dividers. when the pll is enabled, this routing also allows the use of the pll with an external vco or vcxo with a frequency < 2400 mhz. in this configuration, the internal vco is not used and is powered off. the external vco/vcxo feeds directly into the prescaler. the register settings shown in table 26 are the default values of these regist ers at power - up or after a reset operation . table 26 . default register s ettings for clock distribution mode register description 0x 0 10 [ 1:0 ] = 01b pll asynchronous power - down (pll off ) 0x1e0 [ 2:0 ] = 00 0b set vco divider = 2 0x1e1 [ 0 ] = 0b use the vco divider 0x1e1 [ 1 ] = 0b clk selected as the source when us ing the internal pll with an external vco, the pll must be turned on. table 27. s ettings w hen u sing an e xternal vco register description 0x 0 10 [ 1:0 ] = 00b pll normal operation (pll on) 0x010 to 0x01e pll settings; select and enable a reference input; set r, n (p, a, b), pfd polarity, and i cp according to the intended loop configuration 0x1e1 [ 1 ] = 0b clk selected as the source an external vco requires an external loop filter that must be conne cted between cp and the tuning pin of the vco. this loop filter determines the loop bandwidth and stability of the pll. make sure to select the proper pfd polarity for the vco being used. table 28. s etting the pfd p olarity register description 0x 0 10 [ 7 ] = 0b pfd polarity positive (higher control voltage produces higher frequency) 0x 0 10 [ 7 ] = 1b pfd polarity negative (higher control voltage produces lower frequency) rev. a | page 33 of 84
ad9522- 0 data sheet programmable n del a y refin clk clk ref1 ref2 buf am p ad9522 r divider clock doubler sta tus programmable r del a y reference switchover ref_se l cprset vc p vs gnd rset distribution reference refmon cp sta tus ld p , p + 1 prescaler a/b counters n divider by p ass lf low dropout regul a t or (ldo) phase frequenc y detec t or lock detect charge pum p pll reference hold 0 1 divide b y 1, 2, 3, 4, 5, or 6 pd sync refin reset eeprom digi t al logic eeprom divide b y 1 t o 32 out0 out0 out1 out1 out2 out2 divide b y 1 t o 32 out3 out3 out4 out4 out5 out5 divide b y 1 t o 32 out6 out6 out7 out7 out8 out8 divide b y 1 t o 32 out9 out9 out10 out10 out 1 1 out 1 1 zero del a y block l vds/cmos outputs sta tus sta tus sp1 sp0 spi inter f ace i 2 c inter f ace sclk/sc l sdio/sd a sdo cs seria l port decode optiona l 07219-029 figure 38 . high frequency clock dis tribution or external vco > 1600 mhz (mode 2) rev. a | page 34 of 84
data sheet ad9522- 0 phase - locked loop (pll) programmable n delay refin clk clk ref1 ref2 buf status status r divider clock doubler status programmable r delay reference switchover ref_sel cprset vcp vs gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) phase frequency detector lock detect charge pump pll reference hold 0 1 divide by 1, 2, 3, 4, 5, or 6 zero delay block from channel divider 0 optional refin 07219-064 figure 39 . pll functional bl ock diagram the ad9522 inclu des an on - chip pll with an on - chip vco. the pll blocks can be used either with the on - chip vco to create a complete phase - locked loop or with an external vco or vcxo. the pll requires an external loop filter, which usually consists of a small number of cap acitors and resistors. the configuration and components of the loop filter help to establish the loop bandwidth and stability of the operating pll. the ad9522 pll is useful for generating clock frequencies from a supplied reference frequency. this includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution. in addition, th e pll can be use d to clean up jitter and phase noise on a noisy reference. the exact choice of pll parameters and loop dynamics is application specific. the flexibility and depth of the ad9522 p ll allow the part to be tailored to function in many different applications and signal environments. configuration of the pll the ad9522 allows flexible confi guration of the pll, accom m odating various reference frequencies, pfd comparison frequencies, vco frequencies, internal or external vco/vcxo, and loop dynamics. this is accomplished by the various settings for the r divider, the n divider, the pfd polarity (only applicable to external vco/vcxo), the a ntibacklash pulse width, the charge pump current, the selection of internal vco or external vco/ vcxo, and the loop bandwidth. these are managed through programmable register settings (see table 49 and table 53) and by the design of the external loop filter. successful pll operation and satisfactory pll loop performance are highly depend e nt upon proper conf iguration of the pll settings , and t he design of the external loop filter is crucial to the proper operation of the pll. adisimclk ? is a free program that can help with the design and exploration of the capabili ties and features of the ad9522 , including the design of the pll loop filter. the ug - 077 is the ad9522 evaluation software user guide that allows users to easily set the correct register values when the desired configuration is determined. both are available at www.analog.com/clocks . phase frequency detector (pfd) the pfd take s inputs from the r divider and the n divider and produces an output proportional to the phase and frequency difference between them. the pfd includes a programmable delay element that controls the width of the a ntibacklash pulse. this pulse ensures that t here is no dead zone in the pfd transfer function and minimizes phase noise and referen ce spurs. the a ntibacklash pulse width is set by register 0x 0 17[ 1:0 ] . an important limit to keep in mind is the maximum frequency allowed into the pfd. the maximum input frequency in to th e pfd is a function of the a ntibacklash pulse setting , as specified in the phase/frequency detector (pfd) parameter in table 2 . charge pump (cp) the charge pump is controlled by the pfd. the pfd monitors the phase and frequency relationship between its two inputs and tells the cp to pump up or pump down to charge or discharge the integrating node (part of the loop filter). the integrated and filtered cp current is transformed into a voltage that drives the tuning node of the internal vco through the lf pin (or the tunin g pin of an external vco) to move the vco frequency up or down. the cp can be set (register 0x010[3:2]) for high impedance (allows holdover operation), for normal operation (attempt s to lock the pll loop), for pump - up, or for pump - down (test modes). the cp current is programmable in eight steps from (nominally) 0.6 ma to 4.8 ma. the exact value of the cp current lsb is set by the cprset resistor and is calculated using the following equation: cprset i cp 06 . 3 = rev. a | page 35 of 84
ad9522- 0 data sheet on - chip vco the ad9522 includes an on - chip vco covering the fre quency range shown in table 2 . the calibration procedure ensures that the vco operating voltage is centered for the desired vco frequency. the vco must be calibrated when the vco loop is first set up, as well as any time the nominal vco frequency changes. however, once the vco is calibrated, the vco has sufficient operating range to stay locked over temperature and voltage extremes without needing additional calibration. see the vco calibration section for additional information. to tune over the wide range of frequencies covered by this vco, tuning ranges are used. the calibration procedure selects the correct range for the desired vco frequency. see the vco calibration section for additional information. the on - chip vco is powered by an on - chip, low dropout (ldo), linear voltage regulator. the ldo provides some isolation of the vco from variations in the power supply voltage level. the bypass pin must be connected to ground by a 220 nf capacitor to ensure stability. this ldo employs the same technology used in the anycap? line of regulators from analog devices, inc., making it insensitive to the type of capacitor used. driving an external load from the bypass pin is not supported. when using an external vco/vcxo, leave the bypass and lf pins floating. this configuration is shown in figure 41. pll external loop filter when using the internal vco, the extern al loop filter must be referenced to the bypass pin for optimal noise and spurious performance. an example of an external loop filter for a pll that uses the internal vco is shown in figure 40 . a loop filter must be calculated for each desired pll configuration. the values of the components depend upon the vco frequency, the k vco , the pfd frequency, the cp current, the desired loop bandwidth, and the desired phase margin. the loop filter affects the phase noise, t he loop settling time, and the loop stability. a basic knowledge of pll theory is helpful for understanding loop filter design. the adisimclk can help with the calculation of a loop filter acc ording to the application requirements. when using an external vco, the external loop filter must be referenced to ground. an example of an external loop filter for a pll using an external vco is shown in figure 41. 07219-065 lf 31pf vco charge pum p c p by p ass c1 c2 c3 r1 r2 c b p = 220nf ad9522 figure 40 . example of external loop filter for a pll using the internal vco 07219-265 clk/clk external vco/vcxo charge pump cp c1 c2 c3 r1 r2 ad9522 figure 41 . example of external loop filter for a pll using an external vco figure 42 and figure 43 show the typical pll loop filters used to generate the plots in figure 30 and figure 31 , respectively. c1 62pf c3 33pf c2 240nf c12 220nf by p ass ca p aci t or for ldo r1 820? r2 390? lf c p by p ass 07219-334 figure 42 . typical pll loop filter used for clock generation c1 1.5nf c3 2.2nf c2 4.7f c12 220nf by p ass ca p aci t or for ldo r1 2.1k? r2 3k? lf c p by p ass 07219-335 figure 43 . typical pll loop filter used for clock cleanup pll reference inputs the ad9522 features a flexible pll reference input circuit that allows a fully differential input, two separate single - ended inputs , or a 16.62 mhz to 33.33 mhz cryst al oscillator with an on - chip maintaining amplifier. an optional reference clock doubler can be used to double the pll reference frequency. the input frequency range for the reference inputs is specified in table 2 . both the differential and the single - ended inputs are self - biased, allowing for easy ac coupling of input signals. either a differential or a single - ended reference must be specifically enabled. all pll reference inputs are off by default. the differe ntial input and the single - ended inputs share two pins, refin (ref1) and refin (ref2). the desired reference input type is selected and controlled by register 0x01c (see table 49 and table 53). when the differential reference input is selected, the self - bias level of the two sides is offset slightly (~100 mv, see table 2 ) to prevent chattering of the input buffer when the reference is slow or missing . this increases the voltage swing that is required of the driver and overcomes the offset. the differential reference input can be driven by either ac - coupled lvds or ac - coupled lvpecl signals. rev. a | page 36 of 84
data sheet ad9522- 0 the single - ended inputs can be driven by either a dc - coupled cmos level signal or an ac - coupled sine wave or square wave. to avoid input buffer chatter when a single - ended, ac - coupled input signal stops toggling, the user can set register 0x018[7] to 1b. this setting shifts the dc offset bias point down 140 mv. to increase isolation and reduce power, each single - ended input can be independently powered down. the differential reference input receiver is powered down when it is not selected or when the pll is powered down. the sing le - ended buffers power down when the pll is powered down or when their respective individual power - down registers are set. when the differential mode is selected, the single - ended inputs are powered down. vs ref1 ref2 refin 150? 150? 10k? 12k? 10k? 10k? refin 85k? vs 85k? vs 07219-066 figure 44 . refin equival ent circuit for non - xtal m ode in differential mode, the reference input pins are internally self - biased so that they can be ac - coupled via capacitors. it is possible to dc couple to these inputs. if the differential refin is driven by a single - ended signal , decouple the unused side ( refin ) via a suitable capacitor to a quiet ground. figure 44 shows the equivalent circuit of refin. crystal mode is nearly identical to differ ential mode. the user enables a mai ntain ing amplifier by setting the e nable xtal osc bit, and putting a series resonant, at fundamental cut crystal across the refin / refin pins. reference switchover the ad9522 supports dual single - ended cmos inputs, as well as a single differential reference input. in the dual single - ended reference mode, the ad9522 supports automatic revertive and manual pll reference clock switching between ref1 (on pin refin) and ref2 (on pin refin ). this feature supports networking and other applications that require redundant references. when used in conjunction with the automatic holdover function, the ad9522 can achieve a worst - case reference input switchover with an output frequency disturbance as low as 10 ppm. the ad9522 features a dc offset option in single - ended mode. this option is designed to eliminate the risk of the reference inputs chattering when they are ac - coupled and the reference clock disappears. when using the reference switchover, the single - ended reference inputs must be dc - coupled cmos levels (with the ad9522 dc offset feature disabled). alternatively, the inputs can be ac - coupled and dc offset feature enabled. k eep in mind, however, that the minimum input amplitude for the reference inputs is g reater when the dc offset is turned on. reference switchover can be performed manually or automatically. manual switchover is performed either through register 0x01c or by using the ref_sel pin. manual switchover requires the presence of a clock on the ref erence input that is being switched to; otherwise, the deglitching feature must be disabled in bit 7 of register 0x01c. the reference switching logic fails if this condition is not met, and the pll does not reacquire. automatic revertive switchover relies on the refmon pin to indicate when ref1 disappears. by programming register 0x01b = 0xf7 and register 0x01c = 0x26, the refmon pin is programmed high when ref1 is invalid, which commands the switch to ref2. when ref1 is valid again, the refmon pin goes low , and the device again locks to ref1. the status pin can also be used for this function, and ref2 can be used as the preferred reference. a switchover deglitch feature ensures that the pll does not receive rising edges that are far out of alignment with t he newly selected reference. for the switchover deglitch feature to work correctly, the presence of a clock is required on the reference input that is being switched to. the deglitching feature can also be disabled (register 0x01c[7]). automatic nonreverti ve switching is not supported. reference divider r the reference inputs are routed to the r eference divider, r . r (a 14- bit counter) can be set t o any value from 0 to 16 , 383 by writing to register 0x 0 11 and register 0x 0 12. ( both r = 0 and r = 1 give divi de - by - 1. ) the output of the r divider goes to one of the pfd inputs to be compared with the vco frequency divided by the n divider . the frequency applied to the pfd must not exceed the maximum allowable frequency, which depends on the a ntibacklash pulse se tting ( s ee table 2 ) . the r divider has its own reset . the r divider can be reset using the shared reset bit of the r, a , and b counters. it can also be reset by a sync operation . vco / vcxo feed back divider n : p, a, b the n d ivider is a combination of a prescaler (p) and two counters, a and b . the total divider value is n = ( p b ) + a where p can be 2, 4, 8, 16, or 32. rev. a | page 37 of 84
ad9522- 0 data sheet prescaler the prescaler of the ad9522 allows for two modes of operation: a fixed divide (fd) mode of 1, 2, or 3, and a dual modulus (dm) mode where the prescaler divides by p and (p + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. the prescaler modes of operation are given in table 53 , register 0x016[2:0]. not all modes are available at all frequencies (see table 2 ). it is common to use a prescaler of 8 for vc frequencies <2400 mhz, and p = 32 is usually used for very large feedback divider values only. when operating the ad9522 in dual modulus mode, p/(p + 1), the equation used to relate the input reference frequency to the vco output frequency is f vco = ( f ref / r ) ( p b + a ) = f ref n / r however, when operating the prescaler in fd mode 1, fd mode 2, or fd mode 3, the a counter is not used (a = 0; the divide is a fixed divide of p = 2, 4, 8, 16, or 32) and the equation simplifies to f vco = ( f ref / r ) ( p b ) = f ref n / r by using combinations of dm and fd modes, the ad9522 can achieve values of n from 1 to 262,175. table 29 shows how a 10 mhz reference input can be locked to any integer multiple of n. note that the same value of n can be derived in different ways, as illustrated by the case of n = 12. the user can choose a fix ed divide mode of p = 2 with b = 6, use the dual modulus mode of 2/3 with a = 0, b = 6, or use the dual modulus mode of 4/5 with a = 0, b = 3. a and b counters the b counter must b e 3 or bypassed, and unlike the r counter, a = 0 is ac tually zero. the b counter must always be greater than or equal to the a counter. the maximum input frequency to the a/b counter is reflected in the maximum prescaler output frequency (~300 mhz) specifie d in table 2 . this is the prescaler input frequency (vco or clk) divided by p. for example, dual modulus p = 8/9 mode is not allowed if the vco frequency is greater than 2400 mhz because the frequency going to the a/b counter is too high. when the ad9522 b counter is bypassed (b = 1), the a counter must be set to zero, and the overall resulting divide is equal to the p rescal e r setting, p. the possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. although manual reset is not normally required, the a/b counters have their own reset bit. alternatively, the a and b counters can be reset using the shared reset bit of the r, a, and b counters. note that these reset bits are not self - clearing. r, a, and b counters: sync pin reset the r, a, and b counters can be reset simultaneously through the sync pi n. this function is control led by register 0x019[7:6] (see table 53 ). the sync pin reset is disabled by default. r and n divider delays both the r and n dividers feature a programmable delay cell. these delays can be enabl ed to allow adjustment of the phase relationship between the pll reference clock and the vco or clk, and are useful for controlling the input/output phase relationship in zero delay mode. each delay is controlled by three bits. the total delay range is abo ut 1 ns. see register 0x019 in table 2 and table 53 . table 29 . how a 10 mhz reference input can be locked to any integer multi ple of n (x= dont care) f ref (mhz) r p a b n f vco (mhz) mode notes 10 1 1 x 1 1 10 fd p = 1, b = 1 (a and b counters are bypassed). 10 1 2 x 1 2 20 fd p = 2, b = 1 (a and b counters are bypassed). 10 1 1 x 3 3 30 fd a counter is bypassed. 10 1 1 x 4 4 40 fd a counter i s bypassed. 10 1 1 x 5 5 50 fd a counter is bypassed. 10 1 2 x 3 6 60 fd a counter is bypassed. 10 1 2 0 3 6 60 dm 10 1 2 1 3 7 70 dm maximum frequency into prescaler in p 2/3 mode is 200 mhz. if n = 7 or n = 11 is desired for prescaler input frequenc y of 200 mhz to 300 mhz, use p = 1 and n = 7, or 11, respectively. 10 1 2 2 3 8 80 dm 10 1 2 1 4 9 90 dm 10 1 8 6 18 150 1500 dm 10 1 8 7 18 151 1510 dm 10 1 16 7 9 151 1510 dm 10 10 32 6 47 151 1510 dm 10 1 8 0 25 200 2000 dm 10 1 16 0 15 240 2400 dm 10 10 32 0 75 2400 2400 dm rev. a | page 38 of 84
data sheet ad9522-0 rev. a | page 39 of 84 digital lock detect (dld) by selecting the proper output through the mux on each pin, the dld function is available at the ld, status, and refmon pins. the digital lock detect circuit indicates a lock when the time difference of the rising edges at the pfd inputs is less than a specified value (the lock threshold). the loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator. the lock detect window timing depends on the value of the cprset resistor, as well as three settings: the digital lock detect window bit (register 0x018[4]), the antibacklash pulse width bit (register 0x017[1:0], see table 2), and the lock detect counter (register 0x018[6:5]). the lock and unlock detection values in table 2 are for the nominal value of cprset = 5.11 k. doubling the cprset value to 10 k doubles the values in table 2. a lock is not indicated until there is a programmable number of consecutive pfd cycles with a time difference less than the lock detect threshold. the lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. for the lock detect to work properly, the period of the pfd frequency must be greater than the unlock threshold. the number of consecutive pfd cycles required for lock is programmable (register 0x018[6:5]). note that it is possible in certain low (<500 hz) loop bandwidth, high phase margin cases that the dld can chatter during acquisition, which can cause the ad9522 to automatically enter and exit holdover. to avoid this problem, it is recommended that the user make provisions for a capacitor to ground on the ld pin so that current source digital lock detect (csdld) mode can be used. analog lock detect (ald) the ad9522 provides an ald function that can be selected for use at the ld pin. there are two operating modes for ald. ? n-channel open-drain lock detect. this signal requires a pull-up resistor to the positive supply, vs. the output is normally high with short, low going pulses. lock is indicated by the minimum duty cycle of the low going pulses. ? p-channel open-drain lock detect. this signal requires a pull-down resistor to gnd. the output is normally low with short, high going pulses. lock is indicated by the minimum duty cycle of the high going pulses. the analog lock detect function requires an rc filter to provide a logic level indicating lock/unlock. the adisimclk tool can be used to help the user select the right passive component values for ald to ensure its correct operation. ad9522 ald ld r1 c v out r2 v s = 3.3v 07219-067 figure 45. example of analog lock detect filter using n-channel open-drain driver current source digital lock detect (csdld) during the pll locking sequence, it is normal for the dld signal to toggle a number of times before remaining steady. there may be applications where it is necessary to have dld asserted without chattering and only after the pll is solidly locked. this is possible by using the current source digital lock detect function. the current source lock detect provides a current of 110 a when dld is true and shorts to ground when dld is false. if a capacitor is connected to the ld pin, it charges at a rate determined by the current source during the dld true time but is discharged nearly instantly when dld is false. by monitoring the voltage at the ld pin (top of the capacitor), ld = high happens only after the dld is true for a sufficiently long time. any momentary dld false resets the charging. by selecting a properly sized capacitor, it is possible to delay a lock detect indication until the pll is stably locked and the lock detect does not chatter. to use current source digital lock detect, do the following: ? place a capacitor to ground on the ld pin ? set register 0x01a[5:0] = 0x04 ? enable the ld pin comparator (register 0x01d[3] = 1) the ld pin comparator senses the voltage on the ld pin, and the comparator output can be made available at the refmon pin control (register 0x01b[4:0]) or the status pin control (register 0x017[7:2]). the internal ld pin comparator trip point and hysteresis are given in table 17. the voltage on the capacitor can also be sensed by an external comparator connected to the ld pin. in this case, enabling the on-board ld pin comparator is not necessary. the user can asynchronously enable individual clock outputs only when csdld is high. to enable this feature, set the appropriate bits in the enable output on the csdld registers (register 0x0fc and register 0x0fd). ad9522 ld refmon or status c v out 110a dld ld pin comparator 07219-068 figure 46. current source digital lock detect
ad9522- 0 data sheet external vcxo/vco clock input (clk/ clk ) this differential input is used to drive the ad9522 clock distribution section. this input can receive up to 2.4 ghz. the pin s are internally self - biased , and the input signal must be ac - coupled via capacito rs. vs clock input stage clk clk 5k? 5k? 2.5k? 2.5k? 07219-032 figure 47 . clk equivalent input circuit the self - biased clk/ clk input can be used either as a distribution only input (with the pll off) or as a feedback input for an external vco/vcxo using the internal pl l when the internal vco is not used. these inputs are also used as a feedback path for the external zero delay mode. holdover the ad9522 pll has a holdover function. holdover mode allows the vco to maintain a relatively constant frequency even though there is no reference clock. this function is useful when the pll reference clock is lost. holdover is implemented by placing the charge pump in a high impedance state. without this function, t he charge pump is placed into a constant pump - up or pump - down state, resulting in a significant vco frequency shift. because the charge pump is placed in a high impe dance state, any leakage that occurs at the charge pump output or the vco tuning node causes a drift of the vco frequency. this drift can be mitigated by using a loop filter that contains a large capacit ive component because this drift is limited by the cu rrent leakage induced slew rate (i leak /c) of the vco control voltage. both a manual holdover mode, using the sync pin, and an automatic holdover mode are provided. to use either function, the holdover function must be enabled (register 0 x01d[0]). external/ manual holdover mode a manual holdover mo de can be enabled that allows the user to place the charge pump into a high impedance state when the sync pin is asserted low . t his operation is edge sensitive, not level sensit ive. the charge pump enters a high impedance state immediately. to take the charge pump out of a high impedance state , take the sync pin high . the charge pump then leave s the high impedance state synchronous ly with the next pfd rising edg e from the reference clock. this prevents extraneous charge pump events from occurring during the time between sync going high and the next pfd event. this also means that the charge pump stay s in a high impedance state if there is no ref erence clock present. t he b counter (in the n divider) is reset synchronous ly with the charge pump leaving the high impedance state on the reference path pfd event. this helps align the edges out of the r and n dividers for faster settling of the pll. beca use the prescaler is not reset, this feature works best when the b and r numbers are close because this result s i n a smaller phase difference for the loop to settle out. when using this mode, set the channel dividers to ignore the sync pi n (at least after an initial sync event). if the dividers are not set to ignore the sync pin, any time sync is taken low to put the part into holdover, the distribution outputs turn off. the channel div ider ignore sync function is found in register 0x191[6], register 0x194[6], register 0x197[6], and register 0x19a[6] for channel divider 0, channel divider 1, channel divider 2, and channel divider 3, respectively. automatic/internal holdover mode when ena bled, this function automatically puts the charge pump into a high impedance state when the loop loses lock. the assumption is that the only reason the loop lose s lock is due to the pll losing the r eference clock ; t herefore, the holdover function puts the charge pump into a high impedance state to maintain the vco frequency as close as possible to the original frequency before the r eference clock disappeared. a flow chart of the automatic / internal hold over function operation is shown in figure 48. rev. a | page 40 of 84
data sheet ad9522-0 rev. a | page 41 of 84 no no no no yes yes yes yes pll enabled dld == low was ld pin == high when dld went low? high impedance charge pump reference edge at pfd? release charge pump high impedance dld == high loop out of lock. digital lock detect signal goes low when the loop leaves lock as determined by the phase difference at the input of the pfd. analog lock detect pin indicates lock was previously achieved. (0x01d[3] = 1; use ld pin voltage with holdover. 0x01d[3] = 0; ignore ld pin voltage, treat ld pin as always high.) charge pump is made high impedance. pll counters continue operating normally. charge pump remains high impedance until the reference returns. take charge pump out of high impedance. pll can now resettle. wait for dld to go high. this takes 5 to 255 cycles (programming of the dld delay counter) with the reference and feedback clocks inside the lock window at the pfd. this ensures that the holdover function waits for the pll to settle and lock before the holdover function can be retriggered. 0 7219-069 figure 48. flowchart of automatic/internal holdover mode the holdover function senses the logic level of the ld pin as a condition to enter holdover. the signal at ld can be from the dld, ald, or current source ld (csdld) mode. it is possible to disable the ld comparator (register 0x01d[3]), which causes the holdover function to always sense ld as high. if dld is used, it is possible for the dld signal to chatter while the pll is reacquiring lock. the holdover function may retrigger, thereby preventing the holdover mode from terminating. use of the current source lock detect mode is recommended to avoid this situation (see the current source digital lock detect (csdld) section). when in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. as in the external holdover mode, the b counter (in the n divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path pfd event. this helps align the edges out of the r and n dividers for faster settling of the pll and reduces frequency errors during settling. because the prescaler is not reset, this feature works best when the b and r numbers are close because this results in a smaller phase difference for the loop to settle out. after leaving holdover, the loop then reacquires lock and the ld pin must go high (if register 0x01d[3] = 1) before it can reenter holdover.
ad9522- 0 data sheet the holdover function always responds to the state of the currently selected reference (register 0x01c). if the loop loses lock during a reference switchover (see the reference switchover section), holdover is triggered briefly until the next reference clock edge at the pfd. the following registers affect the automatic / internal holdover function: ? register 0x 0 18[ 6:5 ] l ock detect c ounter. this changes how many consecutive pfd cycles with edges inside the lock d etect window are required for the dld indicator to indicate lock. this impact s the time required before the ld pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged. ? register 0x 0 18[ 3 ] dis able digital lock detect . this bit must be set to 0 to enable the dld circuit. internal/ a utomatic holdover does not operate correctly without the dld function enabled. ? register 0x 0 1a [ 5:0 ] l ock detect pin control . set this to 000100b to put it in the curren t source lock detect mode if using the ld pin comparator. load the ld pin with a cap acitor of an appropriate value . ? register 0x 0 1d [ 3 ] ld pin comparator enable . 1 = e nable; 0 = d isable. when disabled, the holdover function always senses the ld pin as high . ? register 0x 0 1d [ 1 ] external holdover control . ? register 0x 0 1d [ 0 ] h oldover enable. if holdover is disabled, both external and automatic/internal holdover are disabled . in the following example, automatic holdover is configured with ? automatic reference switc hover , prefer ref1 . ? digital lock detect: five pfd cycles, h igh range window . ? automatic holdover using the ld pin comparator . t he following registers are set (in addition to the normal pll registers): ? register 0x 0 18[ 6:5 ] = 00b ; l ock detect co unter = five cy cles . ? register 0x 0 18[ 4 ] = 0 b ; digital l ock detect w indow = high range . ? register 0x 0 18[ 3 ] = 1 b ; disable dld normal operation . ? register 0x 0 1a [ 5:0 ] = 000100 b ; program ld pin control to current source lock detect mode. ? register 0x 0 1c [ 4 ] = 1 b ; enable a utomatic switchover . ? register 0x 0 1c [ 3 ] = 0b ; p refer ref1 . ? register 0x 0 1c [ 2:1 ] = 11b ; e na ble ref1 and ref2 input buffers . ? register 0x 0 1d [ 3 ] = 1 b ; enable ld pin comparator . ? register 0x 0 1d [ 1 ] = 0 b ; disable external holdover mode and u se automatic / internal holdover mo de . ? register 0x 0 1d [ 0 ] = 1 b ; enable holdover . frequency status monitors the ad9522 contains three frequency status monitors that are used to indicate if the pll reference (or references in the case of single - ended mode) and the external vco/clk input fall below a threshold frequency. note that the vco frequency monitor becomes a clk input frequency monitor if the clk input is selected instead of the internal vco. a diagram showing their location in the pll is shown in figure 49. the pll reference monitors have two threshold frequencies: normal and extended (see table 17 ). the reference frequency monitor thresholds are selected in register 0x01a[6]. vco calibration the ad9522 on - chip vco must be calibrated to ensure proper operation over p rocess and temperature. the vco calibration is controlled by a calibration controller running off a divided refin clock. the calibration requires that the pll be set up properly to lock the pll loop and that the refin clock be present. the refin clock must come from a stable source external to the ad9522 . vco calibration can be performed two ways: automatically at power - up and manually. automatic vco calibration occurs when the eeprom is set to automatically load the preprogrammed values in the eeprom and then automatically calibrate the vc o. a valid reference must be provided at power - up in order for the automatic calibration to complete. if this is not the case, the user must calibrate the vco manually. rev. a | page 42 of 84
data sheet ad9522- 0 programmable n delay clk clk ref1 ref2 buf status status r divider clock doubler vco status programmable r delay reference switchover ref_sel cprset vcp vs gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider bypass lf low dropout regulator (ldo) phase frequency detector lock detect charge pump pll reference hold 0 1 divide by 1, 2, 3, 4, 5, or 6 zero delay block from channel divider 0 refin optional refin 07219-070 figure 49 . reference and vco /clk frequency status moni tors during the first initialization after a power - up or a reset of the ad9522 , a manual vco calibration sequence is initiated by setting register 0x018[0] = 1b. this can be done as part of the initial setup before executing update registers (register 0x232[0] = 1b). subsequent to the ini tial setup, a vco calibration sequence is initiated by resetting register 0x018[0] = 0b, executing an update registers operation, setting register 0x018[0] = 1b, and executing another update registers operation. a readback bit ( register 0x01f[6]) indicates when a vco calibration is finished by returning a logic true (that is, 1b). the sequence of operation s for the vco calibration follows : 1. program the pll registers to the proper values for the pll loop. note that the vco divider ( register 0x1e0[2:0]) must not be set to static during vco calibration. 2. for the initial setting of the registers after a power - up or reset, i nitiate a vco cal ibration by setting register 0x 0 18[ 0 ] = 1 b . subsequently, whenever a calibration is desired, set register 0x 0 18[ 0 ] = 0b, upd ate re gisters and set register 0x 0 18[ 0 ] = 1b, update registers. 3. a sync operation is initiated internally, causing the outputs to go to a static s tate determined by normal sync function operation . 4. vco is calibrate d to the desired setting for the requested vco frequency. 5. internal ly , the sync signal is released, allowing outputs to continue clocking . 6. the pll loop is closed . 7. p ll locks . a sync is exec uted during the vco calibration ; t herefore , the outputs of the ad9522 are held static during the calibration , which prevents unwanted frequencies from being produced. however, at the end of a vco calibration, the outputs may resume clocking before the pll loop is completely settled. the vco calibration clock di vider is set as shown in table 53 ( register 0x 0 18[ 2:1 ] ) . the calibration div ider divides the pfd frequency (reference frequency divided by r) down to the calibration clock. the calibration occurs at the pfd frequency divided by the cal ibration divider setting. low er vco calibration clock frequencies result in longer times for a calibration to be complete d . the vco calibration clock frequency is given by f cal_clock = f refin / ( r cal_div ) w here: f refin is the frequency of the refin signal . r is the value of the r counter . cal_div is the division set f or the vco calibration divider ( register 0x 0 18[ 2:1 ] ) . c hoose a calibration divider such that the calibration frequency is less than 6.25 mhz. table 30 shows th e appropriate value for the calibration divider. table 30 . vco calibration divider values for different phase detector frequencies pfd rate (mhz) recommended vco cal ibration divider <12 any 12 to 25 4, 8, 16 25 to 50 8, 16 50 to 100 16 the vco calibration takes 4400 calibration cl ock cycles. therefore, the vco calibration time in pll reference clock cycles is given by time to calibrate vco = 4400 r cal_div pll reference clock cycles rev. a | page 43 of 84
ad9522- 0 data sheet table 31 . example time to complete a vco calibration with different f re fin frequencies f refin (mhz) r divider pfd time to calibrate vco 100 1 100 mhz 88 s 10 10 1 mhz 8.8 ms 10 100 100 khz 88 ms the ad9522 does not automatically recalibrate its vco when the pll settings change . this feature allows for flexibility in deciding what order to program the registers and when to initiate a calibration, instead of having it happen every time certain pll registers have their values change. for example, this feature allows for the vco frequency to be changed by small amounts without having an automatic calibrat ion occur each time; however, do this with caution and only when the vco control voltage does not exceed the nominal best performance limits. for example, a few 100 khz steps are fine, but a few mhz may not be. in addition, because the calibration procedu re results in rapid changes in the vco frequency, the distribution section is automatically placed in sync until the calibration is finished. therefore, expect this temporary loss of outputs. initiate a vco calibration in the following conditions: ? after ch anging any of the pll r, p, b , and a divider settings or after a change in the pll reference c lock frequency. this, in effect, means any time a pll register or reference clock is changed such that a different vco frequency result s. ? when system calibration is desired . the vco is designed to operate properly over extremes of temperature even when it is first calibrated at the opposite extreme. however, a vco calibration can be initia ted at any time , if desired. rev. a | page 44 of 84
data sheet ad9522-0 rev. a | page 45 of 84 divide by 1, 2, 3, 4, 5, or 6 lf clk/clk r divider r delay n divider n delay pfd cp loop filter mux1 reg 0x01e[1] = 1 01 refin/ refin mux3 reg 0x01e[0] zero delay internal feedback path external feedback path zero delay feedback clock channel divider 0 channel divider 1 channel divider 2 channel divider 3 out0 to out2 out3 to out5 out6 to out8 out9 to out11 ad9522 0 7219-053 figure 50. zero delay function zero delay operation zero delay operation aligns the phase of the output clocks with the phase of the external pll reference input. there are two zero delay modes on the ad9522 : internal and external. note that when the ad9522 is configured in zero delay mode with output frequencies that are integer multiples of each other (for example, 50 mhz, 100 mhz, 200 mhz), it is critical to use the lowest output frequency in the feedback path of the pll. otherwise, the input/output phase relationship of the lowest frequency is not guaranteed. internal zero delay mode the internal zero delay function of the ad9522 is achieved by feeding the output of channel divider 0 back to the pll n divider. in figure 50, the change in signal routing for internal zero delay mode is shown in blue. set register 0x01e[2:1] = 01b to select internal zero delay mode. in the default internal zero delay mode, the output of channel divider 0 is routed back to the pll (n divider) through mux3 and mux1 (feedback path shown in blue in figure 50). the pll synchronizes the phase/edge of the output of channel divider 0 with the phase/edge of the reference input. external zero delay mode must be used if channel divider 1, channel divider 2, or channel divider 3 is used for zero delay feedback. this is accomplished by changing the value in register 0x01e[4:3]. because the channel dividers are synchronized to each other, the outputs of the channel divider are synchronous with the reference input. both the r delay and the n delay inside the pll can be programmed to compensate for the propagation delay from the output drivers and pll components to minimize the phase offset between the clock output and the reference input to achieve zero delay. external zero delay mode the external zero delay function of the ad9522 is achieved by feeding one clock output back to the clk input and ultimately back to the pll n divider. in figure 50, the change in signal routing for external zero delay mode is shown in red. set register 0x01e[2:1] = 11b to select the external zero delay mode. in external zero delay mode, one of the twelve output clocks (out0 to out11) can be routed back to the pll (n divider) through the clk/ clk pins and through mux3 and mux1. this feedback path is shown in red in figure 50. the user must specify which channel divider is used for external zero delay mode in order for vco calibration to work correctly. channel divider 0 is the default. channel divider 1, channel divider 2, or channel divider 3 can be sele cted for zero delay feedback by changing the value in register 0x01e[4:3]. the pll synchronizes the phase/edge of the feedback output clock with the phase/edge of the reference input. because the channel dividers are synchronized to each other, the clock outputs are synchronous with the reference input. both the r delay and the n delay inside the pll can be programmed to compensate for the propagation delay from the pll components to minimize the phase offset between the feedback clock and the reference input.
ad9522-0 data sheet rev. a | page 46 of 84 mode 0 (internal vco mode) clk clk lf 01 divide by 1, 2, 3, 4, 5, or 6 clock distri- bution pll distribution clock mode 1 (clock distribution mode) distribution clock mode 2 (hf clock distribution mode) clk clk lf 01 divide by 1, 2, 3, 4, 5, or 6 clock distri- bution pll clk clk lf 01 divide by 1, 2, 3, 4, 5, or 6 clock distri- bution pll distribution clock 07219-054 figure 51. simplified diagram of the three clock distribution operation modes clock distribution a clock channel consists of three lvds clock outputs or six cmos clock outputs that share a common divider. a clock output consists of the drivers that connect to the output pins. the clock outputs have either lvds or cmos at the pins. the ad9522 has four clock channels. each channel has its own programmable divider that divides the clock frequency applied to its input. the channel dividers can divide by any integer from 1 to 32. divide by 1 is achieved by setting the divider n bypass bit (where n = 0 through 3) in the appropriate channel divider register. the ad9522 features a vco divider that divides the vco output by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers. the vco divider has two purposes. the first is to limit the max- imum input frequency of the channel dividers to 1.6 ghz. see the vco divider section for discussion of special cases where the channel divider maximum input frequency is >1.6 ghz. the other is to allow the ad9522 to generate lower output frequencies than is normally possible with only a simple post divider. external clock signals connected to the clk input can also use the vco divider. the channel dividers allow for a selection of various duty cycles, depending on the currently set division. that is, for any specific division, d, the output of the divider can be set to high for n + 1 input clock cycles and low for m + 1 input clock cycles (where d = n + m + 2). for example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide-by-5 can be high for three divider input cycles and low for two cycles. other combinations are also possible. the channel dividers include a duty-cycle correction function that can be disabled. in contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. however, this requires that the division be set by m = n + 1. note that the duty cycle correction feature is not available when the vco divider is set to 1. in addition, the channel dividers allow a coarse phase offset or delay to be set. depending on the division selected, the output can be delayed by up to 15 input clock cycles. for example, if the frequency at the input of the channel divider is 1 ghz, the channel divider output can be delayed by up to 15 ns. the divider outputs can also be set to start high or to start low. operation modes there are three clock distribution operating modes, and these are shown in figure 51. one of these modes uses the internal vco, whereas the other two modes bypass the internal vco and use the signal provided on the clk/ clk pins. in mode 0 (internal vco mode), there are two signal paths available. in the first path, the vco signal is sent to the vco divider and then to the individual channel dividers. in the second path, the user bypasses the vco and channel dividers and sends the vco signal directly to the drivers. when clk is selected as the source, it is not necessary to use the vco divider if the clk frequency is less than the maximum channel divider input frequency (1600 mhz); otherwise, the vco divider must be used to reduce the frequency going to the channel dividers. table 32 shows how the vco, clk, and vco divider are selected. register 0x1e1[1:0] selects the channel divider source and determines whether the vco divider is used. it is not possible to select the vco without using the vco divider. table 32. operation modes 0x1e1 mode [1] [0] channel divider source vco divider 2 0 0 clk used 1 0 1 clk not used 0 1 0 vco used 1 1 not allowed not allowed
data sheet ad9522- 0 clock fre quency divisio n the total frequency division is a combination of the vco divider (when used) and the channel divider. when the vco divider is used, the total division from the vco or clk to the output is the product of the vco divider ( 1, 2, 3, 4, 5, and 6 ) and the division of the channel divider. table 33 indicate s how the frequency division for a channel is set . table 33 . frequenc y d ivision clk or vco selected vco divider setting 1 chann el divider setting resulting frequency division clk or vco input 1 to 6 2 to 32 (1 to 6) (2 to 32) clk or vco input 2 to 6 bypass (2 to 6) (1) clk or vco input 1 bypass output static (illegal state) clk(internal vco off ) vco divider bypassed bypa ss 1 clk (internal vco off ) vco divider bypassed 2 to 32 2 to 32 1 the bypass vco divider ( register 0x1e1 [ 0 ] = 1) is not the same as vco d ivider = 1 . the channel divider s feeding the output drivers contain one 2 - to - 32 frequency divider. this divider pr ovides for division - by - 1 to division - by - 32. divi sion - by - 1 is accomplished by bypassing the divider. the dividers also provide for a programmable duty cycle , with optional duty - cycle corr ection when the divide ratio is odd. a p hase offset or delay in increm ents of the input clock cycle is select able . the channel dividers operate with a signal at their inputs up to 1600 mhz. the features and settings of the dividers are selected by programming the appropriate setup and control registers (see table 49 through table 60). vco d ivider the vco divider provides frequency division between the internal vco or the external clk input and the clock distribution channel dividers. the vco divider can be set to divide by 1, 2, 3, 4, 5, or 6 (s ee table 56, register 0x1e0 [ 2:0 ] ) . however, when the vco divider is set to 1, none of the channel output dividers can be bypassed. the vco divider can also be set to static, which is useful for applications where the only desired output frequency is the vco frequency. making the vco divider static increases the wide band spurious - free dynamic range (sfdr). if the vco divider is static during vco calibration, th ere is no output signal. therefore, it is important to calibrate the vco with the vco divider set to a nonstatic value during vco calibration, and then set the vco divider to static when vco calibration is complete. the recommended alternative to achieving the same sfdr performance is to set the vco divider to 1. this allows the user to program the eeprom with the desired values and does not require further action after the vco calibration is complete. channel divider s a channel divider drives each group of three lvds outputs . there are four channel dividers (0, 1, 2, and 3 ) drivi ng 12 lvds outputs (out0 to out11 ). table 34 gives the register locations used for setting the division and other functions of these divi ders . the division is set by the values of m and n . t he divider can be bypassed ( equivalent to divide - by - 1 , divider circuit is powered down ) by setting the bypass bit. the duty - cycle correction can be enabled or disabled according to the setting of the dis able div ider dcc bit s. table 34 . setting d x for the output dividers divider low cycles m high cycles n bypass disable div dcc 0 0x190 [ 7:4 ] 0x190 [ 3:0 ] 0x191 [ 7 ] 0x192 [ 0 ] 1 0x193 [ 7:4 ] 0x193 [ 3:0 ] 0x194 [ 7 ] 0x195 [ 0 ] 2 0x196 [ 7:4 ] 0x196 [ 3:0 ] 0x197 [ 7 ] 0x198 [ 0 ] 3 0x199 [ 7:4 ] 0x199 [ 3:0 ] 0x19a [ 7 ] 0x19b [ 0 ] channel divider maximum frequency the maximum frequency at which all features of the channel divider are guaranteed to work is 1.6 ghz; this is the number that appears elsewhere in the dat a sheet. however, if the divide - by - 3 and divide - by - 17 settings are avoided, the maximum channel divider input frequency is 2 ghz. c hannel frequency d ivision (0, 1, 2, and 3 ) for each channel (where the channel number x is 0, 1, 2 , or 3 ) , the frequency divi sion, d x , is set by the values of m and n ( four bits each, representing d ecimal 0 to d ecimal 15) , where number of low cy cles = m + 1 number of high cycle s = n + 1 the high and low cycles are cycles of the clock signal currently routed to the input of the channel dividers (vco divider out or clk). when a divider is bypassed, d x = 1 . otherwise, d x = (n + 1) + (m + 1) = n + m + 2 . this allows each channel divider to divide by any integer from 2 to 32. duty cycle and duty - cycle correction the duty cycle of th e clock signal at the output of a channel is a result of some or all of the following conditions: ? t he m and n values for the channel ? dcc enabled/disabled ? vco divider enabled/bypassed ? the clk input duty cycle ( n ote that t he internal vco has a 50% duty cycle ) the dcc function is enabled by default for each channel divider. however, the dcc function can be disabled individually for each channel divider by setting the disable divider dcc bit for that channel. rev. a | page 47 of 84
ad9522- 0 data sheet certain m and n values for a channel divider result in a non - 50% duty cycle. a non - 50% duty cycle can also result with an even division, if m n. the duty - cycle correction function automatically corrects non - 50% duty cycles at the channel divider output to 50% duty cycle. note that the duty - cycle correction feature is not available when the vco divider is set to 1. duty - cycle correction require s the following channel divider conditions: ? an even division must be set as m = n . ? an odd division must be set as m = n + 1 . ? the vco divider is not set to 1. when not bypassed or corrected by the dcc function, the duty cycle of each channel divider output is the numerical value of (n + 1)/(n + m + 2) expressed as a percent . t he duty cycle at the output of the channel divider for various configurations is s hown in table 35 to table 38. table 35 . channel divider output duty c ycle with vco d ivider 1 , input duty cycle i s 50% vco d ivider d x output duty cy cle n + m + 2 disable div dcc = 1 disable div dcc = 0 even channel d ivider bypassed 50% 50% odd = 3 channel d ivider bypassed 33.3% 50% odd = 5 channel d ivider bypassed 40% 50% even, o dd even (n + 1)/ (n + m + 2) 50% , r equires m = n even, o dd odd (n + 1)/ (n + m + 2) 50% , r equires m = n + 1 table 36 . channel divider ou tput duty c ycle with vco divider 1 , input duty cycle is x% vco d ivider d x output duty cy cle n + m + 2 disable div dcc = 1 disable div dcc = 0 even channel d ivider bypassed 50% 50% odd = 3 channel d i vider bypassed 33.3% (1 + x%)/3 odd = 5 channel d ivider bypassed 40% (2 + x%)/5 even even (n + 1)/ (n + m + 2) 50% , r equires m = n even odd (n + 1)/ (n + m + 2) 50% , r equires m = n + 1 odd = 3 even (n + 1)/ (n + m + 2) 50% , r eq u ires m = n odd = 3 odd (n + 1)/ (n + m + 2) (3n + 4 + x%)/(6n + 9) , r equires m = n + 1 vco d ivider d x output duty cy cle n + m + 2 disable div dcc = 1 disable div dcc = 0 odd = 5 even (n + 1)/ (n + m + 2) 50% , r equires m = n odd = 5 odd (n + 1)/ (n + m + 2) (5n + 7 + x%)/(10n + 15) , r equires m = n + 1 table 37 . channel divider output duty cycle when the vco divider i s enabled and set to 1 input clock duty cycle d x output duty cycle n + m + 2 disable div dcc = 1 disable div dcc = 0 any even (n + 1)/ (m + n + 2) 50%, requires m = n 50% odd (n + 1)/ (m + n + 2) (n + 1)/(m + n + 2) x% odd (n + 1)/ (m + n + 2) (n + 1 + x%)/(2 n + 3), requires m = n + 1 note tha t the channel divider must be enabled when the vco divider = 1. table 38 . channel divider output duty c ycle w hen the vco divider is bypassed input clock duty c ycle d x output duty cycle n + m + 2 disable div dcc = 1 disable div dcc = 0 any chan n el d ivider bypassed same as input duty cycle same as input duty cycle any even (n + 1)/ (m + n + 2) 50% , r equires m = n 50% odd (n + 1)/ (m + n + 2) 50% , r equires m = n + 1 x% odd (n + 1)/ (m + n + 2) (n + 1 + x%)/(2 n + 3) , r equires m = n + 1 th e internal vco has a duty cycle of 50%. therefore, when the vco divider equals 1 , the duty cycle is 50% . if the clk input is routed direct ly to the output, the duty cycle of the output is the same as the clk input. phase o ffset or coarse time de lay each channel divider allows for a phase offset , or a coarse time delay, to be programmed by setting register bits ( s ee table 39) . th ese setting s determine the number of cycles ( successive rising edges) of the channel divider input frequency by which to offset , or delay , the rising edge of the output of the divider . this delay is with respect to a non delayed output (that is, with a phase offset of zero ) . the amount of the delay is set by five bits loaded int o the phase offset (po) reg ister plus the start high (sh) bit for each channel divider . when the start high bit is set , t he delay is also affected by the number of low cycles (m) programmed for the divider. it is necessary to use the sync function to make phase offsets effective ( s e e th e synchronizing the outputs function section) . rev. a | page 48 of 84
data sheet ad9522-0 rev. a | page 49 of 84 table 39. setting phase offset and division divider start high (sh) phase offset (po) low cycles m high cycles n 0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0] 1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0] 2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0] 3 0x19a[4] 0x19a[3:0] 0x199[7:4] 0x199[3:0] let t = delay (in seconds). c = delay (in cycles of clock signal at input to d x ). t x = period of the clock signal at the input of the divider, d x (in seconds). = 16 sh[4] + 8 po[3] + 4 po[2] + 2 po[1] + 1 po[0] the channel divide by is set as n = high cycles and m = low cycles. case 1 for 15, t = t x c = t / t x = case 2 for 16, t = ( ? 16 + m + 1) t x c = t / t x by giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. figure 52 shows the results of setting such a coarse offset between outputs. 0 1 2 3 4 5 6 7 8 9 101112131415 tx divider 0 divider 1 divider 2 channel divider input sh = 0 po = 0 sh = 0 po = 1 sh = 0 po = 2 1 tx 2 tx channel divider outputs div = 4, duty = 50% 07219-071 figure 52. effect of coarse phase offset (or delay) synchronizing the outputs sync function the ad9522 clock outputs can be synchronized to each other. outputs can be individually excluded from synchronization. synchronization consists of setting the nonexcluded outputs to a preset set of static conditions. these conditions include the divider ratio and phase offsets for a given channel divider. this allows the user to specify different divide ratios and phase offsets for each of the four channel dividers. releasing the sync pin allows the outputs to continue clocking with the preset conditions applied. synchronization of the outputs is executed in the following ways: ? the sync pin is forced low and then released (manual sync). ? by setting and then resetting any one of the following three bits: the soft sync bit (register 0x230[0]), the soft reset bit (register 0x000[5] [mirrored]), and the power-down distribution reference bit (register 0x230[1]). ? synchronization of the outputs can be executed as part of the chip power-up sequence. ? the reset pin is forced low and then released (chip reset). ? the pd pin is forced low and then released (chip power-down). ? whenever a vco calibration is completed, an internal sync signal is automatically asserted at the beginning and released upon the completion of a vco calibration. the most common way to execute the sync function is to use the sync pin to perform a manual synchronization of the outputs. this requires a low going signal on the sync pin, which is held low and then released when synchronization is desired. the timing of the sync operation is shown in figure 53 (using the vco divider) and in figure 54 (the vco divider is not used). there is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the sync signal with respect to the clock edges inside the ad9522. the pipeline delay from the sync rising edge to the beginning of the synchronized output clocking is between 14 cycles and 15 cycles of clock at the channel divider input, plus one cycle of the vco divider input (see figure 53) or one cycle of the channel divider input (see figure 54), depending on whether the vco divider is used. cycles are counted from the rising edge of the signal. in addition, there is an additional 1.2 ns (typical) delay from the sync signal to the internal synchronization logic, as well as the propagation delay of the output driver. the driver propagation delay is approximately 100 ps for the lvds driver and approximately 1.5 ns for the cmos driver. another common way to execute the sync function is by setting and resetting the soft sync bit at register 0x230[0]. both setting and resetting of the soft sync bit require an update all registers (register 0x232[0] = 1b) operation to take effect. a sync operation brings all outputs that are not excluded (by the ignore sync bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. the preset condition takes into account the settings in each of the channels start high bit and its phase offset. these settings govern both the static state of each output when the sync operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the sync operation. a sync operation must take place for the phase offsets setting to take effect. the ad9522 differential lvds outputs are four groups of three, sharing a channel divider per triplet. in the case of cmos, each lvds differential pair can be configured as two single-ended cmos outputs. the synchronization conditions apply to all of the drivers that belong to that channel divider. each channel (a divider and its outputs) can be excluded from any sync operation by setting the ignore sync bit of the channel. channels that are set to ignore sync (excluded channels) do not set their outputs static during a sync operation, and their outputs are not synchronized with those of the included channels.
ad9522-0 data sheet rev. a | page 50 of 84 1234567 8 910 input to vco divider input to channel divider output of channel divider s ync pin 1 11 12 13 14 14 to 15 cycles at channel divider input + 1 cycle at vco divider input channel divider output static channel divide r output clocking channel divide r output clocking 07219-073 figure 53. sync timing pipeline delay when the vco divider is usedclk or vco is input input to clk input to channel divide r output of channel divider sync pin 14 to 15 cycles at channel divider input + 1 cycle at clk input 1234567 8 910 11 12 13 14 1 channel divider output static channel divide r output clocking channel divider output clocking 0 7219-074 figure 54. sync timing pipeline delay when the vco divider is not usedclk input only lvds output drivers the ad9522 output drivers can be configured as either an lvds differential output or as a pair of cmos single-ended outputs. the lvds outputs allow for selectable output current from ~1.75 ma to ~7 ma. the lvds output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. each lvds output can be individually powered down to save power. out out 3 .5m a 3 .5m a 07219-134 figure 55. lvds output simplified equivalent circuit with 3.5 ma typical current source
data sheet ad9522- 0 cmos output drivers the user can also individually configure each lvds output as a pair of cmos outputs , which provide s up to 24 cmos outputs . when an output is configured as cmos, cmos o utput a and cmos output b are autom atically turned on. for a given differential pair, either cmos o utput a or output b can be turned on or off independently. the user can also select the relative polarity of the cmos outputs for any combination of inverting and noninverting (s ee register 0x 0f 0 to register 0x0fb ) . the user can power down each cmos output as needed to save power. the cmos output power - down is individually controlled by the enable cmos output register ( register 0x0f0[6:5] to register 0x0fb[6:5]). the cmos driver is in tristate when it is powered down. out1/ out1 vs_drv 07219-035 figure 56 . cmos equivalent output circui t reset modes the ad9522 has a power - on reset (por ) and several other ways to apply a reset condition to the chip . power - on reset during chip power - up, a power - on reset pulse is issued when vs re aches ~2.6 v (<2.8 v) and restores the chip either to the setting stored in eeprom (with the eeprom pin = 1) or to the on - chip setting (with the eeprom pin = 0). at power - on, the ad9522 also executes a sync operation, ~50 ms after the supply reaches ~2.4 v, which brings the outputs into ph ase alignment according to the default settings. it takes ~70 ms for the outputs to begin toggling after the power - on reset pulse signal is internally generated. hardware reset via the reset p in reset , a hard reset (an asynchronous hard reset is executed by briefly pulling reset low), restores the chip either to the setting stored in eeprom (the eeprom pin = 1 b ) or to the on - chip setting (the eeprom pin = 0 b ). a hard reset also executes a sync operation , bringing the outputs into phase alignment according to the default settings. when eeprom is inactive (the eeprom pin = 0 b ), it takes ~2 s for the outputs to begin toggling after reset is issued. when eeprom is active (the eeprom pin = 1 b ), it takes ~20 ms for the outputs to toggle after reset is brought high. soft reset via the serial port the serial port control register allows for a soft reset by setting bit 2 and bit 5 in register 0x000. the function of this regist er is determined by the state of the eeprom pin. when bit 2 and bit 5 are set and the eeprom pin is high, the c hip is restored to the settings saved in the eeprom. when bit 2 and bit 5 are set and the eeprom pin is low, the chip is restored to the on - chip defaults. except for the self - clearing bits, bit 2 and bit 5, register 0x000 retains its previous value prior to reset. during the internal reset, the outputs hold static. however, the self - clearing operation does not complete until an additional serial p ort sclk cycle occurs, and the ad9520 is held in reset until that happens . soft reset to settings in eeprom when eeprom pin = 0 via the serial port the serial port control register allows the chip to be reset to settings in eeprom when the eeprom pin = 1 v ia register 0xb02[1]. this bit is self - clearing. this bit does not have any effect when the eeprom pin = 0. it takes ~20 ms for the outputs to begin toggling after the soft_eeprom register is cleared. power - down modes chip power - down via pd the ad9522 can be put into a p ower - down condition by pulling the pd pin low. power - down turns off most of the functions and currents inside the ad9522 . the chip remains in this power - down state until pd is brought back to logic high . when taken out of power - down mode, the ad9522 returns to the settings programmed int o its registers prior to the power - down, unless the registers are changed by new programming while the pd pin is held low. powering d own the chip shuts down the currents on the chip. because this is not a complete power - down, it can be ca lled sleep mode. the ad9522 contai ns special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode. when the ad9522 is in a pd power - down, the chip is in the following state: ? the pll is off (asynchronous power - down). ? the vco is off. ? the clk input buffer is off , bu t the clk input dc bias circuit is on. ? in differential mode, the reference input buffer is off, but the dc bias circuit is still on. ? in singled - ended mode, the reference input buffer is off, and the dc bias circuit is off. ? all dividers are off. ? all cmos ou tputs are tristated . ? all lvds outputs are in power - down (high impedance) mode. ? the serial control port is active, and the chip responds to commands. rev. a | page 51 of 84
ad9522- 0 data sheet pll power - down the pll section of the ad9522 can be selectively power ed down. there are two pll power - down modes set by reg is ter 0x 0 10[ 1:0 ] : asynchronous and synchronous . in asynchronous power - down mode, the device powers down as soon as the registers are updated. in synchronous power - down mode, the pll power - down is gated by the charge pump to prevent unwanted frequency jumps. the device go es into power - down on the occurrence of the next charge pump event after the registers are updated. distribution power - down the distribution section can be powered down by writing register 0x230 [ 1 ] = 1b , which turns off the bias to the distribution section . if the lvds power - d own mode is normal operation (0 b), it is possible for a low impedance load on that lvds output to draw significant current during this power - down. if the lvds power - down mode is set to 1b, the lvds output is not protected from reverse bias and can be damaged under certain termination conditions. individual clock output power - down any of the clock distribution outputs can be put into power - down mode by individually writing to the appropriate registers. the register map details the indivi dual power - down settings for each output. these settings are found in register 0x 0f0 [ 0 ] to register 0x 0f b [ 0 ] . individual clock channel power - down any of the clock distribution channels can be powered down individually by writing to the appropriate register s. powering down a clock channel is similar to powering down an individual driver, but it saves more power because the dividers are also powered down. powering down a clock channel also automatically powers down the drivers connected to it. the register ma p details the individual power - down settings for each output channel. these settings are found in register 0x 192[ 2 ] , register 0x195 [ 2 ] , register 0x198 [ 2 ] , and register 0x19b [ 2 ] . rev. a | page 52 of 84
data sheet ad9522-0 rev. a | page 53 of 84 serial control port the ad9522 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. the ad9522 serial control port is compatible with most synchronous transfer formats, including philips i2c, motorola? spi?, and intel? ssr protocols. the ad9522 i2c implementation deviates from the classic i2c specification on two specifications, and these deviations are documented in table 14 of this data sheet. the serial control port allows read/write access to all registers that configure the ad9522. spi/i2c port selection the ad9522 has two serial interfaces, spi and i2c. users can select either spi or i2c depending on the states of the three logic level (high, open, low) input pins, sp1 and sp0. when both sp1 and sp0 are high, the spi interface is active. otherwise, i2c is active with eight different i2c slave address (seven bits wide) settings, see table 40. the four msbs of the slave address are hardware coded as 1011, and the three lsbs are programmed by sp1 and sp0. table 40. serial port mode selection sp1 sp0 address low low i2c, 1011000 low open i2c, 1011001 low high i2c, 1011010 open low i2c, 1011011 open open i2c, 1011100 open high i2c, 1011101 high low i2c, 1011110 high open i2c, 1011111 high high spi i2c serial port operation the ad9522 i2c port is based on the i2c fast mode standard. the ad9522 supports both i2c protocols: standard mode (100 khz) and fast mode (400 khz). the ad9522 i2c port has a 2-wire interface consisting of a serial data line (sda) and a serial clock line (scl). in an i2c bus system, the ad9522 is connected to the serial bus (data bus sda and clock bus scl) as a slave device, meaning that no clock is generated by the ad9522 . the ad9522 uses direct 16-bit (two bytes) memory addressing instead of traditional 8-bit (one byte) memory addressing. i 2 c bus characteristics table 41. i 2 c bus definitions abbreviation definition s start sr repeated start p stop a acknowledge a no acknowledge w write r read one pulse on the scl clock line is generated for each data bit transferred. the data on the sda line must not change during the high period of the clock. the state of the data line can change only when the clock on the scl line is low. sda scl data line stable; data valid change of data allowed 0 7219-160 figure 57. valid bit transfer a start condition is a transition from high to low on the sda line while scl is high. the start condition is always generated by the master to initialize the data transfer. a stop condition is a transition from low to high on the sda line while scl is high. the stop condition is always generated by the master to end the data transfer. start condition s stop condition p sd a scl 07219-161 figure 58. start and stop conditions a byte on the sda line is always eight bits long. an acknowledge bit must follow every byte. bytes are sent msb first. the acknowledge bit is the ninth bit attached to any 8-bit data byte. an acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. it is accomplished by pulling the sda line low during the ninth clock pulse after each 8-bit data byte.
ad9522-0 data sheet rev. a | page 54 of 84 s d a msb acknowledge from slave-receiver acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 07219-162 figure 59. acknowledge bit s d a msb = 0 acknowledge from slave-receiver acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 07219-163 figure 60. data transfer process (master write mode, 2-byte transfer used for illustration) s d a acknowledge from master-receiver no acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 msb = 1 07219-164 figure 61. data transfer process (master read mode, 2-byte transfer used for illustration) the no acknowledge bit is the ninth bit attached to any 8-bit data byte. a no acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. it is done by leaving the sda line high during the ninth clock pulse after each 8-bit data byte. data transfer process the master initiates data transfer by asserting a start condition. this indicates that a data stream follows. all i2c slave devices connected to the serial bus respond to the start condition. the master then sends an 8-bit address byte over the sda line, consisting of a 7-bit slave address (msb first) plus an r/ w bit. this bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master (transmitter) writes to the slave device (receiver). if the r/ w bit is 1, the master (receiver) reads from the slave device (transmitter). the format for these commands is described in the data transfer format section. data is then sent over the serial bus in the format of nine clock pulses, one data byte (8-bit) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. the number of bytes that can be transmitted per transfer is unrestricted. in write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes with the high address byte first. this addressing scheme gives a memory address up to 2 16 ? 1 = 65,535. the data bytes after these two memory address bytes are register data written into the control registers. in read mode, the data bytes after the slave address byte are register data read from the control registers. when all data bytes are read or written, stop conditions are established. in write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). in read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull it low during the ninth clock pulse. this is known as a no acknowledge bit. by receiving the no acknowledge bit, the slave device knows that the data transfer is finished and releases the sda line. the master then takes the data line low during the low period before the 10th clock pulse and high during the 10th clock pulse to assert a stop condition. a repeated start (sr) condition can be used in place of a stop condition. furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded.
data sheet ad9522-0 rev. a | page 55 of 84 data transfer format send byte formatthe send byte protocol is used to set up the register address for subsequent commands. s slave address w a ram address high byte a ram address low byte a p write byte formatthe write byte protocol is used to write a register address to the ram starting from the specified ram addres s. s slave address w a ram address high byte a ram address low byte a ram data 0 a ram data 1 a ram data 2 a p receive byte formatthe receive byte protocol is used to read the data byte(s) from ram starting from the current address. s slave address r a ram data 0 a ram data 1 a ram data 2 a p read byte formatthe combined format of the send byte and the receive byte. s slave address w a ram address high byte a ram address low byte a sr slave address r a ram data 0 a ram data 1 a ram data 2 a p i2c serial port timing sda scl s sr p s t fall t set; dat t low t rise t hld; str t hld; dat t high t fall t set; str t hld; str t spike t set; stp t rise t idle 07219-165 figure 62. i2c serial port timing table 42. i2c timing definitions parameter description f i2c i2c clock frequency t idle bus idle time between stop and start conditions t hld; str hold time for repeated start condition t set; str setup time for repeated start condition t set; stp setup time for stop condition t hld; dat hold time for data t set; dat setup time for data t low duration of scl clock low t high duration of scl clock high t rise scl/sda rise time t fall scl/sda fall time t spike voltage spike pulse width that must be suppressed by the input filter
ad9522- 0 data sheet spi serial port oper ation pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock . the read data bits transition on the falling edge of sclk . this pin is internally pulled down by a 30 k ? resistor to ground. sdio (serial data input/output) is a dual - purpose pin and acts either as an input only (unidirectional mode) or as an input/ output (bidirectional mode). the ad9522 defaults to the bidirectional i/o mode ( register 0x 0 00[ 7 ] = 0 b ). sdo (serial data out) is used only in the unidirectional i/ o mode ( register 0x 0 00 [ 7 ] = 1b ) as a separate output pin for reading back dat a. cs (chip select bar) is an active low control that gates the read and write cycles. when cs is high, sdo and sdio are in a high impedance s tate. this pin is internally pulled up by a 30 k? resistor to vs . ad9522 serial control port sclk/scl 16 sdo 18 sdio/sda 17 cs 15 07219-036 figure 63 . serial control port spi mode operation in spi mode, single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9522 serial control port can be configured for a single bidirectional i/ o pin (sdio only) or for two unid i rectional i/o pins (sdio/ sdo). by default, the ad9522 is in bidirectional mode. short instruction mode (8 - bit instructions) is not supported. on ly l ong (16 - bit) instruction mode is supported. it is possible that serial activity on the sdio/sdo pins may in duce jitter on the pll while data is transmitted. a write or a read operation to the ad9522 i s initiated by pulling cs low . the cs stall ed high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferre d (see table 43 ). in this mode , the cs pin can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. cs can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort the transfer bef ore all of the data is sent, the state machine must be reset by either completing the remaining transfer s or by returning cs low for at least one complete sclk cycle (but fewer than eight sclk cycles). raising the cs pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. in the streaming mode (see table 43 ), any number of data bytes can be transferred in a continuous stream. the register address is auto matically incremented or decremented (see the spi msb/lsb first transfers section). cs must be raised at the end of the last byte to be transferred, thereby ending streaming mode. communication cycle instruction plus data there are two parts to a communication cycle with the ad9522 . the first part writes a 16 - bit i n struction word into the ad9522 , coincident with the first 16 sclk rising edges. the instruction word provides the ad9522 serial control port with information regarding the data transfer, which is the second part of the communication c y cle. the instructi on word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data tran s fer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation, the secon d part is the transfer of data into the serial control port buffer of the ad9522 . data bits are re gistered on the rising edge of sclk. the length of the transfer ( one , two , or three bytes , or streaming mode) is indicated by two bits (w1:w0) in the instruction byte. when the transfer is one , two, or three bytes , but not streaming , cs can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle) . when the bus is stalled, the serial transfer resumes when cs is lowered. raising the cs pin on a nonbyte boundary resets the serial control port. during a write, streaming mode does not skip over reserved or blank registers , and the user can write 0x00 to the reserved register addresses . beca use data is written into a serial control port buffer area, not directly into the actual control registers of the ad9522 , an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the ad9522 , thereby causing them to become active. the update registers operation consists of setting register 0x232 [ 0 ] = 1b (this bit is self - clearing) . a ny number of bytes of data can be changed before executing an update registers operation . t he update registers operation simultaneously actuates all register changes that have been w ritten to the buffer since any previous update. read the ad9522 supports only the long instruction mode. if the instruction word is f or a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1 to 3 as determined by w1 :w0 . if n = 4, the read operation is in streaming mode , continuing until cs is raised. streaming mode does not skip over reserved or blank registers. the readback data is valid on the falling edge of sclk. rev. a | page 56 of 84
data sheet ad9522-0 rev. a | page 57 of 84 the default mode of the ad9522 serial control port is the bidirectional mode. in bidirectional mode, both the sent data and the readback data appear on the sdio pin. it is also possible to set the ad9522 to unidirectional mode (register 0x000[7] = 1 and register 0x000[0] = 1). in unidirectional mode, the readback data appears on the sdo pin. a readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see figure 64). readback of the buffer or active registers is controlled by register 0x004[0]. the ad9522 uses register address 0x000 to register address 0xb03. serial control port buffer registers update registers write register 0x232 = 0x001 to update registers active registers sclk/scl sdo sdio/sda cs 07219-037 figure 64. relationship between seri al control port buffer registers and active registers of the ad9522 spi instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits (w1:w0) indicate the length of the transfer in bytes. the final 13 bits are the address (a12:a0) at which to begin the read or write operation. for a write, the instruction word is followed by the number of bytes of data indicated by bits[w1:w0], see table 43. table 43. byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode bits[a12:a0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. in msb first mode, subsequent bytes decrement the address. spi msb/lsb first transfers the ad9522 instruction word and byte data can be msb first or lsb first. any data written to register 0x000 must be mirrored; the upper four bits ([7:4]) must mirror the lower four bits ([3:0]). this makes it irrelevant whether lsb first or msb first is in effect. as an example of this mirroring, see the default setting for register 0x000, which mirrors bit 4 and bit 3. this sets the long instruction mode, which is the default and the only mode supported. the default for the ad9522 is msb first. when lsb first is set by register 0x000[1] and register 0x000[6], it takes effect immediately because it only affects the operation of the serial control port and does not require that an update be executed. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes must follow in order from the high address to the low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb first is active, the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. in a multibyte transfer cycle, the internal byte address generator of the serial port increments for each byte. the ad9522 serial control port register address decrements from the register address just written toward register 0x000 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is active, the register address of the serial control port increments from the address just written toward register 0x232 for multibyte i/o operations. streaming mode always terminates when it reaches register 0x232. note that unused addresses are not skipped during multibyte i/o operations. table 44. streaming mode (no addresses are skipped) write mode address direction stop sequence lsb first increment 0x230, 0x231, 0x232, stop msb first decrement 0x001, 0x000, 0x232, stop
ad9522-0 data sheet rev. a | page 58 of 84 table 45. serial control port, 16-bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/w w1 w0 a12 = 0 a11 = 0 a10 = 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don't care sdio a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 0 7219-038 figure 65. serial control port writemsb firs t, 16-bit instruction, two bytes of data 07219-039 t s don't care don't care w1 w0 a12 a11 a10 a9 a0 don?t care r/w t ds t dh t high t low t clk t c cs sclk sdio high impedance d7 d6 d5 d4 d3 d2 d1 d0 high impedance sdo register (n) data 16-bit instruction header figure 66. serial control port readmsb firs t, 16-bit instruction, four bytes of data t s don't care don't care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 don't care don't care r/w t ds t dh t high t low t clk t c cs sclk sdio 07219-040 figure 67. serial control port readmsb first, 16-bit instruction, timing measurements high impedance data bi t n ? 1 data bi t 1 data bit 0 data bit n cs sclk sdio (3-wire mode) sdo (4-wire mode) t dv 07219-041 figure 68. timing diagram for serial control port register read cs sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 0 7219-042 figure 69. serial control port writelsb firs t, 16-bit instruction, two bytes of data
data sheet ad9522-0 rev. a | page 59 of 84 cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 0 7219-043 figure 70. serial control port timingwrite table 46. serial control port timing parameter description t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock t s setup time between the cs falling edge and sclk rising edge (start of communication cycle) t c setup time between sclk rising edge and the cs rising edge (end of communication cycle) t high minimum period that sclk must be in a logic high state t low minimum period that sclk must be in a logic low state t dv sclk to valid sdio and sdo (see figure 68)
ad9522- 0 data sheet eeprom operations the ad9522 contains an internal eeprom (nonvolatile memory) . the eeprom can be programmed by user s to create and store a user - defined register setting file when the power is off . this setting file can be used for power - up and chip reset as a default setting . the eeprom size is 512 bytes. to guarantee proper loading of the eeprom during startup, a high - low - high pulse on the reset pin must occur after the power supply stabilize s. during the data transfer process, the write and read registers via the serial port are generally not available except for one readback register , status_eeprom . to determine the dat a transfer state through the serial port in spi mode, user s can read the value of status_eeprom (1 = in process and 0 = completed ). in i2c mode, the user can address the ad9522 slave port with the external i2c master (send a n address byte to the ad9522 ). if the ad9522 respon d s with a no acknowledge bit , the data transfer process is not done. if the ad9522 responds with an acknowledge bi t , the data transfer process is completed . the user can monitor t he status_eeprom register or program the status pin to moni tor the status of the data transfer . writing to the eepro m the eeprom cannot be programmed directly through the serial port interf ace . to program the eeprom and store a register setting file , do the following : 1. program the ad9522 registers to the desired circuit state . if the user wants the pll to lock automatically after power - up, the vco calibration n ow bit ( register 0x018 [ 0 ] ) must be set to 1. this allow s vco calib ration to start automatically after register loading. note that a valid input reference signal must be present during vco calibration. 2. program the eeprom buffer registers , if necessary ( s ee the programming the eepro m buffer segment section ) . 1. this is only necessary if user s want to use the eeprom to control the default setting of some (but not all) of the ad9522 registers , or if they want to control the register setting update sequence during power - up or chip reset . 3. set the enable eeprom write bit ( r egister 0xb02 [ 0 ] ) to 1 to enable the eeprom . 4. set the reg2eeprom bit ( register 0xb03 [ 0 ] ) to 1 . 5. set the io_update bit ( register 0x232 [ 0 ] ) to 1 , which start s the process of writing data into the eeprom to create the eeprom setting file. this enables the ad9522 eeprom controller to transfer t he current register values, as well as the memory address and instruction bytes from the eeprom buffer segment , into the eeprom . after the write process is completed , the internal controller set s register 0x b03 [ 0 ] (reg2eeprom ) back to 0 . 2. the r ead back reg ister , status_eeprom ( register 0x b00 [ 0 ] ) , is used to indicate the data transfer status between the eeprom and the control registers (0 = done/inactive; 1 = in process/active) . at the beginning of the data transfer, status_eeprom is set to 1 by the eeprom c ontroller and cleared to 0 at the end of the data transfer. the u ser can access status_eeprom through the status p in when the status pin is programmed to monitor status_eeprom . alternat iv ely, the user can monitor the status_eeprom bit . 6. after the data tran sfer process is done ( register 0xb00 [ 0 ] = 0), s et the e nable eeprom w rite r egister ( register 0x b02 [ 0 ] ) to 0 to disable writing to the eeprom . to verify that the data transfer has completed correctly, the user can verify that register 0xb01 [ 0 ] = 0. a value of 1 in this register indicates a data transfer error. reading from the eeprom the following reset - related events can start the proce ss of restoring the setting s stored in eepro m to control registers . when the eeprom pin is set high , do any of the followin g: 1. power u p the ad9522 . 2. perform a h ardware chip r eset by pulling the reset pin low , and then releasing reset . 3. set the self - clearing soft r eset bit ( register 0x000 [ 5 ] ) to 1 . when the e e p rom pin is set low, s et the self - clearing s oft _ eeprom bit ( register 0 xb02 [ 1 ] ) to 1 . the ad9522 then sta rt s to read the eeprom and load s the values into the ad9522 . if the eeprom p in is low during reset or power - up, the eeprom is not active , and the ad9522 default values are loaded instead. w hen using the eeprom to automatically load the ad9522 register values and lock the pll, the vco calibration no w bit ( register 0x018 [ 0 ] ) must be set to 1 when the regist er values are written to the eeprom. this allow s vco calibration to start automatically after register loading. a valid input reference signal must be present during vco calibration. to verify that the data transfer has completed correctly, the user can ve rify that register 0xb01 [ 0 ] = 0. a value of 1 in this register indicates a data transfer error. rev. a | page 60 of 84
data sheet ad9522- 0 programming the eeprom buffer segmen t the eeprom buffer segment is a register space on the ad9522 that allows the user to specify which groups of registers are stored to the eeprom during eeprom programming . normally, this segment does not need to be programmed by the user. instead, the default power - up values for the eeprom buffer segment allow the user to store all of the ad9522 register values from register 0x000 to register 0x231 to the eeprom . for example, if user s wa nt to load only the output driver settings from the eeprom without disturbing the pll register settings currently stored in the ad9522 , they can alter the eeprom buffer seg ment to include only the registers that apply to the output drivers and exclude the registers that apply to the pll co nfiguration. there are two parts to the eeprom buffer segment : register section definition groups and o p erational codes. each register section definition group contains the starting address and number of bytes to be written to the eeprom . if the ad9522 register map were continuous from ad dress 0x000 to address 0x232, only one register section definition group would consist of a starting address of 0x000 and a length of 563 bytes. however, this is not the case. the ad9522 register map is non contiguous, and the eeprom is only 512 bytes long. therefore, the register section definition group tells the eeprom controller how the ad9522 register map is segmented. there are three o p erational codes: io_update , e nd - of - data, and p seudo - end - of - data. it is important that the eeprom buffer segme nt always have either an end - of - data or a p seudo - end - of - data op erational co de and that an io_update op eration code appear at least once before the end - of - data op code. register section definition group the register section definition group is used to define a continuous register section for the eeprom profile. it consists of thre e bytes. the first byte define s how many continuous register bytes are in this group . if the user puts 0x0 0 0 in the first byte, it means there is only one byte in this group . if the user puts 0x 0 01 , it means there are two bytes in this group . the maximum n umber of register s in one group is 128 . the next two bytes are the low byte and high byte of the memory address (16 - bit) of the first register in this group. io _ u pdate ( op erational c ode 0x80 ) the eeprom controller uses operational code 0x80 to generate a n io_update signal to update the active control register bank from the buffer register bank during the download process. at a minimum, there must be at least one io_update op erational code after the end of the final register section definition group. this is needed so that at least one io_update occur s after all of the ad9522 registers are loaded when the eeprom is read. i f this o p erational code is absent during a write to the eeprom, the register values loaded from the eeprom are not transferred to the active register space , and these val ues do not take effect after they are loaded from the eeprom to the ad9522 . end - of - data ( op erational c ode 0xff ) the eeprom controller uses operational code 0xff to terminate the data transfer process between eeprom and the control register during the upload and download process. the last item appearing in the eeprom buffer segment must be either this operational code or the pseudo - end - of - data operational code. p se udo - end - of - data ( op erational c ode 0xfe ) the ad9522 eeprom buffer segment has 23 bytes that can contain up to seven register section definition groups . if user s w ant to define more than seven register section definition groups , the p se udo - end - of - data op erational code (0xfe) can be used . during the upload process, when the eeprom controller receive s the p se udo - end - of - data op erational cod e, it halt s the data transfer process , clear s the reg2eeprom bit , and enable s the ad9522 serial port. u ser s can then program the eep rom buffer segment again and re initiate the data transfer process by setting the reg2eeprom bit ( register 0xb03) to 1 and the io_update bit ( register 0x232) to 1 . the i nternal i2c master then begin s writing to the eeprom starting from the eeprom address held from the last writing. this sequence enables m ore discrete instructions to be written to the eeprom than would otherwise be possible due to the limited size of the eeprom buffer segme nt . it also permits the user to write to t he same register multiple times with a different value each time . rev. a | page 61 of 84
ad9522- 0 data sheet table 47 . example of eeprom buffer segment reg addr (hex) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (l sb) start eeprom buffer segment 0xa00 0 number of bytes [6:0] of the first group of registers 0xa01 address [15:8] of the first group of registers 0xa02 address [7:0] of the first group of registers 0xa03 0 number of bytes [6:0] of the second group o f registers 0xa04 address [15:8] of the second group of registers 0xa05 address [7:0] of the second group of registers 0xa06 0 number of bytes [6:0] of the third group of registers 0xa07 address [15:8] of the third group of registers 0xa08 address [ 7:0] of the third group of registers 0xa09 io_update o p erational code (0x80) 0xa0a end - of - d ata o p erational code (0xff) rev. a | page 62 of 84
data sheet ad9522- 0 thermal performance table 48 . thermal parameters for the 64- lead lfcsp symbol thermal characteristic using a jedec jesd51 - 7 plus jedec jesd51 - 5 2s2p test board value (c/w) ja junction -to - ambient thermal resistance, 0.0 m/sec airflow per jedec jesd51 - 2 (still air) 22.0 jma junction -to - ambient thermal resistance, 1.0 m/sec airflow per jedec jesd51 - 6 (moving air) 19.2 jma junction -to - ambient thermal resistance, 2.0 m/sec a irflow per jedec jesd51 - 6 (moving air) 17.2 jb junction -to - board characterization parameter, 1.0 m/sec airflow per jedec jesd51 - 6 (moving air) and jedec jesd51 -8 11.6 jc junction -to - case thermal resistanc e (die - to - heat sink) per mil - std 883, method 101 2.1 1.3 jt junction - to - top - of - package characterization parameter, 0 m/sec airflow per jedec jesd51 - 2 (still air) 0.1 the ad9522 is specified for a case temperature (t case ). to ensure that t case is not exceeded, an airflow source can be used. use the following equation to determine th e junction temperature on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the use r at the top center of the package. jt is the value from table 48. pd is the power dissipation ( see th e total power dissipation in table 18.) value s of ja are provided for package comparison and pcb design considerations. ja can be used for a first - order approximation of t j by the equation t j = t a + ( ja pd ) wher e t a is the ambient temperature (c). value s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. value s of jb are provided for package comparison and pcb design considerations. rev. a | page 63 of 84
ad9522- 0 data sheet register ma p r egister addresses that are not listed in table 49 are not used , and writing to those registers ha s no effect. writing to register addresses marked u nused must have 00h written to them, unless otherwise noted. n /a is not applicable. table 49. register map overview addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) serial port configuration 000 serial port config (spi mode) sd o active lsb first/ addr incr soft reset (self - clearing) unused unused soft reset (self - clearing) lsb first/ addr incr sd o active 00 serial port config (i2c mode) unused soft reset (self - clearing) unused unused soft reset (self - clearing) unused 00 001 unused n/a 002 silicon r evision silicon revision (read only) 11 003 part id part id (read only) 20 004 readback control unused readback active regs 00 eeprom id 005 eeprom customer version id eeprom customer version id (lsb) 00 006 eeprom customer version id (msb) 00 007 to 00f unused 00 pll 010 pfd charge pump pfd polarity c harge pump current c harge pump mode pll power - down 7d 011 r counter 14- bit r counter, bits [ 7:0 ] (lsb) 01 012 unused 14- bit r counter, bits [ 13:8 ] (msb) 00 013 a counter unuse d 6 - b it a counter 00 014 b counter 13- bit b counter, bits [ 7:0 ] (lsb) 03 015 unused 13- bit b counter, bits [ 12:8 ] (msb) 00 016 pll_ctrl_1 set cp pin to vcp/2 reset r counter reset a and b counters reset all counters b counter bypass prescaler p 06 017 pll_ctrl_2 status pin control antibacklash pulse width 00 018 pll_ctrl_3 enable cmos reference input dc offset lock detect counter digital lock detect window disable digital lock detect vco calibration divider vco calibration now 06 019 pll_ctrl_4 r, a, b counters sync pin reset r path delay n path delay 00 01a pll_ctrl_5 enable status pin divider ref freq monitor threshold ld pin control 00 01b pll_ctrl_6 enable vco frequency monitor enable ref2 frequency monitor enable ref1 (re fin) frequency monitor refmon pin control 00 01c pll_ctrl_7 disable switchover deglitch select ref2 use ref_sel pin reserved enable ref2 enable ref1 enable differential reference 00 01d pll_ctrl_8 enable status _eeprom at status pin enable xtal osc enab le clock doubler disable pll status register enable ld pin comparator unused enable external holdover enable holdover 80 rev. a | page 64 of 84
data sheet ad9522- 0 addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 01e pll_ctrl_9 unused external z ero delay feedback channel divider select enable external zero delay enable zero delay unused 00 01f pll_readback ( read only ) unused vco cal finished holdover active ref2 selected vco freq > threshold ref2 freq > threshold ref1 freq > threshold digital lock detect n/a output driver control 0f0 out 0 c ontrol out0 f ormat out0 cmos c onfiguration out0 p o larity out0 lvds differential voltage out0 lvds power - down 62 0f1 out 1 c ontrol out1 f ormat out1 cmos c onfiguration out1 p olarity out1 lvds differential voltage out1 lvds power - down 62 0f2 out 2 c ontrol out2 f ormat out2 cmos c onfiguration out2 p olari ty out2 lvds differential voltage out2 lvds power - down 62 0f3 out 3 c ontrol out3 f ormat out3 cmos c onfiguration out3 p olarity out3 lvds differential voltage out3 lvds power - down 62 0f4 out 4 c ontrol out4 f ormat out4 cmos c onfiguration out4 p olarity o ut4 lvds differential voltage out4 lvds power - down 62 0f5 out 5 c ontrol out5 f ormat out5 cmos c onfiguration out5 p olarity out5 lvds differential voltage out5 lvds power - down 62 0f6 out 6 c ontrol out6 f ormat out6 cmos c onfiguration out6 p olarity out6 lvds differential voltage out6 lvds power - down 62 0f7 out 7 c ontrol out7 f ormat out7 cmos c onfiguration out7 p olarity out7 lvds differential voltage out7 lvds power - down 62 0f8 out 8 c ontrol out8 f ormat out8 cmos c onfiguration out8 p olarity out8 lvds differential voltage out8 lvds power - down 62 0f9 out 9 c ontrol out 9 f ormat out9 cmos c onfiguration out9 p olarity out9 lvds differential voltage out9 lvds power - down 62 0fa out 10 c ontrol out 10 f ormat out10 cmos c onfiguration out10 p olarity out10 lv ds differential voltage out10 lvds power - down 62 0fb out11 c ontrol out11 f ormat out11 cmos c onfiguration out11 p olarity out11 lvds differential voltage out11 lvds power - down 62 0fc enab l e output on csdld csdld en o ut7 csdld en o ut 6 csdld en o ut 5 csdld en out 4 csdld en o ut 3 csdld en out2 csdld en out1 csdld en out 0 00 0fd enable output on csdld unused unused unused unused csdld en out1 1 csdld en out 10 csdld en out 9 csdld en out 8 00 0fe to 18f unused 00 lvds channel dividers 190 div ider 0 divider 0 low cycles divider 0 high cycles 77 191 divider 0 b ypass divider 0 i gnore sync divider 0 force high divider 0 start high divider 0 phase offset 00 192 unused unused channel 0 power - down reserved disable divider 0 dcc 00 rev. a | page 65 of 84
ad9522- 0 data sheet addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 193 div ider 1 divider 1 low cycles divider 1 high cycles 33 194 divider 1 b ypass divider 1 i gnore sync divider 1 force high divider 1 start high divider 1 phase offset 00 195 unused unused channel 1 power - down reserved disable divider 1 dcc 00 196 divider 2 divider 2 low cycles divider 2 high cycles 11 197 divider 2 b ypass divider 2 i gnore sync divider 2 force high divider 2 start high divider 2 phase offset 00 198 unused unused channel 2 power - down reserved disable divider 2 dcc 00 1 99 divider 3 divider 3 low cycles divider 3 high cycles 00 19a divider 3 b ypass divider 3 i gnore sync divider 3 force high divider 3 start high divider 3 phase offset 00 19b unused unused channel 3 power - down reserved disable divider 3 dcc 00 19c to 1df unused 00 vco divider and clk input 1e0 vco divider unused vco divider 00 1e1 input clks unused power - down clock input section power - down vco clock interface power - down vco and clk select vco or clk bypass vco divider 00 1e2 to 22a unused 00 system 230 power - down and sync unused disable power - on sync power - down sync power - down distribution reference soft sync 00 231 unused unused 00 update all registers 232 io_update unused io_update (self - clearing) 00 233 to 9f f unused 00 eeprom buffer segment a00 serial port configuration data transfer: one byte 00 a01 starting address: address 0x000 00 a02 00 a03 eeprom customer version id data transfer: three bytes 02 a04 starting address: address 0x004 00 a05 04 a06 pll settings data transfer: 16 bytes 0e a07 starting address: address 0x010 00 a08 10 a09 output driver control data transfer: 16 bytes 0e a0a starting address: address 0x0f0 00 a0b f0 rev. a | page 66 of 84
data sheet ad9522-0 rev. a | page 67 of 84 addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) a0c lvds channel dividers data transfer: 12 bytes 0b a0d starting address: address 0x190 01 a0e 90 a0f vdo divider and clk input data transfer: two bytes 01 a10 starting address: address 0x1e0 01 a11 e0 a12 power-down and sync data transfer: two bytes 01 a13 starting address: address 0x230 02 a14 30 a15 i/o update action: io_update 80 a16 end of data action: end of data ff a17 to aff unused unused (available for additional eeprom instructions) 00 eeprom control b00 eeprom status (read only) unused unused status_ eeprom 00 b01 eeprom error checking (read only) unused unused eeprom data error 00 b02 eeprom control 1 unused soft_ eeprom (self- clearing) enable eeprom write 00 b03 eeprom control 2 unused unused reg2eeprom (self-clearing) 00
ad9522- 0 data sheet register map descrip tion s table 50 through table 60 provide a detailed description of each of the control register functions. the registers are listed by hexadecimal address. reference to a specific bit or range of bits within a register is indicated by squared brackets. for e xample , [ 3 ] refers to b it 3 and [ 5:2 ] refers to the range of bits from b it 5 through b it 2. table 50. spi mode serial port configuration reg addr (hex) bit(s) name de scription 0 00 [ 7 ] sdo a ctive selects unidirectional or bidirectional data transfer mode. [ 7 ] = 0; sdio pin used for write and read; sdo is hig h impedance ( default ) . [ 7 ] = 1; sdo used for read; sdio used for write; unidirectional mode. 0 00 [ 6 ] lsb first/addr incr spi msb or lsb data orientation. (this register is ignored in i 2 c mode. ) [ 6 ] = 0; data - oriented msb first; addressing decrements ( default ) . [ 6 ] = 1; data - oriented lsb first; addressing increments. 000 [5] soft reset soft reset. [5] = 1 (self - clearing). soft reset; restores default values to internal registers. this bit self - clears on the next sclk cycle after the completion of writing to this register and does not reset the value of register 0x000. 0 00 [ 4 ] unused 000 [3:0] mirror[7:4] bits[3:0] must always mirror bits[7:4] so that it does not matter whether the part is in msb or lsb first mode (see register 0x000[6]). set bits as follows: [0] = [7] [1] = [6] [2] = [5] [3] = [4] 002 [7:0] silicon r evision th is read only register identifies the revision level of the ad9522 . 003 [7:0] part id (read only) uniquely identifies the dash version ( ad9522 -0 through ad9522 - 5 ) of the ad9522 . ad9522 -0 : 0x20 ad952 2 -1 : 0x60 ad952 2 -2 : 0xa0 ad952 2 -3 : 0x61 ad952 2 -4 : 0xe1 ad9522 -5 : 0xe0 0 04 [ 0 ] read b ack active registers select register bank used for a readback. [ 0 ] = 0; read back buffer registers ( default ) . [ 0 ] = 1; read back active registers. table 51. i 2 c mode serial port configuration reg addr (hex) bit(s) name description 000 [ 7:6 ] u nused 000 [ 5 ] soft r eset soft r eset . [ 5 ] = 1 ( self - clearing). soft reset; restores default values to internal registers. this bit self clears on the next scl cycle after the completion of writing to this register. 000 [ 4 ] unused 000 [ 3:0 ] mirror [ 7:4 ] bits [ 3:0 ] should always mirror bits [ 7:4 ] so that it does not matter whether the part is in msb or lsb first mode (see register 0x 0 00[ 6 ] ). s et bits as follows: [ 0 ] = [ 7 ] [ 1 ] = [ 6 ] [ 2 ] = [ 5 ] [ 3 ] = [ 4 ] 002 [7:0] silicon revision this rea d only register identifies the revision level of the ad9522 . rev. a | page 68 of 84
data sheet ad9522- 0 reg addr (hex) bit(s) name description 003 [7:0] part id (read only) uniquely identifies the dash version ( ad9522 -0 through ad9522 - 5 ) of t he ad9522 . ad9522 -0 : 0x20 ad952 2 -1 : 0x60 ad952 2 -2 : 0xa0 ad952 2 - 3 : 0x61 ad952 2 -4 : 0xe1 ad9522 -5 : 0xe0 004 [ 0 ] read b ack active registers select register bank used for a readback. [ 0 ] = 0; read back buffer registers ( default ) . [ 0 ] = 1; read back active registers. table 52 . eeprom id reg addr (hex) bit(s) name description 005 [ 7:0 ] eeprom customer version id (lsb) 16-b it eeprom id [ 7:0 ] . this register, along with register 0x 006, allow s the user to store a unique id to identify which version of the ad9522 register settings is stored in the eeprom. it does not affect ad9522 operation in any way (d efault : 0x 00) . 006 [ 7:0 ] eeprom customer version id (msb) 16-b it eeprom id [ 15:8 ] . this r egister, along with register 0x 005, allow s the user to store a unique id to identify which version of the ad9522 register settings is stored in the eeprom. it does not affect ad9522 operation in any way (d efault : 0x 00) . table 53 . pll reg. addr (hex) bit(s) name description 0 10 [ 7 ] pfd p olarity set s the pfd polarity. negative polarity is for use (if needed) with external vco/vcxo only . the on - chip vco re quires positive polarity , [ 7 ] = 0 . [ 7 ] = 0; positive (higher control voltage produces higher frequency) ( default ) . [ 7 ] = 1; negative (highe r control voltage produces lower frequency). 0 10 [ 6:4 ] cp c urrent charge pump current (with cprset = 5.1 k?). [ 6 ] [ 5 ] [ 4 ] i cp (ma) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 ( default ) 0 10 [ 3:2 ] cp m ode charge pump operating mode. [ 3 ] [ 2 ] charge pump mo de 0 0 high impedance state . 0 1 force source current (pump up) . 1 0 force sink current (pump down) . 1 1 normal operation ( default ) . 010 [ 1:0 ] pll power - down pll o perating mode. [ 1 ] [ 0 ] mode 0 0 normal operation ; t his mode must be selected to use the pll . 0 1 asynchronou s power - down ( default ) . 1 0 unused . 1 1 synchronous power - down . 0 11 [ 7:0 ] 14-b it r counter , bits [ 7:0 ] (lsb) r eference divider l sbs lower eight bits . the reference divider (also called th e r divider or r counter) is 14 bits long. the lower eight bits are in this register ( default : 0x 01) . 0 12 [ 5:0 ] 14-b it r counter , bits [ 13:8 ] (msb) reference divider msbs upper six bits. the refer ence divider (also called th e r divider or r counter) is 14 bits long. the upper six bits are in this register ( default : 0x 00) . rev. a | page 69 of 84
ad9522- 0 data sheet reg. addr (hex) bit(s) name description 0 13 [ 5:0 ] 6 -b it a c ounter a counter (part of n divider). the n divider is also called the f eedback divider ( default : 0x 00) . 0 14 [ 7:0 ] 13-b it b c ounter , bits [ 7:0 ] (lsb) b counter (part of n divider) lower eight bits. the n divider is also called the f eedback divider ( default : 0x 03) . 0 15 [ 4:0 ] 13-b it b c ounter , bits [ 12:8 ] (msb) b counter (part of n divider) upper five bits. the n divider is also called the f eedback divider ( default : 0x 00) . 016 [ 7 ] set cp p in to vcp /2 set s the cp pin to one - half of the vcp supply voltage. [ 7 ] = 0; cp normal operation ( default ) . [ 7 ] = 1; cp pin set to vcp /2. 016 [ 6 ] reset r counter reset r counter (r divider). [ 6 ] = 0; normal ( default ) . [ 6 ] = 1; h old r counter in reset. 016 [ 5 ] reset a and b c ounters reset a and b counters (part of n divider). [ 5 ] = 0; normal ( default ) . [ 5 ] = 1; h old a and b counters in reset . 016 [ 4 ] r eset all counters reset r, a, and b counters. [ 4 ] = 0; normal ( default ) . [ 4 ] = 1; h old r, a, and b counters in reset . 016 [ 3 ] b counter bypass b counter bypass. when this bit is 1, set the a counter in register 0x013 to 0. [ 3 ] = 0; normal ( d efault ) . [ 3 ] = 1; b counter is set to divide - by - 1. this allows the prescaler setting to determine the divide for the n divider. 0 16 [ 2:0 ] prescaler p prescaler: dm = dual modulus and fd = fixed divide. the prescal e r p is part of the f eedback divider. [ 2 ] [ 1 ] [ 0 ] mode prescaler 0 0 0 fd divide -by -1 . 0 0 1 fd divide -by -2 . 0 1 0 dm divide -by -2 and d ivide -by -3 when a 0; divide -by - 2 when a = 0 . 0 1 1 dm divide -by - 4 and d ivide -by -5 when a 0; divide -by - 4 when a = 0 . 1 0 0 dm divide -by -8 and d ivide -by -9 when a 0; divide -by - 8 when a = 0 . 1 0 1 dm divide -by - 16 and d ivide -by -17 when a 0; divide -by - 16 when a = 0 . 1 1 0 dm divide -by - 32 and d ivide -by -33 when a 0; divide -by - 32 when a = 0 ( default ) . 1 1 1 fd divide -by -3 . 017 [ 7:2 ] status pin control select s the signal that appears at the status pin . register 0x01d [ 7 ] must be 0 to reprogram the status pin. [ 7 ] [ 6 ] [ 5 ] [ 4 ] [ 3 ] [ 2 ] level or dynamic signal signal at status pin 0 0 0 0 0 0 lvl ground , dc ( default ) . 0 0 0 0 0 1 dyn n divider output (after the delay) . 0 0 0 0 1 0 dyn r divider output (after the delay) . 0 0 0 0 1 1 dyn a d ivider output . 0 0 0 1 0 0 dyn prescaler output . 0 0 0 1 0 1 dyn pfd up pulse . 0 0 0 1 1 0 dyn pfd down pulse . 0 x x x x x lvl ground ( dc ) ; for all other cases of 0xxxxx not specified . the selections that follow are the same as f or refmon . 1 0 0 0 0 0 lvl ground ( dc ) . 1 0 0 0 0 1 dyn ref1 clock (differential reference when in differential mode) . 1 0 0 0 1 0 dyn ref2 clock (n/a in differential mode) . 1 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode) . 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode) . rev. a | page 70 of 84
data sheet ad9522- 0 reg. addr (hex) bit(s) name description [7] [6] [5] [4] [3] [2] level or dynamic signal signal at status pin 1 0 0 1 0 1 lvl status of selected reference (status of different ial reference) ; active high . 1 0 0 1 1 0 lvl status of unselected refere n ce (not available in differential mode) ; active high . 1 0 0 1 1 1 lvl status of ref1 frequency (active high) . 1 0 1 0 0 0 lvl status of ref2 frequency (active high) . 1 0 1 0 0 1 lvl (status of ref1 frequency) and (status of ref2 frequency) . 1 0 1 0 1 0 lvl (dld) and ( s tatus of selected reference) and ( s tatus of vco) . 1 0 1 0 1 1 lvl status of vco f requency (active high) . 1 0 1 1 0 0 lvl selected reference ( low = ref1, high = ref2) . 1 0 1 1 0 1 lvl dld ; active high . 1 0 1 1 1 0 lvl holdover active (active high) . 1 0 1 1 1 1 lvl ld pin comparator output (active high). 1 1 0 0 0 0 lvl vs (pll power supply) . 1 1 0 0 0 1 dyn ref 1 clock (differential reference when in differential mode) . 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode) . 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differenti al mode) . 1 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode) . 1 1 0 1 0 1 lvl status of selected reference (st atus of differential reference); a ctive low. 1 1 0 1 1 0 lvl status of unselect ed reference (not available in differential mode) ; active low . 1 1 0 1 1 1 lvl status of ref1 frequency (active low) . 1 1 1 0 0 0 lvl status of ref2 frequency (active low) . 1 1 1 0 0 1 lvl ( status of ref1 frequency ) and ( s tatus o f ref2 frequency ) . 1 1 1 0 1 0 lvl ( dld ) and ( status of selected reference ) and ( s tatus of vco ) . 1 1 1 0 1 1 lvl status of vco f requency (active low) . 1 1 1 1 0 0 lvl selected reference ( low = ref2, high = ref1) . 1 1 1 1 0 1 lvl dld (active low) . 1 1 1 1 1 0 lvl holdover active (active low) . 1 1 1 1 1 1 lvl ld pin comparator output (active low) . 017 [ 1:0 ] antibacklash pulse width [ 1 ] [ 0 ] antibacklash pulse width (ns) 0 0 2.9 ( default ) 0 1 1.3 1 0 6. 0 1 1 2.9 018 [ 7 ] enable cmos r ef erence i nput dc o ffset enables dc offset in single - ended cmos input mode to prevent chattering when ac - coupled and input is lost. [ 7 ] = 0; d isable dc o ffset ( default ). [ 7 ] = 1; e nable dc o ffset. 0 18 [ 6:5 ] lock detect counter required consecutive number of pfd cycles with edges inside lock detect window before the dld indicates a locked condition. [ 6 ] [ 5 ] pfd cycles to determine lock 0 0 5 ( default ) 0 1 16 1 0 64 1 1 255 rev. a | page 71 of 84
ad9522- 0 data sheet reg. addr (hex) bit(s) name description 018 [ 4 ] digital loc k detect window if the time difference of the rising edges at the inputs to the pfd are less than the lock detect window time, the digital lock detect flag is set. the flag remains set until the time difference is greater than the loss - of - lock threshold. [ 4 ] = 0; high range . the default setting is 3.5 ns. [ 4 ] = 1; low range. 018 [ 3 ] disable digital lock detect digital lock detect operation. [ 3 ] = 0; normal lock detect operation ( default ) . [ 3 ] = 1; disable lock detect. 018 [ 2:1 ] vco calibr ation divider divider used to generate the vco calibration clock from the pll reference clock (see the vco calibration section for the recommended setting of the vco calibration di vider based on the pfd rate) . [ 2 ] [ 1 ] vco calibration clock divider 0 0 2 . this setting is fine for pfd frequencies < 12.5 mhz. the pfd frequency is f ref /r. 0 1 4. this setting is fine for pfd frequencies < 25 mhz. the pfd frequency is f ref /r. 1 0 8. this setting is fine for pfd frequencies < 50 mhz . 1 1 16 (default) . this setting is fine for any pfd frequency , but results in the longest vco calibration time. 0 18 [ 0 ] vco calibration now bit used to initiate the vco calibration. this bit must be toggled from 0 to 1 in the active registers. the sequence to initiate a calibration follows: program to 0, followed by an ioupdate bit (register 0x232[0]); then program to 1, followed by another ioupdate bit (register 0x232[0]). this sequence gives complete control over when the vco calibration occurs relative to the programming of other registers that can impact the calibration (default = 0). note that the vco divider (register 0x1e0[2:0]) must not be static during vco calibration. 019 [ 7:6 ] r, a, b c ounters sync pin reset [ 7 ] [ 6 ] action 0 0 do nothing on sync ( default ). 0 1 asynchronous reset. 1 0 synchronous reset. 1 1 do nothing on sync . 0 19 [ 5:3 ] r p ath d elay r path delay , see table 2 ( default : 0x 0) . 0 19 [ 2:0 ] n p ath d elay n path delay , see table 2 ( default : 0x 0) . 01a [ 7 ] enable status pin divider enables a divide -by - 4 on the status pin. this makes it easier to l ook at low duty - cycle signals out of the r and n dividers. [ 7 ] = 0; d ivide -by - 4 disable d on status pin (default) . [ 7 ] = 1; di vide -by - 4 enable d on status pin. 01a [ 6 ] ref freq monitor threshold sets the reference (ref1/ref2) frequency monitors de tection threshold frequency. this does not affect the vco frequency monitors detection threshold (see table 17 , ref1, ref2, and vco frequency status monitor parameter ). [ 6 ] = 0; frequency valid if frequency is above 1.02 m hz ( default ) . [ 6 ] = 1; frequency valid if frequency is abov e 8 khz. 01a [ 5:0 ] ld pin control select s the signal that is connected to the ld pin. [ 5 ] [ 4 ] [ 3 ] [ 2 ] [ 1 ] [ 0 ] level or dynamic signal signal at ld pin 0 0 0 0 0 0 lvl d igital lock detect (high = lock ; low = unlock , default ) . 0 0 0 0 0 1 dyn p - channel , open - drain lock detect (analog lock detect) . 0 0 0 0 1 0 dyn n - channel , open - drain lock detect (analog lock detect) . 0 0 0 0 1 1 hiz tri state ( h igh -z ) ld pin . 0 0 0 1 0 0 cur current source lock detect (110 a when dld is true) . 0 x x x x x lvl ground ( dc ) ; for all other cases of 0xxxxx not specified . the selections that follow are the same as for refmon . 1 0 0 0 0 0 lvl ground ( dc ) . 1 0 0 0 0 1 dyn ref1 clock (differential reference when in differential mode) . 1 0 0 0 1 0 dyn ref2 clock ( not available in differential mode) . 1 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode) . 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode) . rev. a | page 72 of 84
data sheet ad9522- 0 reg. addr (hex) bit(s) name description [5] [4] [3] [2] [1] [0] level or dynamic signal signal at ld pin 1 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 lvl status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 lvl status of ref1 frequency (active high). 1 0 1 0 0 0 lvl status of ref2 frequency (active high). 1 0 1 0 0 1 lvl (status of ref1 frequency) a nd (status of ref2 frequency). 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco). 1 0 1 0 1 1 lvl status of vco frequency (active high). 1 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 1 0 1 1 0 1 lv l dld; active high. 1 0 1 1 1 0 lvl holdover active (active high). 1 0 1 1 1 1 lvl nor available, do not use. 1 1 0 0 0 0 lvl vs (pll supply). 1 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 1 0 1 0 0 dyn unselected referen ce to pll (not available when in differential mode). 1 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 lvl status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 lvl status of ref1 frequency (active low). 1 1 1 0 0 0 lvl status of ref2 frequency (active low). 1 1 1 0 0 1 lvl ( status of ref1 frequency ) and ( status of ref2 frequency ) . 1 1 1 0 1 0 lvl ( dld ) a nd ( status of selected reference ) and ( status of vco ) . 1 1 1 0 1 1 lvl status of vco frequency (active low). 1 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 1 0 1 lvl dld; active low. 1 1 1 1 1 0 lvl holdover active ( active low). 1 1 1 1 1 1 lvl n/a, do not use. 01b [7] enable vco frequency monitor enables or disables the vco frequency monitor. [7] = 0; disable the vco frequency monitor (default). [7] = 1; enable the vco frequency monitor. 01b [6] enable ref2 frequency monitor enables or disables the ref2 frequency monitor. [6] = 0; disable the ref2 frequency monitor (default). [6] = 1; enable the ref2 frequency monitor. 01b [5] enable ref1 (refin) frequency monitor ref1 (refin) frequency monito r enabled; this is for both ref1 (single - ended) and refin (differential) inputs (as selected by differential reference mode). [5] = 0; disable the ref1 (refin) frequency monitor (default). [5] = 1; enable the ref1 (refin) frequency monitor. rev. a | page 73 of 84
ad9522- 0 data sheet reg. addr (hex) bit(s) name description 01b [ 4:0] refmon pin control selects the signal that is connected to the refmon pin. [4] [3] [2] [1] [0] level or dynamic signal signal at refmon pin 0 0 0 0 0 lvl ground, dc (default). 0 0 0 0 1 dyn ref1 clock (differential reference when in diffe rential mode). 0 0 0 1 0 dyn ref2 clock (n/a in differential mode). 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high. 0 0 1 1 0 lvl status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 lvl status ref1 frequency (active high). 0 1 0 0 0 lvl status ref2 frequency (active high). 0 1 0 0 1 lvl (status ref1 frequency) and (status ref2 frequency). 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco). 0 1 0 1 1 lvl status of vco frequency (active high). 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 0 1 1 0 1 lvl dld; active low. 0 1 1 1 0 lvl holdover active (active high). 0 1 1 1 1 lvl ld pin comparator output (active high). 1 0 0 0 0 lvl vs (pll supply). 1 0 0 0 1 d yn ref1 clock (differential reference when in differential mode). 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 0 0 1 1 dyn selected reference to pll (differential reference w hen in differential mode). 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode). 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 0 1 1 0 lvl status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 lvl status of ref1 frequency (active low). 1 1 0 0 0 lvl status of ref2 frequency (active low). 1 1 0 0 1 lvl ( status of ref1 frequency ) and ( sta tus of ref2 frequency ) . 1 1 0 1 0 lvl ( dld ) and ( status of selected reference ) and ( status of vco ) . 1 1 0 1 1 lvl status of vco frequency (active low). 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 0 1 lvl dld; active low. 1 1 1 1 0 lvl holdover active (active low). 1 1 1 1 1 lvl ld pin comparator output (active low). 01c [7] disable switchover deglitch disables or enables the switchover deglitch circuit. [7] = 0; enable the switchover d eglitch circuit (default). [7] = 1; disable the switchover deglitch circuit. 01c [6] select ref2 if register 0x01c[5] = 0, selects the reference for pll when in manual; register selected reference control. [6] = 0; select ref1 (default). [6] = 1; select ref2. 01c [5] use ref_sel pin if register 0x01c[4] = 0 (manual), sets the method of pll reference selection. [5] = 0; use register 0x01c[6] (default). [5] = 1; use ref_sel pin. rev. a | page 74 of 84
data sheet ad9522- 0 reg. addr (hex) bit(s) name description 01c [4:3] reserved default: 00b. 01c [2] enable ref2 thi s bit turns the ref2 power on. [2] = 0; ref2 power off (default). [2] = 1; ref2 power on. 01c [1] enable ref1 this bit turns the ref1 power on. [1] = 0; ref1 power off (default). [1] = 1; ref1 power on. 01c [0] enable differential referen ce selects the pll reference mode, differential or single - ended. register 0x01c[2:1] must be cleared when this bit is set. [0] = 0; single - ended reference mode (default). [0] = 1; differential reference mode. 01d [7] enable status_eeprom at status pin enables the status_eeprom signal at the status pin. [7] = 0; the status pin is controlled by the register 0x017[7:2] selection. [7] = 1; select the status_eeprom signal at status pin. this bit overrides register 0x017[7:2] (default). 01d [6] enable xtal osc enables the maintaining amplifier needed by a crystal oscillator at the pll reference input. [6] = 0; crystal oscillator maintaining amplifier disabled (default). [6] = 1; crystal oscillator maintaining amplifier enabled. 01d [5] enable clock doubler enable pll reference input clock doubler. [5] = 0; doubler disabled (default). [5] = 1; doubler enabled. 01d [4] disable pll status register disables the pll status register readback. [4] = 0; pll status register enabled ( default). [4] = 1; pll status register disabled. if this bit is set, register 0x01f is not automatically updated. 01d [3] enable ld pin comparator enables the ld pin voltage comparator. this is used with the ld pin current source lock detect mode. wh en the ad9522 is in internal (auto matic) holdover mode, this enables the use of the voltage on the ld pin to determine if the pll was previously in a locked state (see figure 48 ). otherwise, this can be used with the refmon and status pins to mon itor the voltage on the ld pin. [3] = 0; disable ld pin comparator and ignore the ld pin voltage; internal/automatic holdover controller treats this pin as true (high, default). [3] = 1; enable ld pin comparator (use ld pin voltage to determine if the pll was previously locked). 01d [1] enable external holdover enables the external hold control through the sync pin. (this disables the internal holdover mode.) [1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default). [1] = 1; external holdover mode, holdover controlled by sync pin. 01d [0] enable holdover enables the internally controlled holdover function. [0] = 0; holdover disabled (default). [0] = 1; holdov er enabled. 01e [4:3] external zero delay feedback channel divider select [4] [3] selects which channel divider to use in the external zero delay path 0 0 select channel divider 0 (default). 0 1 select channel divider 1. 1 0 select channel d ivider 2. 1 1 select channel divider 3 01e [2] enable external zero delay selects which zero delay mode to use. [2] = 0; enables internal zero delay mode if register 0x01e[1] = 1 (default). [2] = 1; enables external zero delay mode if register 0x01e[1] = 1. 01e [1] enable zero delay enables zero delay function. [1] = 0; disables zero delay function (default). [1] = 1; enables zero delay function. 01f [6] vco calibration finished (read only) readback register. indicates the status of the vco calibration. [6] = 0; vco calibration not finished. [6] = 1; vco calibration finished. rev. a | page 75 of 84
ad9522- 0 data sheet reg. addr (hex) bit(s) name description 01f [5] holdover active (read only) readback register. indicates if the part is in the holdover state (see fi gure 48 ). this is not the same as holdover enabled. [5] = 0; not in holdover. [5] = 1; holdover state active. 01f [4] ref2 selected (read only) readback register. indicates which pll reference is selected as the input to the pll. [4] = 0; r ef1 selected (or differential reference if in differential mode). [4] = 1; ref2 selected. 01f [3] vco frequency > threshold (read only) readback register. indicates if the vco frequency is greater than the threshold (see table 17 , ref1, ref2, and vco frequency status monitor parameter). [3] = 0; vco frequency is less than the threshold. [3] = 1; vco frequency is greater than the threshold. 01f [2] ref2 frequency > threshold (read only) readback regi ster. indicates if the frequency of the signal at ref2 is greater than the threshold frequency set by register 0x01a[6]. [2] = 0; ref2 frequency is less than the threshold frequency. [2] = 1; ref2 frequency is greater than the threshold frequency. 01f [1] ref1 frequency > threshold (read only) readback register. indicates if the frequency of the signal at ref1 is greater than the threshold frequency set by register 0x01a[6]. [1] = 0; ref1 frequency is less than the threshold frequency. [ 1] = 1; ref1 frequency is greater than the threshold frequency. 01f [0] digital lock detect (read only) readback register. digital lock detect. [0] = 0; pll is not locked. [0] = 1; pll is locked. table 54. output driver control reg. addr (hex) bit(s) name description 0f0 [ 7 ] out0 f ormat selects the output type for out0 . [ 7 ] = 0; lvds ( default ). [ 7 ] = 1; cmos . 0f0 [ 6:5 ] out0 cmos c onfiguration sets the cmos output configuration for out0 when register 0x 0 f0 [ 7 ] = 1 . [ 6:5 ] out0a out0b 00 tristate tristate 01 on tristate 10 tristate on 11 ( default ) on on 0f0 [ 4:3 ] out0 p olarity sets the output polarity for out0 . [ 7 ] [ 4 ] [ 3 ] output type out0a out0b 0 ( default ) x 0 lvds non inverting invertin g 0 x 1 lvds inverting non inverting 1 0 ( default ) 0 (default) cmos non inverting non inverting 1 0 1 cmos inverting inverting 1 1 0 cmos non inverting inverting 1 1 1 cmos inverting non inverting 0f0 [ 2:1 ] out0 lvds differential voltage se ts the lvds output differential voltage (v od ). [ 2 ] [ 1 ] i od (ma) 0 0 1.75 (v od = 175 mv for 100 ? termination across differential pair) 0 (default) 1 (default) 3.5 (v od = 350 mv for 100 ? termination across differential pair) 1 0 5.25 (v od = 525 mv for 100 ? termination across differential pair) 1 1 7. 0 (v od = 700 mv for 100 ? termination across differential pair) rev. a | page 76 of 84
data sheet ad9522- 0 reg. addr (hex) bit(s) name description 0f0 [ 0 ] out0 lvds power - down lvds power - down. [ 0 ] = 0; normal operation ( default ) . [ 0 ] = 1; power - down . output driver is in a high impedance state. 0 f1 [ 7:0 ] out1 c ontrol this register controls out1, and the bit assignments for this register are identical to register 0x 0 f0. 0 f2 [ 7:0 ] out2 c ontrol this register controls out 2 , and the bit assignments for this register ar e identical to register 0x 0 f0. 0 f3 [ 7:0 ] out3 c ontrol this register controls out 3 , and the bit assignments for this register are identical to register 0x0f0 . 0 f4 [ 7:0 ] out4 c ontrol this register controls out 4 , and the bit assignments for this register ar e identical to register 0x0f0 . 0 f5 [ 7:0 ] out5 c ontrol this register controls out 5 , and the bit assignments for this register are identical to register 0x0f0 . 0 f6 [ 7:0 ] out 6 c ontrol this register controls out 6 , and the bit assignments for this register ar e identical to register 0x0f0 . 0 f7 [ 7:0 ] out7 c ontrol this register controls out 7 , and the bit assignments for this register are identical to register 0x0f0 . 0 f8 [ 7:0 ] out8 c ontrol this register controls out 8 , and the bit assignments for this register ar e identical to register 0x0f0 . 0 f9 [ 7:0 ] out9 c ontrol this register controls out 9 , and the bit assignments for this register are identical to register 0x0f0 . 0 fa [ 7:0 ] out10 c ontrol this register controls out1 0 , and the bit assignments for this register are identical to register 0x0f0 . 0 fb [ 7:0 ] out11 c ontrol this register controls out1 1 , and the bit assignments for this register are identical to register 0x0f0 . 0 fc [ 7 ] csdld en out 7 o ut7 is enabled o nly if cs dld is high. [ 7 ] cs dld signal o ut 7 enabl e status 0 0 not affected by cs dld signal (default) . 1 0 asynchronous power - down . 1 1 asynchronously enable o ut 7 if not powered down by other settings. to use this f eature, the user must use current source digital lock detect , and set the enab le ld pin comparator bit ( register 0x01d [ 3 ] ). 0 f c [ 6 ] csdld en out 6 o ut 6 is enabled o nly if cs dld is high . setting is identical to register 0x0 fc [ 7 ] . 0 fc [ 5 ] csdld en o ut 5 o ut 5 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fc [ 4 ] csdld en o ut 4 o ut 4 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fc [ 3 ] csdld en o ut 3 o ut 3 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fc [ 2 ] csdld en o ut 2 o ut 2 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fc [ 1 ] csdld en o ut 1 o ut 1 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fc [ 0 ] csdld en o ut 0 o ut 0 is enabled only if cs dld is high. setting is identical to regist er 0x0fc [ 7 ] . 0 fd [ 3 ] csdld en o ut 11 o ut 11 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fd [ 2 ] csdld en o ut 10 o ut 10 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fd [ 1 ] csdld en o ut 9 o ut 9 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . 0 fd [ 0 ] csdld en o ut 8 o ut 8 is enabled only if cs dld is high. setting is identical to register 0x0fc [ 7 ] . table 55. lvds channel dividers reg. addr (hex) bit(s) name description 190 [ 7:4 ] divider 0 low cycles number of clock cycles (minus 1) of the divider input during which divider output stays low. a value of 0x 7 means the divider is low for eight input clock cycles (default: 0x 7) . 190 [ 3:0 ] divider 0 high cycles number of clock cycles (minus 1) of the divider input during which divider output stays high. a value of 0x 7 means the divider is high for eight input clock cycles (default: 0x 7) . 191 [ 7 ] divider 0 b ypass bypass es and power s down the divider; route s input to divider output. [ 7 ] = 0; use the divider (default) . [ 7 ] = 1; bypass the divider. 191 [ 6 ] divider 0 i gnore sync ignore sync . [ 6 ] = 0; obey chip - level sync signal (default) . [ 6 ] = 1; ignore chip - level sync signal. rev. a | page 77 of 84
ad9522- 0 data sheet reg. addr (hex) bit(s) name description 191 [5] di vider 0 force high forces divider output to a specific state. this requires that ignore sync also be set. note that this bit has no effect if the channel divider is bypassed. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 191 [ 4 ] divider 0 start high selects clock output to start high or start low. [ 4 ] = 0; start low (default) . [ 4 ] = 1; start high. 191 [ 3:0 ] divider 0 phase offset phase offset (default: 0x 0) . 192 [ 2 ] chann el 0 power - down channel 0 power s down . [ 2 ] = 0; n ormal operation (default) . [ 2 ] = 1; p owered down . ( out0/ out0 , out1/ out1 , and out2/ out2 are put into the high impedance power - d own mode by setting this bit.) 192 [ 0 ] dis able divider 0 dcc duty - cycle correction function. [ 0 ] = 0; enable duty - cycle correction (default) . [ 0 ] = 1; disable duty - cycle correction. 193 [ 7:4 ] divider 1 low cycles number of clock cycles (minus 1) of the divider input during which the divid er output stays low. a value of 0x 3 means the divider is low for four input clock cycles (default: 0x 3) . 193 [ 3:0 ] divider 1 high cycles number of clock cycles (minus 1) of the divider input during which the divider output stays high. a value of 0x 3 mea ns the divider is high for four input clock cycles (default: 0x 3) . 194 [ 7 ] divider 1 b ypass bypass es and power s down the divider; route s input to divider output. [ 7 ] = 0; use divider (default) . [ 7 ] = 1; bypass divider. 194 [ 6 ] divider 1 i gnore sy nc ignore sync . [ 6 ] = 0; obey chip - level sync signal (default) . [ 6 ] = 1; ignore chip - level sync signal. 194 [ 5 ] divider 1 force high force s divider output to a specific state. this requires that ignore sync also be set. note that this bit has no e ffect if the channel divider is bypassed. [ 5 ] = 0; divider output forced to low (default) . [ 5 ] = 1; divider output forced to high. 194 [ 4 ] divider 1 start high selects clock output to start high or start low. [ 4 ] = 0; start low (default) . [ 4 ] = 1; start high. 194 [ 3:0 ] divider 1 phase offset phase offset (default: 0x 0) . 195 [ 2 ] channel 1 power - down channel 1 power s down . [ 2 ] = 0; n ormal operation (default) . [ 2 ] = 1; p owered down . ( out3/ out3 , out4/ out4 , and out5/ out5 are pu t into the high impedance power - down mode by setting this bit.) 195 [ 0 ] disable divider 1 dcc duty - cycle correction function. [ 0 ] = 0; enable duty - cycle correction (default) . [ 0 ] = 1; d isable duty - cycle correction. 196 [ 7:4 ] divider 2 low cycles number of clock cycles (minus 1) of the divider input during which the divider output stays low. a value of 0x 1 means the divider is low for two input clock cycles (default: 0x 1) . 196 [ 3:0 ] di vider 2 high cycles number of clock cycles (minus 1) of the divider input during which the divider output stays high. a value of 0x 1 means the divider is high for two input clock cycles (default: 0x 1) . 197 [ 7 ] divider 2 b ypass bypass es and power s down th e divider; route s input to divider output. [ 7 ] = 0; use divider (default) . [ 7 ] = 1; bypass divider. 197 [ 6 ] divider 2 i gnore sync ignore sync . [ 6 ] = 0; obey chip - level sync signal (default) . [ 6 ] = 1; ignore chip - level sync signal. rev. a | page 78 of 84
data sheet ad9522- 0 reg. addr (hex) bit(s) name description 197 [ 5 ] divider 2 force high force s divider output to a specific state. this requires that ignore sync also be set. note that this bit has no effect if the channel divider is bypassed. [ 5 ] = 0; divider output forced to low (default) . [ 5 ] = 1; divider outp ut forced to high. 197 [ 4 ] divider 2 start high selects clock output to start high or start low. [ 4 ] = 0; start low (default) . [ 4 ] = 1; start high. 197 [ 3:0 ] divider 2 phase offs et phase offset (default: 0x0). 198 [ 2 ] channel 2 power - down channel 2 power s down . [ 2 ] = 0; n ormal operation (default) . [ 2 ] = 1; p owered down . ( out6/ out6 , out7/ out7 , and out8/ out8 are put into the high impedance power - down mode by setting this bit.) 198 [ 0 ] di sable divider 2 dcc duty - cycle correction function. [ 0 ] = 0; enable duty - cycle correction (default) . [ 0 ] = 1; disable duty - cycle correction. 199 [ 7:4 ] divider 3 low cycles number of clock cycles (minus 1) of the divider input during which the divi der output stays low. a value of 0x 0 means the divider is low for one input clock cycle (default: 0x 0 ) . 199 [ 3:0 ] divider 3 high cycles number of clock cycles (minus 1) of the divider input during which the divider output stays high. a value of 0x 0 mean s the divider is high for one input clock cycle (default: 0x 0 ) . 19a [ 7 ] divider 3 b ypass bypass es and power s down the divider; route s input to divider output. [ 7 ] = 0; use divider (default) . [ 7 ] = 1; bypass divider. 19a [ 6 ] divider 3 i gnore sync ignore sync . [ 6 ] = 0; obey chip - level sync signal (default) . [ 6 ] = 1; ignore chip - level sync signal. 19a [ 5 ] divider 3 force high force s divider output to a specific state. this requires that ignore sync also be set. note that this bit has no effe ct if the channel divider is bypassed. [ 5 ] = 0; divider output forced to low (default) . [ 5 ] = 1; divider output forced to high. 19a [ 4 ] divider 3 start high selects clock output to start high or start low. [ 4 ] = 0; start low (default) . [ 4 ] = 1; start high. 19a [ 3:0 ] divider 3 phase offs et phase offset (default: 0x 0) . 19b [ 2 ] channel 3 power - do wn channel 3 power s down . [ 2 ] = 0; n ormal operation (default) . [ 2 ] = 1; p owered down . ( out9/ out9 , out10/ out 10 , and out11/ out11 are put into the high impedance power - down mode by setting this bit .) 19b [ 0 ] disable divider 3 dcc duty - cycle correction function. [ 0 ] = 0; enable duty - cycle correction (default) . [ 0 ] = 1; disable duty - cy cle correction. rev. a | page 79 of 84
ad9522- 0 data sheet table 56 . vco divider and c lk input reg. addr (hex) bit(s) name description 1e0 [ 2:0 ] vco d ivider [ 2 ] [ 1 ] [ 0 ] divide 0 0 0 2 (default) 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 output st atic 1 1 0 1 ( b ypass) 1 1 1 output static 1e1 [ 4 ] power - down clock input section power s down the clock input section (including clk buffer, vco divider, and clk tree). [ 4 ] = 0; normal operation (default) . [ 4 ] = 1; power down. 1e1 [ 3 ] powe r - d own vco clock interface power s down the interface block between vco and clock distribution. [ 3 ] = 0; normal operation (default) . [ 3 ] = 1; power down. 1e1 [ 2 ] power - d own vco and clk power s down both the clk input and vco . [ 2 ] = 0; normal ope ration (default) . [ 2 ] = 1; power down. 1e1 [1] select vco or clk selects either the vco or the clk as the input to vco divider. [1] = 0; select external clk as input to vco divider (default). [1] = 1; select vco as input to vco divider; cannot bypass vco divider when this is selected. this bit must be set to use the pll with the internal vco. 1e1 [ 0 ] bypass vco d ivider bypass es or use s the vco divider. [ 0 ] = 0; use vco divider (default) . [ 0 ] = 1; bypass vco divider; cannot select vco as input when this is selected. t able 57 . system reg. addr (hex) bit(s) name description 230 [ 3 ] disable power - on sync power - on sync m ode. used to disable the antiruntpulse circuitry . [ 3 ] = 0; e nable the antiruntpulse circuit ry (default) . [ 3 ] = 1; d isable the antiruntpulse circuitry. 230 [ 2 ] power - d own sync power s down the sync function. [ 2 ] = 0; normal operation of the sync function (default) . [ 2 ] = 1; power - down sync circuitry. 230 [ 1 ] power - down distribution r eference power s down the reference for the distribution section. [ 1 ] = 0; normal operation of the reference for the distribution section (default) . [ 1 ] = 1; power s down the reference for the distribution section. 230 [ 0 ] soft sync the soft sync bi t works the same as the sync pin, except that the polarity of the bit is reversed ; t hat is, a high level forces selected channels into a predetermined static state, and a 1 -to - 0 transition triggers a sync . [ 0 ] = 0; same as sync high. [ 0 ] = 1; same as sync low. rev. a | page 80 of 84
data sheet ad9522- 0 table 58 . update all registers reg. addr (hex) bit(s) name description 232 [0] io_update this bit must be set to 1 to transfer the contents of the buffer regi sters into the active registers. this bit is self - clearing; that is, it does not have to be set back to 0. [0] = 1 (self - clearing); update all active registers to the contents of the buffer registers. table 59 . eeprom buffer s egment reg. addr (hex) bit(s) name description a00 to a16 [7:0] eeprom buffer segment register 1 to eeprom buffer segment register 23 the eeprom buffer segment section stores the starting address and number of bytes that are to be stored and read back t o and from the eeprom. because the ad9522 register space is noncontiguous, the eeprom controller needs to know the starting address and number of bytes in the ad9522 register space to store and retrieve from the eeprom. in addition, there are special instructions for the eeprom controller, operational codes (that is, io _update and end - of - data) that are also stored in the eeprom buffer segment. the on - chip default setting of the eeprom buffer segment registers is designed such that all registers are transferred to/from the eeprom, and an io_update is issued after transf er. see the programming the eeprom buffer segment section for more information. table 60. eeprom control reg. addr (hex) bit(s) name description b00 [ 0 ] status_eeprom ( read only ) this rea d only register indicates the status of the data transfe r r ed between the eeprom and the buffer register bank during the writing and reading of the eeprom. this signal is also available at the status p in when register 0x 0 1d [ 7 ] is set. [ 0 ] = 0; d ata tran sfer is done. [ 0 ] = 1; d ata transfer is not done. b01 [ 0 ] eeprom data error ( read only ) this read only register indicates an error during the data transfer red between the eeprom and the b uffer. [ 0 ] = 0; n o error. data is correct. [ 0 ] = 1; i nc orrect data detected. b02 [ 1 ] s oft _eeprom when the eeprom pin is tied low, setting s oft _ eeprom reset s the ad9522 using the settings saved in eeprom . [ 1 ] = 1; s oft reset with eeprom settings (self - clearing) . this bit self clears on the next serial port clock cycle after the completion of writing to this register. b02 [ 0 ] enable eeprom w rite enables the user to write to the eeprom. [ 0 ] = 0; eeprom write pro tection is ena bled . user cannot write to eeprom (default) . [ 0 ] = 1; e eprom write pr otection is disabled . user can write to eeprom. b03 [ 0 ] reg2eeprom transfers data from the buffer register to the eeprom (self - clearing) . [ 0 ] = 1; setting this bit initiates the data transfer from the buffer register to the eeprom (writing process); it is reset by the i2c master after the data transfer is done. rev. a | page 81 of 84
ad9522- 0 data sheet application s information frequency planning u sing the ad9522 the ad9522 is a highly flexible pll. when choosing the pll settings and version of the ad9522 , keep the following guidelines in mind. the ad9522 has four frequency dividers: the reference (or r) divider, the feedback (or n) divider, the vco divider, and the channel divider. when trying to achieve a par ticularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the vco divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. within the ad9522 family, lower vco frequencies generally result in slightly better jitter. the difference in integrated jitter (from 12 khz to 20 mhz offset) for the same output frequency is usually less than 1 5 0 fs over the entire vco frequency rang e (1.4 ghz to 2.95 ghz) of the ad9522 family . if the desired frequency plan can be achieved with a version of the ad9522 that has a lower vco frequency, choosing the lower frequency part result s in the lowest phase noise and the lowest jitter. however, choosing a higher vco frequency can result in more flexibility in frequency plann ing. choosing a nominal charge pump current in the middle of the allowable range as a starting point allow s the designer to increase or decrease the charge pump current , and thus allow s the designer to fine - tune the pll loop bandwidth in either direction. adisimclk is a powerful pll modeling too l that is a very accurate tool for determining the optimal loop filter for a given application. using the ad9522 outputs for adc cloc k applications any high speed adc is extremely sens itive to the quality of the sampling clock of the ad9522 . an adc can be thought of as a sampling mixer, and any noise, distortion, or tim e jitter on the clock is combined with the desired signal at the analog - to - digital output. clock i n tegrity requirements scale with the analog input frequ ency and resolution, with higher analog input frequency applications at 14- bit resolution being the most stringent. the theoretical snr of an adc is limited by the adc resolution and the jitter on the sampling clock. considering an ideal adc of infinite resolution where the step size and quantization error can be ignored, the available snr can be expressed approximately by ? ? ? ? ? ? ? ? = j a t f snr 2 1 20log (db) where: f a is the highest analog frequency being digitized. t j is the rms jitter on the sampling clock. figure 71 shows the required sampli ng clock jitter as a function of the analog frequency and effective number of bits (enob). f a (mhz) snr (db) enob 10 1k 100 30 40 50 60 70 80 90 100 110 6 8 10 12 14 16 18 t j = 100fs t j = 200fs t j = 400fs t j = 1ps t j = 2ps t j = 10ps snr = 20log 1 ?i a t j 07219-044 figure 71 . snr and enob vs. analog input frequency see the an - 756 application note , sampled systems and the effects of clock phase noise and jitter , and the an - 501 application note , aperture uncertainty and adc system performance . many high performance adcs feature diffe rential clock inputs to simplify the task of providing the required lo w jitter clock on a noisy pcb. distributing a single - ended clock on a noisy pcb can result in coupled noise on the sampl ing clock. differential distribution has inherent common - mode reje ction that can provide superior clock performance in a noisy environment. the differential lvds outputs of the ad9522 enable clock solutions that maximize converter snr performance. consider t he input requirements of the adc (differential or single - ended, logic level termination) when sel ecting the best clocking/converter solution. in some cases, the lvpecl outputs of the ad9520 may be desirable for clocking a converter instead of the lvds output s of the ad9522 . lvds clock distribution the ad9522 provides clock outputs that are selectable as ei ther cmos or lvds level outputs. lvds is a differential output option that uses a current mode output stage. the nominal current is 3.5 ma, which yields 350 mv output swing across a 100 ? resistor. an output current of 7 ma is also available in cases where a larger output swing is required. the lvds output meets or exceeds all ansi/tia/eia - 644 specifications. a recommended terminat ion circuit for the lvds outputs is shown in figure 72 . if ac coupling is necessary, place decoupling capacitors either before or after the 100 ? termination resistor. vs lvds vs lvds ? ? differential (couples) 07219-047 figure 72 . lvds out put termination see the an - 586 application note for more information on lvds. rev. a | page 82 of 84
data sheet ad9522- 0 cmos clock distribut ion the output drivers of the ad9522 can be configured a s cmos drivers. when selected as a cmos driver , each output becomes a pai r of cmos outputs, each of which can be individually turned on or off and set as inverting or non inverting . these outputs are 3.3 v cmos compatible. when single - ended cmos clocking is used, some of the following guidelines apply . point - to - point connection s must be designed such that each driver has only one receive r, if possible. connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace . series termination at the source is generally required to provide transmission line matc h ing and/or to reduce current transients at the driver. the value of the resistor is dependent on the board design and timing r e quirements (typically 10 ? to 100 ? is used). cmos outputs are al so limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 3 inches are re c ommended to preserve signal r ise/fall times and signal integrity. cmos cmos 10? 60.4? (1.0 inch) microstrip 07219-076 figure 73 . series termination o f cmos output termination at the far end of the pcb trace is a second option. the cmos outputs of the ad9522 do not supply enough current to provide a full voltage swing with a low impedance resistive, far - end termination , as shown in figure 74. the far - end termination network must match the pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet r e ceiver input requirements in some applications. this can be useful when driving long trace lengths on less critical nets. cmos cmos 10? 50? 100? 100? v s 07219-077 figure 74 . cmos output with far - end termination because of the limitations of single - ended cmos clocking, consider using differential outputs when driving high speed signals over long traces. the ad9522 offers lvds outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. rev. a | page 83 of 84
ad9522- 0 data sheet outline dimensions compliant to jedec standards mo-220-vmmd-4 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 nom 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom se a ting plane pin 1 indic a t or 6.35 6.20 sq 6.05 pin 1 indic a t or 0.30 0.23 0.18 0.60 0.42 0.24 0.60 0.42 0.24 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. t o p view exposed pad bot t om view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 01-22-2015-d pkg- 1 184 figure 75 . 64 - lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 64 - 4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9522 -0 bcpz ?40c to +85c 64- lead lead frame chip scale package [ lfcsp_vq ] cp -64-4 ad9522 -0 bcpz - reel7 ? 40c to +85c 64- lead lead frame chip scale package [ lfcsp_vq ] cp -64-4 ad9522 -0 /pcb z evaluation board 1 z = rohs compliant part. ? 2008 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07219 - 0 - 3/15(a) rev. a | page 84 of 84
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