rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9630 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1999 low distortion 750 mhz closed-loop buffer amp pin configuration 1 2 3 4 8 7 6 5 nc = no connect ad9630 *** nc ** input +v s nc Cv s output note: for best settling time performance use optional power supplies. all specifications are based on using single 6 v s connections, except for settling time to 0.02% and small signal s21. consult the factory for versions with optional power supply pins disconnected internal to the package. **optional +v s ***optional Cv s features excellent gain accuracy: 0.99 v/v wide bandwidth: 750 mhz slew rate: 1200 v/ m s low distortion C65 dbc @ 20 mhz C80 dbc @ 4.3 mhz settling time 5 ns to 0.1% 8 ns to 0.02% low noise: 2.4 nv/ ? hz improved source for clc-110 applications if/communications impedance transformations drives flash adcs line driving general description the ad9630 is a monolithic buffer amplifier that utilizes a patented, innovative, closed-loop design technique to achieve exceptional gain accuracy, wide bandwidth, and low distortion. slew rate limiting has been overcome as indicated by the 1200 v/ m s slew rate; this improvement allows the user greater flexibility in wideband and pulse applications. the second har- monic distortion terms for an analog input tone of 4.3 mhz and 20 mhz are C80 dbc and C66 dbc, respectively. clearly, the ad9630 establishes a new standard by com bining out- standing dc and dynamic performance in one part. the large signal bandwidth, low distortion over frequency, and drive capabilities of the ad9630 make the buffer an ideal flash adc driver. the ad9630 provides better signal fidelity than many of the flash adcs that it has been designed to drive. other applications that require increased current drive at unity voltage gain (such as cable driving) benefit from the ad9630s performance. the ad9630 is available in plastic dip (n) and s oic (r). * protected under u.s. patent numbers 5,150,074 and 5,537,079. obsolete
C2C rev. b ad9630Cspecifications test ad9630an/ar parameter conditions temp level min typ max units dc specifications output offset voltage +25 ciC8 3+8mv offset voltage tc full iv C40 8 +40 m v/ c input bias current +25 c i C25 2 +25 m a bias current tc full iv C100 20 +100 na/ c input resistance +25 to t max ii 300 450 k w t min vi 150 250 k w input capacitance +25 cv 1.0 pf gain v out = 2 v p-p +25 to t max ii 0.983 0.990 v/v v out = 2 v p-p t min vi 0.980 0.985 v/v output voltage range full vi +3.2 3.6 C3.2 v output current (50 w load) +25 to t max ii 50 ma t min vi 40 ma output impedance at dc +25 cv 0.6 w psrr d v s = 5% full vi 44 55 db dc nonlinearity 2 v full scale +25 c v 0.03 % frequency domain bandwidth (C3 db) small signal v o 0.7 v p-p t min to +25 ii 400 750 mhz v o 0.7 v p-p t max ii 330 550 mhz large signal v o = 5 v p-p t min to +25 v 120 mhz v o = 5 v p-p t max v 105 mhz output peaking 200 mhz full ii 0.4 1.2 db output rolloff 200 mhz full ii 0 0.3 db group delay dc to 150 mhz +25 cv 0.7 ns linear phase deviation dc to 150 mhz +25 c v 0.7 degrees 2nd harmonic distortion 2 v p-p; 4.3 mhz full iv C80 C73 dbc 2 v p-p; 20 mhz full iv C66 C58 dbc 2 v p-p; 50 mhz full ii C52 C43 dbc 3rd harmonic distortion 2 v p-p; 4.3 mhz full iv C86 C79 dbc 2 v p-p; 20 mhz full iv C75 C68 dbc 2 v p-p; 50 mhz t min to +25 ii C47 C41 dbc 2 v p-p; 50 mhz t max ii C46 C40 dbc spectral input noise voltage 10 mhz +25 c v 2.4 nv/ ? hz integrated output noise 100 khz C 200 mhz +25 cv 32 m v time domain slew rate v out = 5 v step +25 c iv 700 1200 v/ m s rise/fall time v out = 1 v step +25 civ 1.11.7ns v out = 1 v step t min to t max iv 1.3 1.9 ns v out = 5 v step +25 civ 4.25.7ns v out = 5 v step t min to t max iv 5.0 6.5 ns overshoot amplitude v out = 2 v step full iv 2 12 % settling time to 0.1% v out = 2 v step t min to +25 iv 6 10 ns v out = 2 v step t max iv 7 12 ns to 0.02% 4 v out = 2 v step t min to +25 iv 8 ns v out = 2 v step t max v12ns differential gain 4.4 mhz +25 c v 0.015 % differential phase 4.4 mhz +25 c v 0.025 degree supply currents v cc (+i s )v cc = +5 v full ii 19 26 ma v ee (Ci s )v ee = C5 v full ii 19 26 ma notes 1 short-term settling with 50 w source impedance. specifications subject to change without notice. electrical characteristics (unless otherwise noted, 6 v s = 6 5 v; r in = 50 v , r load = 100 v ) obsolete
ad9630 C3C rev. b absolute maximum ratings 1 supply voltages ( v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v continuous output current 2 . . . . . . . . . . . . . . . . . . . . . 70 ma temperature range over which specifications apply ad9630an/ar . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c lead soldering temperature (10 sec) . . . . . . . . . . . . . +300 c storage temperature ad9630an/ar . . . . . . . . . . . . . . . . . . . . C65 c to +150 c junction temperature 3 ad9630an/ar . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 output is short-circuit protected to ground, but not to supplies. prolonged short circuit to ground may affect device reliability. 3 typical thermal impedances (part soldered onto board): plastic dip (n): q ja = 110 c/w; q jc = 30 c/w; soic (r): q ja = 155 c/w; q jc = 40 c/w. ordering guide temperature package package model range description option ad9630an C40 c to +85 c 8-lead plastic dip n-8 ad9630ar C40 c to +85 c 8-lead soic so-8 ad9630ar-reel C40 c to +85 c13 " tape and reel so-8 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9630 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. explanation of test levels test level i 100% production tested. ii 100% production tested at +25 c and sample tested at specified temperatures. ac testing of an and ar grades done on sample basis only. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v typical value. vi s versions are 100% production tested at temperature extremes. other grades are sample tested at extremes. 1 2 3 4 8 7 6 5 top view (not to scale) nc = no connect ad9630 nc nc nc nc 100 v (5%, 0.25w) 24 v (5%, 0.25w) +5v C5.2v 0.1 m f 0.1 m f ad9630 burn-in circuit theory of operation the ad9630 is a wide-bandwidth, closed-loop, unity-gain buffer that makes use of a new voltage-feedback architecture. this architecture brings together wide bandwidth and high slew rate along with exceptional dc linearity. most previous wide- bandwidth buffers achieved their bandwidth by utilizing an open-loop topology which sacrificed both dc linearity and fre- quency distortion when driven into low load impedances. the designs high loop correction factor radically improves dc lin- earity and distortion characteristics without diminishing bandwidth. this, in combination with high slew rate, results in exceptionally low distortion over a wide fre quency range. the ad9630 is an excellent choice to drive high speed and high resolution analog-to-digital converters. its output stage is de- signed to drive high speed flash converters with minimal or no series resistance. a current booster built into the output driver helps to maintain low distortion. parasitic or load capacitance (>7 pf) connected directly to the ad9630 output will result in frequency peaking. a small series resistor (r s ) connected between the buffer output and capaci- tive load will negate this effect. figure 1 shows the optimal value of r s as a function of c l to obtain the flattest frequency re- spon se. figure 2 illustrates frequency response for various capacitive loads utilizing the recommended r s . c l C pf 50 40 0 0 100 20 r series C v 40 60 80 30 20 10 7 r s c l 200 v "r" no r s needed when c l < 7pf; for c l > 30pf, "r" can be omitted figure 1. recommended r s vs. c l warning! esd sensitive device obsolete
ad9630 C4C rev. b in pulse mode applications, with r s equal to approximately 12 w , capacitive loads of up to 50 pf can be driven with mini- mal settling time degradation. the output stage has short circuit protection to ground. the output driver will shut down if more than approximately 130 ma of instantaneous sink or source current is reached. this level of current ensures that output clipping will not result when driving heavy capacitive loads during high slew conditions, although average load currents above 70 ma may reduce device reliability. layout considerations due to the high frequency operation of the ad9630 attention to board layout is necessary to achieve optimum dynamic perfor- mance. a two ounce copper ground plane on the top side of the board is recommended; it should cover as much of the board as possible with appropriate openings for supply decoupling ca- pacitors as well as for load and source termination resistors, (see figure 3). optimum settling time and ac performance results will be achieved with surface mount 0.1 m f supply decoupling ceramic chip capacitors mounted within 50 mils of the corresponding device pins with the other side soldered directly to the ground plane. for best high resolution (<0.02%) settling times, the op- tional power supply pins should be decoupled as shown above. if the optional power supply pins are not used, they should be left open. if surface mount capacitors cannot be used, radial lead ceramic capacitors with leads less than 30 mils long are recommended. low frequency power supply decoupling is necessary and can be accomplished with 4.7 m f tantalum capacitors mounted within 0.5 inches of the supply pins. due to the series inductance of these capacitors interacting with the 0.1 m f capacitors and power supply leads, high frequency oscillations might appear on c l 2 <0.1mhz frequency response C db 1 0 C1 C2 C3 C4 C5 C6 C7 C8 100mhz 200mhz 300mhz 10pf 25pf 50pf figure 2. frequency response vs. c l with recommended r s the device output. to avoid this occurrence, the power supply leads should be tightly twisted (if appropriate). ferrite beads mounted between the tantalum and ceramic capacitors will serve the same purpose. all unused pins (except the optional power supply pins) should be connected to ground to reduce pin-to-pin capacitive coupling and prevent external rf interference. if the source and drive electronics require remote operation (> 1 inch from the ad9630), the pc board line impedances should be matched with the buffer input and output resistances. basic microstrip techniques should be observed. r in and r s should be connected as close to the ad9630 as possible. with only minimal pulse overshoot and ringing, the ad9630 can drive terminated cables directly without the use of an output termination resistor (r s ). termination resistors (r s and r in ) can be either standard carbon composition or microwave type. for matching characteristic impedances, precision microwave resistors of 1% or better tolerance are preferred. the ad9630 should be soldered directly to the pc board with as little vertical clearance as possible. the use of zero insertion sockets is strongly discouraged because of the high effective pin inductances. use of this type socket will result in peaking and possibly induce oscillation. 8 1 6 ad9630 0.1 m f 5 2 * * 4.7 m f 0.1 m f 0.1 m f 0.1 m f 4.7 m f Cv s r in v in v out +v s r s ** *see pinouts **see figure 1 figure 3. ad9630 application circuit obsolete
ad9630 C5C rev. b typical performance curves C volts ppm 0 C1000 C3 C2 3 C1 0 1 2 C100 C600 C700 C800 C900 C200 C300 C500 C400 r l = 100 v r l = 200 v figure 4. endpoint dc linearity frequency C hz 50 0 1m 10m 1g 100m 10 20 40 psrr C db 30 figure 7. psrr vs. frequency phase gain v in = 100mv v in = 750mv v in = 100mv frequency C hz magnitude C db 2 C5 C8 0m 1g 200m 400m 600m 800m 1 C4 C6 C7 C2 C3 0 C1 0 C45 C90 C135 C180 phase C degrees figure 10 . forward gain and phase v frequency C hz 1m 100k 1 1m 1k 100 10 10k 10m 100m 1g figure 5. input impedance intercept C +dbm frequency C mhz 50 0 dc 250 50 100 150 200 20 10 30 40 50 v 50 v test circuit figure 8. 2-tone intermodulation distortion frequency C mhz magnitude C db 3 C4 C7 0 200 r l = 50 v r l = 100 v r l = 200 v 40 80 120 160 2 C3 C5 C6 C1 C2 1 0 figure 11. frequency response vs. r load v C |zo| frequency C hz 30 25 0 1m 10m 1g 100m 15 10 5 20 phase C degrees 100 80 40 20 0 60 |zo| figure 6. output impedance case temperature C 8 c 10 C10 C2 C4 C6 C8 C55 25 125 offset voltage C mv 50 40 C50 C10 C20 C30 C40 20 0 10 30 bias current C m a 8 4 0 2 6 bias current offset voltage figure 9. offset voltage and bias current vs. temperature figure 12. small-signal pulse response 2ns/division volts C0.25 50 v 6pf 50 v test circuit 0.5 C0.5 0 0.25 obsolete
ad9630 C6C rev. b C0.04 0.1 C0.08 0 0.04 0.08 0.06 0.02 C0.02 C0.06 C0.1 10 20 30 40 50 time C ns 100 v 6pf test circuit settling percentage C % v out = 2v step figure 13. short-term settling time dbc frequency C mhz 40 50 100 110 100 70 80 90 60 r l = 100 v 2nd 3rd figure 16. harmonic distortion v out = 4 v p-p settling percentage C % C0.04 0.1 C0.08 0 0.04 0.08 0.06 0.02 C0.02 C0.06 C0.1 10 100 1k 10k 100k time C ns v out = 2v step 1 100 v 6pf test circuit figure 14. long-term settling time dbc frequency C mhz 40 50 100 110 r l = 100 v 100 70 80 90 60 2nd 3rd figure 17. harmonic distortion v out = 2 v p-p C0.5 5ns/division volts 50 v 6pf 50 v test circuit 3.0 0 1.5 2.5 2.0 1.0 0.5 C1.0 C1.5 C2.0 C2.5 C3.0 figure 15. large-signal pulse response obsolete
ad9630 C7C rev. b outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 8 14 5 pin 1 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc 0.430 (10.92) 0.348 (8.84) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 8-lead soic (so-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 8 0 8 0.0196 (0.50) 0.0099 (0.25) 3 45 8 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) c1401aC0C12/99 (rev. b) printed in u.s.a. obsolete
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