integrated circuit systems, inc. general description av9154a-39 features block diagram low cost 16-pin frequency generator 9154 -39 rev b 09 / 18 / 97 pin configuration 16-pin soic the ics9154a-39 is a 0.8mm technology low-cost frequency generator designed for general purpose pc and disk drive applications. however, because the ics9154a-39 uses 0.8mm technology and the latest phase-locked loop architecture, it offers significant performance advantages that enable the device to be used in high performance systems when clock jitter is a key design issue. the ics9154a-39 guarantees a 45/55 duty cycle over all frequencies. in addition, a worst case jitter of 250ps is achieved. the cpu clock offers the unique feature of smooth, glitch- free transitions from one frequency to the next, making this the ideal device to use whenever slowing the cpu speed. the ics9154a-39 makes a gradual transition between frequencies. ? all loop filter components internal ? 5v operation ? 16-pin 150-mil soic ? power-down control of cpu clock and fixed clock when pd# goes low ? output enable control of all output pins product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. preliminary product preview
2 preliminary product preview av9154a-39 pin descriptions note: the following input pins are pulled-up to vdd internal: 9, 10, 15 and 16. these frequencies assume an input frequency of 10.0 mhz. pin number pin name type description 1 8.33 mhz out 8.33 mhz output clock.* 2 x2 out crystal out. 3 x1 in crystal in, nominally 10.0 mhz. 4 vdd pwr digital power (+5v). 5 gnd pwr digital ground. 6 100 mhz out 100 mhz clock output.* 7 10 mhz out 10 mhz keyboard clock output.* 8 agnd pwr analog ground. 9 oe in tristates outputs when low. 10 fs0 in frequency select 0 for cpu clock. 11 nc - no connect (do not connect to this pin.). 12 gnd pwr digital ground. 13 vdd pwr digital power (+5v). 14 cpuclk out cpu clock output. 15 fs1 in frequency select 1 for cpu clock. 16 pd# in power-down, shuts off internal clocks and forces outputs to low logic level when input pulled logic low. functionality fs1 fs0 clk(mhz) 0 0 40.0 0 1 30.0 1 0 37.0 1 1 25.0
3 preliminary product preview av9154a-39 electrical characteristics at 5v absolute maximum ratings vdd referenced to gnd . . . . . . . . . . . . . . . . . . . . . . 7v voltage on i/o pins referenced to gnd. . . . . . . . . . . gnd -0.5v to vdd +0.5v operating temperature under bias. . . . . . . . . . . . . . . . 0c to +70c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 watts storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. v dd = +5v10%, t a =0c to 70c notes: 1. parameter is guaranteed by design and characterization, not subject to production testing. dc characteristics parameter symbol test conditions min typ max units input low voltage v il 0.8 v input high voltage v ih 2.0 v input low current i il v in =0v -35 -16.0 a input high current i ih v in =v dd -5 5 a output low voltage v ol i ol =10ma 0.15 0.4 v output high voltage 1 v oh i oh =-30ma 2.4 3.7 v output low current 1 i ol v ol =0.8 15 32 ma output high current 1 i oh v oh =2.0v -48 -30 ma supply current i dd unloaded, 40 mhz 25 50 ma output frequency change over supply and temperature 1 f d with respect to typical frequency 0.002 0.01 % input capacitance 1 c i except x1, x2 10 pf load capacitance 1 c l pins x1, x2 20 pf
4 preliminary product preview av9154a-39 electrical characteristics at 5v v dd = +5v10%, t a =0c to 70c note: crystal load capacitors are internal to the ics9154a-39 device and no external components are required. notes: 1. parameter is guaranteed by design and characterization, not subject to production testing. figure 1: typical crystal circuitry ics9154a-39 ac characteristics parameter symbol test conditions min typ max units input clock rise time 1 ticr 20 ns input clock fall time 1 ticf 20 ns output rise time 1 tr 15pf load, 0.8 to 2.0v - 0.8 2 ns rise time 1 tr 15pf load, 20% to 80% vdd -1.43ns output fall time 1 tf 15pf load, 2.0 to 0.8v - 0.7 2 ns fall time 1 tf 15pf load, 80% to 20% vdd -0.82ns duty cycle 1 dt 15pf load @ 1.4v 45 55 % duty cycle, reference clocks 1 dt 15pf load @ 1.4v 40 60 % jitter, one sigma, 32 mhz-100 mhz clocks 1 tjls 80 120 ps jitter, one sigma, 16 mhz-30 mhz clocks 1 tjls 100 150 ps jitter, one sigma, clocks below 16 mhz 1 tjls 400 500 ps jitter, absolute, 32 mhz-100 mhz clocks 1 tjab -250 250 ps jitter, absolute, 16-30 mhz clock 1 tjab -700 700 ps jitter, absolute, clocks below 16 mhz 1 tjab -2 2 ns input frequency 1 fin 10.0 mhz power-up time 1 tpo to 100 mhz 10 20 ms frequency transition time 1 tft from 25.0 to 40.0 mhz 8 ms
5 preliminary product preview av9154a-39 ordering information AV9154A-39CS16 example: xxx xxxx-ppp m x#w 16-pin soic package lead count & package width lead count=1, 2 or 3 digits w=.3? soic or .6? dip; none=standard w idth package type s=soic pattern number (2 or 3 digit number for parts with rom code patterns) device t ype (consists of 3 or 4 digit numbers) prefix ics, av=s tandard device; gsp=genlock device product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice.
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