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10-bit, 170/200 msps 3.3 v a/d converter data sheet ad9411 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2012 analog devices, inc. all rights reserved. features snr = 60 db @ f in up to 70 mhz @ 200 msps enob of 9.8 @ f in up to 70 mhz @ 200 msps (C0.5 dbfs) sfdr = 80 dbc @ f in up to 70 mhz @ 200 msps (C0.5 dbfs) excellent linearity: dnl = 0.15 lsb (typical) inl = 0.25 lsb (typical) lvds output levels 700 mhz full-power analog bandwidth on-chip reference and track-and-hold power dissipation = 1.25 w typical @ 200 msps 1.5 v input voltage range 3.3 v supply operation output data format option clock duty cycle stabilizer pin compatible to lvds mode ad9430 applications wireless and wired broadband communications cable reverse path communications test equipment radar and satellite subsystems functional block diagram ad9411 sense vref vin+ vin? clk+ clk? s1 s5 dco+ dco? scalable reference lvds outputs data, overrange in lvds track and hold lvds timing clock management adc 10-bit pipeline core 10 / agnd drgnd drvdd avdd 04530-0-001 figure 1. power amplifier linearization general description the ad9411 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. the product operates up to a 200 msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. all necessary functions, including track-and-hold (t/h) and reference, are included on the chip to provide a complete conversion solution. the adc requires a 3.3 v power supply and a differential sample clock for full performance operation. the digital outputs are lvds compatible and support both twos complement and offset binary format. a data clock output is available to ease data capture. fabricated on an advanced bicmos process, the ad9411 is available in a 100-lead surface-mount plastic package (e-pad tqfp-100) specified over the industrial temperature range (C40c to +85c). product highlights 1. high performance. maintains 60 db snr @ 200 msps with a 70 mhz input. 2. low power. consumes only 1.25 w @ 200 msps. 3. ease of use. lvds output data and output clock signal allow interface to current fpga technology. the on-chip reference and sample-and-hold function provide flexibility in system design. use of a single 3.3 v supply simplifies system power supply design. 4. out-of-range (or). the or output bit indicates when the input signal is beyond the selected input range. obsolete
ad9411 data sheet rev. b | page 2 of 28 table of contents dc specifications ............................................................................. 3 ? ac specifications .............................................................................. 4 ? digital specifications ........................................................................ 5 ? switching specifications .................................................................. 6 ? explanation of test levels ........................................................... 6 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? terminology .................................................................................... 10 ? equivalent circuits ......................................................................... 12 ? typical performance characteristics ........................................... 13 ? application notes ........................................................................... 18 ? clock input .................................................................................. 18 ? analog input ............................................................................... 18 ? lvds outputs ............................................................................. 19 ? clock outputs (dco+, dcoC) ............................................... 19 ? voltage reference ....................................................................... 19 ? noise power ratio testing (npr) ............................................ 19 ? evaluation board ............................................................................ 21 ? power connector ........................................................................ 21 ? analog inputs ............................................................................. 21 ? gain .............................................................................................. 21 ? clock ............................................................................................ 21 ? voltage reference ....................................................................... 21 ? data format select ..................................................................... 21 ? data outputs ............................................................................... 21 ? clock xtal ............................................................................ 21 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 1/12data sheet changed from rev. a to rev. b added exposed pad notation to figure 3 ..................................... 8 added pin 55 to table 6 ................................................................... 9 changes to ordering guide .......................................................... 27 7/04data sheet changed from rev. 0 to rev. a added 200 msps grade .................................................... universal updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 27 1/04revision 0: initial version obsolete
data sheet ad9411 rev. b | page 3 of 28 dc specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, unless otherwise noted. table 1. ad9411-170 ad9411-200 parameter temp test level min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full vi guaranteed guaranteed offset error 25c i C3 +3 C3 +3 mv gain error 25c i C5 +5 C5 +5 % fs differential nonlinearity (dnl) 25c i C0.5 0.15 +0.5 C0.5 0.15 +0.5 lsb full vi C0.6 0.25 +0.6 C0.6 0.25 +0.6 lsb integral nonlinearity (inl) 25c i C0.8 0.5 +0.8 C0.8 0.5 +0.8 lsb full vi C1 0.5 +1 C1 0.5 +1 lsb temperature drift offset error full v 58 58 v/c gain error full v 0.02 0.02 %/c reference out (vref) full v +0.12/ C0.24 +0.12/ C0.24 mv/c reference reference out (vref) 25c i 1.15 1.235 1.3 1.15 1.235 1.3 v output current 1 25c iv 3.0 3.0 ma i vref input current 2 25c i 20 20 ma i sense input current 2 25c i 1.6 5.0 1.6 5.0 ma analog inputs (vin+, vinC) 3 differential input voltage range (s5 = gnd) full v 1.536 1.536 v differential input voltage range (s5 = avdd) full v 0.766 0.766 v input common-mode voltage full vi 2.65 2.8 2.9 2.65 2.8 2.9 v input resistance full vi 2.2 3 3.8 2.2 3 3.8 k input capacitance 25c v 5 5 pf power supply (lvds mode) avdd full iv 3.1 3.3 3.6 3.2 3.3 3.6 v drvdd full iv 3.0 3.3 3.6 3.0 3.3 3.6 v supply currents i analog (avdd = 3.3 v) 4 full vi 335 372 385 425 ma i digital (drvdd = 3.3 v) 4 full vi 49 57 49 57 ma power dissipation 4 full vi 1.27 1.42 1.43 1.59 w power supply rejection 25c v C7.5 C7.5 mv/v 1 internal reference mode; sense = floats. 2 external reference mode; sense = drvdd; vref driven by external 1.23 v reference. 3 s5 (pin 1) = gnd. see the analog input section. s5 = gnd in all dc, ac tests, unless otherwise specified 4 i avdd and i drvdd are measured with an analog input of 10.3 mhz, C0.5 dbfs, sine wave, rated clock rate, and in lvds output mode. see the typical performance characteristics and applicat ion notes sect ions for i drvdd . power consumption is measured with a dc inpu t at rated clock rate in lvds output mode. obsolete
ad9411 data sheet rev. b | page 4 of 28 ac specifications 1 avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, unless otherwise noted. table 2. ad9411-170 ad9411-200 parameter temp test level min typ max min typ max unit snr analog input @ C0.5 dbfs 10 mhz 25c i 59 60.2 59 60.2 db 70 mhz 25c i 59 60.1 59 60.1 db 100 mhz 25c v 60 60 db 240 mhz 25c v 59.1 59.1 db sinad analog input @ C0.5 dbfs 10 mhz 25c i 58.5 60 58.5 60 db 70 mhz 25c i 58.5 60 58.5 60 db 100 mhz 25c v 59.5 59.5 db 240 mhz 25c v 57.5 57.5 db effective number of bits (enob) 10 mhz 25c i 9.5 9.8 9.5 9.8 bits 70 mhz 25c i 9.5 9.8 9.5 9.8 bits 100 mhz 25c v 9.7 9.7 bits 240 mhz 25c v 9.3 9.3 bits worst harmonic (second or third) analog input @ C0.5 dbfs 10 mhz 10 mhz 25c i C80 C73 C80 C70 dbc 70 mhz 25c i C80 C73 C80 C70 dbc 100 mhz 25c v ?74 ?74 dbc 240 mhz 25c v ?69 ?69 dbc worst harmonic (fourth or higher) analog input @ C0.5 dbfs 10 mhz 10 mhz 25c i C82 C75 C82 C75 dbc 70 mhz 25c i C82 C75 C82 C75 dbc 100 mhz 25c v ?76 ?76 dbc 240 mhz 25c v ?70 ?70 dbc two-tone imd 2 f1, f2 @ C7 dbfs 25c v 70 70 dbc analog input bandwidth 25c v 700 700 mhz 1 all ac specifications tested by driving clk+ and clkC differentially. 2 f1 = 30.5 mhz, f2 = 31 mhz. obsolete
data sheet ad9411 rev. b | page 5 of 28 digital specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, unless otherwise noted. table 3. ad9411-170 ad9411-200 parameter temp test level min typ max min typ max unit clock inputs (clk+, clkC) 1 differential input voltage 2 full iv 0.2 0.2 v common-mode voltage 3 full vi 1.375 1.5 1.575 1.375 1.5 1.575 v input resistance full vi 3.2 5.5 6.5 3.2 5.5 6.5 k input capacitance 25c v 4 4 pf logic inputs (s1, s2, s4, s5) logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v logic 1 input current full vi 190 190 a logic 0 input current full vi 10 10 a input resistance 25c v 30 30 k input capacitance 25c v 4 4 pf lvds logic outputs 4 v od differential output voltage full vi 247 454 247 454 mv v os output offset voltage full vi 1.125 1.375 1.125 1.375 v output coding twos complement or binary twos complement or binary 1 see the equivalent circuits section. 2 all ac specifications tested by driving clk+ and clkC differentially, |(clk+) C (clkC)| > 200 mv. 3 clock inputs common mode can be externally set, such that 0.9 v < clk ?? < 2.6 v. 4 lvds r term = 100 , lvds output current set resistor (r set ) = 3.74 k ? (1% tolerance). obsolete
ad9411 data sheet rev. b | page 6 of 28 switching specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, unless otherwise noted. table 4. ad9411-170 ad9411-200 parameter (conditions) temp test level min typ max min typ max unit maximum conversion rate 1 full vi 170 200 msps minimum conversion rate 1 full v 40 40 msps clk+ pulse width high (t eh ) 1 full iv 2 12.5 2 12.5 ns clk+ pulse width low (t el ) 1 full iv 2 12.5 2 12.5 ns output (lvds mode) valid time (t v ) full vi 2.0 2.0 ns propagation delay (t pd ) full vi 3.2 4.3 3.2 4.3 ns rise time (t r ) (20% to 80%) 25c v 0.5 0.5 ns fall time (t f ) (20% to 80%) 25c v 0.5 0.5 ns dco propagation delay (t cpd ) full vi 1.8 2.7 3.8 1.8 2.7 3.8 ns data to dco skew (t pd Ct cpd ) full iv 0.2 0.5 0.8 0.2 0.5 0.8 ns latency full iv 14 14 cycles aperture delay (t a ) 25c v 1.2 1.2 ns aperture uncertainty (jitter, t j ) 25c v 0.25 0.25 ps rms out-of-range recovery time 25c v 1 1 cycles 1 all ac specifications tested by driving clk+ and clkC differentially. explanation of test levels i. 100% production tested. ii. 100% production tested at 25c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25c; guaranteed by design and char acterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. clk+ a in t eh t el t pd t cpd 1/f s dco+ dco? n?1 n?14 n?13 n 14 cycles n+1 n+1 n clk? data out 04530-0-002 figure 2. lvds timing diagram obsolete
data sheet ad9411 rev. b | page 7 of 28 absolute maximum ratings table 5. parameter rating avdd, drvdd 4 v analog inputs C0.5 v to avdd +0.5 v digital inputs C0.5 v to drvdd +0.5 v refin inputs C0.5 v to avdd +0.5 v digital output current 20 ma operating temperature C55oc to +125c storage temperature C65oc to +150c maximum junction temperature 150c maximum case temperature 150c ja 1 25c/w, 32c/w 1 typical ja = 32c/w (heat slug not soldered); typical ja = 25c/w (heat slug soldered) for multilayer board in still air with solid ground plane. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside of those indicated in the operation section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. obsolete
ad9411 data sheet rev. b | page 8 of 28 pin configuration and fu nction descriptions 04530-0-003 s5 dnc agnd agnd agnd avdd avdd avdd agnd agnd agnd avdd avdd agnd clk+ clk? agnd avdd avdd agnd dnc dnc dnc dnc dnc drvdd drgnd dnc dnc agnd avdd avdd agnd agnd avdd avdd agnd agnd agnd avdd avdd avdd agnd agnd or+ or? dvrdd drgnd d9+ d9? d8+ d8? d7+ d7? avdd s1 lvdsbias avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vin? agnd avdd agnd drvdd drgnd d6+ d6? d5+ d5? d4+ d4? drgnd d3+ d3? dco+ dco? drvdd drgnd d2+ d2? d1+ d1? d0+ d0? drvdd drgnd dnc dnc ad9411 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 notes 1. the ad9411 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. figure 3. tqfp_ep pinout obsolete
data sheet ad9411 rev. b | page 9 of 28 table 6. pin function descriptions pin no. mnemonic function 1 s5 full-scale adjust pin. avdd sets fs = 0.768 v p-p differential; gnd sets fs = 1.536 v p-p differential. 2, 42C46,49C52 dnc do not connect. 3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 agnd analog ground. agnd and drgnd shou ld be tied together to a common ground plane. 5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 avdd 3.3 v analog supply. 6 s1 data format select. gnd = binary; avdd = twos complement. 7 lvdsbias set pin for lvds output current. place a 3.74 k resistor terminated to ground. 10 sense reference mode select pin. float for internal reference operation. 11 vref 1.235 v reference input/outp ut. function depends on sense. 21 vin+ analog input. true. 22 vinC analog input. complement. 36 clk+ clock input. true (lvpecl levels). 37 clkC clock input. complement (lvpecl levels). 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd digital output ground. agnd and drgn d should be tied together to a common ground plane. 55 d0C d0 complement output bit. 56 d0+ d0 true output bit. 57 d1C d1 complement output bit. 58 d1+ d1 true output bit. 59 d2C d2 complement output bit. 60 d2+ d2 true output bit. 63 dcoC data clock output. complement. 64 dco+ data clock output. true. 65 d3C d3 complement output bit. 66 d3+ d3 true output bit. 68 d4C d4 complement output bit. 69 d4+ d4 true output bit. 70 d5C d5 complement output bit. 71 d5+ d5 true output bit. 72 d6C d6 complement output bit. 73 d6+ d6 true output bit. 76 d7C d7 complement output bit. 77 d7+ d7 true output bit. 78 d8C d8 complement output bit. 79 d8+ d8 true output bit. 80 d9C d9 complement output bit. 81 d9+ d9 true output bit. 84 orC overrange complement output bit. 85 or+ overrange true output bit. obsolete
ad9411 data sheet rev. b | page 10 of 28 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the clock command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. crosstalk coupling onto one channel being driven by a low level (C40 dbfs) signal when the adjacent interfering channel is driven by a full- scale signal. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 and again taking the peak measurement. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) calculated from the measured snr based on the equation 02.6 db76.1 ? ? measured snr enob clock pulse width/duty cycle pulse width high is the minimum amount of time the clock pulse should be left in the logic 1 state to achieve rated performance; pulse width low is the minimum time the clock pulse should be left in the low state. refer to the timing implications of changing t ench in the application notes, clock input section. at a given clock rate, these specifications define an acceptable clock duty cycle. full-scale input power expressed in dbm. computed using the following equation: ? ? ? ? ? ? ? ? ? ? ? ? ? 001.0 log10 2 input rms fullscale fullscale z v power gain error the difference between the measured and ideal full-scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of clk+ and clkC and the time when all output data bits are within valid logic levels. obsolete
data sheet ad9411 rev. b | page 11 of 28 noise (for any range within the adc) calculated as follows: ? ? ? ? ? ? ?? ??? 10 10001.0 dbfs dbc dbm noise signal snr fs zv where z is the input impedance, fs is the full scale of the device for the frequency in question, snr is the value of the particular input level, and signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered) or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dbc. transient resp onse time the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. obsolete
ad9411 data sheet rev. b | page 12 of 28 equivalent circuits 04530-0-004 12k ? 150 ? 150 ? 12k ? 10k ? 10k ? clk+ avdd clk? figure 4. clock inputs avdd 3.5k ? 3.5k ? 20k ? 20k ? vin+ vin? 04530-0-005 figure 5. analog inputs vdd 30k ? s1,s5 04530-0-006 figure 6. s1 to s5 inputs 04530-0-007 vref k a1 disable a1 sense vdd 200 ? 1v 0.1 ? f full scale 1k ? figure 7. vref, sense i/o 04530-0-008 v+ v+ dx+ drvdd dx? v? v? figure 8. data outputs obsolete
data sheet ad9411 rev. b | page 13 of 28 typical performance characteristics ?120 ?100 ?80 ?90 ?110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 4030 10 20 0 50607080 mhz 04530-0-009 snr = 60.1db sinad = 59.9db h2 = ?91.3dbc h3 = ?75.2dbc sfdr = 75.3dbc figure 9. fft: fs = 170 msps, ain = 10.3 mhz @ ?0.5 dbfs 40 30 10 20 0 50607080 ?120 ?100 ?80 ?90 ?110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 mhz 04530-0-010 snr = 59.8db sinad = 59.8db h2 = ?91.9dbc h3 = ?80.6dbc sfdr = 73.2dbc figure 10. fft: fs = 170 msps, ain = 65 mhz @ C0.5 dbfs 4030 10 20 0 50607080 ?120 ?100 ?80 ?90 ?110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 mhz 04530-0-011 snr = 59.2db sinad = 59.1db h2 = ?70.1dbc h3 = ?87.0dbc sfdr = 69.8dbc figure 11. fft: fs = 170 msps, ain = 10.3, mhz @ C0.5 dbfs, single-ended input, 0.76 v input range 04530-a-001 mhz 100 02 0 10 4030 6050 80 90 70 db 0 ?20 ?10 ?40 ?30 ?60 ?50 ?80 ?70 ?100 ?90 ?110 ?120 snr = 59.7db sinad = 59.5db h2 = ?83.6dbc h3 = ?72.6dbc sfdr = 72.5dbc figure 12. fft: fs = 200 msps, ain = 10.3 mhz @ ?0.5 dbfs 04530-a-002 mhz 100 02 03 0 10 40 50 60 70 80 90 db 0 ?20 ?10 ?40 ?30 ?60 ?50 ?80 ?70 ?100 ?90 ?120 ?110 snr = 59.5db sinad = 59.4db h2 = ?82.5dbc h3 = ?72.8dbc sfdr = 72.7dbc figure 13. fft: fs = 200 msps, ain = 65 mhz @ ?0.5 dbfs 04530-a-003 mhz 100 02 0 10 4030 6050 80 90 70 db 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 snr = 50.6db sinad = 43.8db h2 = ?44.8dbc h3 = ?67.4dbc sfdr = 43.6dbc figure 14. fft: fs = 200 msps, ain = 70 mhz @ ?0.5 dbfs, single-ended drive, 1.5 v input range obsolete
ad9411 data sheet rev. b | page 14 of 28 40 50 60 70 80 90 100 db 200 150 50 100 0 250 300 350 400 a in (mhz) 04530-0-015 third sfdr second figure 15. harmonic distortion (second and third) and sfdr vs. ain frequency @ 170 msps 04530-a-006 (mhz) 400 0 50 100 150 200 250 300 350 (db) 100 90 80 70 60 50 40 third second sfdr figure 16. harmonic distortion (second and third) and sfdr vs. ain frequency @ 200 msps 04530-a-007 (mhz) 450 0 50 100 150 200 250 300 350 400 (db) 61 59 57 55 53 51 49 47 45 snr_200 snr_170 sinad_200 sinad_170 figure 17. snr and sinad vs. ain frequency; fs = 170/200 msps, ain @ C0.5 dbfs full scale = 1.536 v ?120 ?100 ?80 ?90 ?110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 4030 10 20 0 50607080 mhz 04530-0-019 sfdr = 71.5dbc figure 18. two-tone intermodulation distortion (30.5 mhz and 31.0 mhz; fs = 170 msps) 04530-a-004 (mhz) 100 0 2040608090 10 30 50 70 (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 sfdr = 78.8dbc figure 19. two-tone intermodulation distortion (69.3 mhz and 70.3 mhz; fs = 200 msps) 04530-a-008 (msps) 250 0 50 100 150 200 (db) 80 70 75 65 55 60 50 45 40 sfdr_170 sfdr_200 sinad_170 sinad_200 figure 20. sinad and sfdr vs. clock rate (ain = 10.3 mhz @ C0.5 dbfs) 170/200 grade obsolete
data sheet ad9411 rev. b | page 15 of 28 0 10 20 30 40 50 60 70 80 90 i drvdd output supply current (ma) 0 50 100 150 200 250 300 350 400 450 i avdd analog supply current (ma) 100 120 140 160 180 200 220 240 encode (msps) 04530-2-023 output supply current analog supply current figure 21. iavdd and idrvdd vs. clock rate, 170 msps grade, cload = 5 pf (ain = 10.3 mhz @ C0.5 dbfs) 04530-a-009 sample rate (msps) 240 100 120 140 180 160 200 220 i drvdd output supply current (ma) 0 90 80 70 60 50 40 30 20 10 i avdd analog supply current (ma) 450 400 350 300 250 200 150 100 50 0 output supply current analog supply current figure 22. iavdd and idrvdd vs. clock rate, 200 msps grade, cload = 5 pf (ain = 10.3 mhz @ C0.5 dbfs) 55 57 59 61 63 65 67 69 71 73 75 db 20 30 40 50 60 70 80 90 encode positive duty cycle (%) 04530-0-025 sfdr snr sinad figure 23. sinad and sfdr vs. clock pulse width high (ain = 10.3 mhz @ C0.5 dbfs, 170 msps) 04530-a-010 sample clock positive duty cycle 80 20 30 40 50 60 70 (db) 80 75 70 65 60 55 50 sfdr snr sinad figure 24. sinad and sfdr vs. clock pulse width high (ain = 10.3 mhz @ C0.5 dbfs, 200 msps) 04530-a-016 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v ref (v) 43 12 05678 i load (ma) r o = 13 ? typ figure 25. vrefout vs. iload (both speed grades) 04530-a-011 v ref (v) 1.5 0.5 0.7 0.9 1.1 1.3 (db) 80 75 70 65 60 55 50 sfdr sinad figure 26. sinad, sfdr vs. vref in external reference mode (ain = 70 mhz @ C0.5 dbfs, 200 msps) obsolete
ad9411 data sheet rev. b | page 16 of 28 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 gain error (%) 1.0 1.5 2.0 ?50 ?30 ?10 10 30 50 70 90 temperature (c) 04530-0-028 % gain error using ext ref figure 27. full-scale gain error vs. temperature (ain = 10.3 mhz @ C0.5 dbfs, 170/200 msps) 04530-a-012 temperature (c) 80 ?40?200 204060 (db) 60 59 58 57 56 55 avdd = 3.0v avdd = 3.15v avdd = 3.3v avdd = 3.6v figure 28. sinad vs. temperature and avdd (ain = 10.3 mhz @ C0.5 dbfs, 200 msps) 04530-0-029 1.225 1.230 1.235 1.240 1.245 1.250 v refout (v) 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 avdd (v) figure 29. vref output voltage vs. avdd (both speed grades) 50 55 60 65 70 75 db 80 85 90 ?50 ?30 ?10 10 30 50 70 90 temperature (c) 04530-0-030 sfdr snr sinad figure 30. snr, sinad, and sfdr vs. temperature (ain = 10.3 mhz @ C0.5 dbfs, 170 msps) ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 lsb 0.50 0.75 1.00 0 100 200 300 400 500 600 700 800 900 1000 code 04530-0-032 figure 31. typical inl plot (ain = 10.3 mhz @ C0.5 dbfs, 170/200 msps) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 lsb 0 100 200 300 400 500 600 700 800 900 1000 code 04530-0-033 figure 32. typical dnl plot (ain = 10.3 mhz @ C0.5 dbfs) 170/200 msps obsolete
data sheet ad9411 rev. b | page 17 of 28 0 10 30 70 90 110 50 20 60 80 100 40 db ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 analog input level (dbfs) 04530-0-034 sfdr ?dbfs sfdr ?dbc 80db reference line figure 33. sfdr vs. ain input level 10.3 mhz, ain @ 170 msps 04530-a-013 analog input level (dbfs) 0 ?70 ?60 ?50 ?40 ?30 ?20 ?10 db 90 80 70 60 50 40 30 20 10 0 70db reference line sfdr ?dbc sfdr ?dbfs figure 34. sfdr vs. ain input level 70 mhz, ain @ 200 msps ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 noise level (db) 04530-0-035 mhz 10 0203040 npr = 51.2db encode = 170msps notch @ 18.15mhz figure 35. noise power ratio plot (170 msps grade) 04530-a-005 mhz 40 0 5 10 15 20 25 30 35 db 0 ?20 ?40 ?60 ?80 ?100 ?120 npr = 51 db clk = 200msps notch at 18.5mhz figure 36. noise power ratio plot (200 msps grade) ns 2.5 3.0 3.5 4.0 4.5 04530-0-036 ?40 ?20 0 20 40 60 80 100 temperature (c) t pd t cpd figure 37. propagation delay vs. temperature (both speed grades) 0 100 200 300 400 500 600 700 800 900 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 v dif (mv) v os (v) 04530-0-037 02468101214 rset (k ?? v os v od figure 38. lvds output swing, common-mode voltage vs. rset, placed at lvdsbias (both speed grades) obsolete
ad9411 data sheet rev. b | page 18 of 28 application notes the ad9411 architecture is optimized for high speed and ease of use. the analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantiza- tion by the 10-bit core. for ease of use, the part includes an on- board reference and input logic that accepts ttl, cmos, or lvpecl levels. the digital outputs logic levels are lvds (ansi-644) compatible. clock input any high speed a/d converter is extremely sensitive to the quality of the sampling clock provided by the user. a track-and- hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the a/d output. for this reason, considerable care has been taken in the design of the clock inputs of the ad9411, and the user is advised to give careful thought to the clock source. th e ad9411 has an internal clock duty cycle stabilization circuit that locks to the rising edge of clk+ and optimizes timing internally. this allows a wide range of input duty cycles at the input without degrading performance. jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 30 mhz nominally. the time constant associated with the loop should be considered in applications where the clock rate changes dynamically, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase before valid data is available. this circuit is always on and cannot be disabled by the user. the clock inputs are internally biased to 1.5 v (nominal) and support either differential or single-ended signals. for best dynamic performance, a differential signal is recommended. an mc100lvel16 performs well in the circuit to drive the clock inputs, as illustrated in figure 39. note that for this low voltage pecl device, the ac coupling is optional. 04530-a-017 ad9411 clk+ 0.1? f 0.1? f 510 ? 510 ? pecl gate clk? figure 39. driving clock inputs with lvel16 table 7. output select coding 1 s1 ( data format select) s5 (full-scale select) 2 mode 1 x twos complement 0 x offset binary x 1 full scale = 0.768 v x 0 full scale = 1.536 v 1 x = dont care. 2 s5 full-scale adjust (refer to the analog input section). analog input the analog input to the ad9411 is a differential buffer. for best dynamic performance, impedances at vin+ and vinC should match. the analog input is optimized to provide superior wide- band performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades signifi- cantly if the analog input is driven with a single-ended signal. a wideband transformer, such as mini-circuits adt1-1wt, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 2.8 v (refer to the equivalent circuits section). note that the input common-mode can be overdriven by approximately +/?150 mv around the self-bias point, as shown in figure 42. special care was taken in the design of the analog input section of the ad9411 to prevent damage and corruption of data when the input is overdriven. the nominal differential input range is approximately 1.5 v p-p ~ (768 mv 2). note that the best performance is achieved with s5 = 0 (full-scale = 1.5). see figure 40 and figure 41. 04530-0-041 s5 = gnd vin+ 2.8v 768mv 2.8v vin? digitalout = all 1s digitalout = all 0s figure 40. differential analog input range obsolete
data sheet ad9411 rev. b | page 19 of 28 04530-0-042 s5 = avdd vin+ 2.8v 768mv 2.8v vin? = 2.8v figure 41. single-ended analog input range 04530-a-014 analog input common mode (v) 3.2 2.0 2.2 2.4 2.6 2.8 3.0 db 61 60 59 58 57 56 sinad figure 42. sinad sensitivity to analog input common-mode voltage, (ain = ?.5 dbfs differential drive, s5 = 0) lvds outputs the off-chip drivers provide lvds compatible output levels. a 3.74 k rset resistor placed at pin 7 (lvdsbias) to ground sets the lvds output current. the rset resistor current is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 ma (11 irset). a 100 differential termi- nation resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. lvds mode facilitates interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point network topologies are recommended with a 100 termination resistor as close to the receiver as possible. it is recommended to keep the trace lengths < 4 inches and to keep differential output trace lengths as equal as possible. clock outputs (dco+, dcoC) the input clock is buffered on-chip and available off-chip at dco+ and dcoC. these clocks can facilitate latching off-chip, providing a low skew clocking solution (see figure 2). the on- chip clock buffers should not drive more than 5 pf of capacitance to limit switching transient effects on performance. the output clocks are lvds signals requiring 100 differential termination at receiver. voltage reference a stable and accurate 1.23 v voltage reference is built into the ad9411 (vref). the analog input full-scale range is linearly proportional to the voltage at vref. note that an external reference can be used by connecting the sense pin to vdd (disabling internal reference) and driving vref with the external reference source. no appreciable degradation in performance occurs when vref is adjusted 5%. a 0.1 f capacitor to ground is recommended at the vref pin in internal and external reference applications. float the sense pin for internal reference operation. 04530-0-043 vref k a1 disable a1 sense vdd 200 ? 1v 3.3v external 1.23v reference 0.1? f full scale s5 = 0 k = 1.24 s5 = 1 k = 0.62 1k ? figure 43. using an external reference noise power ratio testing (npr) npr is a test that is commonly used to characterize the return path of cable systems where the signals are typically qam sig- nals with a noise-like frequency spectrum. npr performance of the ad9411 was characterized in the lab yielding an effective npr = 51.2 db at an analog input of 18 mhz. this agrees with a theoretical maximum npr of 51.6 db for a 10-bit adc at 13 db backoff. the rms noise power of the signal inside the notch is compared with the rms noise level outside the notch using an fft. this test requires sufficiently long record lengths to guarantee a large number of samples inside the notch. a high- order band-stop filter that provides the required notch depth for testing is also needed. obsolete
ad9411 data sheet rev. b | page 20 of 28 04530-0-044 ad9411 evaluation board avdd gnd gnd gnd vdl drvdd 3.3v 3.3v 3.3v +++ signal generator band-pass filter data capture and processing analog j4 clock j5 signal generator refin 10mhz refout figure 44. evaluation board connections obsolete
data sheet ad9411 rev. b | page 21 of 28 evaluation board the ad9411 evaluation board offers an easy way to test the ad9411 in lvds mode. it requires a clock source, an analog input signal, and a 3.3 v power supply. the clock source is buffered on the board to provide the clocks for the adc, latches, and a data-ready signal. the digital outputs and output clocks are available at a 40-pin connector, p23. the board has several different modes of operation and is shipped in the following configurations: ? offset binary ? internal voltage reference ? full-scale adjust = low power connector power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). table 8. power connector, lvds mode avdd 1 3.3 v analog supply for adc (350 ma) drvdd 1 3.3 v output supply for adc (50 ma) vdl 1 3.3 v supply for support logic vclk/v_xtal supply for cloc k buffer/optional xtal ext_vref 2 optional external reference input 1 avdd, drvdd, and vdl are the min imum required po wer connections. 2 lvel16 clock buffer can be powered from avdd or vclk at e47 jumper. analog inputs the evaluation board accepts a 1.3 v p-p analog input signal centered at ground at smb connector j4. this signal is terminated to ground through 50 by r16. the input can be alternatively terminated at the t1 transformer secondary by r13 and r14. t1 is a wideband rf transformer that provides a single-ended-to-differential conversion, allowing the adc to be driven differentially, which minimizes even-order harmonics. an optional second transformer, t2, can be placed following t1 if desired. this provides some performance advantage (~1 db to 2 db) for high analog input frequencies (>100 mhz). if t2 is placed, cut the two shorting traces at the pads. the analog signal can be low-pass filtered by r41, c12 and r42, c13 at the adc input. the footprint for transformer t2 can be modified to accept a wideband differential amplifier (ad8351) for low frequency applications where gain is required. see the pcb schematic for more information. gain full scale is set at e17Ce19, e17Ce18 sets s5 low, full scale = 1.5 v differential; e17Ce19 sets s5 high, full scale = 0.75 v differential. best performance is obtained at 1.5 v full scale. clock the clock input is terminated to ground through 50 resistor at smb connector j5. the input is ac-coupled to a high speed differential receiver (lvel16) that provides the required low jitter, fast edge rates needed for optimum performance. j5 input should be > 0.5 v p-p. power to the lvel16 is set at jumper e47. e47Ce45 powers the buffer from avdd; e47Ce46 powers the buffer from vclk/v_xtal. voltage reference the ad9411 has an internal 1.23 v voltage reference. the adc uses the internal reference as the default when jumpers e24Ce27 and e25Ce26 are left open. the full scale can be increased by placing an optional resistor (r3). the required value varies with the process and needs to be tuned for the specific application. full scale can similarly be reduced by placing r4; tuning is required here as well. an external reference can be used by shorting the sense pin to 3.3 v (place jumper e26Ce25). jumper e27Ce24 connects the adc vref pin to the ext_vref pin at the power connector. data format select data format select (dfs) sets the output data format of the adc. setting dfs (e1Ce2) low sets the output format to be offset binary; setting dfs high (e1Ce3) sets the output to twos complement. data outputs the adc lvds digital outputs are routed directly to the connector at the card edge. resistor pads placed at the output connector allow for termination if the connector receiving logic lack the differential termination for the data bits and dco. each output trace pair should be terminated differentially at the far end of the line with a single 100 ohm resistor. clock xtal an optional xtal oscillator can be placed on the board to serve as a clock source for the pcb. power to the xtal is through the vclk/vxtal pin at the power connector. if an oscillator is used, ensure proper termination for best results. the board was tested with a valpey fisher vf561 and a vectron jn00158-163.84. obsolete
ad9411 data sheet rev. b | page 22 of 28 table 9. evaluation board bill of materialad9411 pcb no. quantity reference designator device package value 1 33 c1, c3*, c4Cc11, c15Cc17, c18*, c19Cc32, c35, c36, c39*, c40*, c58-c62 capacitor 0603 0.1 f 2 4 c33*, c34*, c37*, c38* capacitor 0402 0.1 f 3 4 c63Cc66 capacitor tajd capl 10 f 4 1 c2* capacitor 0603 10 pf 5 2 c12*, c13* capacitor 0603 20 pf 6 2 j4, j5 jacks smb 7 2 p21, p22 power connectorstop 25.602.5453.0 wieland 8 2 p21, p22 power connectorsposts z5.531.3425.0 wieland 9 1 p23 40-pin right angle connector digi-key s2131-20-nd 10 16 r1, r6Cr12*, r15*, r31Cr37* resistor 0402 100 11 1 r2 resistor 0603 3.7 k 12 3 r5, r16, r27 resistor 0603 50 13 2 r17, r18 resistor 0603 510 14 2 r19, r20 resistor 0603 150 15 2 r29, r30 resistor 0603 1 k 16 2 r41, r42 resistor 0603 25 17 2 r3, r4 resistor 0603 3.8 k 18 2 r13, r14 resistor 0603 25 19 6 r22*, r23*, r24*, r25*, r26*, r28* resistor 0603 100 20 5 r38*, r39*, r40*, r45*, r47* resistor 0402 25 21 2 r43*, r44* resistor 0402 10 k 22 1 r46* resistor 0402 1.2 k 23 2 r48*, r49* resistor 0402 0 24 2 r50*, r51* resistor 0402 1 k 25 1 t1, t2* rf transformer mini circuits adt1-1wt 26 1 u2 rf amp ad8351 27 1 u9 optional xtal jn00158 or vf561 28 1 u1 ad9411 tqfp-100 29 1 u3 mc100lvel16 so8nb * c2, c3, c12, c13, c18, c33, c34, c37, c38, c39, c40, r1, r6Cr12, r15, r22Cr26, r28, r31C r40, r43Cr51 and t2 not placed. obsolete
data sheet ad9411 rev. b | page 23 of 28 gnd 40 drb 38 gnd 36 d11b 34 d10b 32 gn d dr gn d d11 d10 39 37 35 33 31 d9b 30 d8b 28 d7b 26 d6b 24 d5b 22 d9 d8 d7 d6 d5 29 27 25 23 21 d4b 20 d3b 18 d2b 16 d1b 14 d0b 12 d4 d3 d2 d1 d0 19 17 15 13 11 d1fb 10 d2fb 8 dorb 6 4 gnd 2 d1f d2f do r gn d 9 7 5 3 1 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 u1 ad9411 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 r1 100? dor dorb r6 100 ? d11 d11b r7 100 ? d10 d10b r8 100? d9 d9b r15 100 ? d1 d1b r36 100? d0 d0b r35 100 ? d1f d1fb r34 100? d2f d2fb r31 100? d2 d2b r10 100? d6 d6b r37 100? dr drb r32 100? d3 d3b r11 100? d7 d7b r9 100? d5 d5b r33 100 ? d4 d4b r12 100 ? d8 d8b gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc vcc vcc gnd gnd drvdd gnd drvdd drvdd drvdd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc gnd gnd gnd gnd gnd drvdd gnd ~enc vcc c4 0.1 ?f gnd gnd r5 50 ? c10 0.1 ?f c9 0.1 ?f elout eloutb gnd r19 510 ? r20 510 ? gnd c36 0.1 ?f vcc vee vbb dn d q qn 2 3 4 5 6 7 8 gnd r18 510? r17 510 ? c8 0.1 ?f vcc e46 e47 vdl e45 10el16 u3 j5 gnd gnd c5 0.1 ?f encode r27 50 ? c13 20pf gnd gnd vcc gnd gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc c12 20pf c15 0.1 ?f c3 0.1 ?f c2 10pf c30 0.1 ?f c7 0.1 ? f c11 0.1 ? f c6 0.1 ? f j4 gnd r16 50? r14 25? r42 25? t2 optional gnd gnd r13 25? gnd ampinb ampin r41 25? t1 adt1-1wt 1 5 3 4 2 6 t2 adt1-1wt 1 5 3 4 2 6 nc nc pri sec pri sec gnd gnd amp analog vcc e19 vcc e3 e17 gnd gnd e18 r30 1k? vcc r29 1k ? e1 gnd e2 r2 3.8k ? gnd gnd r3 3.8k ? r4 3.8k ? vcc e26 vref e24 e25 e27 gnd c1 0.1 ?f p16 gnd ground pad under part p1 p2 1 2 gnd vref p3 p4 3 4 gnd vdl p1 p2 1 2 gnd drvdd p3 p4 3 4 gnd vcc p21 ptm1cro4 p22 ptm1cro4 h4 mthole6 h3 mthole6 h2 mthole6 h1 mthole6 gnd connector agnd avdd avdd agnd agnd avdd avdd agnd agnd agnd avdd avdd avdd agnd agnd or+ or? dvrdd drgnd d9+ d9? d8+ d8? d7+ d7? drvdd drgnd d6+ d6? d5+ d5? d4+ d4? drgnd d3+ d3? dc0+ dc0? drvdd drgnd d2+ d2? d1+ d1? d0+ d0? drvdd drgnd dnc dnc s5 dnc s4 agnd s2 s1 lvdsbias avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd gnd ain ainb agnd avdd agnd agnd avdd avdd avdd agnd agnd agnd avdd avdd agnd clk+ clk? agnd avdd avdd agnd dnc dnc dnc dnc dnc drvdd drgnd dnc dnc 04530-a-015 figure 45. evaluation board schematic obsolete
ad9411 data sheet rev. b | page 24 of 28 04530-0-046 + c64 10 ? f c16 0.1? f c17 0.1? f c19 0.1? f c21 0.1? f c20 0.1? f c23 0.1? f c22 0.1? f c25 0.1? f c24 0.1? f c27 0.1? f c26 0.1? f c29 0.1? f c28 0.1? f c31 0.1? f c32 0.1? f c35 0.1? f vcc gnd + c65 10 ? f c61 0.1? f c62 0.1? f c60 0.1? f c59 0.1? f c58 0.1? f drvdd gnd c66 10 ? f c18 0.1? f vdl gnd + c63 10 ? f vref gnd + to use vf561 crystal e/d 1 nc 2 gnd 3 vcc outputb output 6 5 4 jn00158 u9 gnd r28 100 ? r22 100 ? gnd vdl vdl gnd r23 100 ? r25 100 ? vdl gnd r24 100 ? r26 100 ? p4 p5 figure 46. evaluation board schematic (continued) 04530-0-053 vdl vdl gnd gnd gnd amp in amp power down use r43 or r44 u2 ad8351 r44 10k ? r39 25k ? r38 25k ? r40 25k ? r46 1.2k ? r45 25k ? r43 10k ? c33 0.1? f c34 0.1? f vdl gnd gnd r51 1k ? r50 1k ? c38 0.1? f c37 0.1? f r49 0 ? c39 0.1? f r48 0 ? c40 0.1? f ampinb ampin gnd r47 25k ? pwup 1 rgp1 2 inhi 3 inlo 4 rpg2 5 vocm vpos ophi oplo comm 10 9 8 7 6 figure 47. evaluation board schematic (continued) obsolete
data sheet ad9411 rev. b | page 25 of 28 figure 48. pcb top side silkscreen 04530-0-048 figure 49. pcb top side copper routing 04530-0-049 figure 50. pcb ground layer 04530-0-050 figure 51. pcb split power plane obsolete
ad9411 data sheet rev. b | page 26 of 28 04530-0-051 figure 52. pcb bottom side copper routing 04530-0-052 figure 53. pcb bottom side silkscreen obsolete
data sheet ad9411 rev. b | page 27 of 28 outline dimensions compliant to jedec standards ms-026-aed-hd 021809-a 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 6.50 nom 7 3.5 0 coplanarity 0.08 0.20 0.09 top view (pins down) bottom view (pins up) conductive heat sink pin 1 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 54. 100-lead thin quad flat package, exposed pad [tqfp_ep] (sv-100) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9411bsvz-170 C40c to +85c 100-lead thin qu ad flat package, exposed pad [tqfp_ep] sv-100 ad9411bsvz-200 C40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100 1 z = rohs compliant part. obsolete
ad9411 data sheet rev. b | page 28 of 28 notes ?2004C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04530-0-1/12(b) obsolete

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