View MT29F8G08MAAWC_7859905.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein ar e subject to change by micron without notice. 8gb, 16gb, and 32gb: x8 nand flash memory features micron confidential and proprietary mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__1.fm - rev. b 11/07 en 1 ?2007 micron technology, inc. all rights reserved. nand flash memory mlc MT29F8G08MAAWC, mt29f8g08maawp, mt29f16g08qaawc,mt29f32g08taawc features ? organization ? page size x8: 2,112 bytes (2,048 + 64 bytes) block size: 128 pages (256k + 8k bytes) ? plane size: 2,048 blocks ? device size: 8gb: 4,096 blocks; 16gb: 8,192 blocks; 32gb: 16,384 blocks ?read performance ? random read: 50s ? sequential read: 25ns ?write performance ? program page: 650s (typ) ? block erase: 2ms (typ) ? endurance: 10,000 program/erase cycles (with ecc and invalid block mapping) ? first block (block address 00h) guaranteed to be valid with ecc when shipped from factory ? industry-standard basic nand flash command set ? new commands ? page read cache mode ? two-plane/multiple-die read status ? two-plane commands for concurrent-plane oper- ations ? read unique id (contact factory) ? read id2 (contact factory) ? operation status byte provides a software method of detecting: ? program/erase/read operation completion ? program/erase pass/fail condition ? write-protect status ? ready/busy# (r/b#) signal provides a hardware method of detecting program, read, or erase cycle completion ? wp# signal: entire device hardware write protect ? staggered power-up sequence: issue reset (ffh) command figure 1: 48-pin tsop type 1 notes: 1. for part numbering and markings, see figure 2 on page 2. 2. ocpl = off-center parting line. 3. for et devices. options ?density 1 ? 8gb (single-die stack) ? 16gb (dual-die stack) ? 32gb (quad-die stack) ? device width: x8 ? configuration # of die # of ce# # of r/b# i/o 1 1 1 common 2 2 2 common 4 2 2 common ?v cc : 2.7?3.6v ? first-generation die ?package ? 48-pin tsop type i (lead-free plating) ? 48-pin tsop type i ocpl 2 (lead-free plating) ? operating temperature ? commercial (0c to 70c) ? extended (?40c to +85c) 3 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__1.fm - rev. b 11/07 en 2 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory part numbering information micron confidential and proprietary part numbering information micron nand flash devices ar e available in several different configurations and densi- ties (see figure 2). figure 2: part number chart valid part number combinations after building the part number from the part numbering chart, verify that the part number is offered and valid by using the micron parametric part search web site: www.micron.com/products/parametric . if the device required is not on this list, contact the factory. mt 29f 8g 08 m a a w c e s :b mi c ron te c hnolo g y pro d u c t family 29f = s in g le-supply nand flash memory density 8g = 8g b 16g = 16g b 32g = 32g b devi c e wi d th 08 = 8 b its operatin g volta g e ran g e a = 3.3v (2.70?3.60v) feature s et a = first b = s e c on d c = thir d desi g n revision a = first g eneration b = s e c on d g eneration pro d u c tion s tatus blank = pro d u c tion e s = en g ineerin g sample m s = me c hani c al sample q s = qualifi c ation sample operatin g temperature ran g e blank = c ommer c ial (0 c to +70 c ) et = exten d e d (?40 c to +85 c ) reserve d for future use blank flash performan c e blank = s tan d ar d pa c ka g e c o d es w c = 48-pin t s op 1 o c pl (lea d -free) wp = 48-pin t s op 1 c pl (lea d -free) c lassifi c ation # of d ie # of c e# # of r/b# i/o m 1 1 1 c ommon q 2 2 2 c ommon t 4 2 2 c ommon www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlctoc.fm - rev. b 11/07 en 3 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory table of contents micron confidential and proprietary table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 page read 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 random data read 05h-e0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 page read cache mode start 31h; page read cache mode start last 3fh . . . . . . . . . . . . . . . . . . . 24 read id 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 read status 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program page 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 serial data input 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 random data input 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program page cache mode 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 read for internal data move 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 program for internal data move 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 block erase 60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 two-plane operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 two-plane addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 two-plane page read 00h-00h-30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 two-plane random data read 06h-e 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 two-plane program page 80h-11h-80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 two-plane random data input 80h-85h-11h (or 80h-85h-10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 two-plane program page cache mode 80h-11h-80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 two-plane internal data move 00h-00h- 35h/85h-11h-80h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 two-plane read for internal data move 00h -00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 two-plane program for internal data mo ve 85h-11h-80h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 two-plane block erase 60h-60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 two plane/multiple-die read status 78h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 interleaved die operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 interleaved page read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 interleaved two-plane page read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 interleaved program page operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 interleaved program page cache mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 interleaved two-plane program page operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interleaved two-plane program page cach e mode operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interleaved block erase operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlctoc.fm - rev. b 11/07 en 4 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory table of contents micron confidential and proprietary interleaved two-plane block erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 reset ffh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 v cc power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlclof.fm - rev. b 11/07 en 5 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory list of figures micron confidential and proprietary list of figures figure 1: 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3: nand flash functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4: pin assignment (top view) 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5: memory map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6: array organization for mt29f8g08maa and mt29f16g 08qaa (x8). . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7: array organization for mt29f32g08taa (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8: ready/busy# open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9: tfall and trise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10: iol vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11: tc vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14: page read cache mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16: status register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17: program and read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18: random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19: program page cache mo de example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20: internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21: internal data move with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 22: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 23: two-plane page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 24: two-plane page read with random data read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 25: two-plane program page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 26: two-plane program page with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 27: two-plane program page cache mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 28: two-plane internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 29: two-plane internal data move with random da ta input . . . . . . . . . . . . . . . . . . . . . . . 44 figure 30: two-plane block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 31: two-plane/multiple-die read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 32: interleaved page read with r/b# monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 33: interleaved page read with status register monitori ng. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 34: interleaved two-plane page read with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 35: interleaved two-plane page re ad with status register monitoring . . . . . . . . . . . . . . . . . . . . . 50 figure 36: interleaved program page with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 37: interleaved program page with status register monito ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 38: interleaved program page cach e mode with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 39: interleaved program page cache mode with st atus register monitoring . . . . . . . . . . . . . . . 52 figure 40: interleaved two-plane program page with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 41: interleaved two-plane progra m page with status register monitoring . . . . . . . . . . . . . . . . 54 figure 42: interleaved two-plane pr ogram page cache mode with r/b# monitoring . . . . . . . . . . . 55 figure 43: interleaved two-plane program page cache mode with status register monitoring . . 56 figure 44: interleaved block erase with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 45: interleaved block erase with stat us register monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 46: interleaved two-plan e block erase with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 47: interleaved two-plane block erase with status register monitoring . . . . . . . . . . . . . . . . . . . 59 figure 48: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 49: erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 50: erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 51: program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 52: program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 53: program for internal data move enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 54: program for internal data move disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 55: two-plane erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 56: two-plane erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlclof.fm - rev. b 11/07 en 6 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory list of figures micron confidential and proprietary figure 57: two-plane program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 58: two-plane program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 59: two-plane program for internal data move enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 60: two-plane program for internal data move disabl e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 61: ac waveforms during power transi tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 62: command latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 63: address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 64: input data latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 65: serial access cycle after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 66: read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 67: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 68: read operation with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 69: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 70: page read cache mode operation, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 71: page read cache mode operation, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 72: page read cache mode operation without r/b#, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 73: page read cache mode operation without r/b#, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 74: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 75: program operation with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 76: program page op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 77: program page operation with random data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 78: internal data move operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 79: program page cache mode operat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 80: program page cache mode operat ion ending on 15h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 81: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 82: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 83: 48-pin tsop type 1 ocpl (wc pa ckage code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 84: 48-pin tsop type 1 cpl (wp package code). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlclot.fm - rev. b 11/07 en 7 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory list of tables micron confidential and proprietary list of tables table 1: signal/pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2: operational example (8gb x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3: array addressing: mt29f8g08maa an d mt29f16g08qaa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4: array addressing: mt29f32g08taa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6: command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7: two-plane command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8: device id and configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9: status register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10: status register contents after re set operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 11: absolute maximum ratings by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 12: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 13: m29fxgxx device dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 14: valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 15: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 16: test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 17: ac characteristics ? command, data, and address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 18: ac characteristics ? normal operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 19: program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 8 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory general description micron confidential and proprietary general description nand flash technology provides a cost-effec tive solution for applications requiring high-density, solid-state storage. the mt29f8g08 is an 8gb nand flash memory device. the mt29f16g08 is a two-die stack that operates as two independent 8gb devices (mt29f8g08). the mt29f 32g08 is a four-die stacked device that operates as two independent 16gb devices (mt29f16g08), providing a total storage capacity of 32gb in a single, space-saving package. micron ? nand flash devices include standard nand flash features as well as new features designed to enhance system-level perfor- mance. these nand flash devices utilize multilevel cell (mlc) technology. each memory cell stores 2 bits of information. micron nand flash devices use a highly multiplexed 8-bit bus (i/o[7:0]) to transfer data, addresses, and instructions. the five command signals (cle, ale, ce#, re#, we#) implement the nand flash command bus inte rface protocol. two additional signals control hardware write protection (wp#) and monitor device status (r/b#). this hardware interface creates a low-pin-coun t device with a standard pinout that is the same from one density to another, allowing future upgrades to higher densities with- out board redesign. the mt29fxg devices contain two planes per di e. each plane consists of 2,048 blocks. each block is subdivided into 128 progra mmable pages. each page consists of 2,112 bytes (x8). the pages are further divided into a 2,048-byte data storage region with a sep- arate 64-byte area on the x8 device. the 64-b yte area is typically used for error manage- ment functions. the contents of each 2,112-byte page can be programmed in t prog (typ), and an entire 264k-byte block can be erased in t bers (typ). on-chip cont rol logic automates pro- gram and erase operations to maximize cycle endurance. program/erase endur- ance is specified at 10,000 cycles when a ppropriate error correction code (ecc) and error management are used. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 9 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory general description micron confidential and proprietary figure 3: nand flash functional block diagram figure 4: pin assignment (top view) 48-pin tsop type 1 notes: 1. ce2# and r/b2# on 1 6g b and 32 g b device only. these pins are nc for other configurations. address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# i/o [7:0] control logic i/o control r/b# row decode column decode x8 n c n c n c n c n c r/b2# 1 r/b# re# c e# c e2# 1 n c v cc v ss n c n c c le ale we# wp# dnu dnu dnu n c n c x8 dnu n c n c n c i/o7 i/o6 i/o5 i/o4 n c n c dnu v cc v ss n c n c n c i/o3 i/o2 i/o1 i/o0 n c n c dnu dnu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 10 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory general description micron confidential and proprietary table 1: signal/pin descriptions symbol type function ale input address latch enable: du ring the time ale is hi g h, address information is transferred from i/o[7:0] into the on-chip address registe r on the rising edge of we# . when address information is not bein g loaded, ale should be driven low. ce#, ce2# input chip enable: ce# and ce2# are used to gate transfers between the host system and the nand flash device. after the device starts a pro g ram or erase operation, chip enable(s) ca n be de-asserted. for the 1 6g b configuration, ce# controls the first 8 g b of memory, and ce2e co ntrols the second 8 g b. for the 32 g b configuration, ce# controls the first 1 6g b of memory; ce2# controls the second 1 6g b. see ?bus operation? on page 15 for additional operational details. cle input command latch enable: when cle is hi g h, information is transferred from i/o[7:0] to the on-chip co mmand register on the rising edge of we#. when command information is not being loaded, cle should be driven low. re# input read enable: re# is used to gate transfe rs from the nand flash device to the host system. we# input write enable: we# is used to gate transfers from the host system to the nand flash device. wp# input write protect: wp# protects against inadvertent pro g ram and erase operations. all pro g ram and erase operations are disabled when the wp# is low. i/o[7:0] mt29fx g 08 i/o data inputs/outputs: the bi directional i/os transfer address, data, and instruction information. data is output only during read operations; at other times the i/os are inputs. r/b#, r/b2# output ready/busy: this is an open-drain , active-low output that uses an external pull- up resistor. r/b# and r/b2# are used to indicate when the chip is processing a pro g ram or erase operation. r/b# and r/b2 # are also used during read operations to indicate when data is be ing transferred from the array into the serial data register. after these operatio ns have completed, the r/b# returns to the high-impedance state. in the 1 6g b configuration, r/b# is used for the 8 g b of memory enabled by ce#, an d r/b2# is used for the 8 g b of memory enabled by ce2#. in the 32 g b configuration, r/b# used is for the 1 6g b of memory enabled by ce#, and r/b2# is used for the 1 6g b of memory enabled by ce2#. v cc supply v cc : the v cc pin is the power supply pin. v ss supply v ss : the v ss pin is the ground connection. nc ? no connect: nc pins are not internally connected. these pins can be driven or left unconnected. dnu ? do not use: these pins must be left disconnected. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 11 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory architecture micron confidential and proprietary architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins. this provides a memory device with a low pin count. the internal memory array is accessed on a page basis. for reads, a page of data is cop- ied from the memory array into the data regist er. after being copied to the data register, data is output sequentially, byte by byte on x8 devices. the memory array is programmed on a page basis. after the starting address is loaded into the internal address register, data is sequ entially written to the internal data register up to the end of a page. after all of the page data has been loaded into the data register, array programming is started. in order to increase programming bandwidth, this device incorporates a cache register. in the cache programming mode, data is first copied into the cache register and then into the data register. after the data is copi ed into the data register, programming begins. after the data register has been loaded an d programming started, the cache register becomes available for loading additional data. loading of the next page of data into the cache register takes place while page programming is in process. the internal data move command also uses the internal cache register. normally, moving data from one area of external memo ry to another requires a large number of external memory cycles. when the internal cache register and data register are used, array data can be copied from one page and then programmed into another without requiring external memory cycles. addressing nand flash devices do not contain dedicate d address pins. addresses are loaded using a 5-cycle sequence, as shown in figures 6 and 7 on pages 13 and 14. table 3 on page 13 presents address functions internal to the x8 device. see figure 5 on page 12 for addi- tional memory mapping and addressing details. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 12 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory addressing micron confidential and proprietary figure 5: memory map x8 notes: 1. as shown in table 3 on page 13, the high nibble of address cycle 2 has no assigned address bits; however, these 4 bits must be held low during the address cycle to ensure that the address is interpreted correctly by the nand flash device. these extr a bits are accounted for in address cycle 2 even though they have no address bits assigned to them. 2. block address concatenated wi th page address = row address. table 2: operational example (8gb x8) block page min address in page max address in page out-of-bounds addresses in page 0 0 0x00000000 0x0000083f 0x00000840-0x00000fff 0 1 0x00010000 0x0001083f 0x00010840-0x00010fff 0 2 0x00020000 0x0002083f 0x00020840-0x00020fff ... ... ... ... ... 4,095 12 6 0x7fffe0000 0x7fffe083f 0x7fffe0840-0x7fffe0fff 4,095 127 0x7ffff0000 0x7ffff083f 0x7ffff0840-0x7ffff0fff ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? blo c ks 8g b , 16g b : ba[18:7] 32g b : ba[19:7] pa g es pa[6:0] bytes c a[11:0] 012 0 1 2 127 0 1 2 2,047 ? ? ? 2,111 4,095 s pare area 32g b : 8,192 b lo c ks per c e# www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 13 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory addressing micron confidential and proprietary figure 6: array organization fo r mt29f8g08maa and mt29f16g08qaa (x8) note: for the 1 6g b mt29f1 6g 08qaa, the 8 g b array organization shown applies to each chip enable (ce# and ce2#). notes: 1. block address concatenat ed with page address = actual page address. cax = column address; pax = page address; bax = block address. 2. if ca11 is ?1,? then ca[10: 6 ] must be ?0.? this keeps a max limit of 2,112 bytes addressed per page. 3. plane select bit. table 3: array addressing: mt29f8g08maa and mt29f16g08qaa cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca 6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low ca11 ca10 ca9 ca8 third ba7 3 pa 6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low ba18 ba17 ba1 6 c a c he re g ister data re g ister 2,048 b lo c ks per plane 4,096 b lo c ks per d evi c e 1 block 1 block i/o0 i/o7 1 pa g e = (2k + 64 b ytes) 1 b lo c k = (2k + 64) b ytes x 128 pa g es = (256k + 8k) b ytes 1 plane = (256k + 8k) b ytes x 2,048 b lo c ks = 4,224m b 1 d evi c e = 4,224m b x 2 planes = 8,448m b plane of even-num b ere d b lo c ks (0, 2, 4, 6, ..., 4,092, 4,094) plane of o dd -num b ere d b lo c ks (1, 3, 5, 7, ..., 4,093, 4,095) 64 2,048 64 2,112 b ytes 2,112 b ytes 64 64 2,048 2,048 2,048 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 14 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory addressing micron confidential and proprietary figure 7: array organization for mt29f32g08taa (x8) notes: 1. die 0, plane 0: ba19 = 0; ba7 = 0 2. die 0, plane 1: ba19 = 0; ba7 = 1 3. die 1, plane 0: ba19 = 1; ba7 = 0 4. die 1, plane 1: ba19 = 1; ba7 = 1 5. for the 32 g b mt29f32 g 08taa, the 1 6g b array organization show n applies to each chip enable (ce# and ce2#). notes: 1. cax = column address; pax = page address; bax = block address. 2. if ca11 is ?1,? then ca[10: 6 ] must be ?0.? this keeps a max limit of 2,112 bytes addressed per page. 3. die address boundary: 0 = 0?8 g b; 1 = 8 g b?1 6g b. 4. plane select bit. table 4: array addressing: mt29f32g08taa cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca 6 ca5ca4ca3ca2ca1ca0 second low low low low ca11 ca10 ca9 ca8 third ba7 4 pa 6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low ba19 3 ba18 ba17 ba1 6 c a c he re g ister data re g ister 4,096 b lo c ks per plane 8,192 b lo c ks per d ie 1 block 1 block plane 0: even- num b ere d b lo c ks (0, 2, 4, 6, ..., 4,092, 4,094) 1 plane 1: o dd - num b ere d b lo c ks (1, 3, 5, 7, ..., 4,093, 4,095) 2 plane 0: even- num b ere d b lo c ks (4,096, 4,098, ..., 8,188, 8,190) 3 plane 1: o dd - num b ere d b lo c ks (4,097,4,099, ..., 8,189, 8,191 ) 4 64 2,048 64 2,112 b ytes 2,112 b ytes 64 64 2,048 2,048 2,048 1 block 1 block 64 2,048 64 2,112 b ytes 2,112 b ytes 64 64 2,048 2,048 2,048 1 pa g e = (2k + 64 b ytes) 1 b lo c k = (2k + 64) b ytes x 128 pa g es = (256k + 8k) b ytes 1 plane = (256k + 8k) b ytes x 2,048 b lo c ks = 4,224m b 1 d ie = 4,224m b x 2 planes = 8,448m b 1 d evi c e = 8,448m b x 2 d ie = 16,896m b i/o0 i/o7 die 0 die 1 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 15 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory bus operation micron confidential and proprietary bus operation the bus on the mt29fxxx devices is multip lexed. data i/o, addresses, and commands all share the same pins. the command sequence normally consists of a command latch cycle, an address latch cycle, and a data cycle?either read or write. control signals ce#, we#, re#, cle, ale, and wp# control flash device read and write operations. on the 16gb mt29f16g devices, ce# and ce2# each control an independent 8gb array. on the 32gb mt29f32g devices, ce# and ce 2# each control independent 16gb arrays. ce2# functions the same as ce# for its own ar ray; all operations described for ce# also apply to ce2#. ce# is used to enable a device. when ce# is low and the device is not in the busy state, the flash memory will accept command, data, and address information. when the device is not performing an operat ion, ce# is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power consump- tion. see figure 68 on page 74 and figure 75 on page 80 for examples of ce# ?don?t care? operations. the ce# ?don?t care? operation allows the nand flash to reside on the same asynchro- nous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flash is busy with internal operations. this capa- bility is important for designs that requir e multiple nand flash devices on the same bus. one device can be programmed while another is being read. a high cle signal indicates th at a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. commands commands are written to the command register on the rising edge of we# when: ? ce# and ale are low, and ?cle is high, and ? the device is not busy. as exceptions, the device accepts the read status, two-plane/multiple-die read status and reset commands when busy. commands are transferred to the command register on the rising edge of we# (see figure 62 on page 71). address input addresses are written to the address register on the rising edge of we# when: ? ce# and cle are low, and ?ale is high. see figure 63 on page 71 for ad ditional address input details. the number of address cycles required for each command varies. refer to the command descriptions to determine addressing requirements. see tables 6 and 7 on pages 20 and 21. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 1 6 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory bus operation micron confidential and proprietary data input data is written to the data register on the rising edge of we# when: ? ce#, cle, and ale are low, and ? the device is not busy. see figure 64 on page 72 for additional data input details. read after a read command is issued, data is tran sferred from the memory array to the data register from the rising edge of we#. r/b# goes low for t r and transitions high after the transfer is complete. when data is availab le in the data register, it is clocked out of the device by re# going low. see figure 67 on page 74 for detailed timing information. the read status (70h) or two-plane/multiple-die read status (78h) com- mand or the r/b# signal can be used to determine when the device is ready. ready/busy# the r/b# output provides a hardware meth od of indicating th e completion of pro- gram, erase, and read operations. the signal requires a pull-up resistor for proper operation. the signal is typically high, and it transitions to low after the appropriate command is written to the device. the signal?s open-drain driver enables multiple r/b# outputs to be or-tied. the read status command can be used in place of r/b#. typi- cally, r/b# would be connected to an interrupt pin on the system controller (see figure 8 on page 17). on 16gb mt29f16g devices, r/b# indicate s the 8gb section enabled by ce#, and r/b2# does the same for the 8gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 8gb section. on 32gb mt29f32g devices, r/b# indicates the 16gb section enabled by ce#, and r/b2# does the same for the 16gb section en abled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 16gb section. the combination of rp and capacitive loadin g of the r/b# circuit determines the rise time of the r/b# signal. the actual value used for rp depends on system timing require- ments. large values of rp cause r/b# to be de layed significantly. at the 10- to 90-percent points on the r/b# waveform, rise time is approximately two time constants (tc). the fall time of the r/b# signal is determ ined mainly by the output impedance of the r/b# signal and the total load capacitance. figure 9 on page 17 and figure 10 on page 18 de pict approximate rp values for a circuit load of 100pf. the minimum value for rp is determined by th e output drive capability of the r/b# sig- nal, the output voltage swing, and v cc . tc r c = where r rp (resistance of pull-up resisto r), and c total capacitive load. = = www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 17 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory bus operation micron confidential and proprietary figure 8: ready/busy# open drain figure 9: t fall and t rise notes: 1. t fall and t rise are calculated at 10 percent?90 percent points. 2. t rise is dependent on external capacitance and resistive loading and output transistor impedance. 3. t rise is primarily dependent on external pull -up resistor and extern al capacitive loading. 4. t fall 10ns at 3.3v. 5. see tc values in figure 11 on page 18 for approximate rp value and tc. rp v cc max () v ol max () ? i ol il + --------------------------------------------------------------- 3.2 v 8 ma il + -------------------------- == where il is the sum of the input currents of all devices tied to the r/b# pin. rp r/b# open drain output v cc g nd device i ol 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise v cc 3.3 t c v www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 18 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory bus operation micron confidential and proprietary figure 10: i ol vs. rp note: to calculate rp value, see page 1 6 . figure 11: tc vs. rp 3.50ma 3.00ma 2.50ma 2.00ma 1.50ma 1.00ma 0.50ma 0.00ma 0 2,000 4,000 6,000 8,000 10,000 12,000 i ol at 3.60v (max) rp 1.20s 1.00s 800ns 6 00ns 400ns 200ns 0ns 0 2k 4k 6 k 8k 10k 12k i ol at 3. 6 0v (max) rc = tc c = 100pf rp t www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 19 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory bus operation micron confidential and proprietary notes: 1. wp# should be biased to cmos hi g h or low for standby. 2. mode selection settings for this table: h = logic level hi g h; l = logic level low; x = v ih or v il . table 5: mode selection cle ale ce# we# re# wp# 1 mode hll hx read mode command input lhl hx address input hll hh write mode command input lhl hh address input lll hh data input lllh x sequential read and data output xxxxhx during read (busy) xxxxxh during program (busy) xxxxxh during erase (busy) xxxxxl write protect xxhxx0v/v cc standby www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 20 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary command definitions notes: 1. indicates required data cycles between command cycle 1 and command cycle 2. 2. do not cross block address boundaries when using pa g e read cache mode operations. see table 4 on page 14 for die address boundary definitions. 3. do not cross plane address boundaries when using read for internal data move and pro g ram for internal data move. see table 4 on page 14 for die address boundary definitions. 4. random data read command is limited to use within a single page. 5. random data input command is limi ted to use within a single page. table 6: command set operation command cycle 1 number of address cycles data cycles required 1 command cycle 2 valid during busy notes pa g e read 00h 5 no 30h no pa g e read cache mode 31h ? no ? no 2 pa g e read cache mode last 3fh ? no ? no 2 read for internal data move 00h 5 no 35h no 3 random data read 05h 2 no e0h no 4 read id 90h 1 no ? no read status 70h ? no ? yes pro g ram pa g e 80h 5 yes 10h no pro g ram pa g e cache mode 80h 5 yes 15h no pro g ram for internal data move 85h 5 optional 10h no 3 random data input 85h 2 yes ? no 5 block erase 6 0h 3 no d0h no reset ffh ? no ? yes www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 21 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary notes: 1. do not cross plane address boundaries when using two-plane read for internal data move and two-plane pro g ram for internal data move. see table 4 on page 14 for die address bounda ry definitions. 2. two-plane random data read command is limited to use within a single page. 3. do not cross block address boundaries when using cache operations. see table 4 on page 14 for die address boundary definitions. table 7: two-plane command set operation command cycle 1 number of address cycles command cycle 2 number of address cycles command cycle 3 valid during busy notes two-plane pa g e read 00h 5 00h 5 30h no two-plane read for internal data move 00h 5 00h 5 35h no 1 two-plane random data read 0 6 h5e0h? ?no2 two-plane/multiple-die read status 78h 3 ? ? ? yes two-plane pro g ram pa g e 80h 5 11h-80h 5 10h no two-plane pro g ram pa g e cache mode 80h 5 11h-80h 5 15h no 3 two-plane pro g ram for internal data move 85h 5 11h-80h 5 10h no 1 two-plane block erase 6 0h 3 6 0h 3 d0h no www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 22 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary read operations page read 00h-30h to enter read mode while the device is in operation, write the 00h command to the command register, then write 5 address cycles, and conclude with the 30h command. to determine the progress of the data transfer from the flash array to the data register ( t r), monitor the r/b# signal, or, alternativel y, issue a read status command. if the read status command is used to monitor the data transfer, the user must re-issue the read (00h) command to receive data output from the data register (see figure 72 on page 78 and figure 73 on page 79 for examples). after the read command has been re- issued, pulsing the re# line will result in ou tputting data, starting from the initial col- umn address. a serial page read sequence outputs a complete page of data. after 30h is written, the page data is transferred to the data regist er, and r/b# goes low during the transfer. when the transfer to the data register is complete, r/b# returns high. at this point, data can be read from the device. starting from the initial column address and going to the end of the page, read the data by repeatedly pulsing re# at the maximum t rc rate (see figure 12). figure 12: page read operation re# ce# ale cle i/ox 00h address (5 cycles) data output (serial access) 30h r/b# we# t r don?t care www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 23 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary random data read 05h-e0h the random data read command enables the user to specify a new column address so the data at single or multiple addresses can be read. the random read mode is enabled after a normal page read (00h-30h sequence). random data can be output after the initial page read by writing an 05h-e0h command sequence along with the new column address (2 cycles). the random data read command can be issued without limit within the page. only data on the current page can be read. pulsing re# outputs data sequentially (see figure 13). figure 13: random data read operation re# i/ox 00h address (5 cycles) data output data output 30h 05h address (2 cycles) e0h r/b# t r www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 24 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary page read cache mode start 31h; page read cache mode start last 3fh micron nand flash devices have a cache register that can be used to increase the read operation speed when accessing sequential pages in a block. first, a normal page read (00h-30h) comma nd sequence is issued (see figure 14 on page 25 for operation details). the r/b# signal goes low for t r during the time it takes to transfer the first page of data from the memory to the data register. after r/b# returns to high, the page read cache mode start (31h) command is latched into the com- mand register. r/b# goes low for t dcbsyr1 while data is being transferred from the data register to the cache register. after the data register contents are transferred to the cache register, another page read is automa tically started as part of the 31h command. data is transferred from the next sequential page of the memory array to the data regis- ter during the same time data is being read serially (pulsing of re#) from the cache regis- ter. if the total time to output data exceeds t r, then the page read is hidden. the second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. r/b# will stay low up to t dcbsyr2. this time can vary, depending on whether the previous memory -to-data-register transfer was completed prior to issuance of the next 31h command (see table 18 on page 69 for timing parame- ters). if the data transfer from memory to the data register is not completed before the 31h command is issued, r/b# stays low until the transfer is complete. it is not necessary to output a whole page of data before issuing another 31h command. r/b# will stay low until the previous page read is complete and the data has been transferred to the cache register. to read out the last page of data, the page read cache mode start last (3fh) com- mand is issued. this command transfers data fr om the data register to the cache register without issuing another page read (see figure 14 on page 25). random data read commands are permi tted during a page read cache mode operation. page read cache mode cannot be used to cross block boundaries. if monitoring the progress of page read cache mode via the read status register, use only read status (70h) commands. two-plane/multiple-die read status (78h) commands are not supported during a page read cache mode operation. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 25 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary figure 14: page read cache mode re# ce# ale cle i/ox 00h address (5 cycles) data output (serial access) data output (serial access) 31h 30h 31h 3fh r/b# we# t r data output (serial access) t dcbsyr1 t dcbsyr2 t dcbsyr2 don?t care www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 2 6 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary read id 90h the read id command is used to read the 5 bytes of identifier codes programmed into the devices. the read id command reads a 5-byte table that includes manufacturer?s id, device configuration, and part-specific information. see table 8 on page 27, which shows complete listings of all configuration details. writing 90h to the command register puts the device into the read id mode. the com- mand register stays in this mode until another valid command is issued (see figure 15 ). figure 15: read id operation note: see table 8 on page 27 for byte definitions. we# ce# ale cle re# i/ox address, 1 cycle 90h 00h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 27 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary notes: 1. b = binary; h = hex. 2. the mt29f1 6g xx device id code reflects the configuration of each 8 g b section. table 8: device id and configuration codes options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 notes byte 0 manufacturer id micron 001011002ch byte 1 device id mt29f8 g 08maa 8 g b, x8, 3.3v 11010011d3h mt29f1 6g 08qaa 1 6g b, x8, 3.3v 11010011d3h2 mt29f32 g 08taa 32 g b, x8, 3.3v 11010101d5h byte 2 number of die per ce 1 0 000b 2 0 101b cell type mlc 0 100b number of simultaneously programmed pages 2 0 101b interleaved operations between multiple die not supported 00b supported 11b cache programming supported 11b byte value mt29f8 g xx1001010094h mt29f1 6g xx1001010094h mt29f32 g xx11010101d5h byte 3 page size 2kb 0 101b spare area size (bytes) 6 4b 11b block size (w/o spare) 25 6 kb 1 0 10b organization x8 00b serial access (min) 50ns/30ns 0 0 0xxx0b 25ns 1 0 1xxx0b byte value mt29fx g 0810100101a5h byte 4 reserved 0 000b planes per ce# 2 0 101b 4 1 010b plane size 4 g b 1 1 0 110b reserved 00b byte value mt29f8 g xx01100100 6 4h mt29f1 6g xx01100100 6 4h 2 mt29f32 g xx01101000 6 8h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 28 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary read status 70h these nand flash devices have an 8-bit status register that the software can read during device operation. table 9 describes the status register. after a read status (70h) command, all read cycles are from the status register until a new command is given. changes in the status register are seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to start a new read cycle to see these changes. in devices that have more than one die sharing a common ce# connection, the read status (70h) command reports the status of th e die that was last addressed. if concur- rent operations are started on both die, then the two-plane/multiple-die read status (78h) command must be used to select the die that should report status. in this situation, using the read status (70h) comm and will result in bus contention, as both die will respond until the next operation is issued. while monitoring the read status to determine when the transfer from the flash array to the data register ( t r) is complete, the user must re -issue the read (00h) command to make the change from status to data. after the read command has been re-issued, pulsing the re# line will result in outputti ng data, starting from the initial column address. notes: 1. status register bit 0 reports a ?1? if a two-plane pro g ram operation fails on one or both planes. status register bit 1 reports a ?1? if a two-plane pro g ram pa g e cache mode operation fails on one or both plan es. use two-plane/multiple-die read status (78h) to determine the plane on which the operation failed. 2. status register bit 5 is ?0? during the actual pr ogramming operation. if cache mode is used, this bit will be ?1? when al l internal operatio ns are complete. 3. status register bit 6 is ?1? when the cache is ready to accept new data. r/b# follows bit 6 (see figure 14 on page 25 and figure 19 on page 31). table 9: status register bit definition sr bit program page program page cache mode page read page read cache mode block erase definition 0 1 pass/fail pass/fail (n) ? ? pass/fail 0 = successful pro g ram/erase 1 = error in pro g ram/erase 1 ? pass/fail (n -1) ? ? ? 0 = successful pro g ram 1 = error in pro g ram 2 ????? 0 3 ????? 0 4 ????? 0 5 ready/busy ready/busy 2 ready/busy ready/busy 2 ready/busy 0 = busy 1 = ready 6 ready/busy ready/busy cache 3 ready/busy ready/busy cache 3 ready/busy 0 = busy 1 = ready 7 write protect write protect write protect write protect write protect 0 = protected 1 = not protected www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 29 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary figure 16: status register operation notes: 1. command can be 70h or 78h. program operations program page 80h-10h micron nand flash devices are inherently page-programmed devices. within a block, the pages must be programmed consecutively from the least significant page address to the most significant page address. random page address programming is prohibited. these mlc nand flash devices do not support partial-page programming operations? a page can only be programmed one time before requiring an erase operation. if a reset (ffh) command is issued during a program page operation while r/b# is low, the data in the shared memory cells being programmed could become invalid. interrupting a programming operation on on e page could corrupt the data in another page within the block being programmed. serial data input 80h program page operations require loading the serial data input (80h) command into the command register, followed by 5 address cycles, then the data. serial data is loaded on consecutive we# cycles starting at the given address. the program (10h) command is written after the data input is complete. the control logic automatically executes the proper algorithm and controls all the necessary timing to program and ver- ify the operation. write verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low for the duration of array programming time, t prog. the read status (70h, 78h) and the reset (ffh) commands are the only commands valid during the pro- gramming operation. bit 5 of the status register will reflect the state of r/b#. when the device reaches ready, read bi t 0 of the status register to determine if the programming operation passed or failed (see figure 17). th e command register st ays in read status register mode until another va lid command is written to it. random data input 85h after the initial data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input com- mand can be used any number of times in th e same page prior to issuance of the page write (10h) command. see figure 18 for the proper command sequence. 70h 1 ce# cle we# re# i/ox status output t rea t clr www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 30 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary figure 17: program and read status operation notes: 1. command can be 70h or 78h. figure 18: random data input notes: 1. command can be 70h or 78h. program page cache mode 80h-15h cache programming is actually a buffered programming mode of the standard pro- gram page command. programming is started by loading the serial data input (80h) command to the command register, followed by 5 cycles of address, and a full or partial page of data. the data is initially copied into the cache register, and the cache write (15h) command is then latched to th e command register. data is transferred from the cache register to the data register on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data register and r/b# returns to high, memory array programming begins. when r/b# returns to high, new data can be written to the cache register by issuing another cache program command sequence. th e time that r/b# stays low will be controlled by the actual programming time. the first time through equals the time it takes to transfer the cache register contents to the data register. on the second and sub- sequent programming passes, transfer from the ca che register to the data register is held off until current data register content has been programmed into the array. the program page cache mode command ca n cross block boundaries; it cannot cross die boundaries. random data input commands are allowed during program page cache mode operations. bit 6 (cache r/b#) of the status register can be read by issuing the read status (70h, 78h) commands to determine when the cache register is ready to accept new data. r/b# always follows bit 6. bit 5 (r/b#) of the status register can be polled to determine when the actual program- ming of the array is complete for the current programming cycle. if just r/b# is used to determine programming completion, the last page of the program sequence must use the program page (10h) command instead of the cache pro- gram (15h) command. if the cache progra m (15h) command is used every time, including the last page of the programming se quence, status register bit 5 must be used to determine when programming is complete (see figure 19 on page 31). i/ox 80h address (5 cycles) 10h 70h 1 r/b# t pro g status i/o 0 = 0 pro g ram successful i/o 0 = 1 pro g ram error d in i/ox 80h address (5 cycles) 85h address (2 cycles) 10h 70h 1 r/b# t pro g d in d in status www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 31 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary bit 0 of the status register returns the pass/f ail for the previous page when bit 6 of the status register is a ?1? (ready state). the pass/fail status of the current program opera- tion is returned with bit 0 of the status regist er when bit 5 of the status register is a ?1? (ready state) (see figure 19). if a reset (ffh) command is issued during a program page cache mode operation while r/b# or bit 5 or bit 6 of the status register is low, the data in the shared memory cells being programmed could become invalid. interruption of a program operation on one page could corrupt the data in anot her page within the block being programmed. figure 19: program page cache mode example notes: 1. command can be 70h or 78h. 2. check i/o[ 6 :5] for internal ready/busy. check i/o[1: 0] for pass/fail. re# can stay low or pulse multiple times after a 70h or 78h command. t cbsy r/b# i/ox r/b# i/ox address & data input 80h 15h address & data input 80h 15h address & data input 80h 15h address & data input 80h 10h t cbsy t cbsy t lpro g t cbsy address & data input 80h 15h address & data input 80h 10h status output 2 70h 1 t lpro g status output 2 70h 1 a: without status reads b: with status reads www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 32 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary internal data move an internal data move requires two comm and sequences. issue a read for internal data move (00h-35h) command first, then the program for internal data move (85h-10h) command. data moves are only suppo rted within the plane from which data is read. read for internal data move 00h-35h the read for internal data move (00h-35h) command is used in conjunction with the program for internal data move (85h-10h) command. first, 00h is written to the command register, then the internal source address is written (5 cycles). after the address is input, the read for internal data move (35h) command writes to the command register. this transfers a page from memory into the cache register. the written column addresses are ignored even though all 5 address cycles are required. the memory device is now ready to accept the program for internal data move command. please refer to the description of this command in the following section. program for internal data move 85h-10h after the read for internal data move (00h-35h) command has been issued and r/b# goes high, the program for internal data move (85h-10h) command can be written to the command register. this command transfers the data from the cache register to the data register, and programming of the new destination page begins. the sequence: 85h, destination address (5 cycles), then 10h, is written to the device. after 10h is written, r/b# goes low while the control logic automatically programs the new page. the read status commands and bit 6 of the st atus register can be used instead of the r/b# line to determine when the write is comple te. bit 0 of the status register indicates if the operation was successful. the random data input (85h) command can be used during the program for internal data move command sequence to modify a word or multiple words of the original data. first, data is copied into the cache register using the 00h-35h command sequence, then the random data input (8 5h) command is written along with the address of the data to be modified next. new da ta is input on the external data pins. this copies the new data into the cache register. when 10h is written to the command register, the original data plus the modified data is transferred to the data register, and progra mming of the new page is started. the ran- dom data input command can be issued as many times as necessary before starting the programming sequence with 10h (see figures 20 and 21 on page 33). because internal data move operations do not use external memory, ecc cannot be used to check for errors before programming the data to a new page. this can lead to a data error if the source page contains a bit error due to charge loss or charge gain. if multiple internal data move operations are performed, these bit errors may accu- mulate without correction. for this reason, it is highly recommended that systems using internal data move operations also use a robust ecc scheme that can correct more than the minimum 4 bits per sector required. if a reset (ffh) command is issued during a program for internal data move operation while r/b# is low, the data in the shared memory cells being programmed could become invalid. interrupting a progra mming operation on one page could corrupt the data in another page within the block being programmed. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 33 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary figure 20: internal data move notes: 1. command can be 70h or 78h. figure 21: internal data move with random data input notes: 1. command can be 70h or 78h. i/ox 00h address (5 cycles) 35h 85h address (5 cycles) 10h 70h 1 r/b# t pro g t r status i/ox 00h address (5 cycles) 35h 85h address (5 cycles) data data 85h address (2 cycles) unlimited number of repetitions 10h 70h 1 status r/b# t pro g t r www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 34 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary block erase operation block erase 60h - d0h erasing occurs at the block level. the mt29f8g, mt29f16g, and mt29f32g devices have 4,096, 8,192, and 16,384 blocks, respectiv ely. these blocks are organized into 128 pages per block, 2,112 bytes per page (2,048 + 64 bytes). each block is 264k bytes (256k + 8k bytes). the block erase command operates on one block at a time (see figure 22). three cycles of addresses [pa0?ba18] are required for 8gb and 16gb devices, and 3 cycles of addresses [pa0?ba19] are required for 32gb devices. although [pa0?pa6] are loaded, they are a ?don?t care? and are ignored for block erase operations, since these bits normally specify the page address within a block. see figure 5 on page 12 for addressing details. the actual command sequence is a two-st ep process. the erase setup (60h) com- mand is first written to the command register . then 3 cycles of addresses are written to the device. next, the erase confirm (d0h) command is written to the command reg- ister. at the rising edge of we#, r/b# goes low and the control logic automatically con- trols the timing and erase-verify oper ations. r/b# stays low for the entire t bers erase time. the read status (70h, 78h) commands can be used to check the status of the error. when bit 6 = 1, the erase operation is complete. bit 0 indicates a pass/fail condition where 0 = pass (see figure 22, and table 9 on page 28). figure 22: block erase operation notes: 1. command can be 70h or 78h. re# ce# ale cle i/ox 6 0h address input (3 cycles) status d0h 70h 1 r/b# we# t bers don?t care i/o 0 = 0 erase successful i/o 0 = 1 erase error www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 35 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary two-plane operations this nand flash device is divided into tw o physical planes. each plane contains a 2,112-byte data register, a 2,112-byte cache register, and a 2,048-block flash array. two- plane commands make better use of the flash arrays on these physical planes by per- forming program, read, or erase operations simultaneously, significantly improving system performance. two-plane addressing two-plane commands require two addresse s, one address per plane. these two addresses are subject to the following requirements: ? the least significant block address bit (ba7), must be different for each address. ? the most significant block address bit for 32gb devices (ba19), must be identical for both addresses. ? the page address bits, pa[6:0], must be identical for both addresses. two-plane page read 00h-00h-30h the two-plane page read (00h-00h-30h) operation is similar to the page read (00h-30h) operation. it transfer two pages of data from the flash array to the data regis- ters. each page must be from a different plane on the same die. to enter the two-plane page read mode, write the 00h command to the command register, then write 5 address cycles for plane 0 (ba7 = 0). next, write the 00h command to the command register, then write 5 address cycles for plane 1 (ba7 = 1). finally, issue the 30h command. the first plane and second plane addresses must meet the two-plane addressing requirements, and, in addition, they must have identical column addresses. after the 30h command is written, page data is transferred from both planes to their respective data registers in t r. during these transfers, r/b# goes low. when the trans- fers are complete, r/b# returns high. to read out the data from the first plane data reg- ister, pulse re#. after the data cycle from the plane address completes, issue a two- plane random data read (06h-e0h) command to select the second-plane address, then pulse re# to read out the data from the second-plane data register. alternatively, the read status (70h) command can monitor the data transfers. when the transfers are complete, status register bit 6 is set to ?1.? to read data from one of the two planes, the user must first issue the two-plane ran- dom data read (06h-e0h) command, followed by 5 address cycles (see figure 23 on page 36). to read out data from the plane and column address specified by the two- plane random data read command, pulse re#. when the data cycle is complete, issue a two-plane random data read (0 6h-e0h) command to select the other plane. to output the data beginning at the specified column address, pulse re#. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 3 6 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary figure 23: two-plane page read notes: 1. column and page addresses must be the same. 2. the least significant bloc k address bit must not be the same for the first- and second-plane addresses. cle we# ale re# i/ox r/b# cle we# ale re# i/ox r/b# 00h col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 00h 30h d out 0d out 1d out 0 6 he0h d out 0d out 1d out t r plane 0 address column address j plane 1 address plane 1 address plane 0 data plane 1 data page address m page address m 1 1 column address j www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 37 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary two-plane random data read 06h-e0h the two-plane random data read (06-e0 h) command selects a plane and column address from which to read data after a two-plane page read (00h-00h-30h) com- mand. to issue a two-plane random data read command, issue the 06h command, then 5 address cycles, and follow with the e0h command. pulse re# to read data from the new plane beginning at the specified column address. the primary purpose of the two-plane rand om data read command is to select a new plane and column address within that pl ane. if a new plane does not need to be selected, then the random data read (05h -e0h) command can be used instead. see figure 24 on page 38. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 38 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary figure 24: two-plane page read with random data read r/b# re# i/ox r/b# re# i/ox 00h 00h address (5 cycles) 05h e0h 30h t r plane 0 address plane 0 data plane 0 data address (5 cycles) address (2 cycles) data output data output plane 1 address 0 6 h05h e0h e0h plane 1 data plane 1 data address (5 cycles) address (2 cycles) data output data output plane 1 address 1 1 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 39 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary two-plane program page 80h-11h-80h-10h the two-plane program page operation is similar to the program page (80h- 10h) operation. it programs two pages of data from the data registers to the flash arrays. the pages must be programmed to different plan es on the same die. within a block, the pages must be programmed consecutively from the least significant to most significant page address. random page programming within a block is prohibited. the first plane address and the second plane address must meet the two-plane addressing require- ments (see ?two-plane addressing? on page 35). to begin the two-plane program page operation, write the 80h command, fol- lowed by 5 address cycles for the first plane; then write the data. serial data is loaded on consecutive we# cycles, starting at the given address. next, write the 11h command. the 11h command is a ?dummy? command that informs the control logic that the first set of data for the first plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read status (70h, 78h) commands also indicate that the device is ready when the status register bit 6 is set to ?1.? the only valid commands during t dbsy are read status (70h, 78h) and reset (ffh). after t dbsy, write the 80h command, followed by 5 address cycles for the second plane; then write the data. the program (10h) command is written after the second plane data input is complete. after the 10h command is written, the contro l logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operations to both planes. program verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low for the duration of the array programming time ( t prog). when pro- gramming and verification are complete, r/b# returns high. the read status com- mands also indicate that the device is ready wh en the status register bit 6 is set to ?1.? the only valid commands during t prog are the read status (70h, 78h) commands and reset (ffh). if a reset (ffh) command is issued duri ng a two-plane program page (80h-11h- 80h-10h) operation while r/b# is low, the da ta in the shared memory cells being pro- grammed could become invalid. interrupti ng a programming operation on one page could corrupt the data in another page within the blocks being programmed. if a read status command indicates an error in the operation (status register bit 0 = 1), use the two-plane/multiple-die read status (78h) command twice?one time for each plane?to determine which plane operations failed. during serial data input for either plan e, the random data input (85h) command can be used any number of times to change th e column address within that plane?s page. see figure 25 for more details on two-plane program page operation. figure 25: two-plane program page notes: 1. command can be 70h or 78h. r/b# i/ox 80h 70h 1 10h 11h 80h t dbsy t pro g 1st-plane address address (5 cycles) data input data input status 2nd-plane address address (5 cycles) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 40 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary two-plane random data input 80h-85h-11h (or 80h-85h-10h) after the initial data set is input, additional data can be written to a new column address in the data register with the two-plan e random data input (85h) command. the two-plane random data input command can be used any number of times. it can be used while inputting data to either plane. see figure 26 for the proper command sequence. figure 26: two-plane program page with random data input r/b# i/ox r/b# i/ox 80h address (5 cycles) 11h 80h 85h t dbsy t pro g 1st-plane address address (2 cycles) data input address (5 cycles) 2nd-plane address data input data input 85h 10h address (2 cycles) 1 1 data input different column address than previous 5 address cycles, for 1st plane only different column address than previous 5 address cycles, for 2nd plane only repeat as many times as necessary repeat as many times as necessary www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 41 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary two-plane program page cache mode 80h-11h-80h-15h the two-plane program page cache mode (80h-11h-80h-15h) operation is simi- lar to the program page cache mode (80h-15h) operation. it cache programs two pages of data from the data registers to the flash arrays. the pages must be programmed to different planes on the same die. within a block, the pages must be programmed con- secutively from the least significant to the most significant page address. random page programming within a block is prohibited. the first plane and second plane address must meet the two-plane addressing requirements (see ?two-plane addressing? on page 35). to enter the two-plane program page cache mode, write the 80h command to the command register, write 5 address cycles for the first plane, then write the data. serial data is loaded on consecutive we# cycles, starting at the given address. next, write the 11h command. the 11h command is a ?dummy? command that informs the control logic that the first set of data for the firs t plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read sta- tus (70h) command also indicates that the devi ce is ready when status register bit 6 is set to ?1.? the program page cache mode command ca n cross block boundaries; it cannot cross die boundaries. the only valid commands during t dbsy are read status (70h, 78h) and reset (ffh). after t dbsy, write the 80h command to the command register, write 5 address cycles for the second plane, then write the data. the cache write (15h) command is written after the second-plane data input is complete . data is transferred from the cache regis- ters to the data registers on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data registers and r/b# returns high, memory array programming to both planes begins. when r/b# returns high, new data can be written to the cache registers by issuing another two-plane program page cache mode (80h-11h-80h-15h) sequence. the time that r/b# stays low ( t cbsy) is determined by the actual programming time of the previous operation. for the first cache operation, t cbsy duration is the time it takes for the data to be copied from the cache registers to the data registers. on the second and subsequent two-plane program page cache mode operations, transfer from the cache registers to the data registers is delayed until the contents of the current data registers have been programmed into the arrays. if r/b# is used to determine programming co mpletion, the last operation of the program sequence must use the two-plane prog ram page (80h-11h-80h-10h) command instead of the two-plane program page cache mode (80h-11h-80h-15h) com- mand. if the two-plane program page cache mode (80h-11h-80h-15h) com- mand is used for the last operation, then use read status (70h, 78h) to monitor the operation's progress; status register bit 5 indicates when programming is complete. to determine when the current two-plane program page cache mode (80h-11h- 80h-10h) operation has completed, issue the read status (70h) command and check status register bits 5 and 6. when the device is ready, use status register bit 0 to deter- mine if the current operation passed and status register bit 1 to determine if the previous operation passed. if either bit 0 or bit 1 = 1, indicating a failed operation, then use the two-plane/multiple-die read status (7 8h) command twice?one time for each plane?to determine which current or previous plane operation failed. for more infor- mation on status register bit de finitions, see table 9 on page 28. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 42 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary during the serial data input for either plane, the two-plane random data input (85h) command may be used any number of times to change the column address within that plane. if a reset (ffh) command is issued during a two-plane program page cache mode operation while r/b# or bit 5 or bit 6 of the status register is low, the data in the shared memory cells being programmed could become invalid. interruption of a pro- gram operation on one page could corrupt th e data in another page within the block being programmed. figure 27: two-plane program page cache mode two-plane internal data move 00h-00h-35h/85h-11h-80h-10h a two-plane internal data move operation is similar to an internal data move operation and requires two sequences. first, issue a two-plane read for internal data move (00h-00h-35h) command, then issue the two-plane pro- gram for internal data move (85h-11h-80h-10h) command. data moves are only supported within the planes from which data is read. the first plane and second plane addresses must meet the two-plane addressing requirements for both the two-plane read for internal data move (00h-00h-35h) and two-plane program for internal data move (85h-11h-80h-10h) co mmands (see ?two-plane addressing? on page 35). two-plane read for internal data move 00h-00h-35h the two-plane read for internal data move (00h-00h-35h) command is used in conjunction with the two-plane program for internal data move (85h-11h- 80h-10h) command. first, write 00h to the command register, then write the first plane internal source address (5 cycles). again, wr ite 00h to the command register, followed by r/b# i/ox 80h address/data input 11h 80h 15h t dbsy t cbsy 1st plane 2nd plane address/data input 1 1 2 r/b# i/ox 80h address/data input 11h 80h 15h t dbsy t cbsy 1st plane 2nd plane address/data input r/b# i/ox 80h address/data input 11h 80h 10h t dbsy t lpro g 1st plane 2nd plane address/data input 2 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 43 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary the second-plane internal source address (5 cycles). finally, write 35h to the command register. after the 35h command, r/b# goes low for t r while two pages are read into their respective cache registers. the memory device is now ready to acce pt the two-plane program for internal data move (85h-11h-80h-10h) command. two-plane program for internal data move 85h-11h-80h-10h after the two-plane read for internal data move (00h-00h-35h) command has been issued and r/b# goes high (or the st atus register bit 6 = 1), the two-plane pro- gram for internal data move (85h-11h-80h-10h) command is used. pages must be read from and programmed to the same plane. first, write 85h to the command register, th en write the first-plane destination address (5 cycles), then write 11h to the command register. the 11h command is a ?dummy? command that informs the contro l logic that the first set of data for the first plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. a read status command also indicates that the device is ready when status register bit 6 is set to 1. the only valid commands during t dbsy are read status (70h, 78h) and reset (ffh). after t dbsy, write the 80h command to the comma nd register, then write the second- plane destination address (5 cycles), then write 10h to the command register. data is transferred from the cache registers to the data registers on the rising edge of we#, and programming begins on both planes. r/b# goes low for the duration of array programming time, t prog. when program- ming and verification are complete, r/b# returns high. the read status (70h) com- mand also indicates that the device is ready when status register bit 6 is ?1.? the only valid commands during t prog are read status (70h, 78h) commands and reset (ffh). if a reset (ffh) command is issued during a two-plane program for internal data move (85h-11h-80h-10h) operation whil e r/b# is low, the data in the shared memory cells being programmed could become invalid. interrupting a programming operation on one page could corrupt the data in another page within the blocks being programmed. if the read status (70h) command indicates an error in the operation (status register bit 0 = 1), use the two-plane/multiple-d ie read status (78h) command twice? one time for each plane?to determine which plane operation failed. during the serial data input for either plane, the two-plane random data input (85h) command may be used any number of times to change the column address within that plane. see figure 29 on page 44 for an example. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 44 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary figure 28: two-plane internal data move notes: 1. command can be 70h or 78h. figure 29: two-plane internal data move with random data input notes: 1. command can be 70h or 78h. r/b# i/ox 00h 00h address (5 cycles) 35h t r t dbsy 1st-plane source 85h 11h address (5 cycles) 1st-plane destination address (5 cycles) 2nd-plane source 1 r/b# i/ox 80h 10h address (5 cycles) t pro g 2nd-plane destination 70h 1 status 1 r/b# i/ox 00h 00h address (5 cycles) 35h t r 1st-plane source 1st-plane destination 2nd-plane destination 85h data data address (5 cycles) optional 85h 11h address (2 cycles) address (5 cycles) 2nd-plane source 1 unlimited number of repetitions unlimited number of repetitions r/b# i/ox t pro g t dbsy 80h data data address (5 cycles) optional 85h 10h 70h 1 status address (2 cycles) 1 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 45 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary two-plane block erase 60h-60h-d0h the two-plane block erase (60h-60h-d0h) operation is similar to the block erase (60h-d0h) operation. it erases two blocks instead of one. the blocks to be erased must be on different planes on the same die. the first plane and second plane addresses must meet the two-plane addressing requirements (see ?two-plane addressing? on page 54). additionally, the page addresses, pa[6:0], for both planes must be low. begin a two-plane block erase operation by writing 60h to the command register, followed by 3 address cycles of the first plane block address. then write 60h again to the command register, followed by 3 address cycles of the second-plane block address. finally, issue the d0h command. r/b# goes low for the dura tion of block erase time, t bers. when block erasure is com- plete, r/b# returns high. a read status command also indicates that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t bers are read status (70h, 78h) and reset (ffh). if the read status (70h) command indicates an error in the operation (status register bit 0 = 1), then use the two-plane/multiple-die read status (78h) command twice?one time for each plane?to de termine which plane operation failed. figure 30: two-plane block erase operation notes: 1. command can be 70h or 78h. re# c e# ale c le i/ox 60h a dd ress input (3 c y c les) s tatus d0h 70h 1 r/b# we# t ber s don ? t c are 60h a dd ress input (3 c y c les) i/o 0 = 0 era s e su cc essful i/o 0 = 1 era s e error 1st plane 2n d plane www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__2.fm - rev. b 11/07 en 4 6 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory command definitions micron confidential and proprietary two plane/multiple-die read status 78h in micron nand flash devices that have two planes and possibly more than one die in a package that share the same ce# connection, it is possible to independently poll the status register of a particular plane and die using the two-plane/multiple-die read status (78h) command. this feature operates regardless of device size, organization, or status. this command can be used to check the status during and after two-plane operations. after the 78h command is issued, the device requires 3 address cycles containing the block and page addresses. the most significant block address bit in the third address cycle selects the proper die, and the least significant block address bit in the first address cycle selects the proper plane within that die. after the 78h command and the 3 address cycles, the status register is output on i/o[7:0] when re# is low. changes in the status regist er will be seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to is sue a new read status command to see these changes. the status register bit definitions are identical to those reported by the read status command (see table 9 on page 28). while monitoring the read status to determine when the transfer from the flash array to the data register ( t r) is complete, the user must re -issue the read (00h) command to make the change from status to data. after the read command has been re-issued, pulsing the re# line could result in outputti ng data, starting from the initial column address. the two-plane/multiple-die read status command may be used with all two- plane operations on one die. figure 31: two-plane/multiple-die read status cycle 78h a dd ress (3 c y c les) s tatus output t whr t ar t rea c e# c le we# ale re# i/ox www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 47 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved die operations in devices that have more than one die sharin g a common ce# pin, it is possible to sig- nificantly improve performance by interleavi ng operations between the die. when both die are idle (r/b# is high or status register bit 5 is ?1?), issue a command to the first die . then, while the first die is busy (r/b# is low), issue a command to the other die . there are two methods to determine operatio n completion. the r/b# signal indicates when both die have finished their operatio ns. r/b# remains low while either die is busy. when r/b# goes high, then both die are idle and the operations are complete. alternatively, the two-plane/multiple-die read status (78h) command can report the status of each die individually. if a die is performing a cache operation, like program page cache mode (80h-15h) or two-plane program page cache mode (80h-11h-80h-15h), then the die is able to accept the data for another cache operation when status register bit 6 is ?1.? all operations, including cache operations, are complete on a die when status register bit 5 is ?1.? during and following interleaved die operations, the read status (70h) command is prohibited. instead, use the 78h command to monitor status. these commands select which die will report status. interleaved two-plane commands must also meet the requirements in ?two-plane addressing? on page 35 . page read, two-plane page read, program page, program page cache mode, two-plane program page, two-plane program page cache mode, block erase, and two-plane block erase can be used in any combination as interleaved operations on separate die that share a common ce#. interleaved page read operations figures 32 and 33 show how to perform two types of interleaved page read operations. in figure 32, the r/b# signal is monitore d for operation completion. in figure 33 on page 48, the status register is monitore d for operation completion with the two- plane/multiple-die read status (78h) command. in an interleaved page read operatio n, the two-plane/multiple-die random data read (06h-e0h) command must be used before data is read from each die. the 06h-e0h command selects the die that will ou tput data at the specified column address. figure 32: interleaved page read with r/b# monitoring address address address 00h 30h 0 6 h e0h data address 0 6 h e0h data 00h 30h die 1 die 1 die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 48 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary figure 33: interleaved page read with status register monitoring address 00h 30h address 0 6 h address e0h data address 0 6 h e0h data address 00h 30h die 1 die 1 die 1 die 2 die 2 address die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h 78h status status www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 49 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved two-plane page read operations figures 34 and 35 show how to perform two types of interleaved two-plane page read operations. in figure 34, the r/b# signal is monitored for operation completion. in figure 35 on page 50, the status register is monitored for operation completion with the two-plane/multiple-die read status (78h) command. in an interleaved two-plane page read operation, the two-plane/multiple-die random data read (06h-e0h) command must be used before data is read from each die and each plane. this command selects the die that will output data at the specified column address. the interleaved two-plane page read oper ation must meet tw o-plane addressing requirements. see ?two-plane addressing? on page 35 for details. figure 34: interleaved two-plane page read with r/b# monitoring notes: 1. two-plane addressing requirements apply. 1 1 address 00h 00h address 00h 00h address 30h address 30h die 1 die 2 die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) address 0 6 h e0h data address 0 6 h e0h data die 2 die 2 address 0 6 h e0h data address 0 6 h e0h data die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 50 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary figure 35: interleaved two-plane page read with status register monitoring notes: 1. two-plane addressing requirements apply. 1 1 address 00h 00h address 00h 00h address 30h address 30h die 1 die 2 die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) address 0 6 h e0h data address 0 6 h e0h die 2 die 2 address 0 6 h e0h address die 1 die 2 address 0 6 h address e0h data die 1 die 1 78h 78h status status data data i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 51 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved program page operations figures 36 and 37 show how to perform two types of interleaved program page opera- tions. in figure 36, the r/b# signal is monitored for operation completion. in figure 37 , the status register is monitored for op eration completion with the two-plane/ multiple-die read status (78h) command. random data input (85h) is permitted during interleaved program page opera- tions. figure 36: interleaved program page with r/b# monitoring figure 37: interleaved program page with status register monitoring data address 80h 10h data address 80h 10h die 1 die 2 data address 80h 10h data address 80h 10h die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data address 80h 10h data address 80h 10h die 1 die 2 status address data address 80h 10h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 52 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved program page cache mode operations figures 38 and 39 show how to perform two types of interleaved program page cache mode operations. in figure 38, the r/b# signal is monitored. in figure 39, the status register is monitored with the two-plane/multiple-die read status (78h) command. random data input (85h) is permitted during interleaved program page cache mode operations. figure 38: interleaved program page cache mode with r/b# monitoring figure 39: interleaved program page cach e mode with status register monitoring data address 80h 15h data address 80h 15h die 1 die 2 data address 80h 15h data address 80h 15h die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data address 80h 15h data address 80h 15h die 1 die 2 status address data address 80h 15h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 53 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved two-plane program page operation figures 40 and 41 show how to perform two types of interleaved two-plane program page operations. in figure 40, the r/b# signal is monitored for operation completion. in figure 41 on page 54, the two-plane/multiple-die read status (78h) command is used to monitor the st atus register for operation completion. the interleaved two-plane program pa ge operation must meet two-plane addressing requirements. see ?two-plane addressing? on page 35 for details. random data input (85h) is permitted during interleaved two-plane program page operations. figure 40: interleaved two-plane program page with r/b# monitoring notes: 1. two-plane addressing requirements apply. data address 80h 11h data address 80h 10h die 1 die 1 data address 80h 11h data address 80h 10h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data address 80h 11h data address 80h die 1 die 1 1 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 54 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary figure 41: interleaved two-plane progra m page with status register monitoring notes: 1. two-plane addressing requirements apply. data address 80h 11h data address 80h 10h die 1 die 1 data address 80h 11h data address 80h 10h die 2 die 2 address data address 80h 11h die 1 die 1 data address 80h 10h address die 1 data address 80h 11h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) status status 78h 78h 1 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 55 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved two-plane program page cache mode operations figures 42 and 43 show how to perform two types of interleaved two-plane program page cache mode operations. in fi gure 42, the r/b# signal is monitored. in figure 43 on page 56, the status register is monitored with the two- plane/multiple-die read status (78h) command. the interleaved two-plane program page cache mode operation must meet two-plane addressing requirements. see ?two-plane addressing? on page 35 for details. random data input (85h) is permitted during interleaved two-plane program page cache mode operations. figure 42: interleaved two-plane progra m page cache mode with r/b# monitoring notes: 1. two-plane addressing requirements apply. 1 1 data address 80h 11h data address 80h 15h die 1 die 1 data address 80h 11h data address 80h 15h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data address 80h 11h data address 80h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 5 6 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary figure 43: interleaved two-plane program page cache mode with status register monitoring notes: 1. two-plane addressing requirements apply. data address 80h 11h data address 80h 15h die 1 die 1 data address 80h 11h data address 80h 15h die 2 die 2 address data address 80h 11h die 1 die 1 data address 80h 15h address die 1 data address 80h 11h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) status status 78h 78h 1 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 57 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved block erase operations figures 44 and 45 show how to perform two types of interleaved block erase operations. in figure 44, the r/b# signal is monitored for operation completion. in figure 45, the two-plane/multiple-die read status (78h) command is used to monitor the status register for operation completion. figure 44: interleaved block erase with r/b# monitoring figure 45: interleaved block erase with status register monitoring address 6 0h d0h die 1 address 6 0h d0h die 2 address 6 0h d0h die 1 address 6 0h d0h die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) address 6 0h d0h die 1 address 6 0h d0h die 2 address status die 1 address 6 0h d0h die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 58 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary interleaved two-plane block erase operations figures 46 and 47 show how to perform two types of interleaved two-plane block erase operations. in figure 46, the r/b# sign al is monitored for operation completion. in figure 47 on page 59, the two-plane/multiple-die read status (78h) command is used to monitor the stat us register for operation completion. the interleaved two-plane block erase oper ation must meet two-plane addressing requirements. see ?two-plane addressing? on page 35 for details. figure 46: interleaved two-plane block erase with r/b# monitoring notes: 1. two-plane addressing requirements apply. address 6 0h die 1 address 6 0h d0h die 1 address 6 0h die 2 address 6 0h d0h die 2 address 6 0h die 1 address 6 0h d0h die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__3.fm - rev. b 11/07 en 59 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary figure 47: interleaved two-plane block erase with status register monitoring notes: 1. two-plane addressing requirements apply. address 6 0h die 1 address 6 0h d0h die 1 address 6 0h die 2 address 6 0h d0h address die 2 address die 1 die 1 address 6 0h die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h status d0h 6 0h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 0 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary reset operation reset ffh the reset command is used to put the memory device into a known condition and to abort a command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partiall y erased or programmed, and is invalid. the command register is cleared and is ready for the next command. the data register and cache register contents are marked invalid. if a reset command is issued during any type of programming operation (program page, program page cache mode, program for internal data move, two- plane program page, two-plane program page cache mode, or two- plane program for internal data move) while r/b# is low, the data in the shared memory cells being programmed could become invalid. interrupting any pro- gramming operation on one page could corrupt the data in another page within the block being programmed. the status register contains the value e0h wh en wp# is high; otherwise, it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register (see figure 48 and table 10). the reset command must be issued to all ce#s as the first command after power-on. the device will be busy for a maximum of 1ms. during and following the initial reset (ffh) command, and prior to issuing the next command, use of the two-plane/mul- tiple-die read status (78h) command is prohibited. figure 48: reset operation table 10: status register contents after reset operation condition status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex wp# hi g hready 11100000e0h wp# low ready and write protected 01100000 6 0h cle ce# we# r/b# i/ox t rst t wb ffh reset command www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 1 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary write protect operation it is possible to enable and disable program and erase commands using wp#. figures 49 through 60 illu strate the setup time ( t ww) required from wp# toggling until a program or erase command is latched in to the command register. after command cycle 1 is latched, wp# must not be toggled until the command is complete and the device is ready (status register bit 5 is ?1?). figure 49: erase enable figure 50: erase disable figure 51: program enable figure 52: program disable t ww 6 0h d0h we# i/ox wp# r/b# t ww 6 0h d0h we# i/ox wp# r/b# t ww 80h 10h or 15h we# i/ox wp# r/b# t ww 80h 10h or 15h we# i/ox wp# r/b# www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 2 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary figure 53: program for internal data move enable figure 54: program for internal data move disable figure 55: two-plane erase enable figure 56: two-plane erase disable t ww 85h 10h we# i/ox wp# r/b# t ww 85h 10h we# i/ox wp# r/b# t ww 6 0h 6 0h d0h we# i/ox wp# r/b# t ww 6 0h 6 0h d0h we# i/ox wp# r/b# www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 3 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory micron confidential and proprietary figure 57: two-plane program enable figure 58: two-plane program disable figure 59: two-plane program for internal data move enable figure 60: two-plane program for internal data move disable t ww 80h 11h 80h 10h or 15h we# i/ox wp# r/b# t ww 80h 11h 80h 10h or 15h we# i/ox wp# r/b# t ww 85h 11h 80h 10h we# i/ox wp# r/b# t ww 85h 11h 80h 10h we# i/ox wp# r/b# www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 4 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory error management micron confidential and proprietary error management micron nand flash devices are specified to have a minimum of 3,996 valid blocks (n vb ) out of every 4,096 total available blocks for every 8gb. this means the devices may have blocks that are invalid when they are shipped. invalid blocks are blocks that contain more bad bits than can be corrected by required ecc. additional bad blocks may develop with use. however, the total number of available blocks will not fall below n vb during the endurance life of the product. although nand flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block mapping, replacement, and error correction algorithms. this type of software environment ensures data integrity. internal circuitry isolates ea ch block from other blocks, so the presence of a bad block does not affect the operation of the rest of the flash device. the first block (physical block address 00h) for each ce# is guaranteed to be valid with ecc when shipped from the factory. before nand flash devices are shipped from micron, they are erased. the factory iden- tifies invalid blocks before shipping by pr ogramming data other than ffh into the first spare location (column address 2,048) of the first page (page 0) or the second page (page 1) of each bad block. system software should check the first spare address on the first 2 pages of each block prior to performing any erase or programmi ng operations on the flash device. a bad block table can then be created, allowing system software to map around these areas. factory testing is performed under worst-case conditions. because blocks marked ?bad? may be marginal, it may not be possible to recover these bad block markings if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over th e life of the flash device, certain precautions must be taken: ? always check status after a program, erase, or data move operation. ? under typical use conditions, utilize a mi nimum of 4-bit ecc per 528 bytes of data. ? use a bad-block replacement algorithm. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 5 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory electrical characteristics micron confidential and proprietary electrical characteristics stresses greater than those listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods ma y affect reliability. table 11: absolute maximum ratings by device voltage on any pin relative to v ss parameter/condition symbol min max unit voltage input mt29fx g xx v in ?0. 6 +4. 6 v v cc supply voltage mt29fx g xx v cc ?0. 6 +4. 6 v storage temperature t st g ? 6 5 +150 c short circuit output current, i/os ?5ma table 12: recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a 0 ? +70 c extended ?40 ? +85 c v cc supply voltage mt29fx g xx v cc 2.7 3.3 3. 6 v g round supply voltage v ss 000v www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 66 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory electrical characteristics micron confidential and proprietary v cc power cycling micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. (the wp# signal permits additional hardware pro- tection during power transitions.) when v cc reaches 2.3v for a 3v device, a minimum of 100s should be allowed for the flash device to initialize before any commands are exe- cuted (see figure 61 for the states of signals during v cc power cycling). the reset command must be issued to all ce#s as the first command after the nand flash device is powered on. each ce# will be busy for a maximum of 1ms after a reset command is issued. figure 61: ac waveforms during power transitions 100s (min) un d efine d don?t c are ffh 1ms (max) 3v d evi c e: 2.3v 3v d evi c e: 2.3v t cs v cc c le c e# wp# lo c k 1 we# ale re# i/ox r/b# www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 7 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory electrical characteristics micron confidential and proprietary notes: 1. invalid blocks are blocks that contain more bad bits than can be corre cted by required ecc. see ?error management? on page 6 4 for device ecc requirements. the device may contain bad blocks upon shipment. additional bad bl ocks may develop over time; however, the total number of available blocks will not drop below n vb during the endurance life of the device. do not erase or program bloc ks marked invalid by the factory. 2. block 00h (the first block) is guaranteed to be valid with ecc wh en shipped from factory. 3. each ce# has a maximum of 100 invalid blocks. 4. each ce# has a maximum of 200 invalid blocks, not to exceed 100 invalid blocks for each nand flash die. table 13: m29fxgxx device dc and operating characteristics parameter conditions symbol min typ max unit sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc 1? 15 20ma program current ?i cc 2? 15 20ma erase current ?i cc 3? 15 20ma standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb 1? ? 1 ma standby current (cmos) mt29f8 g 08maa ce# = v cc - 0.2v; wp# = 0v/v cc i sb 2? 10 50a mt29f1 6g 08qaa ?20100a mt29f32 g 08taa ?40200a input leakage current mt29f8 g 08maa v in = 0v to v cc i li ? ? 10 a mt29f1 6g 08qaa ? ? 20 a mt29f32 g 08taa ? ? 40 a output leakage current mt29f8 g 08maa v out = 0v to v cc i lo ? ? 10 a mt29f1 6g 08qaa ? ? 20 a mt29f32 g 08taa ? ? 40 a input high voltage i/o [7:0], i/o [15:0], ce#, cle, ale, we#, re#, r/b#, wp# v ih 0.8 x v cc ?v cc + 0.3 v input low voltage (all inputs) ?v il ?0.3 ? 0.2 x v cc v output high voltage i oh = ?400a v oh 2.4 ? ? v output low voltage i ol = 2.1ma v ol ??0.4v output low current (r/b#) v ol = 0.4v i ol (r/b#) 8 10 ? ma table 14: valid blocks parameter symbol device min max unit notes valid block number n vb mt29f8 g xx 3,99 6 4,09 6 blocks 1, 2, 3 mt29f1 6g xx 7,992 8,192 1, 2, 3 mt29f32 g xx 15,984 1 6 ,384 1, 2, 4 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 8 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory electrical characteristics micron confidential and proprietary notes: 1. these parameters are verified in device characterization and are not 100 percent tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. notes: 1. verified in device charac terization; not 100 percent tested. notes: 1. timing for t adl begins in the address cy cle, on the final rising edge of we#, and ends with the first rising edge of we# for data input. table 15: capacitance description symbol device max unit notes input capacitance c in mt29f8 g xx 10 pf 1, 2 mt29f1 6g xx 20 mt29f32 g xx 40 input/output capacitance (i/o) c out mt29f8 g xx 10 pf 1, 2 mt29f1 6g xx 20 mt29f32 g xx 40 table 16: test conditions parameter value notes input pulse levels mt29fx g xx 0.0v to 3.3v input rise and fall times 5ns input and output timing levels v cc /2 output load mt29fx g xx (v cc = 3.0v 10%) 1 ttl g ate and cl = 50pf 1 mt29fx g xx (v cc = 3.3v 10%) 1 ttl g ate and cl = 100pf 1 table 17: ac characteristics ? command, data, and address input parameter symbol min max unit notes ale to data start t adl 70 ? ns 1 ale hold time t alh 5?ns ale setup time t als 10 ? ns ce# hold time t ch 5?ns cle hold time t clh 5?ns cle setup time t cls 10 ? ns ce# setup time t cs 15 ? ns data hold time t dh 5?ns data setup time t ds 10 ? ns write cycle time t wc 25 ? ns we# pulse width hi g h t wh 10 ? ns we# pulse width t wp 12 ? ns wp# setup time t ww 30 ? ns www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 6 9 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory electrical characteristics micron confidential and proprietary notes: 1. for pa g e read cache mode and pro g ram pa g e cache mode operations, the cache mode timing applies. 2. transition is measured 200mv from steady-sta te voltage with load. this parameter is sam- pled and not 100 percent tested. 3. the first time the reset (ffh) co mmand is issued while the device is idle, the device goes busy for a maximum of 1ms. thereafter, th e device goes busy for a maximum of 5s. 4. do not issue a ne w command during t wb, even if r/b# is ready. table 18: ac characteristics ? normal operation parameter symbol cache mode standard mode unit notes min max min max ale to re# delay t ar 10 ? 10 ? ns ce# access time t cea ?25?25ns1 ce# hi g h to output high-z t chz ?30?30ns2 cle to re# delay t clr 10 ? 10 ? ns ce# hi g h to output hold t coh 15 ? 15 ? ns cache busy in page read cache mode (first 31h) t dcbsyr1 730730s cache busy in page read cache mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 50 t dcbsyr1 50 s output high-z to re# low t ir 0?0?ns1 data transfer from flash array to data register t r ?50?50s read cycle time t rc 35 ? 25 ? ns 1 re# access time t rea ?22?15ns1 re# hi g h hold time t reh 15 ? 10 ? ns 1 re# hi g h to output hold t rhoh 15 ? 15 ? ns re# hi g h to we# low t rhw 100 ? 100 ? ns re# hi g h to output high-z t rhz ?100?100ns2 re# low to output hold t rloh 5?5?ns re# pulse width t rp 17 ? 12 ? ns 1 ready to re# low t rr 20 ? 20 ? ns reset time (read/pro g ram/erase) t rst ? 5/10/500 ? 5/10/500 s 3 we# hi g h to busy t wb ? 100 ? 100 ns 3, 4 we# hi g h to re# low t whr 6 0? 6 0?ns www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 70 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory electrical characteristics micron confidential and proprietary notes: 1. one total to the same page. 2. t cbsy max time depends on timi ng between internal progra m completion and data in. 3. t lpro g = t pro g (last page) + t pro g (last - 1 page) - command load time (last page) - address load time (last page) - data load time (last page). table 19: program/erase characteristics parameter description typ max unit notes nop number of part ial page programs ? 1 cycles 1 t bers block erase operation time 210ms t cbsy busy time for pro g ram cache operation 30 2,200 s 2 t dbsy busy time for two-plane pro g ram pa g e operation 0.5 1 s t lpro g last pro g ram pa g e operation time ???3 t pro g pro g ram pa g e operation time 6 50 2,200 s www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 71 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary timing diagrams figure 62: command latch cycle figure 63: address latch cycle we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls don?t care we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 don?t care undefined t wc www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 72 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 64: input data latch cycle notes: 1. d in final = 2,111. we# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in 1 d in final 1 don ? t care t wc d in 0 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 73 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 65: serial access cycle after read figure 66: read status cycle notes: 1. command can be 70h or 78h. ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea don ? t care t rhz t chz t rhz t rhoh r/b# t coh d out d out d out re# ce# we# cle i/ox t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h 1 don ? t care t cea t coh status output www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 74 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 67: page read operation figure 68: read operation with ce# ?don?t care? d out n d out n + 1 d out m we# ce# ale cle re# r/b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3 re# ce# t rea t chz t coh t cea re# ce# ale cle i/ox i/ox out r/b# we# data output t r don ? t care address (5 cycles) 00h 30h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 75 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 69: random data read operation we# ce# ale cle re# r/b# i/ox busy col add 1 col add 2 row add 1 row add 2 row add 3 00h t r t wb t ar t rr don ? t care t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n d out n + 1 30h t whr column address n column address m www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 7 6 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 70: page read cache mode operation, part 1 of 2 t wc we# ce# ale cle re# r/b# i/ox column address 0 1 d out page address m page address m + 1 t cea t ds t cls t cs t ch t dh don ? t care t rr t wb t r t dcbsyr2 column address 0 continued to 1 of next page t rc t rea 30h d out 0 d out 0 d out 1 column address 00h page address m 31h 31h col add 1 col add 2 row add 1 row add 2 row add 3 00h t dcbsyr1 t clh www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 77 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 71: page read cache mode operation, part 2 of 2 we# ce# ale cle re# r/b# i/ox 1 page address m + 1 don ? t care column address 0 continued from 1 of previous page page address m + x column address 0 t clh t rea t cea t ds t dh t rr t dcbsyr2 t dcbsyr2 t wb column address 0 d out 0 d out 1 31h d out 0 d out 3fh d out 1 d out 0 d out d out 1 t cls t cs t rc d out 31h t ch t dcbsyr2 d out page address m + 2 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 78 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 72: page read cache mode operation without r/b#, part 1 of 2 t wc we# ce# ale cle re# i/ox 30h 70h 70h status d out 0 column address 0 1 d out 0 d out column address 00h page address m page address m t cea t ds t clh t cls t cs t ch t dh don ? t care 31h 31h column address 0 70h status i/o 6 = 0, cache busy = 1, cache ready i/o 5 = 0, busy = 1, ready continued to 1 of next page col add 1 col add 2 row add 1 row add 2 row add 3 00h 00h 00h t rc t rea status i/o 6 = 0, cache busy = 1, cache ready page address m + 1 d out 1 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 79 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 73: page read cache mode operation without r/b#, part 2 of 2 we# ce# ale cle re# i/ox 1 don ? t care column address 0 continued from 1 of previous page column address 0 t rea t cea t ds t dh column address 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d out d out 1 d out 0 t rc d out 31h 70h status i/o 6 = 0, cache busy = 1, cache ready status i/o 6 = 0, cache busy = 1, cache ready 70h 70h status i/o 6 = 0, cache busy = 1, cache ready 00h 00h 00h t clh t ch t cls t cs d out 0 page address m + 1 page address m + 2 page address m + x www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 80 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 74: read id operation note: see table 8 on page 27 for actual values. figure 75: program operation with ce# ?don?t care? we# ce# ale cle re# i/ox address, 1 cycle 90h 00h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr cle ce# we# ale i/ox address (5 cycles) data input 10h we# ce# t wp t ch t cs don?t care data input 80h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 81 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 76: program page operation notes: 1. command can be 70h or 78h. figure 77: program page operation with random data input notes: 1. command can be 70h or 78h. we# ce# ale cle re# r/b# i/ox t wc t adl serial data input command x8 device: m = 2,112 bytes pro g ram command read status command 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h 1 status 10h t pro g t wb don?t care we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in n+1 t adl t adl random data input command column address pro g ram command read status command serial input 85h t pro g t wb don?t care col add 1 col add 2 d in n d in n+1 70h 1 status 10h www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 82 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 78: internal data move operation notes: 1. command can be 70h or 78h. figure 79: program page cache mode operation notes: 1. command can be 70h or 78h. 2. pro g ram pa g e cache mode operations must not cross die address boundaries. we# ce# ale cle re# r/b# i/ox t wb t r t pro g busy busy t wc internal data move don?t care t adl 70h 1 10h status data n col add 1 00h 35h col add 2 row add 1 row add 2 row add 3 85h data 1 row add 3 row add 2 co1 add 2 row add 1 col add 1 read status command t wb we# ce# ale cle re# r/b# i/ox t cbsy t wb t wb t lpro g col add 1 10h 70h 1 status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 d in m d in n last page - 1 last page serial data input serial input pro g ram t wc don?t care 80h t adl row add 3 pro g ram 80h 15h d in m d in n row add 3 www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 83 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 80: program page cache mode operation ending on 15h notes: 1. command can be 70h or 78h. we# ce# ale cle re# i/ox 15h col add 1 80h 15h status 70h 1 70h 1 70h 1 status status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page - 1 serial data input serial input pro g ram pro g ram t wc don?t care 80h poll status until: i/o 6 = 1, ready to ensure pro g ram success, last 2pages: i/o5 = 1, ready i/o0 = 0, last page pro g ram successful i/o1 = 0, last page -1 pro g ram successful t adl www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 84 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory timing diagrams micron confidential and proprietary figure 81: block erase operation notes: 1. command can be 70h or 78h. figure 82: reset operation we# ce# ale cle re# r/b# i/ox auto block erase setup command erase command read status command busy row address 6 0h row add 1 row add 2 row add 3 70h 1 status d0h t wc t bers t wb t whr don ? t care i/o0 = 0, pass i/o0 = 1, fail cle ce# we# r/b# i/ox t rst t wb ffh reset command www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 85 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory package dimensions micron confidential and proprietary package dimensions figure 83: 48-pin tsop type 1 ocpl (wc package code) note: all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 12.00 0.08 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 g age plane 0.25 for reference only 0.50 for reference only 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. www.datasheet.in
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits spec ified over the power supply an d temperature range set forth herein. although considered final, these specifications ar e subject to change, as furthe r product development and data characterization sometimes occur. 8gb, 16gb, and 32gb: x8 nand flash memory package dimensions mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 8 6 ?2007 micron technology, inc. all rights reserved. micron confidential and proprietary figure 84: 48-pin tsop type 1 cpl (wp package code) note: all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 g age plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. www.datasheet.in
mlc pdf: 09005aef828313aa / source: 09005aef82831392 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_l41b_mlc__4.fm - rev. b 11/07 en 87 ?2007 micron technology, inc. all rights reserved. 8gb, 16gb, and 32gb: x8 nand flash memory revision history micron confidential and proprietary revision history rev. b, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/07 ? ?error management? on page 64: updated n vb to 3,996. ? table 13, ?m29fxgxx device dc and operat ing characteristics,? on page 67: updated values for icc1, icc2, and icc3. ? table 14, ?valid blocks,? on page 67: up dated min valid blocks to 3,996 for the mt29f8gxx; to 7,992 for the mt29f16gxx, and to 15,984 for the mt29f32gxx. updated note 3 from 160 to 100 (max) inva lid blocks per ce#. updated note 4 from 320 to 200 (max) invalid blocks per ce#, and the not-to-exceed count from 200 to 160 per nand flash die. rev a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/07 ?initial restricted release. www.datasheet.in

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