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enpirion ? power datasheet en5395qi 9a powersoc synchronous buck pwm dc - dc converter w ith integrated inductor 3- pin vid output voltage select description th e en539 5 qi is a power s ystem on a chip (p ower soc) dc- dc converter. it is specifically designed to meet the precise voltage and fast transient requirements of present and future high - performance, low - power processor, dsp, fpga, asic, memory boards , and system level applications in a distributed power architecture. advanced circuit techniques, ultra high switching frequency, and innovative , high - density, integrated circuit and proprietary inductor technology deliver high - quality, ultra compact, non- isolated dc - dc conversion. operating this converter requires as few as five external components that include small value input and output ceramic capacitors and a soft - start capacitor. altera?s enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. in addition, a reduction in the number of vendors required for the complete power sol ution helps to enable an overall system cost savings. applications ? area constrained applications ? noise sensitive applications ? low voltage, distributed power architectures with 2.5v, 3.3v or 5v rails ? computing ? enterprise storage ? broadband, networking, lan/wan, optical ? dsl, stb, dvr, dtv, industrial pc ordering information part number temp rating (c) package en53 9 5 qi - 40 to +85 58 - pin qfn t&r evb - en539 5 qi qfn evaluation board features ? i ntegrated inductor technology : integrated i nductor , mosfets, controller in a 10 x 12 x 1.85mm package ? low part count: only 5 mlc capacitors. ? up to 30w continuous output power. ? low output impedance optimized for 90 nm ? master/slave configuration for paralleling. ? 5mhz operating frequency. ? high efficiency, up to 93%. ? wide input voltage range of 2.375v to 5.5v. ? 3- pin vid output voltage select to choose one of 7 pre - programmed output voltages. ? output e nable pin and power ok signal. ? programmable soft - start time. ? adjustable over - current protection. ? thermal shutdown, short circuit, over - voltage and under - voltage protection. ? rohs compliant, msl level 3, 260c reflow. typical application circuit vid output voltage select v out v in vsense 2 x 47 f 15nf vout vs0 vs1 vs2 pok pgnd agnd ss pvin avin 2 x 47 f 1 figure 1 . simple layout. 10mm 12mm www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi pin configuratio n below is a top view diagram of the en5395q package. note: nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. figure 2 . pin diagram, top view. www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi pin descriptions pin n am e function 1-3 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground. this pin may be connected internally. however, this pin must be soldered to the pcb. 4-5 nc (sw) no connect ? these pins are internally connected to the common drain output of the interna l mosfets. nc(sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. 6- 13 nc no connect ? this pin sho uld not be electrically connected to any external signal, voltage, or ground. this pin may be connected internally. however, this pin must be soldered to the pcb. 14- 20 vout regulated converter output. connect these pins to the load and place output ca pacitor from these pins the pgnd pins 24 - 26. 21- 22 nc(sw) no connect ? these pins are internally connected to the common drain output of the internal mosfets. nc(sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. 23 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground. this pin may be connected internally. however, this pin must be soldered to the pcb. 24 - 29 pgnd output power ground. refer to layout guideline section. 30 - 35 pvin input power supply. connect to input power supply. decouple with input capacitor to pgnd. 36- 37 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground. this pin may be connected internally. however, this pin must be soldered to the pcb. 38 rocp optional over current protection adjust pin. place rocp resistor between this pin and agnd (pin 40) to adjust the over current trip point. 39 avin analog voltage input for the controller circuits. connect this pin to the input power supply. 40 agnd analog ground for the controller circuits. 41- 42 nc no connect ? thi s pin should not be electrically connected to any external signal, voltage, or ground. this pin may be connected internally. however, this pin must be soldered to the pcb. 43 vs2 voltage select line 2 input. see table 1. 44 vs1 voltage select line 1 input. see table 1. 45 vs0 voltage select line 0 input. see table 1. 46 pok power ok is an open drain transistor for power system state indication. pok is a logic high when vout is with - 10% to +20% of vout nominal. 47 vsense remote voltage sense input. connect this pin to the load voltage at the point to be regulated. 48 ss soft - start node. the soft - start capacitor is connected between this pin and agnd. the value of this capacitor determines the startup timing. 49 eain optional error amplifier input. allows for customization of the control loop. 50 eaout optional error amplifier output. allows for customization of the control loop. 51 comp output of the buffer leading to the error amplifier. used for external modifications of the compensat ion network. 52 enable input enable. applying a logic high, enables the output and initiates a soft - start. applying a logic low disables the output. 53 pwm pwm input/output. used for optional master/slave configuration. when m/s pin is asserted ?low?, pwm will output the gate - drive pwm waveform. when the m/s pin is asserted ?high?, the pwm pin is configured as an input for pwm signal from the ?master? device. pwm pin can drive up to 3 slave devices. 54 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground. this pin may be connected internally. however, this pin must be soldered to the pcb. 55 m/s op tional master/slave select pin. asserting pin ?low? places device in master mode for current sharing. pwm pin (53) will output pwm drive signal. asserting pin ?high? will place the device 3 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi pin n am e function in slave mode. pwm pin (53) will be configured to input (receive) pwm drive signal from ?master? device. 56- 58 nc no connect ? do not electrically connect these pins to each other or to pcb. caution! may be internally connected. block diagram (+) (-) error amp v out p-drive n-drive uvlo thermal limit over voltage soft start sawtooth generator (+) (-) pwm comp pvin enable compensation bandgap reference pgnd avin eaout ss reference voltage selector current limit eain agnd power good logic v out pok rocp voltage selector vs0 vs1 vs2 vsense comp nc(sw) figure 3 . s yste m block diagram. 4 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond recommended operating conditions is not implied. stress beyond absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter symbol min m ax units input supply voltage v in - 0.5 7.0 v voltages on: enable, v sense , v s0 - v s2 , m/s - 0.5 v in v voltages on: eain, eaout, comp - 0.5 2.5 voltages on: ss, pwm - 0.5 3.0 voltages on: pok - 0.5 v in + 0.3 storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020a 260 c esd rating (based on human body model) 2000 v recommended operating conditions parameter symbol min m ax units input voltage range v in 2.375 5.5 v output voltage range (note 1) v out 0.75 v in - v dropout v output current (note 2 ) i out 0 9 a operating ambient temperature t a - 40 +85 c operating junction temperature t j - 40 +125 c note 1 : v dropout = i load x dropout resistance note 2 : reference figures 5 and 6 for the output current derating curve s. thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) (note 3 ) ja 18 c/w thermal resistance: junction to case (0 lfm) jc 1.5 c/w thermal overload trip point t j - tp +150 c thermal overload trip point hysteresis 20 c note 3: based on four layer board and proper thermal design in line with jedec eij/jesd 51 standards electrical characteristics note: v in =5.5v over operating temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ m ax units v out initial accuracy ? v out_init t a = 25c , 2.375 v ? v out_ all 2.4v t a + 85c 0a i load 9 a vid output voltage setting (v): 1.2, 1.25, 1.5, 1.8, 2.5, 3.3 0.8 -3 -4 +3 +4 % transient response p eak deviation ? v out (i out = 0% to 100% or 100% to 0% or rated load) 5 % 5 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi parameter symbol test conditions min typ m ax units v in = 5v, 1.2v note: reference figures 5 and 6 for the output current derating curves 9 a current limit threshold i ocp_th 11 a shut - down supply current i s enable=0v 50 2.375v v 5.5v a pok threshold high percentage of v out nominal 120 % pok threshold low percentage of v out nominal 90 % pok low voltage i pok = 4ma (max sink current) 0.4 v pok high voltage v in v dropout resistance ? i out with 2 ? 4 converters in parallel, the difference between any 2 parts. ? v in < 50mv; r trace < 10m ? . +/ - 10 % 6 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi typical performance characteristics circuit of figure 1, v in = 5 v, v out = 1.2 v and t a = 25c, unless otherwise noted. top to bottom: v out = 2.5 v, 1.8 v, 1.5 v, 1.2 v, 0.8 v top to bottom: v out = 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, 0.8 v ripple voltage, 5. 5v in /1.2v out , i out =9 a, ripple voltage, 3.3v in /1.2v out , i out =9 a, c out = 5x22uf. c out = 5x22uf. transient response : 5v in /1.2v out , 0 - 9a, 7 a/us. transient response : 5v in /3.3v out , 0 - 9a, 7 a/us. c out = 5x 22uf. c out = 5x 22uf efficiency (vin = 5.0v) 50 55 60 65 70 75 80 85 90 95 0 2 4 6 8 10 load (amperes) efficiency (%) efficiency (vin =3.3v) 60 65 70 75 80 85 90 95 0 2 4 6 8 10 load (amperes) efficiency (%) 7 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi start up waveforms v in =5.0v, v out =1.2v, c ss =15nf, start up waveforms v in =5.0v, v out =3.3v, c ss =15nf, ch 1 = v out , ch 3 = enable, ch 4 = pok. ch 1 = v out , ch 3 = enable, ch 4 = pok. 8 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi functional description the en5395qi is a synchronous, pin programmable power supply with integrated power mosfet switches and integrated inductor. the nominal input voltage range is 2.375 - 5.5v. the output can be set to common pre - set voltages by connecting appropriate combinations of 3 voltage selection pins to ground. the feedback control loop is a type iii voltage - mode and the part uses a low - noise pwm topology. up to 9 a of output current can be drawn from this converter. the 5mhz operating frequency enables the use of small - size output capacitors. the power supply has the following protection features: ? programmable over - current protection (to protect the ic from excessive load current) ? thermal shutdown with hysteresis. ? over - voltag e protection ? under - voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2v additional features include: ? soft - start circuit, limiting the in - rush current when the converter is powered up. ? power good c ircuit indicating whether the output voltage is within 90% - 120% of the programmed voltage. output voltage programming the en5395qi output voltage is programmed using a 3 - pin voltage- id or vid selector. three binary vid pins allow the user to choose one of seven pre - set voltages. refer to table 1 for the proper vid pin settings to program v out . the voltage select pins, vs0, vs1, and vs2, are pulled - up internally and so will default to a logic high, or ?1?, if left ?open?. connecting the voltage select p in to ground will result in a logic ?0?. table 1: output voltage select table vs2* vs1* vs0* output voltage 0 0 0 3.3v 0 0 1 2.5v 0 1 0 1.8v 0 1 1 1.5v 1 0 0 1.25v 1 0 1 1.2v 1 1 0 0.8v 1 1 1 reserved input capacitor selection the en5395qi requires between 40 - 80uf of input capacitance. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these l ose capacitance with frequency, temperature and bias voltage. in some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. table 2. recommended input capacitors. description mfg p/n 22uf, 10v, x7r, 1210 murata grm32er71a226ke20l taiyo yuden lmk325b 7 226km -t 47uf, 10v, x5r, 1210 murata grm32er 6 1 a4 76 ke20l taiyo yuden lmk325bj476km -t output capacitor selection the en5395qi has been optimized for use with approximately 10 0f of output capacitance. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these loose capacitance with frequency, temperature and bias voltage. 9 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi t able 3. recommended output capacitors . description mfg p/n 10uf, 10 v, x7r, 1206 murata grm31cr71a106ka01l taiyo yuden lmk316b 7 106k l - t 22uf, 6.3v, x5r, 1206 murata grm31cr60j226ke19l taiyo yuden lmk316bj226kl -t 47uf, 6.3v, x5r, 1206 murata grm31cr 60j476me19l taiyo yuden j mk316bj476 m l - t output ripple voltage is determined by the aggregate output capacitor impedance. output impedance, denoted as z, is comprised of effective series resistance, esr, and effective series inductance, esl: z = esr + esl. placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. n total zzzz 1 ... 111 21 +++= output capacitor configuration typical output ripple (mvp - p) (as measured on en5395qi evaluation board) 2 x 47uf 20 5 x 22 uf 12 enable operation the enable pin provides a means to shut down the device, or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter into normal operation. when the enable pin is asserted high, the device will undergo a normal soft start. soft - start operation soft start is a method to reduce in - rush current when the device is enabled. the output voltage is ramped up slowly upon start - up. the output rise time is controlled by choice of a soft - start capacitor, which is placed between the ss pin (pin 48) and the agnd pin (pin 40). rise time: t r = c ss * 80k ? during start - up of the converter, the reference voltage to the error amplifier is gradually increased to its final level by an internal current source of typically 10ua. typical soft - start rise time is 1ms to 3ms. typical ss capacitor values are in the range of 15nf to 30 nf. pok operation the pok signal is an open drain signal from the converter indicating the output voltage is within the specified range. the pok signal will be a logic high when the outp ut voltage is within 90% - 120% of the programmed output voltage. if the output voltage goes outside of this range, the pok signal will be a logic low until the output voltage has returned to within this range. in the event of an over - voltage condition the pok signal will go low and will remain in this condition until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state. the internal pok fet is designed to tolerate up to 4ma. the pull - up resistor value should be chosen to limit the current from exceeding this value when pok is logic low. over - current protection when an over current condition occurs, v out is pulled low. this condition is maintained for a period of 1.2 ms and then a normal soft start cyc le is initiated. if the over current condition still persists, this cycle will repeat. the ocp trip point is nominally set to 150% of maximum rated load. it is possible to increase the ocp trip point to 200% of the maximum rated load by connecting a 5k ? resistor between the rocp pin (pin 38) and agnd (pin 40 ). this option is intended for startup into capacitive loads such as certain fpgas and asics. 10 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi over - voltage protection when the output voltage exceeds 120% of the programmed output voltage, the pwm op eration stops, the lower n - mosfet is turned on and the pok signal goes low. when the output voltage drops below 95% of the programmed output voltage, normal pwm operation resumes and pok returns to its high state. thermal overload protection thermal shutdown will disable operation once the junction temperature exceeds approximately 150oc. once the junction temperature drops by approx 20oc, the converter will re - start with a normal soft - start. input under - voltage lock - out circuitry is provided to ensure that when the input voltage is below the specified voltage range, the converter will not start - up. circuits for hysteresis, input de - glitch and output leading edge blanking are included to ensure high noise immunity and prevent false tripping. compensation the en5395 is internally compensated through the use of a type 3 compensation network and is optimized for use with about 10 0f of output capacitance and will provide excellent loop bandwidth and transient performance for most applications. (see the section on capacitor selection for details on recommended capacitor types.) voltage mode operation provides high noise immunity at light load. in some cases modifications to the compensation may be required. the en5395qi provides access to the internal compensation network to allow for customization. for more information, contact power applications support. parallel device operation in order to power a load that is higher than the rated 9 a of the en5395, from 2 to 4 devices can be placed in parallel for providing a single load with up to 36 a of output current. paralleling more than 1 device is accomplished by s electing a master device and tying that m/s pin to agnd. all slave devices should have their m/s pin tied to avin. the pwm pin from the master device is connected to all slave device pwm pins. the pwm signal is a 5 mhz drive signal and must be routed appropriately. (see figure 4.) 1. all master and slave devices should have identical placement and values of input, output and soft - start capacitors. 2. all m aster and slave devices should have their enable pins tied together and should be operated simultaneously with a fast rising edge of 10 usec or less, to ensure that devices start up at the same time. startup imbalance could lead to ocp condition on first device to startup. 3. the maximum board trace resistance between any 2 devices vout pins should be less than 10m ? . 4. the maximum difference of pvin between any 2 devices should be less than 50mv. 11 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi figure 4 . paralleling of two devices. figure 5. output current derating curve, v in = 5.0v 12 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi figure 6 . output current derating curve, v in = 3.3v 13 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi layout recommendations figure 7 . layout of power and ground planes. figure 8 . use of vias connecting local and system ground. recommendation 1: input and output capacitors should be placed as close to the en5395qi package as possible to reduce emi from input and output loop currents. this reduces the physical area of the input and output ac current loops. recommendation 2 : place a slit in the i nput/output capacitor ground plane just beyond the common connection point of the gnd pins of the device as shown in figure 7 . recommendation 3 : multiple small (0.25mm) vias should be used to connect ground terminal of the input capacitor and the output capacitor to the system ground plane as shown in figure 8 . recommendation 4 : the large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. the diameter of the vias should be less than 0.3mm. this provides the quiet, or analog ground for the converter and also provides the path for heat dissipation from the converter. a later section of this note makes a recommendation on the pcb footprint. recommendation 5: the system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and the input and output capacitors that carry large ac currents. recommendation 6 : as with any switch - mode dc/dc converter, do not run sensitive signal or control lines underneath the converter package. 14 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi design considerations for lead -frame based modules exposed metal on bottom o f package lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, , and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead - frame cantilevers be exposed at the point where wire- bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package. only the large thermal pad and the perimeter pads a re to be mechanically or electrically connected to the pc board. the pcb top layer under the en5395qi should be clear of any metal except for the large thermal pad. the ?grayed - out? area in figure 9 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the pcb . figure 10 demonstrates the recommended pcb footprint for the en5395qi. figure 11 shows the shape and location of the exposed metal pads as well as the mechanical dimension of the large thermal pad and the pins. figure 9 . lead - frame exposed metal. grey area highlights exposed metal that is not to be mechanically or electrically connected to the pcb. 15 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi figure 10. en5395qi pcb footprin t ( top view) the solder stencil aperture for the thermal pa d is shown in blue and is based on enpirion power product manufacturing specifications. 16 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi package dimensions figure 11 . package dimensions. 17 www.altera.com/enpirion 02392 december 3, 2013 rev f
en5395qi contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com/ ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com /common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with al tera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 18 www.altera.com/enpirion 02392 december 3, 2013 rev f

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