may 2014 docid026305 rev 1 1/5 TN1181 technical note engineering model quality level introduction stmicroelectronics manufactures aerospace products at its eu ropean dedicated facility in rennes (france), certified by the esa- escc, dla qml-v and dla jans systems. in addition to the qualified prod ucts, often referred to as ?flight parts?, st proposes for most products (die - package combinations) an en gineering model (em) qua lity level, primarily intended to support development. the present document briefly describes the manufacturing and screening flow of this engineering model quality level. www.st.com
eligible products TN1181 2/5 docid026305 rev 1 1 eligible products any st aerospace qualified product can be proposed for the engineering model quality level, whether they are qua lified in the escc, in the ja ns or in the qml system. the em quality level is proposed by default fo r most die - package configurations, with some exceptions, mostly with legacy products and/or rare packages or pinout. each product datasheet provides the details of the available em (a) . non aerospace products may also be proposed for em quality level, with some specific adjustments not discussed in this document. a. contact an st sales office for die - pack age configurations not listed in the datasheets
docid026305 rev 1 3/5 TN1181 production flow 5 2 production flow the em overall simplified production flow is given in figure 1 below: figure 1. simplified production flow with respect to qualified flight models (fms), ems: ? use the same design and the same mask set. ? are diffused in the same diffusion line, using the same process. ? go through the same electrical wafer sort (ews). ? are submitted to the same wafer lot qualification test s, but without radiation tests. ? are assembled on the same space assembly line, using the simplified process flowchart and control plan summarized below. ? use the same packages and piece parts (wires, lid, etc.) ? use the same dice (design, mask set, diffusion line, etc.) ? are not optically sorted. ? are guaranteed against the same escc/smd elec trical test tables, in particular, over the full temperature range test (guaranteed by characterization + 100% final test at 25 c + go/no-go wafer lot qualification sampling at 3 temperatures). ? do not go through any package test (pind test, thermal cycles, etc.) ? are provided with a specific marking, with out agency logo, described in each product datasheet. ? are delivered only with gold-plated terminals. ? are provided with neither certificate of conformance nor traceability. the simplified em assembly and screening flow is summarized below: ? die-attach ? wire bonding ? sealing ? stabilization bake ? fine/gross leak test ? marking ? electrical test go/no-go at 25 c ?packing % j g g v t j p o & |