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freescale semiconductor data sheet: technical data document number: imx6sdlcec rev. 3, 03/2014 mcimx6sxexxxxxb mcimx6sxexxxxxc mcimx6uxexxxxxb mcimx6uxexxxxxc mcimx6sxdxxxxxb mcimx6sxdxxxxxc mcimx6uxdxxxxxb mcimx6uxdxxxxxc package information plastic package bga case 2240 21 x 21 mm, 0.8 mm pitch ordering information see table 1 on page 3 ? 2012-2014 freescale semiconductor, inc. all rights reserved. 1 introduction the i.mx 6solo/6duallite processors represent freescale semiconductor?s latest achievement in integrated multimedia-foc used products offering high performance processing with lower cost, as well as optimization for low power consumption. the processors feature freescale?s advanced implementation of single/dual arm ? cortex ? -a9 core, which operates at speeds of up to 1 ghz. they include 2d and 3d graphics proces sors, 1080p video processing, and integrated power mana gement. each processor provides a 32/64-bit ddr3/lvddr3/lpddr2-800 memory interface and a number of other interfaces for connecting peripherals, such as wlan, bluetooth ? , gps, hard drive, displays, and camera sensors. the i.mx 6solo/6duallite pr ocessors are specifically useful for applications such as: ? web and multimedia tablets i.mx 6solo/6duallite applications processors for consumer products 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 updated signal naming convention . . . . . . . . . . . .8 2 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3 modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1 special signal considerations . . . . . . . . . . . . . . . .20 3.2 recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .22 4.1 chip-level conditions . . . . . . . . . . . . . . . . . . . . . .22 4.2 power supplies requirements and restrictions. . .32 4.3 integrated ldo voltage regulator parameters . . .34 4.4 pll?s electrical characteristics. . . . . . . . . . . . . . . .36 4.5 on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . .37 4.6 i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . .38 4.7 i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . .43 4.8 output buffer impedance parameters . . . . . . . . . .47 4.9 system modules timing . . . . . . . . . . . . . . . . . . . . .50 4.10 general-purpose media inte rface (gpmi) timing .67 4.11 external peripheral interface parameters. . . . . . . .75 5 boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . .137 5.1 boot mode configuration pins . . . . . . . . . . . . . . .137 5.2 boot device interface allocation. . . . . . . . . . . . . .139 6 package information and contact assignments . . . . . .140 6.1 updated signal naming convention . . . . . . . . . .140 6.2 21x21 mm package information . . . . . . . . . . . . . .140 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 2 freescale semiconductor introduction ? web and multimedia tablets ? color ereaders ?iptv ? human machine interfaces (hmi) ? portable medical ? ip phones ? home energy management systems the i.mx 6solo/6duallite processors have some very exciting features, for example: ? applications processors?the processors enha nce the capabilities of high-tier portable applications by fulfilling the ever increasing mips needs of operating systems and games. freescale?s dynamic voltage and frequency scaling (dvfs) provides significant power reduction, allowing the device to run at lower volta ge and frequency with su fficient mips for tasks, such as audio decode. ? multilevel memory system?the multilevel memory system of each proce ssor is based on the l1 instruction and data caches, l2 cache, and intern al and external memory. the processors support many types of external memory devices, in cluding ddr3, low voltage ddr3, lpddr2, nor flash, psram, cellular ram, nand flash (mlc and sl c), onenand?, and managed nand, including emmc up to rev 4.4/4.41. ? smart speed technology?the processors have power management throughout the ic that enables the rich suite of multimedia features and periphe rals to consume minimum power in both active and various low power modes. smart speed technology enables the designer to deliver a feature-rich product, requiring levels of pow er far lower than industry expectations. ? dynamic voltage and frequency sca ling?the processors im prove the power effi ciency of devices by scaling the voltage and fre quency to optimize performance. ? multimedia powerhouse?the multim edia performance of each processor is enhanced by a multilevel cache system, neon? mpe (media proc essor engine) co-processor, a multi-standard hardware video codec, an image processing unit (ipu), a programmable smart dma (sdma) controller, and an asynchronous sample rate converter. ? powerful graphics acceleration? each processor provid es two independent, integrated graphics processing units: an opengl ? es 2.0 3d graphics accelerator w ith a shader and a 2d graphics accelerator. ? interface flexibility?each processor supports connections to a variet y of interfaces: lcd controller for up to two displays (including parallel display, hdmi1.4, mipi display, and lvds display), dual cmos sensor in terface (parallel or through mipi ), high-speed usb on-the-go with phy, high-speed usb host with ph y, multiple expansion card por ts (high-speed mmc/sdio host and other), 10/100/1000 mbps giga bit ethernet controller two ca n ports, esai audio interface, and a variety of other popular interfaces (such as uart, i 2 c, and i 2 s serial audio, and pcie-ii). ? eink panel display cont roller?the processors integrate epd controller that supports e-ink color and monochrome with up to 1650x2332 resolution and 5-bit gray scale (32-levels per color channel).
introduction i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 3 ? advanced security?the processors deliver hardware -enabled security featur es that enable secure e-commerce, digital rights manage ment (drm), information encryption, secure boot, and secure software downloads. the security featur es are discussed in detail in the i.mx 6solo/6duallite security reference manual (imx6dq6sdlsrm). ? integrated power management?the processors integrate linear regul ators and internally generate voltage levels for different domains. this si gnificantly simplifies system power management structure. 1.1 ordering information table 1 provides examples of or derable part numbers cove red by this data sheet. table 1 does not include all possible orderable pa rt numbers. the latest part numbe rs are available on the web page freescale.com/imx6series. if the desi red part number is not listed in table 1 , or there may be any questions about available parts, see the web page freescale.com/imx6ser ies or contact a free scale representative. table 1. example orderable part numbers part number i.mx6 cpu solo/ duallite options speed grade temperature grade package mcimx6u8dvm10ab duallite wi th vpu, gpu, epdc, mlb 2x arm cortex-a9 64-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6u8dvm10ac duallite wi th vpu, gpu, epdc, mlb 2x arm cortex-a9 64-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga MCIMX6U5DVM10AB duallite with vpu, gpu, mlb, no epdc 2x arm cortex-a9 64-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6u5dvm10ac duallite with vpu, gpu, mlb, no epdc 2x arm cortex-a9 64-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6u5evm10ab duallite with vpu, gpu, mlb, no epdc 2x arm cortex-a9 64-bit ddr 1 ghz extended commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6u5evm10ac duallite with vpu, gpu, mlb, no epdc 2x arm cortex-a9 64-bit ddr 1 ghz extended commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6s8dvm10ab solo with vpu, gpu, mlb, epdc 1x arm cortex-a9 32-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6s8dvm10ac solo with vpu, gpu, mlb, epdc 1x arm cortex-a9 32-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6s5dvm10ab solo with vpu, gpu, mlb, no epdc 1x arm cortex-a9 32-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6s5dvm10ac solo with vpu, gpu, mlb, no epdc 1x arm cortex-a9 32-bit ddr 1 ghz commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6s5evm10ab solo with vpu, gpu, mlb, no epdc 1x arm cortex-a9 32-bit ddr 1 ghz extended commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga mcimx6s5evm10ac solo with vpu, gpu, mlb, no epdc 1x arm cortex-a9 32-bit ddr 1 ghz extended commercial 21 mm x 21 mm, 0.8 mm pitch, mapbga
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 4 freescale semiconductor introduction figure 1 describes the part number nomencl ature so that the users can identify the characteristics of the specific part number they have (for example, cores, frequency, temp erature grade, fuse options, and silicon revision). the primary characteristic which describes which data sheet a pplies to a specific part is the temperature grade (junction) field. ? the i.mx 6solo/6duallite automotive and info tainment applications processors data sheet (imx6sdlaec) covers parts listed with an ?a (automotive temp)? ? the i.mx 6solo/6duallite a pplications processors for c onsumer products data sheet (imx6sdlcec) covers parts liste d with a ?d (commercial temp)? or ?e (extended commercial temp)? ? the i.mx 6solo/6duallite a pplications processors for i ndustrial products data sheet (imx6sdliec) covers parts lis ted with ?c (industrial temp)? ensure to have the proper data sheet for specific pa rt by verifying the temperat ure grade (junction) field and matching it to the proper data sheet. if ther e will be any questions, visit see the web page freescale.com/imx6series or contact a freescale representative for details. figure 1. part number nomenclature?i.mx 6solo and 6duallite 1.2 features the i.mx 6solo/6duallite processors are based on arm cortex-a9 mpcore? platform, which has the following features: ? the i.mx 6solo supports single arm cortex-a9 mpcore (with trustzone) ? the i.mx 6duallite supports dual ar m cortex-a9 mpcore (with trustzone) temperature tj + commercial: 0 to + 95 ? cd extended commercial: -20 to + 105 ? ce industrial: -40 to +105 ? cc autom otive: -40 to + 125 ? ca frequency $$ 800 mhz 2 08 1 ghz 3 10 package type rohs mapbga 21 x 21 0.8mm vm qualification level mc prototype samples pc mass production mc special sc part # series x i.mx 6duallite 2x arm cortex-a9, 64-bit ddr u i.mx 6solo 1x arm cortex-a9, 32-bit ddr s silicon revision 1 a rev 1.1 b rev 1.2 c fusing % default settin gs a hdcp enabled c mc ? imx6 x @ + vv $$ % a 1. ? see ? the ? freescale.com\imx6series ? web ? page ? for ? latest ? information ? on ? the ? available ? silicon ? revision. 2. ? if ? a ? 24 ? mhz ? input ? clock ? is ? used ? (required ? for ? usb), ? the ? maximum ? soc speed ? is ? limited ? to ? 792 ? mhz. 3. ? if ? a ? 24 ? mhz ? input ? clock ? is ? used ? (required ? for ? usb), ? the ? maximum ? soc speed ? is ? limited ? to ? 996 ? mhz. part differentiator @ consumer vpu gpu epdc mlb 8 industrial vpu gpu ? ? 7 automotive vpu gpu ? mlb 6 consumer vpu gpu ? mlb 5 automotive ? gpu ? mlb 4 automotive ? ? ? mlb 1
introduction i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 5 ? the core configuration is symmetric, where each core includes: ? 32 kbyte l1 instruction cache ? 32 kbyte l1 data cache ? private timer and watchdog ? cortex-a9 neon mpe (media processing engine) co-processor the arm cortex-a9 mpcore? complex includes: ? general interrupt controller (gic) with 128 interrupt support ? global timer ? snoop control unit (scu) ? 512 kb unified i/d l2 cache: ? used by one core in i.mx 6solo ? shared by two cores in i.mx 6duallite ? two master axi bus inte rfaces output of l2 cache ? frequency of the core (includi ng neon and l1 cache), as per table 9 . ? neon mpe coprocessor ? simd media processing architecture ? neon register file with 32x64- bit general-purpose registers ? neon integer execute pipe line (alu, shift, mac) ? neon dual, single-precision floating poi nt execute pipeli ne (fadd, fmul) ? neon load/store and permute pipeline the soc-level memory system consists of the following a dditional components: ? boot rom, including hab (96 kb) ? internal multimedia / shared, fast access ram (ocram, 128 kb) ? secure/non-secure ram (16 kb) ? external memory interfaces: the i.mx 6solo/6duallite processo rs support latest, high volume, cost effective handheld dram, nor, and nand flash memory standards. ? 16/32-bit lp-ddr2-800, 16/32-bit ddr3-800 and lv-ddr3-800 in i.mx 6solo; 16/32/64-bit lp-ddr2-800, 16/32/64-bit ddr3-800 and lv -ddr3-800, supporting ddr interleaving mode for 2x32 lpddr2-800 in i.mx 6duallite ? 8-bit nand-flash, including support for raw ml c/slc, 2 kb, 4 kb, and 8 kb page size, ba-nand, pba-nand, lba-nand, onenan d? and others. bch ecc up to 40 bit. ? 16/32-bit nor flash. all weimv2 pins are muxed on other interfaces. ? 16/32-bit psram, cellular ram each i.mx 6solo/6duallite processo r enables the following interfaces to external devices (some of them are muxed and not ava ilable simultaneously): ? displays?total five interfaces available. tota l raw pixel rate of all interfaces is up to 450 mpixels/sec, 24 bpp. up to tw o interfaces may be active in parallel (excluding epdc).
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 6 freescale semiconductor introduction ? one parallel 24-bit display port, up to 225 mpix els/sec (for example, wuxga at 60 hz or dual hd1080 and wxga at 60 hz) ? lvds serial ports?one port up to 165 mpixels/s ec or two ports up to 85 mp/sec (for example, wuxga at 60 hz) each ? hdmi 1.4 port ? mipi/dsi, two lanes at 1 gbps ? epdc, color, and monochrome e-ink, up to 1650x2332 resolution and 5-bit grayscale ? camera sensors: ? two parallel camera ports (up to 20 bit and up to 240 mhz peak) ? mipi csi-2 serial port, supporting from 80 mbps to 1 gbps speed per data lane. the csi-2 receiver core can manage one cl ock lane and up to two data lane s. each i.mx 6solo/6duallite processor has two lanes. ? expansion cards: ? four mmc/sd/sdio card ports all supporting: ? 1-bit or 4-bit transfer mode specifications for sd and sd io cards up to uhs-i sdr-104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specific ations for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ?usb : ? one high speed (hs) usb 2.0 otg (up to 480 mbps), with integrated hs usb phy ? three usb 2.0 (480 mbps) hosts: ? one hs host with integrated high speed phy ? two hs hosts with integrated hs-ic usb (high speed inter-chip usb) phy ? expansion pci express por t (pcie) v2.0 one lane ? pci express (gen 2.0) dual m ode complex, supporting root co mplex operations and endpoint operations. uses x1 phy configuration. ? miscellaneous ips and interfaces: ? ssi block is capable of supporting audio samp le frequencies up to 192 khz stereo inputs and outputs with i 2 s mode ? esai is capable of supporting audio sa mple frequencies up to 260 khz in i 2 s mode with 7.1 multi channel outputs ? five uarts, up to 4.0 mbps each: ? providing rs232 interface ? supporting 9-bit rs485 multidrop mode ? one of the five uarts (uart1) supports 8-wire while others four s upports 4-wire. this is due to the soc iomux limitation, since all uart ips are identical. ? four ecspi (enhanced cspi) ? four i 2 c, supporting 400 kbps ? gigabit ethernet controller (ieee1588 compliant), 10/100/1000 1 mbps
introduction i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 7 ? four pulse width modulators (pwm) ? system jtag controller (sjc) ? gpio with interrupt capabilities ? 8x8 key pad port (kpp) ? sony philips digital interconnect format (spdif), rx and tx ? two controller area netw ork (flexcan), 1 mbps each ? two watchdog timers (wdog) ? audio mux (audmux) ? mlb (medialb) provides interface to most networks (most25, most50, most150) with the option of dtcp cipher accelerator the i.mx 6solo/6duallite proces sors integrate advanced power management unit and controllers: ? provide pmu, including ldo su pplies, for on-chip resources ? use temperature sensor for monitoring the die temperature ? support dvfs techniques for low power modes ? use sw state retention and power gating for arm and mpe ? support various levels of system power modes ? use flexible clock gating control scheme the i.mx 6solo/6duallite processo rs use dedicated hardware accel erators to meet the targeted multimedia performance. the use of hardware accelerators is a key f actor in obtaining high performance at low power consumption num bers, while having the cpu core relative ly free for performing other tasks. the i.mx 6solo/6duallite processors incor porate the following hardware accelerators: ? vpu?video processing unit ? ipuv3h?image processing unit version 3h ? gpu3dv5?3d graphics processing un it (opengl es 2.0) version 5 ? gpu2dv2?2d graphics pr ocessing unit (bitblt) ? pxp?pixel processing pipeline. off loading ke y pixel processing operations are required to support the epd disp lay applications. ? asrc?asynchronous sample rate converter security functions are enabled and accelerated by the following hardware: ? arm trustzone including the tz architecture (s eparation of interrupts, memory mapping, etc.) ? sjc?system jtag controller. protecting jt ag from debug port attacks by regulating or blocking the access to th e system debug features. ? caam?cryptographic acceleratio n and assurance module, cont aining cryptographic and hash engines, 16 kb secure ram, an d true and pseudo random number generator (nist certified). ? snvs?secure non-volatile storage, including secure real time clock 1. the theoretical maximum performance of 1 gbps enet is limi ted to 470 mbps (total for tx and rx) due to internal bus throughput limitations. the actual measured performance in optimized environment is up to 400 mbps. for details, see the err004512 erratum in the i.mx 6solo/6d uallite errata document (imx6sdlce).
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 8 freescale semiconductor architectural overview ? csu?central security unit. enhancement for the ic identification module (iim). will be configured during boot and by efus es and will determine the secu rity level operation mode as well as the tz policy. ? a-hab?advanced high assurance boot?hab v4 with the new embedded enhancements: sha-256, 2048-bit rsa key, versi on control mechanism, warm boot , csu, and tz initialization. note the actual feature set depends on th e part numbers as described in table 1, "example orderable part numbers," on page 3 . functions, such as video hardware acceleration, a nd 2d and 3d hardware graphics acceleration may not be enabled for specific part numbers. 1.3 updated signal naming convention the signal names of the i.mx6 series of products have been standardized to bett er align the signal names within the family and across the documentation. some of the benefits of thes e changes are as follows: ? the names are unique within the scope of an soc and within the series of products ? searches will return all occurrences of the named signal ? the names are consistent be tween i.mx 6 series products implementing the same modules ? the module instance is incorporated into the signal name this change applies only to signal na mes. the original ball names have been preserved to prevent the need to change schematics, bsdl models, ibis models, etc. throughout this document, the updated signal names are used except where referenced as a ball name (such as the functional contact assignm ents table, ball map table, and so on). a master list of the signal name changes is in the document, imx 6 series signal name mapping (eb792). this list can be used to map the signal names used in older documentati on to the new standardized naming conventions. 2 architectural overview the following subsections provide an architectural overview of the i.mx 6solo/6duallite processor system. 2.1 block diagram figure 2 shows the functional modules in the i. mx 6solo/6duallite processor system.
architectural overview i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 9 1 144 kb ram including 16 kb ram inside the caam. 2 for i.mx 6solo, there is only one a9-core platform in t he chip; for i.mx 6duallite, there are two a9-core platforms. figure 2. i.mx 6solo/6duallite system block diagram note the numbers in brackets indicate numbe r of module instances. for example, pwm (4) indicates four se parate pwm peripherals. application processor smart dma (sdma) shared peripherals ap peripherals arm cortex a9 ssi (3) ecspi (4) mpcore platform timers/control gpt pwm (4) epit (2) gpio wdog (2) i 2 c(4) iomuxc ocotp_ctrl audmux kpp boot rom csu fuse box debug dap tpiu caam (16kb ram) security usb otg + 3 hs ports ctis internal host phy2 otg phy1 esai external memory i/f ram (144 kb) 1 ldb 1 / 2 lcd displays domain (ap) sjc 512k l2 cache scu, timer wlan usb otg jtag (ieee1149.6) bluetooth mmc/sd emmc/esd e-ink display gps audio, power mngmnt. spba can(2) digital audio 2xcan i/f 5xfast-uart spdif rx/tx video proc. unit (vpu + cache) 3d graphics proc. unit (gpu3d) axi and ahb switch fabric 1 / 2 lvds (wuxga+) battery ctrl device nor flash psram lpddr2/ddr3 1-gbps enet 2x camera parallel/mipi (96 kb) pll (8) ccm gpc src xtalosc osc32k ptm?s cti?s hdmi 1.4 display gpmi hsi/mipi mipi display dsi/mipi csi2/mipi hdmi 2xhsic phy pcie bus asrc snvs (srtc) usdhc (4) modem ic 2d graphics proc. unit (gpu2d) mmc/sd sdxc raw / onfi 2.2 nand flash mmdc weim keypad 1x/2x a9-core l1 i/d cache timer, wdog crystals & clock sources image processing subsystem ipuv3h temp monitor mbps 10/100/1000 ethernet epdc clock and reset (dev/host) 400 mhz (ddr800) pxp power management unit (ldos) mlb 150 dtcp mlb/most network
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 10 freescale semiconductor modules list 3 modules list the i.mx 6solo/6duallite processors contai n a variety of digita l and analog modules. table 3 describes these modules in alphabetical order. table 3. i.mx 6solo/6duallite modules list block mnemonic block name su bsystem brief description arm arm platform arm the arm core platform includes 1x (solo) cortex-a9 core for i.mx 6solo and 2x (dual) cortex-a9 cores for i.mx 6duallite. it also incl udes associated sub-blocks, such as the level 2 cache controller, scu (snoop control unit), gic (general in terrupt controller), private timers, watchdog, and coresight debug modules. apbh-dma nand flash and bch ecc dma controller system control peripherals dma controller used for gpmi2 operation asrc asynchronous sample rate converter multimedia peripherals the asynchronous sample rate converter (asrc) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. the asrc supports concurrent sample rate conversion of up to 10 channels of about -120db thd+n. the sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. the asrc supports up to three sampling rate pairs. audmux digital audio mux multimedia peripherals the audmux is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for exam ple, ssi1, ssi2, and ssi3) and peripheral serial interfaces (audio and voice codecs). the audmux has seven ports with identical functionality and programming models. a desired connectivity is achieved by configuring two or more audmux ports. bch40 binary-bch ecc processor system control peripherals the bch40 module provides up to 40-bit ecc encryption/decryption for nand flash controller (gpmi) caam cryptographic accelerator and assurance module security caam is a cryptograp hic accelerator and assurance module. caam implements several encryption and hashing functions, a run-time integrity checker, and a pseudo random number generator (prng). the pseudo random number generator is certified by cryptographic algorithm validation program (cavp) of national institute of standar ds and technology (nist). its drbg validation number is 94 and its shs validation number is 1455. caam also implements a se cure memory mechanism. in i.mx 6solo/6duallite processors, the security memory provided is 16 kb. ccm gpc src clock control module, general power controller, system reset controller clocks, resets, and power control these modules are responsible for clock and reset distribution in the system, and also for the system power management. csi mipi csi-2 i/f multimedia peripherals the csi ip provides mipi csi-2 standard camera interface port. the csi-2 interface supports from 80 mbps to 1 gbps speed per data lane.
modules list i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 11 csu central security unit security the central security unit (csu) is responsible for setting comprehensive securi ty policy within the i.mx 6solo/6duallite platform. cti-0 cti-1 cti-2 cti-3 cti-4 cross trigger interfaces debug / trace cross trigger interfaces allows cross-triggering based on inputs from masters at tached to ctis. the cti module is internal to the cortex-a9 core platform. ctm cross trigger matrix debug / trace cross trigger matrix ip is used to route triggering events between ctis. the ctm module is internal to the cortex-a9 core platform. dap debug access port system control peripherals the dap provides real-time access for the debugger without halting the core to: ? system memory and peripheral registers ? all debug configuration registers the dap also provides debugger access to jtag scan chains. the dap module is internal to the cortex-a9 core platform. dcic-0 dcic-1 display content integrity checker automotive ip the dcic provides integrity check on portion(s) of the display. each i.mx 6solo/6duallite processor has two such modules. dsi mipi dsi i/f multimedia peripherals the mipi dsi ip provides dsi standard display port interface. the dsi interface support 80 mbps to 1 gbps speed per data lane. dtcp dtcp multimedia peripherals provides encryption function according to digital transmission content protection standard for traffic over mlb150. ecspi1-4 configurable spi connectivity peripherals full-duplex enhanced synchronous serial interface, with data rate up to 52 mbit /s. it is configurable to support master/slave modes, four chip selects to support multiple peripherals. enet ethernet controller connectivity peripherals the ethernet media access controller (mac) is designed to support 10/100/1000 mbps ethernet/ieee 802.3 networks. an external transceiver interface and transceiver function are required to complete the interface to the media. the module has dedicated hardware to support the ieee 1588 standard. see the enet chapter of the reference manual for details. note: the theoretical maximum performance of 1 gbps enet is limited to 470 mbps (total for tx and rx) due to internal bus throughput limitations. the actual measured performance in optimized environment is up to 400 mbps. for details, see the err004512 erratum in the i.mx 6solo/6duallite errata document (imx6sdlce). table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 12 freescale semiconductor modules list epdc electrophoretic display controller peripherals the epdc is a feature-rich, low power, and high-performance direct-drive, active matrix epd controller. it is specifically designed to drive e-ink ? epd panels, supporting a wide variety of tft backplanes. it is available in both i.mx 6duallite and i.mx 6solo. epit-1 epit-2 enhanced periodic interrupt timer timer peripherals each epit is a 32-bit ?set and forget? timer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. esai enhanced serial audio interface connectivity peripherals the enhanced serial audio in terface (esai) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, spdif transceivers, and other processors. the esai consists of independent transmitter and receiver sections, each section with its own clock generator. all serial transfers are synchronized to a clock. additional synchronization signals are used to delineate the word frames. the normal mode of operation is used to transfer data at a periodic rate, one word per period. the network mode is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. th is mode can be used to build time division multiplexed (tdm) networks. in contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. the esai has 12 pins for dat a and clocking connection to external devices. table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
modules list i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 13 usdhc-1 usdhc-2 usdhc-3 usdhc-4 sd/mmc and sdxc enhanced multi-media card / secure digital host controller connectivity peripherals i.mx 6solo/6duallite specific soc characteristics: all four mmc/sd/sdio controller ips are identical and are based on the usdhc ip. they are: ? fully compliant with mmc command/response sets and physical layer as defined in the multimedia card system specification, v4.2/4.3/4.4/4.41 including high-capacity (size > 2 gb) cards hc mmc. ? fully compliant with sd command/response sets and physical layer as defined in the sd memory card specifications, v3.0 including high-capacity sdhc cards up to 32 gb and sdxc cards up to 2 tb. ? fully compliant with sdio command/response sets and interrupt/read-wait mode as defined in the sdio card specification, part e1, v3.0 all four ports support: ? 1-bit or 4-bit transfer mode specifications for sd and sdio cards up to uhs-i sdr104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specifications for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) however, the soc level integration and i/o muxing logic restrict the functionality to the following: ? instances #1 and #2 are primarily intended to serve as external slots or interfaces to on-board sdio devices. these ports are equipped with ?card detection? and ?write protection? pads and do not support hardware reset. ? instances #3 and #4 are primarily intended to serve interfaces to embedded mmc memory or interfaces to on-board sdio devices. these ports do not have ?card detection? and ?write protection? pads and do support hardware reset. ? all ports can work with 1.8 v and 3.3 v cards. there are two completely independent i/o power domains for ports #1 and #2 in four bit configuration (sd interface). port #3 is placed in his own independent power domain and port #4 shares power domain with some other interfaces. flexcan-1 flexcan-2 flexible controller area network connectivity peripherals the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (emi) environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specification, version 2.0 b, which supports both standard and extended message frames. table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 14 freescale semiconductor modules list 512x8 fuse box electrical fuse array security electri cal fuse array. enables to setup boot modes, security levels, security keys, and many other system parameters. the i.mx 6solo/6duallite processors consist of 512x8-bit fuse fox accessible through ocotp_ctrl interface gpio-1 gpio-2 gpio-3 gpio-4 gpio-5 gpio-6 gpio-7 general purpose i/o modules system control peripherals used for general purpose input/output to external ics. each gpio module supports 32 bits of i/o. gpmi general purpose media interface connectivity peripherals the gpmi module supports up to 8x nand devices. 40-bit ecc encryption/decryption for nand flash controller (gpmi2). the gpmi supports separate dma channels per nand device. gpt general purpose timer timer peripherals each gpt is a 32-bit ?free-running? or ?set and forget? mode timer with programmable prescaler and compare and capture register. a timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in ?set and forget? mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. gpu3dv5 graphics processing unit, ver.5 multimedia peripherals the gpu3dv5 provides hardware acceleration for 3d graphics algorithms with sufficient processor power to run desktop quality interactive graphics applications on displays up to hd1080 resolution. the gpu3d provides opengl es 2.0, including extensions, opengl es 1.1, and openvg 1.1 gpu2dv2 graphics processing unit-2d, ver 2 multimedia peripherals the gpu2dv2 provides hardware acceleration for 2d graphics algorithms, such as bit blt, stretch blt, and many other 2d functions. hdmi tx hdmi tx i/f multimedia peripherals the hdmi module provides hdmi standard i/f port to an hdmi 1.4 compliant display. hsi mipi hsi i/f connectivity peripherals the mipi hsi provides a stan dard mipi interface to the applications processor. i 2 c-1 i 2 c-2 i 2 c-3 i 2 c-4 i 2 c interface connectivity peripherals i 2 c provide serial interface for external devices. data rates of up to 400 kbps are supported. iomuxc iomux contro l system control peripherals this module enables flexible io multiplexing. each io pad has default and several alternate functions. the alternate functions are software configurable. table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
modules list i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 15 ipuv3h image processing unit, ver.3h multimedia peripherals ipuv3h enables connectivity to displays and video sources, relevant processing and synchronization and control capabilities, allowing autonomous operation. the ipuv3h supports concurre nt output to two display ports and concurrent input from two camera ports, through the following interfaces: ? parallel interfaces for both display and camera ? single/dual channel lvds display interface ? hdmi transmitter ? mipi/dsi transmitter ? mipi/csi-2 receiver the processing includes: ? image conversions: resizing, rotation, inversion, and color space conversion ? a high-quality de-interlacing filter ? video/graphics combining ? image enhancement: color adjustment and gamut mapping, gamma correction, and contrast enhancement ? support for display backlight reduction kpp key pad port connectivity peripherals kpp supports 8x8 external key pad matrix. kpp features are: ? open drain design ? glitch suppression circuit design ? multiple keys detection ? standby key press detection ldb lvds display bridge connectivity peripherals lvds display bridge is used to connect the ipu (image processing unit) to external lvds display interface. ldb supports two channels; each channel has following signals: ? one clock pair ? four data pairs each signal pair contains lvds special differential pad (padp, padm). mlb150 medialb connectivity / multimedia peripherals the mlb interface module provides a link to a most ? data network, using the st andardized medialb protocol (up to 6144 fs). the module is backward compatible to mlb-50. mmdc multi-mode ddr controller connectivity peripherals ddr controller has the following features: ? supports 16/32-bit ddr3-800 (lv) or lpddr2-800 in i.mx 6solo ? supports 16/32/64-bit ddr3-800 (lv) or lpddr2-800 in i.mx 6duallite ? supports 2x32 lpddr2-800 in i.mx 6duallite ? supports up to 4 gbyte ddr memory space table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 16 freescale semiconductor modules list ocotp_ctrl otp controller security the on-chip otp controller (ocotp_ctrl) provides an interface for reading, prog ramming, and/or overriding identification and control info rmation stored in on-chip fuse elements. the module supports electrically-programmable poly fuses (efuses). the ocotp_ctrl also provides a set of volatile software-accessible signals that can be used for software control of hardwar e elements, not requiring non-volatility. the ocotp_ctrl provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, jtag secure mode, boot characteristics, and various control signals, requiring permanent non-volatility. ocram on-chip memory controller data path the on-chip memory controller (ocram) module is designed as an interface between system?s axi bus and internal (on-chip) sram memory module. in i.mx 6solo/6duallite processors, the ocram is used for controlling the 128 kb multimedia ram through a 64-bit axi bus. osc32khz osc32khz clocking generates 32.768 khz clock from external crystal. pcie pci express 2.0 connectivity peripherals the pcie ip provides pci ex press gen 2.0 functionality. pmu power-management functions data path integrated power management unit. used to provide power to various soc domains. pwm-1 pwm-2 pwm-3 pwm-4 pulse width modulation connectivity peripherals the pulse-width modulator (p wm) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. it uses 16-bit resolution and a 4x16 data fifo to generate sound. pxp pixel processing pipeline display peripherals a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma-mapping, and rotation. the pxp is enhanced with features specifically for gray scale applications. in addition, the pxp supports traditional pixel/frame processing paths for still-image and video processing applications, allowing it to interface with the integrated epd. ram 128 kb internal ram internal memory internal ram, which is accessed through ocram memory controller. ram 16 kb secure/non-secure ram secured internal memory secure/non-secure internal ram, interfaced through the caam. rom 96kb boot rom internal memory supports secure and regular boot modes. includes read protection on 4k region for content protection. romcp rom controller with patch data path rom controller with rom patch support table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
modules list i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 17 sdma smart direct memory access system control peripherals the sdma is multi-channel flexible dma engine. it helps in maximizing system performance by off-loading the various cores in dynamic data routing. it has the following features: ? powered by a 16-bit instruction-set micro-risc engine ? multi-channel dma supporting up to 32 time-division multiplexed dma channels ? 48 events with total flexibility to trigger any combination of channels ? memory accesses including linear, fifo, and 2d addressing ? shared peripherals between arm and sdma ? very fast context-switching with 2-level priority based preemptive multi-tasking ? dma units with auto-flush and prefetch capability ? flexible address management for dma transfers (increment, decrement, and no address changes on source and destination address) ? dma ports can handle unit-directional and bi-directional flows (copy mode) ? up to 8-word buffer for configurable burst transfers ? support of byte-swapping and crc calculations ? library of scripts and api is available sjc system jtag cont roller system control peripherals the sjc provides jtag interface, which complies with jtag tap standards, to internal logic. the i.mx 6solo/6duallite processors use jtag port for production, testing, and system debugging. in addition, the sjc provides bsr (boundary scan register) standard support, which complies with ieee1149.1 and ieee1149.6 standards. the jtag port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. the i.mx 6solo/6duallite sjc incorporates three security modes for protecting against unauthorized accesses. modes are selected through efuse configuration. spdif sony philips digital interconnect format multimedia peripherals a standard audio file transfer format, developed jointly by the sony and phillips corporations. has transmitter and receiver functionality. snvs secure non-volatile storage security secure non-volatile storage, including secure real time clock, security state machine, master key control, and violation/tam per detection and reporting. table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 18 freescale semiconductor modules list ssi-1 ssi-2 ssi-3 i2s/ssi/ac97 interface connectivity peripherals the ssi is a full-duplex synchronous interface, which is used on the ap to provide co nnectivity with off-chip audio peripherals. the ssi supports a wide variety of protocols (ssi normal, ssi network, i2s, and ac-97), bit depths (up to 24 bits per word), and clock / frame sync options. the ssi has two pairs of 8x24 fifos and hardware support for an external dma controller in order to minimize its impact on system performance. the second pair of fifos provides hardware interleaving of a second audio stream that reduces cpu overhead in use cases where two time slots are being used simultaneously. tempmon temperature monitor system control peripherals the temperature sensor ip is used for detecting die temperature. the temperature read out does not reflect case or ambient temperature. it reflects the temperature in proximity of the sensor location on the die. temperature distribution may not be uniformly distributed, therefore the read out value may not be the reflection of the temperature value of the entire die. tzasc trust-zone address space controller security the tzasc (tzc-380 by arm) provides security address region control functi ons required for intended application. it is used on the path to the dram controller. uart-1 uart-2 uart-3 uart-4 uart-5 uart interface connectivity peripherals each of the uartv2 modules support the following serial data transmit/receive protocols and configurations: ? 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) ? programmable baud rates up to 5 mhz. ? 32-byte fifo on tx and 32 half-word fifo on rx supporting auto-baud ? irda 1.0 support (up to sir speed of 115200 bps) ? option to operate as 8-pins full uart, dce, or dte usboh3 usb 2.0 high speed otg and 3x hs hosts connectivity peripherals usboh3 contains: ? one high-speed otg module with integrated hs usb phy ? one high-speed host module with integrated hs usb phy ? two identical high-speed host modules connected to hsic usb ports. vdoa vdoa multimedia peripherals video data order adapter (vdoa): used to re-order video data from the ?tiled? order used by the vpu to the conventional raster-scan order needed by the ipu. table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
modules list i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 19 vpu video processing unit multimedia peripherals a high-performing video processing unit (vpu), which covers many sd-level and hd-level video decoders and sd-level encoders as a multi-standard video codec engine as well as several important video processing, such as rotation and mirroring. see the i .mx 6solo/6duallite reference manual (imx6sdlrm) for complete list of vpu?s decoding/encoding capabilities. wdog-1 watch dog timer peripherals the watch dog timer supports two comparison points during each counting period. each of the comparison points is configurable to evoke an interrupt to the arm core, and a second point evokes an external event on the wdog line. wdog-2 (tz) watch dog (trustzone) timer peripherals the trustzone watchdog (tz wdog) timer module protects against trustzone starvation by providing a method of escaping normal mode and forcing a switch to the tz mode. tz starvation is a situation where the normal os prevents switching to the tz mode. such situation is undesirable as it can compromise the system?s security. once the tz wdog module is activated, it must be serviced by tz software on a periodic basis. if servicing does not take place, the timer times out. upon a time-out, the tz wdog asserts a tz mapped interrupt that forces switching to the tz mode. if it is still not served, the tz wdog asserts a security violation signal to the csu. the tz wdog module cannot be programmed or deactivated by a normal mode sw. weim nor-flash /psram interface connectivity peripherals the weim nor-flash / psram provides: ? support 16-bit (in muxed io mode only) psram memories (sync and async operating modes), at slow frequency ? support 16-bit (in muxed io mode only) nor-flash memories, at slow frequency ? multiple ch ip selects xtalosc crystal oscillator i/f clocks, resets, and power control the xtalosc module enables connectivity to external crystal oscillator device. in a typical application use-case, it is used for 24 mhz oscillator to provide usb required frequency. table 3. i.mx 6solo/6duallite modules list (continued) block mnemonic block name su bsystem brief description
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 20 freescale semiconductor modules list 3.1 special signal considerations table 4 lists special signal considerations for the i.mx 6solo/6duallite processo rs. the signal names are listed in alphabetical order. the package contact assign ments can be found in section 6, ?package information and contact assignments.? signal descriptions are provided in the i.mx 6solo/6duallite reference manual (imx6sdlrm) . table 4. special signal considerations signal name remarks clk1_p/clk1_n clk2_p/clk2_n two general purpose differential high speed clock input/outputs are provided. any or both of them could be used: ? to feed external reference clock to the plls and further to the modules inside soc, for example as alternate reference clock for pcie, video/audio interfaces, etc. ? to output internal soc clock to be used outside the soc as either reference clock or as a functional clock for peripherals, for example it could be used as an output of the pcie master clock (root complex use) see the i.mx 6solo/6duallite reference manual for details on the respective clock trees. the clock inputs/outputs are lvds differential pairs compatible wi th tia/eia-644 standard, the maximum frequency range supported is 0...600 mhz. alternatively one may use single ended signal to drive clkx_p input. in this case corresponding clkx_n input should be tied to the constant voltage level equal 1/2 of the input signal swing. termination should be provided in case of high frequency signals. see lvds pad electrical specification for further details. after initialization, the clkx inputs/outputs could be disabled (if not used). if unused any or both of the clkx_n/p pairs may be left floating. xtalosc_rtc_xtali/ rtc_xtalo if the user wishes to configure xtalosc_rtc_xtali and rtc_xtalo as an rtc oscillator, a 32.768 khz crystal, ( ? 100 k ? esr, 10 pf load) should be connected between xtalosc_rtc_xtali and rtc_xtalo. remember that the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. to hit the exact oscillation frequency, the board capacitors need to be reduced to acco unt for board and chip parasitics. the integrated oscillation amplifier is self biasing, but relatively weak. care must be taken to limit parasitic leakage from xtalosc_rtc_xtali and rtc_xtalo to either power or ground (>100 m ? ). this will debias the amplifier and cause a reduction of st artup margin. typically xtalosc_rtc_xtali and rtc_xtalo should bias to approximately 0.5 v. if it is desired to feed an external low frequency clock into xtalosc_rtc_xtali the rtc_xtalo pin should be left floating or driven with a complime ntary signal. the logic level of this forcing clock should not exceed vdd_snvs_cap level and the frequency should be <100 khz under typical conditions. xtali/xtalo a 24.0 mhz crystal should be connected between xtali and xtalo. level and the frequency should be <32 mhz under typical conditions. the crystal must be rated for a maximum drive level of 250 ? w. an esr (equivalent series resistance) of typical 80 ? is recommended. freescale bsp (board support package) software requires 24 mhz on xtali/xtalo. the crystal can be eliminated if an external 24 mh z oscillator is available in the system. in this case, xtali must be directly driven by the external oscillator and xtalo is floated. the xtali signal level must swing from ~0.8 x nvcc_pll_out to ~0.2 v. if this clock is used as a reference for usb and pcie, then there are strict frequency tolerance and jitter requirements. see osc24m ch apter and relevant interface spec ifications chapters for details.
modules list i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 21 dram_vref when using ddr_vref with ddr i/o, the nominal reference voltage must be half of the nvcc_dram supply. the user must tie ddr_vref to a precision external resistor divider. use a 1k ? 0.5% resistor to gnd and a 1 k ? 0.5% resistor to nvcc_dram. shunt each resistor with a closely-mounted 0.1 f capacitor. to reduce supply current, a pair of 1.5 k ? 0.1% resistors can be used. using resistors with recommended tolerances ensures the 2% ddr_vref tolerance (per the ddr3 specification) is maintained when four ddr3 ics plus the i.mx 6sol o/6duallite are drawing current on the resistor divider. it is recommended to use regulated power supply fo r ?big? memory configurations (more that eight devices) zqpad dram calibration resistor 240 ? 1 % used as reference during dram output buffer driver calibration should be connected between this pad and gnd. nvcc_lvds_2p5 the ddr pre-drivers share the nvcc_lvds _2p5 ball with the lvds interface. this ball can be shorted to vdd_high_cap on the circuit board. vdd_fa fa_ana these signals are reserved for freescale manufacturing use only. user must tie both connections to gnd. gpanaio this signal is reserved for freescale manufacturing use only. user must leave this connection floating. jtag_ nnnn the jtag interface is summarized in ta bl e 5 . use of external resistors is unnecessary. however, if external resistors are used, the user must ensu re that the on-chip pull- up/down configuration is followed. for example, do not use an external pull down on an input that has on-chip pull-up. jtag_tdo is configured wit h a keeper circuit such that the floating condition is eliminated if an external pull resistor is not present. an extern al pull resistor on jtag_tdo is detrimental and should be avoided. jtag_mod is referenced as sjc_mod in the i.mx 6solo/6duallite reference manual. both names refer to the same signal. jtag_mod must be externally connected to gnd for normal operation. termination to gnd through an external pull-down resistor (such as 1 k ? ) is allowed. jtag_mod set to hi configures the jtag interf ace to mode compliant with ieee1149.1 standard. jtag_mod set to low configures the jtag in terface for common sw debug adding all the system taps to the chain. nc these signals are no connect (nc) and should be floated by the user. src_por_b this cold reset negative logic input resets all modules and logic in the ic. may be used in addition to internally generated power on reset signal (logical and, both internal and external signals are considered active low). onoff in normal mode may be connected to on/off button (de-bouncing provided at this input). internally this pad is pulled up. short connection to gnd in off mode causes internal power management state machine to ch ange state to on. in on mode short connection to gnd generates interrupt (intended to sw controllable power down). long above ~5s connection to gnd causes ?forced? off. test_mode test_mode is for freescale factory use. this signal is internally connected to an on-chip pull-down device. the user must either float this signal or tie it to gnd. pcie_rext the impedance calibration process requires connection of reference resistor 200 ? 1% precision resistor on pcie_rext pad to ground. table 4. special signal considerations (continued) signal name remarks
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 22 freescale semiconductor electrical characteristics 3.2 recommended connections for unused analog interfaces the recommended connections for unused analog interfaces can be f ound in the section, ?unused analog interfaces,? of the hardware deve lopment guide for i.mx 6quad, 6dua l, 6duallite, 6solo families of applications proces sors (imx6dq6sdlhdg). 4 electrical characteristics this section provides the device a nd module-level electrical characteristics for the i.mx 6solo/6duallite processors. 4.1 chip-level conditions this section provides the device-level el ectrical characteristics for the ic. see table 6 for a quick reference to the individual tables and sections. csi_rext mipi csi phy reference resistor. use 6.04 k ? 1% resistor connected between this pad and gnd dsi_rext mipi dsi phy reference resistor. use 6.04 k ? 1% resistor connected between this pad and gnd table 5. jtag controller interface summary jtag i/o type on-chip termination jtag_tck input 47 k ? ? pull-up jtag_tms input 47 k ? ? pull-up jtag_tdi input 47 k ? ? pull-up jtag_tdo 3-state output keeper jtag_trstb input 47 k ? ? pull-up jtag_mod input 100 k ? ? pull-up table 6. i.mx 6solo/6duallite chip-level conditions for these characteristics, ? topic appears ? absolute maximum ratings on page 23 bga case 2240 package thermal resistance on page 24 operating ranges on page 25 external clock sources on page 27 maximum supply currents on page 28 low power mode supply currents on page 29 table 4. special signal considerations (continued) signal name remarks
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 23 4.1.1 absolute maximum ratings usb phy current consumption on page 31 pcie 2.0 power consumption on page 31 table 7. absolute maximum ratings parameter description symbol min max unit core supply voltages vdd_arm_in vdd_soc_in -0.3 1.5 v internal supply voltages vdd_arm_cap vdd_soc_cap vdd_pu_cap -0.3 1.3 v gpio supply voltage supplies denoted as i/o supply -0.5 3.6 v ddr i/o supply voltage supplies denoted as i/o supply -0.4 1.975 v mlb i/o supply voltage supplies denoted as i/o supply -0.3 2.8 v lvds i/o supply voltage supplies denoted as i/o supply -0.3 2.8 v vdd_snvs_in supply vo ltage vdd_snvs_in -0.3 3.3 v vdd_high_in supply voltage vdd_high_in -0.3 3.6 v usb vbus usb_h1_vbus usb_otg_vbus ?5.25v input voltage on usb_otg_dp, usb_otg_dn, usb_h1_dp, usb_h1_dn pins usb_dp/usb_dn -0.3 3.63 v input/output voltage range v in /v out -0.5 ovdd 1 +0.3 1 ovdd is the i/o supply voltage. v esd damage immunity: v esd v ? human body model (hbm) ? charge device model (cdm) ? ? 2000 500 storage temperature range t storage -40 150 o c table 6. i.mx 6solo/6duallite chip-level conditions (continued) for these characteristics, ? topic appears ?
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 24 freescale semiconductor electrical characteristics 4.1.2 thermal resistance 4.1.2.1 bga case 2240 package thermal resistance table 8 displays the thermal resistance data. table 8. thermal resistance data rating test conditions symbol value unit junction to ambient 1 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the boar d, and board thermal resistance. single-layer board (1s); natural convection 2 four-layer board (2s2p); natural convection 2 2 per jedec jesd51-2 with the single layer board horizontal. ther mal test board meets jedec specification for the specified package. r ? ja r ? ja 38 23 o c/w o c/w junction to ambient 1 single-layer board (1s); airflow 200 ft/min 2,3 four-layer board (2s2p); airflow 200 ft/min 2,3 3 per jedec jesd51-6 with the board horizontal. r ? ja r ? ja 30 20 o c/w o c/w junction to board 1,4 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r ? jb 14 o c/w junction to case 1,5 5 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). r ? jc 6 o c/w junction to package top 1,6 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. natural convection ? jt 2 o c/w
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 25 4.1.3 operating ranges table 9 provides the operating ranges of the i.mx 6solo/ 6duallite processors. for details on the chip's power structure, see the ?power mana gement unit (pmu)? chapter of the i.mx 6solo/6duallite reference manual (imx6sdlrm) . table 9. operating ranges parameter description symbol min typ max 1 unit comment 2 run mode: ldo enabled vdd_arm_in 1.350 3 ? 1.5 v ldo output set point (vdd_arm_cap) = 1.225 v minimum for operation up to 996mhz. 1.275 3 ? 1.5 v ldo output set point (vdd_arm_cap) = 1.150 v minimum for operation up to 792mhz. 1.175 3 ? 1.5 v ldo output set point (vdd_arm_cap) = 1.05 v minimum for operation up to 396mhz. vdd_soc_in 1.275 3,4 ? 1.5 v vpu ? 328 mhz, vdd_soc and vdd_pu ldo outputs (vdd_soc_cap and vdd_pu_cap) = 1.225 v maximum and 1.15 v minimum. run mode: ldo bypassed vdd_arm_in 1.250 ? 1.3 v ldo bypassed for operation up to 996 mhz 1.150 ? 1.3 v ldo bypassed for operation up to 792 mhz 1.05 ? 1.3 v ldo bypassed for operation up to 396 mhz vdd_soc_in 1.15 5 ?1.225 6 v ldo bypassed for operation vpu ? 328 mhz standby/dsm mode vdd_arm_in 0.9 ? 1.3 v refer to table 12, "stop mode current and power consumption," on page 29 . vdd_soc_in 0.9 ? 1.225 6 v? vdd_high internal regulator vdd_high_in 2.8 ? 3.3 v must match th e range of voltages that the rechargeable backup battery supports. backup battery supply range vdd_snvs_in 7 2.9 ? 3.3 v should be supplied from the same supply as vdd_high_in if the syst em does no t require keeping real time and other data on off state. usb supply voltages usb_otg_vbus 4.4 ? 5.25 v ? usb_h1_vbus 4.4 ? 5.25 v ? ddr i/o supply voltage nvcc_dram 1.14 1.2 1.3 v lpddr2 1.425 1.5 1.575 v ddr3 1.283 1.35 1.45 v ddr3_l supply for rgmii i/o power group 8 nvcc_rgmii 1.15 ? 2.625 v 1.15 v ? 1.30 v in hsic 1.2 v mode 1.43 v ? 1.58 v in rmgii 1.5 v mode 1.70 v ? 1.90 v in rmgii 1.8 v mode 2.25 v ? 2.625 v in rmgii 2.5 v mode
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 26 freescale semiconductor electrical characteristics gpio supply voltages 8 nvcc_csi, nvcc_eim, nvcc_enet, nvcc_gpio, nvcc_lcd, nvcc_nandf, nvcc_sd1, nvcc_sd2, nvcc_sd3, nvcc_jtag 1.65 1.8, 2.8, 3.3 3.6 v ? nvcc_lvds_2p5 9 nvcc_mipi 2.25 2.5 2.75 v ? hdmi supply voltages hdmi_vp 0.99 1.1 1.3 v ? hdmi_vph 2.25 2.5 2.75 v ? pcie supply voltages pcie_vp 1.023 1.1 1.225 v ? pcie_vph 2.325 2.5 2.75 v ? pcie_vptx 1.023 1.1 1.225 v ? junction temperature extended commercial t j -20 ? 105 o c see i.mx 6solo/6duallite product lifetime usage estimates application note , an4725, for information on product lifetime for this processor. junction temperature standard commercial t j 0?95 o c see i.mx 6solo/6duallite product lifetime usage estimates application note , an4725, for information on product lifetime for this processor. 1 applying the maximum voltage results in maximum power consumption and heat gen eration. freescale recommends a voltage set point = (vmin + the supply tolerance). this results in an optimized power/speed ratio. 2 see the hardware development guide for i.mx 6quad, 6dual, 6duallite, 6solo families of applications processors (imx6dq6sdlhdg) for bypass capacitors requirem ents for each of the *_cap supply outputs. 3 vdd_arm_in and vdd_soc_in must be 125 mv higher than th e ldo output set point for correct regulator supply voltage. 4 in ldo enabled mode, the internal ldo output se t points must be configured such that the: ?? vdd_arm ldo output set point does not exceed the vdd_ soc ldo output set point by more than 100 mv. ?? vdd_soc ldo output set point is equal to the vdd_pu ldo output set point. the vdd_arm ldo output set point can be lower than the vdd_soc ldo output set point, however, the minimum output set points shown in this table must be maintained. 5 in ldo bypassed mode, the external power supply must ensu re that vdd_arm_in does not exceed vdd_soc_in by more than 100 mv. the vdd_arm_in supply voltage can be lower than the vdd_soc_in supply voltage. the minimum voltages shown in this table must be maintained. 6 when vdd_soc_in does not supply pcie_vp and pcie_vptx, or when the pcie phy is not used, then this maximum can be 1.3 v. 7 while setting vdd_snvs_in voltage with respect to charging curr ents and rtc, refer to hardware development guide for i.mx 6dual, 6quad, 6solo, 6duallite families of applications processors (imx6dq6sdlhdg). 8 all digital i/o supplies (nvcc_xxxx) must be po wered under normal co nditions whether the a ssociated i/o pins are in use or not and associated io pins need to have a pull-up or pull-down resistor applied to limit any floating gate current. 9 this supply also powers the pre-drivers of the ddr io pins, hence, it must be always provided, even when lvds is not used. table 9. operating ranges (continued) parameter description symbol min typ max 1 unit comment 2
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 27 4.1.4 external clock sources each i.mx 6solo/6duallite processor has two ex ternal input system clocks: a low frequency (rtc_xtali) and a high frequency (xtali). the rtc_xtali is used for low-frequency functio ns. it supplies the clock for wake-up circuit, power-down real time clock operati on, and slow system and watch-dog counters. the clock input can be connected to either external oscillator or a crystal usi ng internal oscillator amplif ier. additionally, there is an internal ring oscillator, which can be used instead of the rtc_xt ali if accuracy is not important. note the internal rtc oscillator does not provide an accurate frequency and is affected by process, voltage and temp erature variations . freescale strongly recommends using an external crystal as the rtc_xtali reference. if the internal oscillator is us ed instead, careful consider ation should be given to the timing implications on all of the soc modules dependent on this clock. the system clock input xtali is used to generate the main system cl ock. it supplies th e plls and other peripherals. the system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. table 10 shows the interface frequency requirements. the typical values shown in table 10 are required for use with freesc ale bsps to ensure precise time keeping and usb operation. for xtalosc_rtc_xtal i operation, two clock sources are available. ? on-chip 40 khz ring oscillat or?this clock source has th e following characteristics: ? approximately 25 a more i dd than crystal oscillator ? approximately 50% tolerance ? no external component required ? starts up quicker than 32 khz crystal oscillator ? external crystal os cillator with on-chip support circuit: ? at power up, ring oscillator is utilized. after crystal oscill ator is stable, the clock circuit switches over to the crystal oscillator automatically. ? higher accuracy th an ring oscillator table 10. external input clock frequency parameter description symbol min typ max unit rtc_xtali oscillator 1,2 1 external oscillator or a crystal with internal oscillator amplifier. 2 the required frequency stability of this clock source is application dependent. for recommendations, see the hardware development guide for i.mx 6dual, 6quad, 6solo, 6duall ite families of applications processors (imx6dq6sdlhdg). f ckil ? 32.768 3 /32.0 3 recommended nominal frequency 32.768 khz. ?khz xtali oscillator 2,4 4 external oscillator or a fundamental frequency crystal with internal oscillator amplifier. f xtal ?24?mhz
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 28 freescale semiconductor electrical characteristics ? if no external crystal is present, then the ring oscillator is used the decision of choosing a clock source should be taken based on real-time clock use and precision timeout. 4.1.5 maximum supply currents the power virus numbers shown in table 11 represent a use case designe d specifically to show the maximum current consumption possibl e. all cores are running at the de fined maximum frequency and are limited to l1 cache accesses only to ensure no pi peline stalls. alt hough a valid condition, it would have a very limited practical use case, if at all, and be limited to an extremel y low duty cycle unless the intention was to specifically show the worst case power consumption. the freescale power management ic, mmpf0100xxxx, which is targeted for the i.mx 6 series processor family, supports the power consumption shown in table 11 , however a robust thermal design is required for the increased system power dissipation. see the i.mx 6solo/6duallite power consumption measurement application note (an4576) for more details on typical power consumpti on under various use case definitions. table 11. maximum supply currents power line conditions max current unit vdd_arm_in 996 mhz arm clock based on power virus operation 2200 ma vdd_soc_in 996 mhz arm clock 1260 ma vdd_high_in ? 125 1 ma vdd_snvs_in ? 275 2 ? a usb_otg_vbus/usb_h1_vbus (ldo 3p0) ? 25 3 ma primary interface (io) supplies nvcc_dram ? ? 4 ? nvcc_enet n=10 use maximum io equation 5 ? nvcc_lcd n=29 use maximum io equation 5 ? nvcc_gpio n=24 use maximum io equation 5 ? nvcc_csi n=20 use maximum io equation 5 ? nvcc_eim n=53 use maximum io equation 5 ? nvcc_jtag n=6 use maximum io equation 5 ? nvcc_rgmii n=6 use maximum io equation 5 ? nvcc_sd1 n=6 use maximum io equation 5 ? nvcc_sd2 n=6 use maximum io equation 5 ? nvcc_sd3 n=11 use maximum io equation 5 ?
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 29 4.1.6 low power mode supply currents table 12 shows the current core consumpt ion (not including i/o) of i.mx 6solo/6duallite processors in selected low power modes. nvcc_nandf n=26 use maximum io equation 5 ? nvcc_lvds2p5 ? nvcc_lvds2p5 is connected to vdd_high_cap at the board level. vdd_high_cap is capable of handing the current required by nvcc_lvds2p5. ? misc ddr_vref ? 1 ma 1 the actual maximum current drawn from vdd_high_in will be as shown plus any additional current drawn from the vdd_high_cap outputs, depending upon actual application confi guration (for example, nvcc_lvds_2p5, nvcc_mipi, or hdmi and pcie vph supplies). 2 under normal operating conditions, the maximum current on vdd_snvs_in is shown in ta bl e 1 1 . the maximum vdd_snvs_in current may be higher depending on specific oper ating configurations, such as boot_mode[1:0] not equal to 00, or use of the tamper feature. during initial power on , vdd_snvs_in can draw up to 1 ma if the supply is capable of sourcing that current. if less than 1 ma is available, the vdd_snvs_cap charge time will increase. 3 this is the maximum current pe r active usb physical interface. 4 the dram power consumption is dependent on several factors, su ch as external signal termination. dram power calculators are typically available from the memory vendors. they take in account factors, such as signal termination. see the i.mx 6solo/duallite power consumption measurement applicatio n note (an4576) for examples of dram power consumption during specific use case scenarios. 5 general equation for estimated, maximum po wer consumption of an io power supply: imax = n x c x v x (0.5 x f) where: n?number of io pins supplied by the power line c?equivalent external capacitive load v?io voltage (0.5 xf)?data change rate. up to 0.5 of the clock rate (f) in this equation, imax is in amps, c in farads, v in volts, and f in hertz. table 12. stop mode current and power consumption mode test conditions supply typical 1 units wait ? arm, soc, and pu ldos are set to 1.225 ? high ldo set to 2.5 v ? clocks are gated. ? ddr is in self refresh. ? plls are active in bypass (24mhz) ? supply voltages remain on vdd_arm_in (1.4v) 4.5 ma vdd_soc_in (1.4v) 23 vdd_high_in (3.0v) 13.5 to t a l 7 9 m w table 11. maximum supply currents (continued) power line conditions max current unit
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 30 freescale semiconductor electrical characteristics stop_on ? arm ldo set to 0.9v ? soc and pu ldos set to 1.225 v ? high ldo set to 2.5 v ? plls disabled ? ddr is in self refresh. vdd_arm_in (1.4v) 4 ma vdd_soc_in (1.4v) 22 vdd_high_in (3.0v) 8.5 to t a l 6 1 . 9 m w stop_off ? arm ldo set to 0.9v ? soc ldo set to: 1.225 v ? pu ldo is power gated ? high ldo set to 2.5 v ? plls disabled ? ddr is in self refresh vdd_arm_in (1.4v) 4 ma vdd_soc_in (1.4v) 13.5 vdd_high_in (3.0v) 7.5 to t a l 4 7 m w standby ? arm and pu ldos are power gated ? soc ldo is in bypass ? high ldo is set to 2.5v ? plls are disabled ? low voltage ? well bias on ? crystal oscillator is enabled vdd_arm_in (0.9v) 0.1 ma vdd_soc_in (0.9v) 5 vdd_high_in (3.0v) 5 to t a l 1 9 . 6 m w deep sleep mode (dsm) ? arm and pu ldos are power gated ? soc ldo is in bypass ? high ldo is set to 2.5v ? plls are disabled ? low voltage ? well bias on ? crystal oscillator and bandgap are disabled vdd_arm_in (0.9v) 0.1 ma vddsoc_in (0.9v) 2 vdd_high_in (3.0v) 0.5 to t a l 3 . 4 m w snvs only ? vdd_snvs_in powered ? all other supplies off ? srtc running vdd_snvs_in (2.8v) 41 ? a to t a l 1 1 5 m w 1 the typical values shown here are for information only and ar e not guaranteed. these values are average values measured on a typical wafer at 25c. table 12. stop mode current and power consumption (continued) mode test conditions supply typical 1 units
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 31 4.1.7 usb phy current consumption 4.1.7.1 power down mode in power down mode, everything is powered down, in cluding the usb_vbus vali d detectors in typical condition. table 13 shows the usb interface current consumption in power down mode. note the currents on the vdd_high_ cap and vdd_usb_cap were identified to be the voltage divider circuits in the usb-specific level shifters. 4.1.8 pcie 2.0 power consumption table 14 provides pcie phy currents und er certain tx operating modes. table 13. usb phy current consumption in power down mode vdd_usb_cap (3.0 v) vdd_high_cap (2.5 v) nvcc_pll_out (1.1 v) current 5.1 ? a 1.7 ? a <0.5 ? a table 14. pcie phy current drain mode test conditions supply max current unit p0: normal operation 5g operations pcie_vp (1.1 v) 40 ma pcie_vptx (1.1 v) 20 pcie_vph (2.5 v) 21 2.5g operations pcie_vp (1.1 v) 27 pcie_vptx (1.1 v) 20 pcie_vph (2.5 v) 20 p0s: low recovery time latency, power saving state 5g operations pcie_vp (1.1 v) 30 ma pcie_vptx (1.1 v) 2.4 pcie_vph (2.5 v) 18 2.5g operations pcie_vp (1.1 v) 20 pcie_vptx (1.1 v) 2.4 pcie_vph (2.5 v) 18 p1: longer recovery time latency, lower power state ? pcie_vp (1.1 v) 12 ma pcie_vptx (1.1 v) 2.4 pcie_vph (2.5 v) 12
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 32 freescale semiconductor electrical characteristics 4.1.9 hdmi power consumption table 15 provides hdmi phy currents for both active 3d tx with lf sr15 data and power-down modes. 4.2 power supplies requir ements and restrictions the system design must comply with power-up sequence, power-down seque nce, and steady state guidelines as described in this section to guarantee the reliable operation of the device. any deviation from these sequences may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the pr ocessor (worst-case scenario) power down ? pcie_vp (1.1 v) 1.3 ma pcie_vptx (1.1 v) 0.18 pcie_vph (2.5 v) 0.36 table 15. hdmi phy current drain mode test conditions supply max current unit active bit rate 251.75 mbps hdmi_vph 14 ma hdmi_vp 4.1 ma bit rate 279.27 mbps hdmi_vph 14 ma hdmi_vp 4.2 ma bit rate 742.5 mbps hdmi_vph 17 ma hdmi_vp 7.5 ma bit rate 1.485 gbps hdmi_vph 17 ma hdmi_vp 12 ma bit rate 2.275 gbps hdmi_vph 16 ma hdmi_vp 17 ma bit rate 2.97 gbps hdmi_vph 19 ma hdmi_vp 22 ma power-down ? hdmi_vph 49 ? a hdmi_vp 1100 ? a table 14. pcie phy current drain (continued) mode test conditions supply max current unit
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 33 4.2.1 power-up sequence the below restrictions must be followed: ? vdd_snvs_in supply must be turned on befo re any other power supply or be connected (shorted) with vdd_high_in supply. ? if a coin cell is used to power vdd_snvs_in, th en ensure that it is connected before any other supply is switched on. ? if the external src_por_ b signal is used to c ontrol the processor por, then src_por_b must be immediately asserted at power-up and remain assert ed until the vdd_arm_cap, vdd_soc_cap, and vdd_pu_cap supplies are stable. vdd_arm_in and vdd_soc_in may be applied in either order w ith no restrictions. in the absence of an exte rnal reset feeding the src_por_b input, the internal por module take s control. see the i.mx 6solo/6duallite reference manual (imx6sdlrm) for further details and to ensure that all necessary requirements are being met. ? if the external src_por_b signal is used to control the processor por, src_por_b must remain low (asserted) until the vdd_arm_c ap and vdd_soc_cap supplies are stable. vdd_arm_in and vdd_soc_in may be applied in either or der with no restrictions. ? if the external src_por_b signal is not used (always held high or left unconnected), the processor defaults to the internal por function (where the pmu controls generation of the por based on the power supplies). if the internal po r function is used, the following power supply requirements must be met: ? vdd_arm_in and vdd_soc _in may be supplied from the same source, or ? vdd_soc_in can be supplied before vdd_arm_in with a maximum delay of 1 ms. ? vdd_arm_cap must not exceed vdd_soc_cap by more than +100 mv. note need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 v supply (f or example, from the external components that use both the 1.8 v and 3.3 v supplies). note usb_otg_vbus and usb_h1_vbus ar e not part of the power supply sequence and may be powered at any time. 4.2.2 power-down sequence no special restrictions fo r i.mx 6solo/6duallite ic. 4.2.3 power supplies usage all i/o pins should not be externally driven while the i/o power supply for the pin (nvcc_xxx) is off. this can cause internal latch-up a nd malfunctions due to reverse curren t flows. for info rmation about i/o power supply of each pin, s ee ?power rail? columns in pin list tables of section 6, ?package information and contact assignments.?
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 34 freescale semiconductor electrical characteristics 4.3 integrated ldo voltage regulator parameters various internal supplies can be powered on from inte rnal ldo voltage regulators. all the supply pins named *_cap must be connected to external capaci tors. the onboard ldos are intended for internal use only and should not be used to power any external circuitry. see the i.mx 6solo/6duallite reference manual (imx6sdlrm) for details on the power tree scheme. note the *_cap signals should not be power ed externally. these signals are intended for internal ldo or ldo bypass operation only. 4.3.1 digital regulators (ldo_arm, ldo_pu, ldo_soc) there are three digital ldo regulators (?digital?, beca use of the logic loads that they drive, not because of their construction). the advantages of the regulator s are to reduce the input s upply variation because of their input supply ripple rejection and their on-die trim ming. this translates into more stable voltage for the on-chip logics. these regulators have three basic modes: ? bypass. the regulation fet is switched fully on pass ing the external voltage, to the load unaltered. the analog part of the regulator is powered down in this state, removing an y loss other than the ir drop through the power grid and fet. ? power gate. the regulation fet is switched full y off limiting the current draw from the supply. the analog part of the regulator is powered down here limiting th e power consumption. ? analog regulation mode. the regulation fet is c ontrolled such that the output voltage of the regulator equals the programmed ta rget voltage. the target voltage is fully programmable in 25 mv steps. for additional information, see the i. mx 6solo/6duallite reference manual. 4.3.2 regulators for analog modules 4.3.2.1 ldo_1p1 the ldo_1p1 regulator implements a programmable linear-regulator function from vdd_high_in (see table 9 for minimum and maximum input requirements). typical program ming operating range is 1.0 v to 1.2 v with the nominal default setting as 1.1 v. the ldo_1p1 supplies the usb phy, lvds phy, hdmi phy, mipi phy, and plls. a programma ble brown-out detector is included in the regulator that can be used by the system to determine when the load capabilit y of the regulator is being exceeded to take the necessary steps. current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. active-pull-down can also be enabled for systems requiring this feature. for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6quad, 6dual, 6duallite, 6s olo families of applic ations processors (imx6dq6sdlhdg). for additional information, see the i. mx 6solo/6duallite reference manual.
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 35 4.3.2.2 ldo_2p5 the ldo_2p5 module implements a programmable linear-regulator f unction from vdd_high_in (see table 9 for minimum and maximum input requirement s). typical programming operating range is 2.25 v to 2.75 v with the nominal default setting as 2.5 v. ldo_2p5 supplies the usb phy, lvds phy, hdmi phy, mipi phy, e-fuse module, and plls. a pr ogrammable brown-out dete ctor is included in the regulator that can be used by the system to determin e when the load capability of the regulator is being exceeded, to take the necessary st eps. current-limiting can be enab led to allow for in-rush current requirements during start-up, if need ed. active-pull-down can also be enabled for systems requiring this feature. an alternate self-biase d low-precision weak-regul ator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main regulator driver and its associ ated global bandgap reference module are disa bled. the output of the weak-regulator is not programmable and is a function of the input suppl y as well as the load curr ent. typically, with a 3 v input supply the weak-regulator output is 2.525 v and its output impedance is approximately 40 ? . for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6quad, 6dual, 6duallite, 6s olo families of applic ations processors (imx6dq6sdlhdg). for additional information, see the i. mx 6solo/6duallite reference manual. 4.3.2.3 ldo_usb the ldo_usb module implements a program mable linear-regulator function from the usb_otg_vbus and usb_h1_vbus voltages ( 4.4 v?5.25 v) to produce a nominal 3.0 v output voltage. a programmable brown-out det ector is included in the regulator that can be used by the system to determine when the load capability of the regulator is be ing exceeded, to take the necessary steps. this regulator has a built in power-mux that allows the us er to select to run th e regulator from either usb_vbus supply, when both are present. if only one of the usb_vbus voltages is present, then, the regulator automatically selects this supply. current limi t is also included to help the system meet in-rush current targets. for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6quad, 6dual, 6duallite, 6s olo families of applic ations processors (imx6dq6sdlhdg). for additional information, see the i. mx 6solo/6duallite reference manual.
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 36 freescale semiconductor electrical characteristics 4.4 pll?s electrical characteristics 4.4.1 audio/video pll?s electrical parameters 4.4.2 528 mhz pll 4.4.3 ethernet pll 4.4.4 480 mhz pll table 16. audio/video pll?s electrical parameters parameter value clock output range 650 mhz ~1.3 ghz reference clock 24 mhz lock time <11250 reference cycles table 17. 528 mhz pll?s electrical parameters parameter value clock output range 528 mhz pll output reference clock 24 mhz lock time <11250 reference cycles table 18. ethernet pll?s electrical parameters parameter value clock output range 500 mhz reference clock 24 mhz lock time <11250 reference cycles table 19. 480 mhz pll?s electrical parameters parameter value clock output range 480 mhz pll output reference clock 24 mhz lock time <383 reference cycles
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 37 4.4.5 mlb pll the medialb pll is necessary in the medialb 6-pi n implementation to phase align the internal and external clock edges, effectively tuning out the delay of the differen tial clock receiver and is also responsible for generating the higher speed internal cl ock, when the internal-to-external clock ratio is not 1:1. 4.4.6 arm pll 4.5 on-chip oscillators 4.5.1 osc24m this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements an oscillator. the oscillator is powered from nvcc_pll_out. the system crystal oscillator consists of a pierce-t ype structure running off the digital supply. a straight forward biased-inverter implementation is used. 4.5.2 osc32k this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements a low power oscillator. it also implements a power mux such that it can be powered from either a ~3 v backup battery (vdd_snvs_in) or vdd_high_in such as the oscillator consumes power from vdd_high_in when that supply is available and transitions to the back up battery when vdd_high_in is lost. in addition, if the clock monitor dete rmines that the osc32k is not pres ent, then the source of the 32 khz clock will automatically switch to the internal ring oscillator. table 20. mlb pll?s electrical parameters parameter value lock time <1 ms table 21. arm pll?s electrical parameters parameter value clock output range 650 mhz ~ 1.3 ghz reference clock 24 mhz lock time <2250 reference cycles
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 38 freescale semiconductor electrical characteristics caution the internal rtc oscillator does not provide an accurate frequency and is affected by process, voltage, and temp erature variations . freescale strongly recommends using an external crystal as the rtc_xtali reference. if the internal oscillator is used instead, careful considerat ion must be given to the timing implications on all of the so c modules dependent on this clock. the osc32k runs from vdd_snvs_cap supply, which comes from the vdd_high_in/vdd_snvs_in. the target battery is a ~3 v coin cell. proper choice of coin cell type is necessary for chosen vdd_high _in range. appropriate series resi stor (rs) must be used when connecting the coin cell. rs depends on the charge curr ent limit that depends on the chosen coin cell. for example, for panasonic ml621: ? average discharge voltage is 2.5 v ? maximum charge current is 0.6 ma for a charge voltage of 3.2 v, rs = (3.2-2.5)/0.6 m = 1.17 k. 4.6 i/o dc parameters this section includes the dc parame ters of the following i/o types: ? general purpose i/o (gpio) ? double data rate i/o (ddr) for lpddr2 and ddr3 modes ? lvds i/o ?mlb i/o table 22. osc32k main characteristics characteristic min typ max comments fosc ? 32.768 khz ? this frequency is nominal and determined mainly by the crystal selected. 32.0 k would work as well. current consumption ? 4 ? a ? the 4 ? a is the consumption of the oscillator alone (osc32k). total supply consumption will depend on what the di gital portion of the rtc consumes. the ring oscillator consumes 1 ? a when ring oscillator is inactive, 20 ? a when the ring oscillator is running. another 1.5 ? a is drawn from vdd_rtc in the power_detect block. so, the total current is 6.5 ? a on vdd_rtc when the ring oscillator is not running. bias resistor ? 14 m ? ? this the integrated bias resistor th at sets the amplifier into a high gain state. any leakage through the esd network, external board leakage, or even a scope probe that is significant relative to this value will debias the amp. the debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations. crystal properties cload ? 10 pf ? usually crystals can be purchased tuned for different cloads. this cload value is typically 1/2 of the capacitances realized on the pcb on either side of the quartz. a higher cload will decrease oscillation margin, but increases current oscillat ing through the crystal. esr ? 50 k ? 100 k ? equivalent series resistance of the crystal. choosing a crystal with a higher value will decrease the oscillating margin.
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 39 note the term ?ovdd? in this section refers to the associated supply rail of an input or output. figure 3. circuit for parameters voh and vol for i/o cells 4.6.1 xtali and rtc_xtali (clock inputs) dc parameters table 23 shows the dc parameters for the clock inputs. table 23. xtali and rtc_xtali dc parameters parameter symbol test conditions min max unit xtali high-level dc input voltage vih ? 0.8 x nvcc_pll_out nvcc_pll_ out v xtali low-level dc input voltage vil ? 0 0.2v v rtc_xtali high-level dc input voltage vih ? 0.8 1.1 v rtc_xtali low-level dc input voltage vil ? 0 0.2v v 0 or 1 predriver pdat ovdd pad nmos (rpd) ovss voh min vol max pmos (rpu)
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 40 freescale semiconductor electrical characteristics 4.6.2 general purpose i/o (gpio) dc parameters table 24 shows dc parameters for gp io pads. the parameters in table 24 are guaranteed per the operating ranges in table 9 , unless otherwise noted. 4.6.3 ddr i/o dc parameters the ddr i/o pads support lpddr2 and ddr3/ddr3l operational modes. table 24. gpio dc parameters parameter symbol test conditions min max units high-level output voltage 1 1 overshoot and undershoot conditions (tr ansitions above ovdd and below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot/unders hoot must not exceed 10% of the system clock cycle. overshoot/ undershoot must be controlled through printed circuit board layout, transmission lin e impedance matching, signal line termination, or other method s. non-compliance to this specification may affect devi ce reliability or cause permanent damage to the device. v oh ioh= -0.1ma (ipp_dse=001,010) ioh= -1ma (ipp_dse=011,100,101,110,111) ovdd-0.15 ? v low-level output voltage 1 vol iol= 0.1ma (ipp_dse=001,010) iol= 1ma (ipp_dse=011,100,101,110,111) ?0.15v high-level input voltage 1,2 2 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. mo notonic input transition time is from 0.1 ns to 1 s. vih ? 0.7*ovdd ovdd v low-level input voltage 1,2 vil ? 0 0.3*ovdd v input hysteresis (ovdd= 1.8v) vhys_lowvdd ovdd=1.8v 250 ? mv input hysteresis (ovdd=3.3v vhys_highvdd ovdd=3.3v 250 ? mv schmitt trigger vt+ 2,3 3 hysteresis of 250 mv is guaranteed over all op erating conditions when hysteresis is enabled. vth+ ? 0.5*ovdd ? mv schmitt trigger vt- 2,3 vth- ? ? 0.5*ovdd mv pull-up resistor (22_k ? pu) rpu_22k vin=0v ? 212 ua pull-up resistor (22_k ? pu) rpu_22k vin=ovdd ? 1 ua pull-up resistor (47_k ? pu) rpu_47k vin=0v ? 100 ua pull-up resistor (47_k ? pu) rpu_47k vin=ovdd ? 1 ua pull-up resistor (100_k ? pu) rpu_100k vin=0v ? 48 ua pull-up resistor (100_k ? pu) rpu_100k vin=ovdd ? 1 ua pull-down resistor (100_k ? pd) rpd_100k vin=ovdd ? 48 ua pull-down resistor (100_k ? pd) rpd_100k vin=0v ? 1 ua input current (no pu/pd) iin vi = 0, vi = ovdd -1 1 ua keeper circuit resistance r_keeper vi =0.3*ovdd, vi = 0.7* ovdd 105 175 k ?
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 41 4.6.3.1 lpddr2 mode i/o dc parameters the lpddr2 interface mode fully complies with jesd209-2b lpddr2 jedec standard release june, 2009. 4.6.3.2 ddr3/ddr3l mode i/o dc parameters the ddr3/ddr3l interface mode fu lly complies with jesd79-3d ddr3 jedec standard release april, 2008. the parameters in table 26 are guaranteed per th e operating ranges in table 9 , unless otherwise noted. table 25. lpddr2 i/o dc electrical parameters 1 1 note that the jedec lpddr2 specification (jesd209_ 2b) supersedes any specification in this document. parameters symbol test conditions min max unit high-level output voltage voh ioh= -0.1ma 0.9*ovdd ? v low-level output voltage v ol iol= 0.1ma ? 0.1*ovdd v input reference voltage vref ? 0.49*ovdd 0.51*ovdd v dc high-level input voltage vih_dc ? vref+0.13 ovdd v dc low-level input voltage vil_dc ? ovss vref-0.13 v differential input logic high vih_diff ? 0.26 note 2 2 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. differential input logic low vil_diff ? note 3 3 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. -0.26 pull-up/pull-down impedance mismatch mmpupd ? -15 15 % 240 ? unit calibration resolution rres ? ? 10 ? keeper circuit resistance rkeep ? 110 175 k ? input current (no pull-up/down) iin vi = 0, vi = ovdd -2.5 2.5 ? a table 26. ddr3/ddr3l i/o dc electrical characteristics parameters symbol test conditions min max unit high-level output voltage voh ioh= -0.1ma voh (for ipp_dse=001) 0.8*ovdd 1 ?v low-level output voltage vol iol= 0.1ma vol (for ipp_dse=001) ?0.2*ovddv high-level output voltage voh ioh= -1ma voh (for all except ipp_dse=001) 0.8*ovdd ? v low-level output voltage vol iol= 1ma vol (for all except ipp_dse=001) ?0.2*ovddv input reference voltage vref ? 0.49*ovdd 0.51*ovdd v dc high-level input voltage vih_dc ? vref 2 +0.1 ovdd v
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 42 freescale semiconductor electrical characteristics 4.6.4 lvds i/o dc parameters the lvds interface complies with tia/eia 644-a standard. see tia/eia standard 644-a, ?electrical characteristics of low voltage differential signaling (lvd s) interface circuits? for details. table 27 shows the low voltage differential signaling (lvds) i/o dc parameters. 4.6.5 mlb i/o dc parameters the mlb interface complies with analog interface of 6-pin differential media local bus specification version 4.1. see 6-pin differential mlb specifi cation v4.1, ?medialb 6-pi n interface electrical characteristics? for details. note the mlb 6-pin interface does not support speed mode 8192 fs. table 28 shows the media local bus (mlb) i/o dc parameters. dc low-level input voltage vil_dc ? ovss vref-0.1 v differential input logic high vih_diff ? 0.2 see note 3 v differential input logic low vil_diff ? see note 3 -0.2 v termination voltage vtt vtt tracking ovdd/2 0.49*ovdd 0.51*ovdd v pull-up/pull-down impedance mismatch mmpupd ? -10 10 % 240 ?? unit calibration resolution rres ? ? 10 ? keeper circuit resistance rkeep ? 105 165 k ? input current (no pull-up/down) iin vi = 0,vi = ovdd -2.9 2.9 ? a 1 ovdd ? i/o power supply (1.425 v?1.575 v for ddr3 and 1.283 v?1.45 v for ddr3l) 2 vref ? ddr3/ddr3l external reference voltage 3 the single-ended signals need to be within the respective limits (v ih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. table 27. lvds i/o dc characteristics parameter symbol test conditions min typ max unit output differential voltage vod rload-100 ? diff 250 350 450 mv output high voltage voh ioh = 0 ma 1.25 1.375 1.6 v output low voltage vol iol = 0 ma 0.9 1.025 1.25 v offset voltage vos ? 1.125 1.2 1.375 v table 26. ddr3/ddr3l i/o dc electrical characteristics (continued) parameters symbol test conditions min max unit
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 43 4.7 i/o ac parameters this section includes the ac parame ters of the following i/o types: ? general purpose i/o (gpio) ? double data rate i/o (ddr) for lpddr2 and ddr3/ddr3l modes ? lvds i/o ?mlb i/o the gpio and ddr i/o load circuit and out put transition time waveforms are shown in figure 4 and figure 5 . figure 4. load circuit for output figure 5. output transition time waveform 4.7.1 general purpose i/o ac parameters the i/o ac parameters for gpio in slow and fast modes are presented in the table 29 and table 30 , respectively. note that the fast or slow i/o behavior is determined by the appropriate control bits in the iomuxc control registers. table 28. mlb i/o dc characteristics parameter symbol test conditions min max unit output differential voltage vod rload-50 ? diff 300 500 mv output high voltage voh rload-50 ? diff 1.25 1.75 v output low voltage vol rload-50 ? diff 0.75 1.25 v common-mode output voltage ((vpadp*+vpadn*)/2) vocm rload-50 ? diff 1 1.5 v differential output impedance zo ? 1.6 ? k ? test point from output under test cl cl includes package, probe and fixture capacitance 0v ovdd 20% 80% 80% 20% tr tf output (at pad)
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 44 freescale semiconductor electrical characteristics 4.7.2 ddr i/o ac parameters the lpddr2 interface mode fully complies with jesd209-2b lpddr2 jedec standard release june, 2009. the ddr3/ddr3l interface mode fully complies with jesd79-3d ddr3 je dec standard release april, 2008. table 31 shows the ac parameters for ddr i/o operating in lpddr2 mode. table 29. general purpose i/o ac parameters 1.8 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=111) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 2.72/2.79 1.51/1.54 ns output pad transition times, rise/fall (high drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 3.20/3.36 1.96/2.07 output pad transition times, rise/fall (medium drive, ipp_dse=100) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 3.64/3.88 2.27/2.53 output pad transition times, rise/fall (low drive. ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 4.32/4.50 3.16/3.17 input transition times 1 1 hysteresis mode is recommended for input s with transition times greater than 25 ns. trm ? ? ? 25 ns table 30. general purpose i/o ac parameters 3.3 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 1.70/1.79 1.06/1.15 ns output pad transition times, rise/fall (high drive, ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 2.35/2.43 1.74/1.77 output pad transition times, rise/fall (medium drive, ipp_dse=010) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 3.13/3.29 2.46/2.60 output pad transition times, rise/fall (low drive. ipp_dse=001) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 5.14/5.57 4.77/5.15 input transition times 1 1 hysteresis mode is recommended for inputs with transition times greater than 25 ns. trm ? ? ? 25 ns table 31. ddr i/o lpddr2 mode ac parameters 1 parameter symbol test condition min max unit ac input logic high vih(ac) ? vref + 0.22 ovdd v ac input logic low vil(ac) ? 0 vref - 0.22 v ac differential input high voltage 2 vidh(ac) ? 0.44 ? v ac differential input low voltage vidl(ac) ? ? 0.44 v input ac differential cross point voltage 3 vix(ac) relative to vref -0.12 0.12 v
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 45 table 32 shows the ac parameters for ddr i/o operating in ddr3/ddr3l mode. over/undershoot peak vpeak ? ? 0.35 v over/undershoot area (above ovdd or below ovss) varea 400 mhz ? 0.3 v-ns single output slew rate, measured between vol(ac) and voh(ac) tsr 50 ?? to vref. 5 pf load. drive impedance = 40 ?? 30% 1.5 3.5 v/ns 50 ?? to vref. 5pf load.drive impedance = 60 ?? 30% 12.5 skew between pad rise/fall asymmetry + skew caused by ssn t skd clk = 400 mhz ? 0.1 ns 1 note that the jedec lpddr2 spec ification (jesd209_2b) supersedes an y specification in this document. 2 vid(ac) specifies the input differential voltage | vtr - vcp | requi red for switching, where vtr is the ?true? input signal and v cp is the ?complementary? input signal. the minimum value is equal to vih(ac) - vil(ac). 3 the typical value of vix(ac) is expected to be about 0.5 x ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. table 32. ddr i/o ddr3/ddr3l mode ac parameters 1 1 note that the jedec jesd79_3c specification supersedes any specification in this document. parameter symbol test condition min typ max unit ac input logic high vih(ac) ? vref + 0.175 ? ovdd v ac input logic low vil(ac) ? 0 ? vref - 0.175 v ac differential input voltage 2 2 vid(ac) specifies the input differential voltage | vtr-vcp | requir ed for switching, where vtr is the ?true? input signal and v cp is the ?complementary? input signal. the minimum value is equal to vih(ac) - vil(ac). vid(ac) ? 0.35 ? ? v input ac differential cross point voltage 3 3 the typical value of vix(ac) is expected to be about 0.5 x ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. vix(ac) relative to vref vref - 0.15 ? vref + 0.15 v over/undershoot peak vpeak ? ? ? 0.4 v over/undershoot area (above ovdd or below ovss) varea 400 mhz ? ? 0.5 v-ns single output slew rate, measured between vol(ac) and voh(ac) tsr driver impedance = 34 ? 2.5 ? 5 v/ns skew between pad rise/fall asymmetry + skew caused by ssn t skd clk = 400 mhz ?? 0.1 ns table 31. ddr i/o lpddr2 mode ac parameters 1 (continued) parameter symbol test condition min max unit
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 46 freescale semiconductor electrical characteristics 4.7.3 lvds i/o ac parameters the differential output transiti on time waveform is shown in figure 6 . figure 6. differential lvds driv er transition time waveform table 33 shows the ac parameters for lvds i/o. 4.7.4 mlb i/o ac parameters the differential output transiti on time waveform is shown in figure 7 . figure 7. differential mlb driver transition time waveform table 33. i/o ac parameters of lvds pad parameter symbol test condition min typ max unit differential pulse skew 1 1 t skd = | t phld -t plhd |, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. t skd rload = 100 ? , cload = 2 pf ? ? 0.25 ns transition low to high time 2 2 measurement levels are 20-80% from output voltage. t tlh ??0.5 transition high to low time 2 t thl ??0.5 operating frequency f ? ? 600 800 mhz offset voltage imbalance vos ? ? ? 150 mv padp padn vdiff 0v (differential) vdiff = {padp} - {padn} t tlh 20% 80% 20% 80% t thl v oh v ol 0v 0v 0v padp padn vdiff 0v (differential) vdiff = {padp} - {padn} t tlh 20% 80% 20% 80% t thl v oh v ol 0v 0v 0v
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 47 a 4-stage pipeline is utilized in the mlb 6-pin im plementation in order to fa cilitate design, maximize throughput, and allow for reasonable pcb trace lengths . each cycle is one ipp_clk_in* (internal clock from mlb pll) clock period. cycles 2, 3, and 4 are mlb phy related. cycle 2 includes clock-to-output delay of signal/data sampling flip-flop and transm itter, cycle 3 includes cl ock-to-output delay of signal/data clocked receiver, cycl e 4 includes clock-to-output delay of signal/data sampling flip-flop. mlb 6-pin pipeline di agram is shown in figure 8 . figure 8. mlb 6-pin pipeline diagram table 34 shows the ac parameters for mlb i/o. 4.8 output buffer impedance parameters this section defines the i/o imped ance parameters of the i.mx 6s olo/6duallite processors for the following i/o types: ? general purpose i/o (gpio) ? double data rate i/o (ddr) for lpddr2, and ddr3/ddr3l modes ? lvds i/o ?mlb i/o table 34. i/o ac parameters of mlb phy parameter symbol test condition min typ max unit differential pulse skew 1 1 t skd = | t phld -t plhd |, is the magnitude difference in differential pr opagation delay time between the positive going edge and the negative going edge of the same channel. t skd rload = 50 ? between padp and padn ?? 0.1 ns transition low to high time 2 2 measurement levels are 20- 80% from output voltage. t tlh ?? 1 transition high to low time t thl ?? 1 mlb external clock operating frequency fclk_ext ? ? ? 102.4 mhz mlb pll clock operating frequency fclk_pll ? ? ? 307.2 mhz
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 48 freescale semiconductor electrical characteristics note gpio and ddr i/o output driver imp edance is measured with ?long? transmission line of impeda nce ztl attached to i/o pad and incident wave launched into transmission line. rpu/rpd and ztl form a volta ge divider that defines specific voltage of incident wave relative to ovdd. output driver impedance is calculated from this voltage divider (see figure 9 ). figure 9. impedance matching load for measurement ipp_do cload = 1p ztl ? , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd?vref1 vref1 ? ztl rpd = ? ztl vref2 vovdd?vref2 vref1 vref2 0
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 49 4.8.1 gpio output buffer impedance table 35 shows the gpio output buffer impedance (ovdd 1.8 v). table 36 shows the gpio output buffer impedance (ovdd 3.3 v). 4.8.2 ddr i/o output buffer impedance the lpddr2 interface fully complies with jesd 209-2b lpddr2 jedec standard release june, 2009. the ddr3 interface fully complies with jesd79- 3d ddr3 jedec standard release april, 2008. table 37 shows ddr i/o output buffe r impedance of i.mx 6sol o/6duallite processors. note: 1. output driver impedanc e is controlled across pvts using zq calibration procedure. 2. calibration is done against 240 ? external reference resistor. 3. output driver impedance devi ation (calibration accuracy) is 5% (max/min impedance) across pvts. table 35. gpio output buffer average impedance (ovdd 1.8 v) parameter symbol drive strength (dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 260 130 90 60 50 40 33 ? table 36. gpio output buffer average impedance (ovdd 3.3 v) parameter symbol drive strength (dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 150 75 50 37 30 25 20 ? table 37. ddr i/o output buffer impedance parameter symbol test conditions dse (drive strength) typical unit nvcc_dram=1.5 v (ddr3) ddr_sel=11 nvcc_dram=1.2 v (lpddr2) ddr_sel=10 output driver impedance rdrv 000 001 010 011 100 101 110 111 hi-z 240 120 80 60 48 40 34 hi-z 240 120 80 60 48 40 34 ?
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 50 freescale semiconductor electrical characteristics 4.8.3 lvds i/o output buffer impedance the lvds interface complies with tia/eia 644-a standard. see, tia/eia standard 644-a, ?electrical characteristics of low voltage differential signaling (lvd s) interface circuits? for details. 4.8.4 mlb i/o differential output impedance table 38 shows mlb i/o differential output impedanc e of the i.mx 6solo/6duallite processors. 4.9 system modules timing this section contains the timing a nd electrical parameters for the m odules in each i.mx 6solo/6duallite processor. 4.9.1 reset timings parameters figure 10 shows the reset timing and table 39 lists the timing parameters. figure 10. reset timing diagram 4.9.2 wdog reset timing parameters figure 11 shows the wdog reset timing and table 40 lists the timing parameters. figure 11. wdog1_b timing diagram table 38. mlb i/o differential output impedance parameter symbol test conditions min typ max unit differential output impedance zo ? 1.6 k ? ? ? table 39. reset timing parameters id parameter min max unit cc1 duration of src_por_b to be qualified as valid. 1 1 src_por_b rise and fall times must be 5 ns or less. 1? xtalosc_rtc_xtali cycle table 40. wdog1_b timing parameters id parameter min max unit cc3 duration of wdog1_b assertion 1 ? xtalosc_rtc_xtali cycle src_por_b cc1 (input) wdog1_b cc3 (output)
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 51 note xtalosc_rtc_xtali is approximately 32 khz. xtalosc_rtc_xtali cycle is one period or approximately 30 ? s. note wdog1_b output signals (for each one of the watchdog modules) do not have dedicated pins, but are muxed out through the iomux. see the iomux manual for detailed information. 4.9.3 external interface module (eim) the following subsections provide information on the eim. maxi mum operating frequency for eim data transfer is 104 mhz. timing parameters in this section that are given as a function of register settings or clock periods are valid for the entire ra nge of allowed fre quencies (0?104 mhz). 4.9.3.1 eim interface pads allocation eim supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes. table 41 provides eim interface pads al location in different modes. table 41. eim internal module multiplexing 1 1 for more information on configuration ports mentioned in this table, see the i.mx 6solo/6duallite reference manual. setup non multiplexed address/data mode multiplexed address/data mode 8 bit 16 bit 32 bit 16 bit 32 bit mum = 0, dsz = 100 mum = 0, dsz = 101 mum = 0, dsz = 110 mum = 0, dsz = 111 mum = 0, dsz = 001 mum = 0, dsz = 010 mum = 0, dsz = 011 mum = 1, dsz = 001 mum = 1, dsz = 011 eim_addr [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_data [09:00] eim_data [07:00], eim_eb0_b eim_data [07:00] ???eim_data [07:00] ?eim_data [07:00] eim_ad [07:00] eim_ad [07:00] eim_data [15:08], eim_eb1_b ?eim_data [15:08] ??eim_data [15:08] ?eim_data [15:08] eim_ad [15:08] eim_ad [15:08] eim_data [23:16], eim_eb2_b ??eim_data [23:16] ??eim_data [23:16] eim_data [23:16] ?eim_data [07:00] eim_data [31:24], eim_eb3_b ???eim_data [31:24] ?eim_data [31:24] eim_data [31:24] ?eim_data [15:08]
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 52 freescale semiconductor electrical characteristics 4.9.3.2 general eim timing-synchronous mode figure 12 , figure 13 , and table 42 specify the timings related to the eim module. all ei m output control signals may be asserted and deasserted by an intern al clock synchronized to the eim_bclk rising edge according to corresponding assert ion/negation control fields. , figure 12. eim outputs timing diagram figure 13. eim inputs timing diagram we4 eim_addrxx eim_csx_b eim_we_b eim_oe_b eim_bclk eim_ebx_b eim_lba_b output data ... we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1 input data eim_wait_b eim_bclk we19 we18 we21 we20
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 53 4.9.3.3 examples of eim synchronous accesses table 42. eim bus timing parameters 1 id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max we1 eim_bclk cycle time 2 t ? 2 x t ? 3 x t ? 4 x t ? we2 eim_bclk low level width 0.4 x t ? 0.8 x t ? 1.2 x t ? 1.6 x t ? we3 eim_bclk high level width 0.4 x t ? 0.8 x t ? 1.2 x t ? 1.6 x t ? we4 clock rise to address valid 3 -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we5 clock rise to address invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we6 clock rise to eim_csx_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we7 clock rise to eim_csx_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we8 clock rise to eim_we_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we9 clock rise to eim_we_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we10 clock rise to eim_oe_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we11 clock rise to eim_oe_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we12 clock rise to eim_ebx_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we13 clock rise to eim_ebx_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we14 clock rise to eim_lba_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we15 clock rise to eim_lba_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we16 clock rise to output data valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we17 clock rise to output data invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we18 input data setup time to clock rise 2 ? 4????? we19 input data hold time from clock rise 2 ? 2????? we20 eim_wait_b setup time to clock rise 2 ? 4????? we21 eim_wait_b hold time from clock rise 2 ? 2?????
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 54 freescale semiconductor electrical characteristics figure 14 to figure 17 provide few examples of ba sic eim accesses to external memory devices with the timing parameters mentioned previously fo r specific control parameters settings. figure 14. synchronous memory read access, wsc=1 1 t is the maximum eim logic (axi_clk) cycle time. the maximum allowed axi_clk frequency depends on the fixed/non-fixed latency configuration, whereas the ma ximum allowed eim_bclk frequency is: ?fixed latency for both read and write is 104 mhz. ?variable latency for read only is 104 mhz. ?variable latency for write only is 52 mhz. in variable latency configuration for write, if bcd = 0 & wb cdd = 1 or bcd = 1, axi_clk must be 104 mhz.write bcd = 1 and 104 mhz axi_clk, will result in a eim_bclk of 52 mhz. when the clock branch to eim is decr eased to 104 mhz, other buses are impacted which are clocked from this source. see the ccm chapter of the i.mx 6solo/6duallite reference manual (imx6sdlrm) for a detailed clock tree description. 2 eim_bclk parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined as 50% as signal value. 3 for signal measurements, ?high? is defined as 80% of si gnal value and ?low? is defined as 20% of signal value. last valid address address v1 d(v1) eim_bclk eim_addrxx eim_dataxx eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we18 we19
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 55 figure 15. synchronous memory, write access, wsc=1, wbea=0 and wadvn=0 figure 16. muxed address/data (a/d) mode, sync hronous write access, wsc=6,adva=0, advn=1, and adh=1 note in 32-bit muxed address/data (a/d) mode the 16 msbs are driven on the data bus. last valid address address v1 d(v1) eim_bclk eim_addrxx eim_dataxx eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17 eim_bclk eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b address v1 write data we4 we16 we6 we7 we9 we8 we10 we11 we14 we15 we17 we5 last valid address eim_addrxx/ eim_adxx
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 56 freescale semiconductor electrical characteristics figure 17. 16-bit muxed a/d mode , synchronous read access, wsc=7, radvn=1, adh=1, oea=0 4.9.3.4 general eim timing-asynchronous mode figure 18 through figure 22 , and table 43 help you determine timing parame ters relative to the chip select (cs) state for asynchronous and dtack eim accesses with corresponding eim bit fields and the timing parameters mentioned above. asynchronous read & write access length in cy cles may vary from what is shown in figure 18 through figure 21 as rwsc, oen and csn is configured differently. see the i.mx 6solo/6dualli te reference manual (imx6sdlrm) for the eim programming model. figure 18. asynchronous memory read access (rwsc = 5) last eim_bclk eim_addrxx/ eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b address v1 data valid address eim_adxx we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we19 we4 last valid address address v1 d(v1) eim_addrxx/ eim_dataxx[7:0] eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 int_clk start of access end of access maxdi maxcso maxco eim_adxx
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 57 figure 19. asynchronous a/d muxed read access (rwsc = 5) figure 20. asynchronous memory write access addr. v1 d(v1) eim_addrxx/ eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we39 we35a we37 we36 we38 we40a we31 we44 int_clk start of access end of access maxdi maxcso maxco we32a eim_adxx last valid address address v1 d(v1) eim_addrxx eim_dataxx eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 58 freescale semiconductor electrical characteristics figure 21. asynchronous a/d muxed write access figure 22. dtack mode read access (dap=0) eim_we_b eim_oe_b eim_ebx_b eim_csx_b we33 we45 we34 we46 we42 addr. v1 d(v1) eim_addrxx/ we31 we42 we41 we32a eim_dataxx eim_lba_b we39 we40a last valid address address v1 d(v1) eim_addrxx eim_dataxx[7:0] eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 eim_dtack_b we47 we48
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 59 figure 23. dtack mode write access (dap=0) table 43. eim asynchronous timing parameters table relative chip to select ref no. parameter determination by synchronous measured parameters 1 min max unit we31 eim_csx_b valid to address valid we4 - we6 - csa 2 ? 3 - csa ns we32 address invalid to eim_csx_b invalid we7 - we5 - csn 3 ?3 - csnns we32a(m uxed a/d eim_csx_b valid to address invalid t 4 + we4 - we7 + (advn 5 + adva 6 + 1 - csa) -3 + (advn + adva + 1 - csa) ?ns we33 eim_csx_b valid to eim_we_b valid we8 - we6 + (wea - wcsa) ? 3 + (wea - wcsa) ns we34 eim_we_b invalid to eim_csx_b invalid we7 - we9 + (wen - wcsn) ? 3 - (wen_wcsn) ns we35 eim_csx_b valid to eim_oe_b valid we10 - we6 + (oea - rcsa) ? 3 + (oea - rcsa) ns we35a (muxed a/d) eim_csx_b valid to eim_oe_b valid we10 - we6 + (oea + radvn + radva + adh + 1 - rcsa) -3 + (oea + radvn+radva+ adh+1-rcsa) 3 + (oea + radvn+radva+ad h+1-rcsa) ns we36 eim_oe_b invalid to eim_csx_b invalid we7 - we11 + (oen - rcsn) ? 3 - (oen - rcsn) ns we37 eim_csx_b valid to eim_ebx_b valid (read access) we12 - we6 + (rbea - rcsa) ? 3 + (rbea - rcsa) ns last valid address address v1 d(v1) eim_addrxx eim_dataxx eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 eim_dtack_b we48 we47
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 60 freescale semiconductor electrical characteristics we38 eim_ebx_b invalid to eim_csx_b invalid (read access) we7 - we13 + (rben - rcsn) ? 3 - (rben- rcsn) ns we39 eim_csx_b valid to eim_lba_b valid we14 - we6 + (adva - csa) ? 3 + (adva - csa) ns we40 eim_lba_b invalid to eim_csx_b invalid (advl is asserted) we7 - we15 - csn ? 3 - csn ns we40a (muxed a/d) eim_csx_b valid to eim_lba_b invalid we14 - we6 + (advn + adva + 1 - csa) -3 + (advn + adva + 1 - csa) 3 + (advn + adva + 1 - csa) ns we41 eim_csx_b valid to output data valid we16 - we6 - wcsa ? 3 - wcsa ns we41a (muxed a/d) eim_csx_b valid to output data valid we16 - we6 + (wadvn + wadva + adh + 1 - wcsa) ? 3 + (wadvn + wadva + adh + 1 - wcsa) ns we42 output data invalid to eim_csx_b invalid we17 - we7 - csn ? 3 - csn ns maxco output maximum delay from internal driving eim_addrxx/control ffs to chip outputs 10 ? ? ns maxcso output maximum delay from csx internal driving ffs to csx out 10 ? ? ns maxdi eim_dataxx maximum delay from chip input data to its internal ff 5??ns we43 input data valid to eim_csx_b invalid maxco - maxcso + maxdi maxco - maxcso + maxdi ?ns we44 eim_csx_b invalid to input data invalid 00?ns we45 eim_csx_b valid to eim_ebx_b valid (write access) we12 - we6 + (wbea - wcsa) ? 3 + (wbea - wcsa) ns we46 eim_ebx_b invalid to eim_csx_b invalid (write access) we7 - we13 + (wben - wcsn) ? -3 + (wben - wcsn) ns table 43. eim asynchronous timing parameters table relative chip to select (continued) ref no. parameter determination by synchronous measured parameters 1 min max unit
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 61 maxdti maximum delay from eim_dtack_b to its internal ff + 2 cycles for synchronization 10 ? ? ? we47 eim_dtack_b active to eim_csx_b invalid maxco - maxcso + maxdti maxco - maxcso + maxdti ?ns we48 eim_csx_b invalid to eim_dtack_b invalid 00?ns 1 for more information on configuration parameters mentioned in this table, see the i.mx 6solo/6duallite reference manual. 2 in this table, csa means wcsa when write operation or rcsa when read operation. 3 in this table, csn means wcsn when write operation or rcsn when read operation. 4 t is axi_clk cycle time. 5 in this table, advn means wadvn when write operation or radvn when read operation. 6 in this table, adva means wadva when write operation or radva when read operation. table 43. eim asynchronous timing parameters table relative chip to select (continued) ref no. parameter determination by synchronous measured parameters 1 min max unit
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 62 freescale semiconductor electrical characteristics 4.9.4 ddr sdram specific parame ters (ddr3/ddr3l and lpddr2) 4.9.4.1 ddr3/ddr3l parameters figure 24 shows the basic timing parameters. the timi ng parameters for this diagram appear in table 44 . figure 24. ddr3 command and address timing parameters 1 all measurements are in reference to vref level. 2 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. table 44. ddr3/ddr3l timing parameter table id parameter symbol ck = 400 mhz unit min max ddr1 dram_sdclkx_p clock high-level width t ch 0.47 0.53 t ck ddr2 dram_sdclkx_p clock low-level width t cl 0.47 0.53 t ck ddr4 dram_csx_b, dram_ras_b, dram_cas_b, dram_sdckex, dram_sdwe_b, dram_odtx setup time t is 800 ? ps ddr5 dram_csx_b, dram_ras_b, dram_cas_b, dram_sdckex, dram_sdwe_b, dram_odtx hold time t ih 580 ? ps ddr6 address output setup time t is 800 ? ps ddr7 address output hold time t ih 580 ? ps dram_sdclkx_p dram_sdwe_b dram_addrxx row/ba col/ba dram_csx_b dram_cas_b dram_ras_b ddr1 ddr2 ddr4 ddr4 ddr4 ddr5 ddr5 ddr5 ddr5 ddr6 ddr7 dram_sdclkx_n dram_odtx/ ddr4 dram_sdckex
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 63 figure 25 shows the ddr3/ddr3l write timing parameters . the timing parameters for this diagram appear in table 45 . figure 25. ddr3/ddr3l write cycle 1 to receive the reported setup and hold values, write calibration should be performed in order to locate the dram_sdqsx_p in the middle of dram_dataxx window. 2 all measurements are in reference to vref level. 3 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. table 45. ddr3/ddr3l write cycle id parameter symbol ck = 400 mhz unit min max ddr17 dram_dataxx and dram_dqmx setup time to dram_sdqsx_p (differential strobe) t ds 420 ? ps ddr18 dram_dataxx and dram_dqmx hold time to dram_sdqsx_p (differential strobe) t dh 345 ? ps ddr21 dram_sdqsx_p latching rising transitions to associated clock edges t dqss -0.25 +0.25 tck ddr22 dram_sdqsx_p high level width t dqsh 0.45 0.55 tck ddr23 dram_sdqsx_p low level width t dqsl 0.45 0.55 tck dram_sdclkx_p dram_sdclkx_n dram_sdqsx_p (output) dram_dataxx (output) dram_dqmx (output) data data data data data data data data dm dm dm dm dm dm dm dm ddr17 ddr17 ddr17 ddr17 ddr18 ddr18 ddr18 ddr18 ddr21 ddr23 ddr22
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 64 freescale semiconductor electrical characteristics figure 26 shows the read ddr3/ddr3l timing parameters . the timing parameters for this diagram appear in table 46 . figure 26. ddr3/ddr3l read cycle 1 to receive the reported setup and hold values, read calibration should be performed in order to locate the dram_sdqsx_p in the middle of dram_dataxx window. 2 all measurements are in reference to vref level. 3 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. table 46. ddr3/ddr3l read cycle id parameter symbol ck = 400 mhz unit min max ddr26 minimum required dram_dataxx valid window width ? 450 ? ps dram_sdclkx_p dram_sdclkx_n dram_sdqsx_p (input) dram_dataxx (input) data data data data data data data data ddr26
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 65 4.9.4.2 lpddr2 parameters figure 27 shows the basic timing parameters. the timi ng parameters for this diagram appear in table 47 . figure 27. lpddr2 command and address timing parameters 1 all measurements are in reference to vref level. 2 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. figure 28 shows the write timing parameters. the timi ng parameters for this diagram appear in table 48 . figure 28. lpddr2 write cycle table 47. lpddr2 timing parameter id parameter symbol ck = 400 mhz unit min max lp1 dram_sdclkx_p clock high-level width t ch 0.45 0.55 t ck lp2 dram_sdclkx_p clock low-level width t cl 0.45 0.55 t ck lp3 dram_addrxx, dram_csx_b setup time t is 380 ? ps lp4 dram_addrxx, dram_csx_b hold time t ih 380 ? ps lp5 dram_sdckex setup time t iscke 770 ? tck lp6 dram_sdckex hold time t ihcke 770 ? tck dram_sdclkx_p dram_csx_b dram_sdckex dram_addrxx lp4 lp4 lp3 lp4 lp3 lp2 lp3 lp5 lp1 lp6 dram_sdclkx_p dram_sdclkx_n dram_sdqsx_p (output) dram_dataxx(output) dram_dqmx (output) data data data data data data data data dm dm dm dm dm dm dm dm lp17 lp17 lp17 lp17 lp18 lp18 lp18 lp18 lp21 lp23 lp22
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 66 freescale semiconductor electrical characteristics 1 to receive the reported setup and hold values, write calibration should be performed in order to locate the dram_sdqsx_p in the middle of dram_dataxx window. 2 all measurements are in reference to vref level. 3 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. figure 29 shows the read timing parameters. the timi ng parameters for this diagram appear in table 49 . figure 29. lpddr2 read cycle 1 to receive the reported setup and hold values, read calibration should be performed in order to locate the dram_sdqsx_p in the middle of dram_dataxx window. 2 all measurements are in reference to vref level. 3 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. table 48. lpddr2 write cycle id parameter symbol ck = 400 mhz unit min max lp17 dram_dataxx and dram_dqmx setup time to dram_sdqsx_p (differential strobe) t ds 375 ? ps lp18 dram_dataxx and dram_dqmx hold time to dram_sdqsx_p (differential strobe) t dh 375 ? ps lp21 dram_sdqsx_p latching rising transitions to associated clock edges t dqss -0.25 +0.25 tck lp22 dram_sdqsx_p high level width t dqsh 0.4 ? tck lp23 dram_sdqsx_p low level width t dqsl 0.4 ? tck table 49. lpddr2 read cycle id parameter symbol ck = 400 mhz unit min max lp26 minimum required dram_dataxx valid window width for lpddr2 ? 270 ? ps dram_sdclkx_p dram_sdclkx_n dram_sdqsx_p (input) dram_dataxx (input) data data data data data data data data lp26
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 67 4.10 general-purpose media interface (gpmi) timing the i.mx 6solo/6duallite gpmi contro ller is a flexible interface nand flash controller with 8-bit data width, up to 200 mb/s i/o speed and individual chip select. it supports asynchronous timing mode, source synchronous timing mode and samsung toggle timing mode separately described in the following subsections. 4.10.1 asynchronous mode ac ti ming (onfi 1.0 compatible) asynchronous mode ac timings are provided as multipli cations of the clock cycle and fixed delay. the maximum i/o speed of gpmi in as ynchronous mode is about 50 mb/s. figure 30 through figure 33 depicts the relative timing betwee n gpmi signals at the module le vel for different operations under asynchronous mode. table 50 describes the timing parameters (nf1?n f17) that are show n in the figures. figure 30. command latch cycle timing diagram figure 31. address latch cycle timing diagram }uuv .!.$?#,% .!.$?#%?" .!.$?7%?" .!.$?!,% .!.$?$!4!xx e&? e&? e& e& e&? e&? e& e&? e&e ??? e& e& e&? e&? e& e& e&? e& e&? .!.$?#,% .!.$?#%?" .!.$?7%?" .!.$?!,% eezd??
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 68 freescale semiconductor electrical characteristics figure 32. write data latch cycle timing diagram figure 33. read data latch cycle timing diagram (non-edo mode) figure 34. read data latch cycle timing diagram (edo mode) table 50. asynchronous mode timing parameters 1 id parameter symbol timing t = gpmi clock cycle unit min. max. nf1 nand_cle setup time tcls (as + ds) ? t - 0.12 [see 2,3 ]ns nf2 nand_cle hold time tclh dh ? t - 0.72 [see 2 ]ns nf3 nand_ce0_b setup time tcs (as + ds + 1) ? t [see 3,2 ]ns nf4 nand_ce0_b hold time tch (dh+1) ? t - 1 [see 2 ]ns nf5 nand_we_b pulse width twp ds ? t [see 2 ]ns nf6 nand_ale setup time tals (as + ds) ? t - 0.49 [see 3,2 ]ns nf7 nand_ale hold time talh (dh ? t - 0.42 [see 2 ]ns ??}e& e& e& e& e& e&? e& e&? .!.$?#,% .!.$?#%?" .!.$?7%?" .!.$?!,% .!.$?$!4!xx e&? e&? ?(?}ue& e&e e&? e& e& e&? e&? .!.$?#,% .!.$?#%?" .!.$?2%?" .!.$?2%!$9?" .!.$?$!4!xx ?(?}ue& e&e e&? e& e& e&? e&? .!.$?#,% .!.$?#%?" .!.$?2%?" .!.$?2%!$9?" eezd??
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 69 in edo mode ( figure 33 ), nf16/nf17 are different from the definition in non-edo mode ( figure 32 ). they are called trea/trhoh (re# access time/re# high to output hold). the typical value for them are 16 ns (max for trea)/15 ns (min for trhoh) at 50 mb/s edo mode. in edo mode, gpmi will sample nand_dataxx at rising edge of delayed nand_re_b provided by an internal dpll. the delay value can be controlled by gpmi_ctrl1.r dn_delay (see the gpmi chapter of the i.mx 6solo/6duallite reference manual). the typical value of this contro l register is 0x8 at 50 mt/s edo mode. but if the board delay is bi g enough and cannot be i gnored, the delay value s hould be made larger to compensate the board delay. nf8 data setup time tds ds ? t - 0.26 [see 2 ]ns nf9 data hold time tdh dh ? t - 1.37 [see 2 ]ns nf10 write cycle time twc (ds + dh) ? t [see 2 ]ns nf11 nand_we_b hold time twh dh ? t [see 2 ]ns nf12 ready to nand_re_b low trr 4 (as + 2) ? t [see 3,2 ]?ns nf13 nand_re_b pulse width trp ds ? t [see 2 ]ns nf14 read cycle time trc (ds + dh) ? t [see 2 ]ns nf15 nand_re_b high hold time treh dh ? t [see 2 ]ns nf16 data setup on read tdsr ? (ds ? t -0.67)/18.38 [see 5,6 ]ns nf17 data hold on read tdhr 0.82/11.83 [see 5,6 ]?ns 1 gpmi?s async mode output timing can be controlled by the module?s internal registers hw_gpmi_timing0_address_ setup, hw_gpmi_timing0_ data_setup, and hw_gpm i_timing0_data_hold. this ac timing depends on these registers settings. in the table, as/ds/dh represents each of these settings. 2 as minimum value can be 0, while ds/dh minimum value is 1. 3 t = gpmi clock period -0.075ns (half of maximum p-p jitter). 4 nf12 is guaranteed by the design. 5 non-edo mode. 6 edo mode, gpmi clock ? 100 mhz (as=ds=dh=1, gpmi_ctl1 [rdn_delay] = 8, gpmi_ctl1 [half_period] = 0). table 50. asynchronous mode timing parameters 1 (continued) id parameter symbol timing t = gpmi clock cycle unit min. max.
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 70 freescale semiconductor electrical characteristics 4.10.2 source synchronous mode ac timing (onfi 2.x compatible) figure 35 to figure 37 show the write and read timi ng of source synchronous mode. figure 35. source synchronous mode command and address timing diagram 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) &0' $'' .!.$?#%?" 1$1'b&/( 1$1'b$/( 1$1'b:(5(b% 1$1'b&/. 1$1'b'46 1$1'b'46 2xwsxwhqdeoh 1$1'b'$7$>@ 1$1'b'$7$>@ 2xwsxwhqdeoh
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 71 figure 36. source synchronous mode data write timing diagram figure 37. source synchronous mode data read timing diagram 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) .!.$?#%?" .!.$?#,% .!.$?!,% 1$1'b:(5(b% .!.$?#,+ .!.$?$13 .!.$?$13 2xwsxwhqdeoh .!.$?$1;= .!.$?$1;= 2xwsxwhqdeoh 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) .!.$?#%?" .!.$?#,% 1$1'b$/( .!.$?7%2% .!.$?#,+ .!.$?$13 .!.$?$13 /utputenable .!.$?$!4!;= .!.$?$!4!;= /utputenable 1)
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 72 freescale semiconductor electrical characteristics figure 38. nand_dqs/nand_dq read valid window for ddr source sync mode, figure 38 shows the timing diagram of nand_dqs/nand_dataxx read valid window. the typical value of tdqsq is 0.85ns (max) and 1ns (max) for tqhs at 200mb/s. gpmi will sample nand_data[7:0] at both rising and fall ing edge of an delaye d nand_dqs signal, which can be provided by an internal dpll. the dela y value can be controlled by gpmi register gpmi_read_ddr_dll_ctrl.slv_dly_target (s ee the gpmi chapter of the i.mx 6solo/6duallite reference ma nual). generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expecte d. but if the board delay is big e nough and cannot be ignored, the delay value should be made larger to compensate the board delay. table 51. source synchronous mode timing parameters 1 1 gpmi?s source synchronous mode output timing can be controlled by the module?s internal registers gpmi_timing2_ce_delay, gpmi_timing_preamble_delay, gpmi_timing2_post_delay. this ac timing depends on these registers settings. in the table, ce_delay/pre _delay/post_delay represents each of these settings. id parameter symbol timing t = gpmi clock cycle unit min. max. nf18 nand_ce0_b access time tce ce_delay ? t - 0.79 [see 2 ] 2 t = tck(gpmi clock period) -0.075ns (half of maximum p-p jitter). ns nf19 nand_ce0_b hold time tch 0.5 ? tck - 0.63 [see 2 ]ns nf20 command/address nand_dataxx setup time tcas 0.5 ? tck - 0.05 ns nf21 command/address nand_dataxx hold time tcah 0.5 ? tck - 1.23 ns nf22 clock period tck ? ns nf23 preamble delay tpre pre_delay ? t - 0.29 [see 2 ]ns nf24 postamble delay tpost post_delay ? t - 0.78 [see 2 ]ns nf25 nand_cle and nand_ale setup time tcals 0.5 ? tck - 0.86 ns nf26 nand_cle and nand_ale hold time tcalh 0.5 ? tck - 0.37 ns nf27 nand_clk to first nand_dqs latching transition tdqss t - 0.41 [see 2 ]ns nf28 data write setup ? 0.25 ? tck - 0.35 nf29 data write hold ? 0.25 ? tck - 0.85 nf30 nand_dqs/nand_dq read setup skew ? ? 2.06 nf31 nand_dqs/nand_dq read hold skew ? ? 1.95 ? ? .!.$?$13 .!.$?$!4!;= e&? e&? e&? e&?
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 73 4.10.3 samsung toggle mode ac timing 4.10.3.1 command and address timing note samsung toggle mode command and addr ess timing is the same as onfi 1.0 compatible async mode ac timing. see section 4.10.1, ?asynchronous mode ac timing (onfi 1.0 compatible),? for details. 4.10.3.2 read and write timing figure 39. samsung toggle mode data write timing .!.$?$!4!;= dev?clk .!.$?#%x?" .!.$?#,% .!.$?!,% .!.$?7%?" .!.$?2%?" .!.$?$13 t#+ .& .& t#+
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 74 freescale semiconductor electrical characteristics figure 40. samsung toggle mode data read timing table 52. samsung toggle mode timing parameters 1 id parameter symbol timing t = gpmi clock cycle unit min max nf1 nand_cle setup time tcls (as + ds) ? t - 0.12 [see 2,3 ] nf2 nand_cle hold time tclh dh ? t - 0.72 [see 2 ] nf3 nand_ce0_b setup time tcs (as + ds) ? t - 0.58 [see 3,2 ] nf4 nand_ce0_b hold time tch dh ? t - 1 [see 2 ] nf5 nand_we_b pulse width twp ds ? t [see 2 ] nf6 nand_ale setup time tals (as + ds) ? t - 0.49 [see 3,2 ] nf7 nand_ale hold time talh dh ? t - 0.42 [see 2 ] nf8 command/address nand_dataxx setup time tcas ds ? t - 0.26 [see 2 ] nf9 command/address nand_dataxx hold time tcah dh ? t - 1.37 [see 2 ] nf18 nand_cex_b access time tce ce_delay ? t [see 4,2 ]?ns nf22 clock period tck ? ? ns nf23 preamble delay tpre pre_delay ? t [see 5,2 ]?ns nf24 postamble delay tpost post_delay ? t +0.43 [see 2 ]? ns dev?clk .!.$?#%x?" .!.$?#,% .!.$?!,% .!.$?7%?" .!.$?2%?" .!.$?$13 .!.$?$!4!;= .& t#+ t#+ .& t#+ t#+ .& t#+
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 75 for ddr toggle mode, figure 38 shows the timing diagram of nan d_dqs/nand_dataxx read valid window. the typical value of tdqsq is 1.4 ns (max) a nd 1.4 ns (max) for tqhs at 133 mb/s. gpmi will sample nand_data[7:0] at both rising and falling edge of an delayed nand_dqs signal, which is provided by an internal dpll. the delay value of th is register can be cont rolled by gpmi register gpmi_read_ddr_dll_ctrl.slv_dly_target (s ee the gpmi chapter of the i.mx 6solo/6duallite reference manual). generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected. but if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 4.11 external peripheral interface parameters the following subsections provide inform ation on external peripheral interfaces. 4.11.1 audmux timing parameters the audmux provides a programmable interconnect logic for voice, a udio, and data routing between internal serial interfaces (ssis) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is governed by the ssi module. for more information, see the respective ssi electrical specifications f ound within this document. 4.11.2 ecspi timing parameters this section describes the timing parameters of the ecspi blocks. the ecspi have separate timing parameters for master and slave modes. nf28 data write setup tds 6 0.25 ? tck - 0.32 ? ns nf29 data write hold tdh 6 0.25 ? tck - 0.79 ? ns nf30 nand_dqs/nand_dq read setup skew tdqsq 7 ?3.18 nf31 nand_dqs/nand_dq read hold skew tqhs 7 ?3.27 1 the gpmi toggle mode output timing can be controlled by the module?s internal registers hw_gpmi_timing0_address_setup, hw_gpmi_timing0_data_setup, and hw_gpmi_timing0_data_hold. this ac timing depends on these registers settings. in the table, as/ds/dh represents each of these settings. 2 as minimum value can be 0, while ds/dh minimum value is 1. 3 t = tck (gpmi clock period) -0.075ns (half of maximum p-p jitter). 4 ce_delay represents hw_gpmi_timing2[ce _delay]. nf18 is guaranteed by the de sign. read/write operation is started with enough time of ale/cle assertion to low level. 5 pre_delay+1) ? (as+ds) 6 shown in figure 39 , samsung toggle mode data write timing diagram. 7 shown in figure 38 , nand_dqs/nand_dq read valid window. table 52. samsung toggle mode timing parameters 1 (continued) id parameter symbol timing t = gpmi clock cycle unit min max
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 76 freescale semiconductor electrical characteristics 4.11.2.1 ecspi master mode timing figure 41 depicts the timing of ecspi in master mode. table 53 lists the ecspi master mode timing characteristics. figure 41. ecspi master mode timing diagram table 53. ecspi master mode timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle time?read ecspix_sclk cycle time?write t clk 43 15 ?ns cs2 ecspix_sclk high or low time?read ecspix_sclk high or low time?write t sw 21.5 7 ?ns cs3 ecspix_sclk rise or fall 1 1 see specific i/o ac parameters section 4.7, ?i/o ac parameters.? t rise/fall ??ns cs4 ecspix_ss_b pulse width t cslh half ecspix_sclk period ? ns cs5 ecspix_ss_b lead time (cs setup time) t scs half ecspix_sclk period - 4 ? ns cs6 ecspix_ss_b lag time (cs hold time) t hcs half ecspix_sclk period - 2 ? ns cs7 ecspix_mosi propagation delay (c load =20pf) t pdmosi -1 1 ns cs8 ecspix_miso setup time ? t smiso 18 ? ns cs9 ecspix_miso hold time t hmiso 0?ns cs10 rdy to ecspix_ss_b time 2 2 spi_rdy is sampled internally by ipg_clk and is asynchronous to all other cspi signals. t sdry 5?ns cs7 cs2 cs2 cs4 cs6 cs5 cs8 cs9 ecspix_sclk ecspix_ss_b ecspix_mosi ecspix_miso ecspix_rdy_b cs10 cs3 cs3 cs1
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 77 4.11.2.2 ecspi slave mode timing figure 42 depicts the timing of ecspi in slave mode. table 54 lists the ecspi slave mode timing characteristics. figure 42. ecspi slave mode timing diagram 4.11.3 enhanced serial audio inte rface (esai) timing parameters the esai consists of independent transmitter and receiver sections, each section with its own clock generator. table 55 shows the interface timing values. the numbe r field in the table refers to timing signals found in figure 43 and figure 44 . table 54. ecspi slave mo de timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle time?read ecspix_sclk cycle time?write t clk 43 15 ?ns cs2 ecspix_sclk high or low time?read ecspix_sclk high or low time?write t sw 21.5 7 ?ns cs4 ecspix_ss_b pulse width t cslh half ecspix_sclk period ? ns cs5 ecspix_ss_b lead time (cs setup time) t scs 5?ns cs6 ecspix_ss_b lag ti me (cs hold time) t hcs 5?ns cs7 ecspix_mosi setup time t smosi 4?ns cs8 ecspix_mosi hold time t hmosi 4?ns cs9 ecspix_miso propagation delay (c load =20pf) t pdmiso 419ns table 55. enhanced serial audio interface (esai) timing no. characteristics 1,2 symbol expression 2 min max condition 3 unit 62 clock cycle 4 t ssicc 4 ? t c 4 ? t c 30.0 30.0 ? ? i ck i ck ns 63 clock high period: ? for internal clock ? for external clock ? ? 2 ? t c ?? 9.0 2 ? t c 6 15 ? ? ? ? ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 ecspix_sclk ecspix_ss_b ecspix_miso ecspix_mosi
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 78 freescale semiconductor electrical characteristics 64 clock low period: ? for internal clock ? for external clock ? ? 2 ? t c ?? 9.0 2 ? t c 6 15 ? ? ? ? ns 65 esai_rx_clk rising edge to esai_rx_fs out (bl) high ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 66 esai_rx_clk rising edge to esai_rx_fs out (bl) low ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 67 esai_rx_clk rising edge to esai_rx_fs out (wr) high 5 ? ? ? ? ? ? 19.0 9.0 x ck i ck a ns 68 esai_rx_clk rising edge to esai_rx_fs out (wr) low 5 ? ? ? ? ? ? 19.0 9.0 x ck i ck a ns 69 esai_rx_clk rising edge to esai_rx_fs out (wl) high ? ? ? ? ? ? 16.0 6.0 x ck i ck a ns 70 esai_rx_clk rising edge to esai_rx_fs out (wl) low ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 71 data in setup time be fore esai_rx_clk (sck in synchronous mode) falling edge ? ? ? ? 12.0 19.0 ? ? x ck i ck ns 72 data in hold time after esai_rx_clk falling edge ? ? ? ? 3.5 9.0 ? ? x ck i ck ns 73 esai_rx_fs input (bl, wr) high before esai_rx_clk falling edge 5 ? ? ? ? 2.0 12.0 ? ? x ck i ck a ns 74 esai_rx_fs input (wl) high before esai_rx_clk falling edge ? ? ? ? 2.0 12.0 ? ? x ck i ck a ns 75 esai_rx_fs input hold time after esai_rx_clk falling edge ? ? ? ? 2.5 8.5 ? ? x ck i ck a ns 78 esai_tx_clk rising edge to esai_tx_fs out (bl) high ? ? ? ? ? ? 18.0 8.0 x ck i ck ns 79 esai_tx_clk rising edge to esai_tx_fs out (bl) low ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 80 esai_tx_clk rising edge to esai_tx_fs out (wr) high 5 ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 81 esai_tx_clk rising edge to esai_tx_fs out (wr) low 5 ? ? ? ? ? ? 22.0 12.0 x ck i ck ns 82 esai_tx_clk rising edge to esai_tx_fs out (wl) high ? ? ? ? ? ? 19.0 9.0 x ck i ck ns 83 esai_tx_clk rising edge to esai_tx_fs out (wl) low ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 84 esai_tx_clk rising edge to data out enable from high impedance ? ? ? ? ? ? 22.0 17.0 x ck i ck ns 86 esai_tx_clk rising edge to data out valid ? ? ? ? ? ? 18.0 13.0 x ck i ck ns table 55. enhanced serial audio interface (esai) timing (continued) no. characteristics 1,2 symbol expression 2 min max condition 3 unit
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 79 87 esai_tx_clk rising edge to data out high impedance 67 ? ? ? ? ? ? 21.0 16.0 x ck i ck ns 89 esai_tx_fs input (bl, wr) setup time before esai_tx_clk falling edge 5 ? ? ? ? 2.0 18.0 ? ? x ck i ck ns 90 esai_tx_fs input (wl) se tup time before esai_tx_clk falling edge ? ? ? ? 2.0 18.0 ? ? x ck i ck ns 91 esai_tx_fs input hold time after esai_tx_clk falling edge ? ? ? ? 4.0 5.0 ? ? x ck i ck ns 95 esai_rx_hf_clk/esai_tx_hf _clk clock cycle ? 2 x t c 15 ? ? ns 96 esai_tx_hf_clk input rising edge to esai_tx_clk output ???18.0?ns 97 esai_rx_hf_clk input rising edge to esai_rx_clk output ???18.0?ns 1 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that esai_tx_clk and esai_rx_clk are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies th at esai_tx_clk a nd esai_rx_clk are the same clock) 2 bl = bit length wl = word length wr = word length relative 3 esai_tx_clk(sckt pin) = transmit clock esai_rx_clk(sckr pin) = receive clock esai_tx_fs(fst pin) = transmit frame sync esai_rx_fs(fsr pin) = receive frame sync esai_tx_hf_clk(hckt pin) = tr ansmit high frequency clock esai_rx_hf_clk(hckr pin) = re ceive high frequency clock 4 for the internal clock, the external clock cycle is defined by icyc and the esai control register. 5 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame. 6 periodically sampled and not 100% tested. table 55. enhanced serial audio interface (esai) timing (continued) no. characteristics 1,2 symbol expression 2 min max condition 3 unit
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 80 freescale semiconductor electrical characteristics figure 43. esai transmitter timing esai_tx_clk (input/output) esai_tx_fs (bit) out esai_tx_fs (word) out data out esai_tx_fs (bit) in esai_tx_fs (word) in 62 64 78 79 82 83 87 86 86 84 91 89 90 91 63 last bit first bit
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 81 figure 44. esai receiver timing esai_rx_clk (input/output) esai_rx_fs (bit) out esai_rx_fs (word) out data in esai_rx_fs (bit) in esai_rx_fs (word) in 62 64 65 69 70 72 71 75 73 74 75 63 66 first bit last bit
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 82 freescale semiconductor electrical characteristics 4.11.4 ultra high speed sd/sdio/ mmc host interface (usdhc) ac timing this section describes the electrical informat ion of the usdhc, which includes sd/emmc4.3 (single data rate) timing, emmc4.4/4.41 (dual date rate) timing and sdr104/50(sd3.0) timing. 4.11.4.1 sd/emmc4.3 (singl e data rate) ac timing figure 45 depicts the timing of sd/emmc4.3, and table 56 lists the sd/emmc4.3 timing characteristics. figure 45. sd/emmc4.3 timing table 56. sd/emmc4.3 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns usdhc output/card inputs sdx_cmd, sdx_datax (reference to clk) sd6 usdhc output delay t od -6.6 3.6 ns sd1 sd3 sd5 sd4 sd7 sdx_clk sd2 sd8 sd6 output from usdhc to card input from card to usdhc sdx_data[7:0] sdx_data[7:0]
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 83 4.11.4.2 emmc4.4/4.41 (dual data rate) ac timing figure 46 depicts the timi ng of emmc4.4/4.41. table 57 lists the emmc4.4/4.41 ti ming characteristics. be aware that only data is sampled on both e dges of the clock (not applicable to cmd). figure 46. emmc4.4/4.41 timing usdhc input/card outputs sdx_cmd, sdx_datax (reference to clk) sd7 usdhc input setup time t isu 2.5 ? ns sd8 usdhc input hold time 4 t ih 1.5 ? ns 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 2 in normal (full) speed mode for sd/sdio card, clock frequency can be any value between 0 ? 25 mhz. in high-speed mode, clock frequency can be any value between 0 ? 50 mhz. 3 in normal (full) speed mode for mmc card, clock frequency can be any value between 0 ? 20 mhz. in high-speed mode, clock frequency can be any value between 0 ? 52 mhz. 4 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. table 57. emmc4.4/4.41 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (emmc4.4/4.41 ddr) f pp 052mhz sd1 clock frequency (sd3.0 ddr) f pp 050mhz usdhc output / card inputs sdx_cmd, sdx_datax (reference to clk) sd2 usdhc output delay t od 2.5 7.1 ns usdhc input / card outputs sdx_cmd, sdx_datax (reference to clk) sd3 usdhc input setup time t isu 2.6 ? ns sd4 usdhc input hold time t ih 1.5 ? ns table 56. sd/emmc4.3 interface timing specification (continued) id parameter symbols min max unit sd1 sd2 sd3 output from esdhcv3 to card input from card to esdhcv3 sdx_data[7:0] sdx_clk sd4 sd2 ...... ...... sdx_data[7:0]
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 84 freescale semiconductor electrical characteristics 4.11.4.3 sdr50/sdr104 ac timing figure 47 depicts the timing of sdr50/sdr104, and table 58 lists the sdr50/sdr104 timing characteristics. figure 47. sdr50/sdr104 timing table 58. sdr50/sdr104 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 4.8 ? ns sd2 clock low time t cl 0.3*t clk 0.7*t clk ns sd2 clock high time t ch 0.3*t clk 0.7*t clk ns usdhc output/card inputs sdx_cmd, sdx_ datax in sdr50 (reference to clk) sd4 usdhc output delay t od ?3 1 ns usdhc output/card inputs sdx_cmd, sdx_datax in sdr104 (reference to clk) sd5 usdhc output delay t od ?1.6 1 ns usdhc input/card outputs sdx_cmd, sdx_datax in sdr50 (reference to clk) sd6 usdhc input setup time t isu 2.5 ? ns sd7 usdhc input hold time t ih 1.5 ? ns usdhc input/card outputs sdx_cmd, sdx_datax in sdr104 (reference to clk) 1 1 data window in sdr100 mode is variable. sd8 card output data window t odw 0.5*t clk ?ns /utput&romu3$(#to#ard )nputfrom#ardtou3$(# 3#+ 3$ 3$ 3$ 3$ 3$ 3$ 3$ 3$
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 85 4.11.4.4 bus operation condition for 3.3 v and 1.8 v signaling 4.11.5 signaling level of sd/emmc4.3 and emmc 4.4/4.41 modes is 3.3 v. signaling level of sdr104/sdr50 mode is 1.8 v. the dc para meters for the nvcc _sd1, nvcc_sd2 and nvcc_sd3 supplies are identical to those shown in table 24, "gpio dc parameters," on page 40 . ethernet controller (enet) ac electrical specifications the following timing specs are defined at the chip i/o pin and must be tr anslated appropria tely to arrive at timing specs/constraint s for the physical interface. 4.11.5.1 enet mii mode timing this subsection describes mii receive, transmit, as ynchronous inputs, and serial management signal timings. 4.11.5.1.1 mii receive si gnal timing (enet_rx_data 3,2,1,0, enet_rx_en, enet_rx_er, and enet_rx_clk) the receiver functions correctly up to an enet_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. additionally, the processor clock frequency must exceed twice the enet_rx_clk frequency. figure 48 shows mii receiv e signal timings. table 59 describes the timing para meters (m1?m4) shown in the figure. figure 48. mii receive signal timing diagram table 59. mii receive signal timing id characteristic 1 min. max. unit m1 enet_rx_data3,2,1,0, en et_rx_en, enet_rx_er to enet_rx_clk setup 5? ns m2 enet_rx_clk to enet_rx_ data3,2,1,0, enet_rx_en, enet_rx_er hold 5? ns m3 enet_rx_clk pulse width high 35% 65% enet_rx_clk period m4 enet_rx_clk pulse width low 35% 65% enet_rx_clk period enet_rx_clk (input) enet_rx_data3,2,1,0 m3 m4 m1 m2 enet_rx_er enet_rx_en (inputs)
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 86 freescale semiconductor electrical characteristics 1 enet_rx_en, enet_rx_clk, and enet0_rxd0 have the same timing in 10 mbps 7-wire interface mode. 4.11.5.1.2 mii transmit signal timing (enet_tx_d ata3,2,1,0, enet_tx_en, enet_tx_er, and enet_tx_clk) the transmitter functions correctly up to an enet_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requi rement. additionally, the processo r clock frequency must exceed twice the enet_tx_clk frequency. figure 49 shows mii transm it signal timings. table 60 describes the timing pa rameters (m5?m8) shown in the figure. figure 49. mii transmit signal timing diagram 1 enet_tx_en, enet_tx_clk, and enet 0_txd0 have the same timing in 10-mbps 7-wire interface mode. 4.11.5.1.3 mii asynchronous inputs signal timing ( enet_crs and enet_col) figure 50 shows mii asynchronous input timings. table 61 describes the timing pa rameter (m9) shown in the figure. figure 50. mii async inputs timing diagram table 60. mii transmit signal timing id characteristic 1 min. max. unit m5 enet_tx_clk to enet_tx_ data3,2,1,0, enet_tx_en, enet_tx_er invalid 5? ns m6 enet_tx_clk to enet_tx_ data3,2,1,0, enet_tx_en, enet_tx_er valid ?20 ns m7 enet_tx_clk pulse width hi gh 35% 65% enet_tx_clk period m8 enet_tx_clk pulse width low 35% 65% enet_tx_clk period enet_tx_clk (input) enet_tx_data3,2,1,0 m7 m8 m5 m6 enet_tx_er enet_tx_en (outputs) enet_crs, enet_col m9
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 87 1 enet_col has the same timing in 10-mbit 7-wire interface mode. 4.11.5.1.4 mii serial management ch annel timing (enet_mdio and enet_mdc) the mdc frequency is designed to be equal to or less than 2.5 mhz to be compatible with the ieee 802.3 mii specification. however the enet can function correctly with a maximum mdc frequency of 15 mhz. figure 51 shows mii asynchronous input timings. table 62 describes the timing parameters (m10?m15) shown in the figure. figure 51. mii serial management channel timing diagram table 61. mii asynchronous inputs signal timing id characteristic min. max. unit m9 1 enet_crs to enet_col minimum pulse width 1.5 ? enet_tx_clk period table 62. mii serial management channel timing id characteristic min. max. unit m10 enet_mdc falling edge to enet_mdio output invalid (min. propagation delay) 0? ns m11 enet_mdc falling edge to enet_mdio output valid (max. propagation delay) ?5 ns m12 enet_mdio (input) to enet_mdc rising edge setup 18 ? ns m13 enet_mdio (input) to enet_mdc rising edge hold 0 ? ns m14 enet_mdc pulse width high 40% 60% enet_mdc period m15 enet_mdc pulse width low 40% 60% enet_mdc period enet_mdc (output) enet_mdio (output) m14 m15 m10 m11 m12 m13 enet_mdio (input)
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 88 freescale semiconductor electrical characteristics 4.11.5.2 rmii mode timing in rmii mode, enet_clk is used as the ref_cl k, which is a 50 mhz 50 ppm continuous reference clock. enet_rx_en is used as the enet_rx_en in rmii. other signals under rmii mode include enet_tx_en, enet_tx_data[1:0] , enet_rx_data[1:0] and enet_rx_er. figure 52 shows rmii mode timings. table 63 describes the timing parame ters (m16?m21) shown in the figure. figure 52. rmii mode signal timing diagram 4.11.5.3 signal switching specifications the following timing specifi cations meet the requirements for rgmii interfaces for a range of transceiver devices. table 63. rmii signal timing id characteristic min. max. unit m16 enet_clk pulse width high 35% 65% enet_clk period m17 enet_clk pulse width low 35% 65% enet_clk period m18 enet_clk to enet0_txd[1:0], enet_tx_data invalid 4 ? ns m19 enet_clk to enet0_txd[1:0 ], enet_tx_data valid ? 15 ns m20 enet_rx_datad[1:0], enet_rx_en (enet_rx_en), enet_rx_er to enet_clk setup 4? ns m21 enet_clk to enet_rx_datad[1:0] , enet_rx_en, enet_rx_er hold 2 ? ns enet_clk (input) enet_tx_en m16 m17 m18 m19 m20 m21 enet_rx_data[1:0] enet_tx_data (output) enet_rx_er enet_rx_en (input)
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 89 figure 53. rgmii transmit signal timing diagram original figure 54. rgmii receive signal timing diagram original table 64. rgmii signal switching specifications 1 1 the timings assume the following configuration: ddr_sel = (11)b dse (drive-strength) = (111)b symbol description min max unit t cyc 2 2 for 10 mbps and 100 mbps, t cyc will scale to 400 ns 40 ns and 40 ns 4 ns respectively. clock cycle duration 7.2 8.8 ns t skewt 3 3 for all versions of rgmii prior to 2.0; this implies that pc board design will require clocks to be routed such that an additio nal trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. for 10/100, the max value is unspecified. data to clock output skew at transmitter -500 500 ps t skewr 3 data to clock input skew at receiver 1 2.6 ns duty_g 4 4 duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not vi olated and stretc hing occurs for no more than three t cyc of the lowest speed transitioned between. duty cycle for gigabit 45 55 % duty_t 4 duty cycle for 10/100t 40 60 % tr/tf rise/fall time (20?80%) ? 0.75 ns 2'-))?48#attransmitter 2'-))?48$nnto 2'-))?48?#4, 2'-))?48#atreceiver 4skew4 48%. 48%22 4skew2 2'-))?28#attransmitter 2'-))?28$nnto 2'-))?28?#4, 2'-))?28#atreceiver 4skew4 28$6 28%22 4skew2
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 90 freescale semiconductor electrical characteristics figure 55. rgmii receive signal timing diagram with internal delay 4.11.6 flexible controller area ne twork (flexcan) ac electrical specifications the flexible controller area network (flexcan) module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. the proces sor has two can modules available for systems design. tx a nd rx ports for both modules are multiplexed with other i/o pins. see the iomuxc chapter of the i.mx 6solo/6duallite refe rence manual (imx6sdlrm) to see which pins expose tx and rx pins; these ports are name d flexcan_tx and flex can_rx, respectively. 4.11.7 hdmi module timing parameters 4.11.7.1 latencies and timing information power-up time (time between tx_p wron assertion and tx_ready a ssertion) for the hdmi 3d tx phy while operating with the slowest input re ference clock supported (13.5 mhz) is 3.35 ms. power-up time for the hdmi 3d tx phy while operating with the fastes t input referenc e clock supported (340 mhz) is 133 ? s. 4.11.7.2 electrical characteristics the table below provides electrical characteristics for the hdmi 3d tx phy. the following three figures illustrate various definitions and measurement conditions sp ecified in the table below. 2'-))?28#sourceofdata 2'-))?28$nnto 2'-))?28?#4, 2'-))?28#atreceiver )nternaldelay 4setup4 4hold4 4setup2 4hold2 28$6 28%22
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 91 figure 56. driver me asuring conditions figure 57. driver definitions figure 58. source termination table 65. electrical characteristics symbol parameter condition min typ max unit operating conditions for hdmi avddtmds termination supply voltage ? 3.15 3.3 3.45 v r t termination resistance ? 45 50 55 ? ($-)?48?$!4!;=?. ($-)?48?#,+?. ($-)?48?$!4!;=?0 ($-)?48?#,+?0 2 4%2- 2 4%2-
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 92 freescale semiconductor electrical characteristics 4.11.8 switching characteristics table 66 describes switching characteristics for the hdmi 3d tx phy. figure 59 to figure 63 illustrate various parameters specified in table. note all dynamic parameters related to th e tmds line drivers? performance imply the use of assembly guidelines. tmds drivers dc specifications v off single-ended standby voltage rt = 50 ? for measurement conditions and definitions, see the first two figures above. compliance point tp1 as defined in the hdmi specification, version 1.3a, section 4.2.4. avddtmds 10 mv mv v swing single-ended output swing voltage 400 ? 600 mv v h single-ended output high voltage for definition, see the second figure above if attached sink supports tmdsclk < or = 165 mhz avddtmds 10 mv mv if attached sink supports tmdsclk > 165 mhz avddtmds - 200 mv ? avddtmds + 10 mv mv v l single-ended output low voltage for definition, see the second figure above if attached sink supports tmdsclk < or = 165 mhz avddtmds - 600 mv ? avddtmds - 400mv mv if attached sink supports tmdsclk > 165 mhz avddtmds - 700 mv ? avddtmds - 400 mv mv r term differential source termination load (inside hdmi 3d tx phy) although the hdmi 3d tx phy includes differential source termination, the user-defined value is set for each single line (for illustration, see the third figure above). note: r term can also be configured to be open and not present on tmds channels. ?50?200 ? hot plug detect specifications hpd vh hot plug detect high range ? 2.0 ? 5.3 v vhpd vl hot plug detect low range ? 0 ? 0.8 v hpd z hot plug detect input impedance ?10??k ? hpd t hot plug detect time delay ? ? ? 100 s table 65. electrical characteristics (continued) symbol parameter condition min typ max unit
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 93 figure 59. tmds clock signal definitions figure 60. eye diagram mask definition for hdmi driver signal specification at tp1 figure 61. intra-pair skew definition figure 62. inter-pair skew definition 0 t #0, t #0( p hdmi_tx_clk 4-$3$!4!0 avddtmds 4-$3$!4!. 6 37).' typ t 3+p )ntra pairskew 4-$3$!4!;= 4-$3$!4!;= 4-$3$!4!;= b;n = b;n = b;n = b;n= b;n= b;n = b;n = b;n = b;n= b;n= b;n = b;n = b;n = b;n= b;n= t 3+pp )nter pairskew 0reviouscycle;n = #urrentcycle;n=
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 94 freescale semiconductor electrical characteristics figure 63. tmds output signals rise and fall time definition table 66. switching characteristics symbol parameter conditions min typ max unit tmds drivers specifications ? maximum serial data rate ? ? ? 3.4 gbps f tmdsclk tmdsclk frequency on tmdsclkp/n outputs 25 ? 340 mhz p tmdsclk tmdsclk period rl = 50 ? see figure 59. 2.94 ? 40 ns t cdc tmdsclk duty cycle t cdc = t cph / p tmdsclk rl = 50 ? see figure 59 . 40 50 60 % t cph tmdsclk high time rl = 50 ? see figure 59. 456ui 1 1 ui means tmds clock unit. t cpl tmdsclk low time rl = 50 ? see figure 59. 456ui 1 ? tmdsclk jitter 2 2 relative to ideal recovery clock, as specified in the hdmi specification, version 1.4a, section 4.2.3. rl = 50 ? ? ? 0.25 ui 1 t sk(p) intra-pair (pulse) skew rl = 50 ? see figure 61. ? ? 0.15 ui 1 t sk(pp) inter-pair skew rl = 50 ? see figure 62. ??1ui 1 t r differential output signal rise time 20?80% rl = 50 ? see figure 63. 75 ? 0.4 ui ps t f differential output signal fall time 20?80% rl = 50 ? see figure 63 . 75 ? 0.4 ui ps ? differential signal overshoot referred to 2x v swing ??15% ? differential signal undershoot referred to 2x v swing ??25%
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 95 4.11.9 i 2 c module timing parameters this section describes the timing parameters of the i 2 c module. figure 64 depicts the timing of i 2 c module, and table 67 lists the i 2 c module timing characteristics. figure 64. i 2 c bus timing table 67. i 2 c module timing parameters id parameter standard mode fast mode unit min max min max ic1 i2cx_scl cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for i2cx_sda signal to bridge the undefined region of the falli ng edge of i2cx_scl. 3.45 2 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic5) of the i2cx_scl signal. 0 1 0.9 2 s ic5 high period of i2cx_scl clock 4.0 ? 0.6 ? s ic6 low period of the i2cx_scl clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 3 a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement of set-up time (id no ic7) of 250 ns must be met. this automatically is the case if t he device does not stretch the low period of the i2cx_scl signal. if such a device does stretch the low period of the i2cx_scl si gnal, it must output the next data bit to the i2cx_sda line max_rise_time (ic9) + data_setup_tim e (ic7) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the i2cx_scl line is released. ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both i2cx_sda and i2cx_scl signals ? 1000 20 + 0.1c b 4 4 c b = total capacitance of one bus line in pf. 300 ns ic11 fall time of both i2cx_sda and i2cx_scl signals ? 300 20 + 0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) ? 400 ? 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2cx_sda i2cx_scl ic1
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 96 freescale semiconductor electrical characteristics 4.11.10 image processing unit (ipu) module parameters the purpose of the ipu is to provide comprehensive su pport for the flow of data from an image sensor and/or to a display device. this support covers all as pects of these activities: ? connectivity to relevant devices ? cameras, displays, graphics accelerators, and tv encoders. ? related image processing and ma nipulation: sensor image signa l processing, display processing, image conversions, and ot her related functions. ? synchronization and control cap abilities, such as avoida nce of tearing artifacts. 4.11.10.1 ipu sensor interface signal mapping the ipu supports a number of sensor input formats. table 68 defines the mapping of the sensor interface pins used for various supported interface formats. table 68. camera input signal cross reference, format, and bits per cycle signal name 1 rgb565 8 bits 2 cycles rgb565 2 8 bits 3 cycles rgb666 3 8 bits 3 cycles rgb888 8 bits 3 cycles ycbcr 4 8 bits 2 cycles rgb565 5 16 bits 2 cycles ycbcr 6 16 bits 1 cycle ycbcr 7 16 bits 1 cycle ycbcr 8 20 bits 1 cycle ipux_csix_ data00 ???????0c[0] ipux_csix_ data01 ???????0c[1] ipux_csix_ data02 ? ? ? ? ? ? ? c[0] c[2] ipux_csix_ data03 ? ? ? ? ? ? ? c[1] c[3] ipux_csix_ data04 ? ? ? ? ? b[0] c[0] c[2] c[4] ipux_csix_ data05 ? ? ? ? ? b[1] c[1] c[3] c[5] ipux_csix_ data06 ? ? ? ? ? b[2] c[2] c[4] c[6] ipux_csix_ data07 ? ? ? ? ? b[3] c[3] c[5] c[7] ipux_csix_ data08 ? ? ? ? ? b[4] c[4] c[6] c[8] ipux_csix_ data09 ? ? ? ? ? g[0] c[5] c[7] c[9] ipux_csix_ data10 ? ? ? ? ? g[1] c[6] 0 y[0] ipux_csix_ data11 ? ? ? ? ? g[2] c[7] 0 y[1] ipux_csix_ data12 b[0], g[3] r[2],g[4],b[2] r/g/b[4] r/g/b[0] y/c[0] g[3] y[0] y[0] y[2]
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 97 4.11.10.2 sensor interface timings there are three camera timi ng modes supported by the ipu. 4.11.10.2.1 bt.656 and bt.1120 video mode smart camera sensors, which include imaging processing, usua lly support video mode transfer. they use an embedded timing syntax to replace the ipu x_csix_vsync and ipux_csix_hsync signals. the timing syntax is defined by the bt.656/bt.1120 standards. this operation mode follows the recommendations of itu bt.656/ itu bt.1120 specifications. the only control signal used is ip ux_csix_pix_clk. start-of-f rame and active-line signa ls are embedded in the data stream. an active line starts with a sav code and ends with a eav code. in some cases, digital blanking is inserted in between eav and sav code . the csi decodes and filte rs out the timing-coding from the data stream, thus rec overing ipux_csix_vsync and ipux_c six_hsync signals for internal use. on bt.656 one component per cycle is rece ived over the ipux_csix_data_en bus. on bt.1120 two components per cycle are receive d over the ipux_csix_data_en bus. ipux_csix_ data13 b[1], g[4] r[3],g[5],b[3] r/g/b[5] r/g/b[1] y/c[1] g[4] y[1] y[1] y[3] ipux_csix_ data14 b[2], g[5] r[4],g[0],b[4] r/g/b[0] r/g/b[2] y/c[2] g[5] y[2] y[2] y[4] ipux_csix_ data15 b[3], r[0] r[0],g[1],b[0] r/g/b[1] r/g/b[3] y/c[3] r[0] y[3] y[3] y[5] ipux_csix_ data16 b[4], r[1] r[1],g[2],b[1] r/g/b[2] r/g/b[4] y/c[4] r[1] y[4] y[4] y[6] ipux_csix_ data17 g[0], r[2] r[2],g[3],b[2] r/g/b[3] r/g/b[5] y/c[5] r[2] y[5] y[5] y[7] ipux_csix_ data18 g[1], r[3] r[3],g[4],b[3] r/g/b[4] r/g/b[6] y/c[6] r[3] y[6] y[6] y[8] ipux_csix_ data19 g[2], r[4] r[4],g[5],b[4] r/g/b[5] r/g/b[7] y/c[7] r[4] y[7] y[7] y[9] 1 ipux_csix stands for ipux_csi0 or ipux_csi1 2 the msb bits are duplicated on lsb bits implementing color extension 3 the two msb bits are duplicated on lsb bits implementing color extension 4 ycbcr, 8 bits?supported within the bt.656 prot ocol (sync embedded within the data stream). 5 rgb 16 bits? supported in two ways: (1) as a ?generic data ? input, with no on-the-fly processing; (2) with on-the-fly processing, but only under some rest rictions on the control protocol. 6 ycbcr 16 bits? supported as a ?generic-d ata? input, with no on- the-fly processing. 7 ycbcr 16 bits? supported as a sub-case of the ycbcr, 20 bits, under the same conditions (bt.1120 protocol). 8 ycbcr, 20 bits, supported only within the bt.11 20 protocol (syncs embedded within the data stream). table 68. camera input signal cross referenc e, format, and bits per cycle (continued) signal name 1 rgb565 8 bits 2 cycles rgb565 2 8 bits 3 cycles rgb666 3 8 bits 3 cycles rgb888 8 bits 3 cycles ycbcr 4 8 bits 2 cycles rgb565 5 16 bits 2 cycles ycbcr 6 16 bits 1 cycle ycbcr 7 16 bits 1 cycle ycbcr 8 20 bits 1 cycle
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 98 freescale semiconductor electrical characteristics 4.11.10.2.2 gated clock mode the ipux_csix_vsync, ipux_csi x_hsync, and ipux_csix_pix_clk signals are used in this mode. see figure 65 . figure 65. gated clock mode timing diagram a frame starts with a rising edge on ipux_csix_vsync (all the timi ngs correspond to straight polarity of the corresponding signals). then ipux_csix_hsync goes to high and hold for the entire line. pixel clock is valid as long as ipux_csix_hsync is high. data is latched at the rising edge of the valid pixel clocks. ipux_csix_hsync goes to low at the end of line. pixel clocks then become invalid and the csi stops receiving data from the stream. for the next line, the ipux_csix_hsync timing repeats. for the next frame, the ipux_csix_vsync timing repeats. 4.11.10.2.3 non-gated clock mode the timing is the same as the ga ted-clock mode (described in section 4.11.10.2.2, ?gated clock mode ,? ) except for the ipux_csix_hsync si gnal, which is not used (see figure 66 ). all incoming pixel clocks are valid and cause data to be latched into the i nput fifo. the ipux_csix_pix _clk signal is inactive (states low) until valid da ta is going to be tr ansmitted over the bus. figure 66. non-gated clock mode timing diagram the timing described in figure 66 is that of a typical sensor. some other sensors may have a slightly different timing. the csi can be programmed to support rising/fal ling-edge triggered ipux_csix_vsync; active-high/low ipux_csix_h sync; and rising/fall ing-edge triggered ipux_csix_pix_clk. )05x?#3)x??0)8?#,+ )05x?#3)x??(39.# )05x?#3)x??639.# 3tartof&rame nthframe )05x?#3)x??$!4!xx invalid stbyte stbyte invalid !ctive,ine nthframe ipux_csix_vsync ipux_csix_pix_clk ipux_csix_data_en[19:0] invalid 1st byte n+1th frame invalid 1st byte nth frame start of frame
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 99 4.11.10.3 electrical characteristics figure 67 depicts the sensor interfac e timing. ipux_csix_pix_clk si gnal described here is not generated by the ipu. table 69 lists the sensor interface timing characteristics. figure 67. sensor interface timing diagram 4.11.10.4 ipu display interface signal mapping the ipu supports a number of di splay output video formats. table 70 defines the mapping of the display interface pins used during variou s supported video interface formats. table 69. sensor interface timing characteristics id parameter symbol min max unit ip1 sensor output (pixel) clock frequency fpck 0.01 180 mhz ip2 data and control setup time tsu 2 ? ns ip3 data and control holdup time thd 1 ? ns table 70. video signal cross-reference i.mx 6solo/6duallite lcd comment 1,2 port name (x=0, 1) rgb, signal name (general) rgb/tv signal allocation (example) 16-bit rgb 18-bit rgb 24 bit rgb 8-bit ycrcb 3 16-bit ycrcb 20-bit ycrcb ipux_dispx_dat00 dat[0] b[0] b[0] b[0] y/c[0] c[0] c[0] ? ipux_dispx_dat01 dat[1] b[1] b[1] b[1] y/c[1] c[1] c[1] ? ipux_dispx_dat02 dat[2] b[2] b[2] b[2] y/c[2] c[2] c[2] ? ipux_dispx_dat03 dat[3] b[3] b[3] b[3] y/c[3] c[3] c[3] ? ipux_dispx_dat04 dat[4] b[4] b[4] b[4] y/c[4] c[4] c[4] ? ipux_dispx_dat05 dat[5] g[0] b[5] b[5] y/c[5] c[5] c[5] ? ipux_dispx_dat06 dat[6] g[1] g[0] b[6] y/c[6] c[6] c[6] ? ip3 ipux_csix_data_en, ipux_csix_vsync, ip2 1/ip1 ipux_csix_pix_clk (sensor output) ipux_csix_hsync
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 100 freescale semiconductor electrical characteristics ipux_dispx_dat07 dat[7] g[2] g[1] b[7] y/c[7] c[7] c[7] ? ipux_dispx_dat08 dat[8] g[3] g[2] g[0] ? y[0] c[8] ? ipux_dispx_dat09 dat[9] g[4] g[3] g[1] ? y[1] c[9] ? ipux_dispx_dat10 dat[10] g[5] g[4] g[2] ? y[2] y[0] ? ipux_dispx_dat11 dat[11] r[0] g[5] g[3] ? y[3] y[1] ? ipux_dispx_dat12 dat[12] r[1] r[0] g[4] ? y[4] y[2] ? ipux_dispx_dat13 dat[13] r[2] r[1] g[5] ? y[5] y[3] ? ipux_dispx_dat14 dat[14] r[3] r[2] g[6] ? y[6] y[4] ? ipux_dispx_dat15 dat[15] r[4] r[3] g[7] ? y[7] y[5] ? ipux_dispx_dat16 dat[16] ? r[4] r[0] ? ? y[6] ? ipux_dispx_dat17 dat[17] ? r[5] r[1] ? ? y[7] ? ipux_dispx_dat18 dat[18] ? ? r[2] ? ? y[8] ? ipux_dispx_dat19 dat[19] ? ? r[3] ? ? y[9] ? ipux_dispx_dat20 dat[20] ? ? r[4] ? ? ? ? ipux_dispx_dat21 dat[21] ? ? r[5] ? ? ? ? ipux_dispx_dat22 dat[22] ? ? r[6] ? ? ? ? ipux_dispx_dat23 dat[23] ? ? r[7] ? ? ? ? dix_disp_clk pixclk ? dix_pin1 ? may be required for anti-tearing dix_pin2 hsync ? dix_pin3 vsync vsync out table 70. video signal cross-reference (continued) i.mx 6solo/6duallite lcd comment 1,2 port name (x=0, 1) rgb, signal name (general) rgb/tv signal allocation (example) 16-bit rgb 18-bit rgb 24 bit rgb 8-bit ycrcb 3 16-bit ycrcb 20-bit ycrcb
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 101 note table 70 provides information for both the disp0 and disp1 ports. however, disp1 port has redu ced pinout depending on iomuxc configuration and therefore may not support all the above configurations. see the iomuxc table for details. 4.11.10.5 ipu display interface timing the ipu display interface supports two kinds of displa y accesses: synchronous and asynchronous. there are two groups of external interface pins to provide synchronous a nd asynchronous controls accordantly. dix_pin4 ? additional frame/row synchronous signals with programmable timing dix_pin5 ? dix_pin6 ? dix_pin7 ? dix_pin8 ? dix_d0_cs ? ? dix_d1_cs ? alternate mode of pwm output for contrast or brightness control dix_pin11 ? ? dix_pin12 ? ? dix_pin13 ? register select signal dix_pin14 ? optional rs2 dix_pin15 drdy/dv data validation/blank, data enable dix_pin16 ? additional data synchronous signals with programmable features/timing dix_pin17 q 1 signal mapping (both data and control/synchroniza tion) is flexible. the table provides examples. 2 restrictions for ports ipux_dispx_dat00 through ipux_dispx_dat23 are as follows: ? a maximum of three continuous groups of bits can be indepen dently mapped to the external bus. groups must not overlap. ? the bit order is expressed in each of the bit groups, for example, b[0] = least significant blue pixel bit. 3 this mode works in compliance with recommendation itu-r bt.656 . the timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. only vi deo data is supported, transm ission of non-video related data during blanking intervals is not supported. table 70. video signal cross-reference (continued) i.mx 6solo/6duallite lcd comment 1,2 port name (x=0, 1) rgb, signal name (general) rgb/tv signal allocation (example) 16-bit rgb 18-bit rgb 24 bit rgb 8-bit ycrcb 3 16-bit ycrcb 20-bit ycrcb
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 102 freescale semiconductor electrical characteristics 4.11.10.5.1 synchronous controls the synchronous control changes its valu e as a function of a sy stem or of an extern al clock. this control has a permanent period a nd a permanent wave form. there are special physical outputs to provide synchronous controls: ? the ipp_disp_clk is a dedicated ba se synchronous signal that is us ed to generate a base display (component, pixel) clock for a display. ? the ipux_dix_pin01?ipux_dix_pin 07 are general purpose synchronous pins, that can be used to provide hsync, vsync, drdy or any other independent signal to a display. the ipu has a system of intern al binding counters for internal events (such as, hsync/vsync) calculation. the internal event (local start point) is synchronized with in ternal di_clk. a suitable control starts from the local start point with predefined up and down values to calculate control?s changing points with half di_clk resolution. a full description of the counters system can be found in the ipu chapter of the i.mx 6solo/6duallite reference manual (imx6sdlrm) . 4.11.10.5.2 asynchronous controls the asynchronous contro l is a data-oriented signal th at changes its value with an output data according to additional internal flags coming with the data. there are special physical outputs to pr ovide asynchronous controls, as follows: ? the ipux_dix_d0_cs and ipux_di x_d1_cs pins are dedicated to pr ovide chip select signals to two displays. ? the ipux_dix_pin11?ipux_dix_pin17 are ge neral purpose asynchronous pins, that can be used to provide wr. rd, rs or any ot her data oriented signal to display. note the ipu has independent signal ge nerators for asynchronous signals toggling. when a di decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. the signals generators calculate predefined up and down values to change pins states with half di_clk resolution. 4.11.10.6 synchronous interfaces to st andard active matr ix tft lcd panels 4.11.10.6.1 ipu display operating signals the ipu uses four control signals and data to operate a standard synchronous interface: ? ipp_disp_clk?clock to display ? hsync?horizontal synchronization ? vsync?vertical synchronization ? drdy?active data all synchronous display controls are generated on the base of an internally generated ?local start point?. the synchronous display controls can be placed on ti me axis with di?s offset, up and down parameters.
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 103 the display access can be whole number of di cloc k (tdiclk) only. the ipp_data can not be moved relative to the local start point. the data bus of the synchronous interface is output direction only. 4.11.10.6.2 lcd interfac e functional description figure 68 depicts the lcd interface timing for a generic act ive matrix color tft panel. in this figure, signals are shown with negative pol arity. the sequence of events for active matrix interface timing is: ? di_clk internal di clock is used for calculation of other controls. ? ipp_disp_clk latches data into the panel on its negative edge (when positive polarity is selected). in active mode, ipp_disp_clk runs continuously. ? hsync causes the panel to start a new line. (u sually ipux_dix_pin02 is used as hsync.) ? vsync causes the panel to start a new frame. it always encompasses at least one hsync pulse. (usually ipux_dix_pin 03 is used as vsync.) ? drdy acts like an output enable signal to the cr t display. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. (drdy can be used either synchronous or asynchronous generic purpose pin as well.) figure 68. interface timing diagram for tft (active matrix) panels 4.11.10.6.3 tft panel sync pulse timing diagrams figure 69 depicts the horizontal timing (tim ing of one line), including bot h the horizontal sync pulse and the data. all the parameters shown in the figur e are programmable. all controls are started by 123 m m-1 hsync vsync hsync line 1 line 2 line 3 line 4 line n-1 line n drdy ipp_disp_clk ipp_data
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 104 freescale semiconductor electrical characteristics corresponding internal events?local start points. the timing diagrams correspond to inverse polarity of the ipp_disp_clk signal and active-low polarity of the hsync, vsync, and drdy signals. figure 69. tft panels timing di agram?horizontal sync pulse figure 70 depicts the vertical timing (t iming of one frame). all parame ters shown in the figure are programmable. figure 70. tft panels timing diagram?vertical sync pulse di clock vsync drdy d0 d1 ip5o ip13o ip9o ip8o ip8 ip9 dn ip10 ip7 ip5 ip6 local start point local start point local start point ipp_disp_ clk ipp_data hsync ip14 vsync hsync drdy start of frame end of frame ip12 ip15 ip13 ip11
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 105 table 71 shows timing characteristic s of signals presented in figure 69 and figure 70 . table 71. synchronous display interface timing characteristics (pixel level) id parameter symbol value description unit ip5 display interface clock period tdicp ( 1 ) display interface clock. ipp_disp_clk ns ip6 display pixel clock period tdpcp disp_clk_per_pixel ? tdicp time of translation of one pixel to display, disp_clk_per_pixel?number of pixel components in one pixel (1.n). the disp_clk_per_pixel is virtual parameter to define display pixel clock period. the disp_clk_per_pixel is received by dc/di one access division to n components. ns ip7 screen width time tsw (screen_width) ? tdicp screen_width?screen width in, interface clocks. horizontal blanking included. the screen_width should be built by suitable di?s counter 2 . ns ip8 hsync width time thsw (hsync_width) hsync_width?hsync width in di_clk with 0.5 di_clk resolution. defined by di?s counter. ns ip9 horizontal blank interval 1 thbi1 bgxp ? tdicp bgxp?width of a horizontal blanking before a first active data in a line (in interface clocks). the bgxp should be built by suitable di?s counter. ns ip10 horizontal blank interval 2 thbi2 (screen_width - bgxp - fw) ? tdicp width a horizontal blanking after a last active data in a line (in interface clocks) fw?with of active line in interface clocks. the fw should be built by suitable di?s counter. ns ip12 screen height tsh (screen_height) ? tsw screen_height? screen height in lines with blanking. the screen_height is a distance between 2 vsyncs. the screen_height should be built by suitable di?s counter. ns ip13 vsync width tvsw vsync_width vsync_ width?vsync width in di_clk with 0.5 di_clk resolution. defined by di?s counter ns ip14 vertical blank interval 1 tvbi1 bgyp ? tsw bgyp?width of first vertical blanking interval in line. the bgyp should be built by suitable di?s counter. ns ip15 vertical blank interval 2 tvbi2 (screen_height - bgyp - fh) ? tsw width of second vertical blanking interval in line. the fh should be built by suitable di?s counter. ns ip5o offset of ipp_disp_cl k todicp disp_clk_offset ?? tdiclk disp_clk_offset?offset of ipp_disp_clk edges from local start point, in di_clk ? 2 (0.5 di_clk resolution). defined by disp_clk counter ns
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 106 freescale semiconductor electrical characteristics the maximum accuracy of up/down edge of controls is: the maximum accuracy of up/down edge of ipp_data is: the disp_clk_period, di_clk _period parameters are progr ammed through the registers. ip13o offset of vsync tovs vsync_offset ?? tdiclk vsync_offset?offset of vsync edges from a local start point, when a vsync should be active, in di_clk ? 2 (0.5 di_clk resolution). the vsync_offset should be built by suitable di?s counter. ns ip8o offset of hsync tohs hsync_offset ? tdiclk hsync_offset?offset of hsync edges from a local start point, when a hsync should be active, in di_clk ? 2 (0.5 di_clk resolution). the hsync_offset should be built by suitable di?s counter. ns ip9o offset of drdy todrdy drdy_offset ? tdiclk drdy_offset?offset of drdy edges from a suitable local start point, when a corresponding data has been set on the bus, in di_clk ? 2 (0.5 di_clk resolution). the drdy_offset should be built by suitable di?s counter. ns 1 display interface clock period immediate value. disp_clk_period?number of di_clk per o ne tdicp. resolution 1/16 of di_clk. di_clk_period?relation of between programing cl ock frequency and current system clock frequency display interface clock period average value. 2 di?s counter can define offset, period an d up/down characteristic of output signal according to programed parameters of the counter. same of parameters in the table are not defined by di?s registers directly (by name), but can be generated by corresponding di?s counter. the screen_width is an input value for di?s hsync generation counter. the distance between hsyncs is a screen_width. table 71. synchronous display interface timing characteristics (pixel level) (continued) id parameter symbol value description unit tdicp t diclk disp_clk_period di_clk_period ---------------------------------------------------- ? = accuracy 0.5 t diclk ? ?? 0.62ns ? = accuracy t diclk 0.62ns ? =
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 107 figure 71 depicts the synchronous display interface ti ming for access level. the disp_clk_down and disp_clk_up parameters are set through the register. table 72 lists the synchronous display interface timing characteristics. figure 71. synchronous display interface timing diagram?access level table 72. synchronous display interfa ce timing characteristics (access level) id parameter symbol min typ 1 1 the exact conditions have not been finalized, but will likely matc h the current customer requirement for their specific display . these conditions may be chip specific. max unit ip16 display interface clock low time tckl tdicd-tdicu-1.24 tdicd 2 -tdicu 3 2 display interface clock down time 3 display interface clock up time where ceil(x) rounds the elements of x to the nearest integers towards infinity. tdicd-tdicu+1.24 ns ip17 display interface clock high time tckh tdicp-tdicd+tdicu-1.24 tdicp-td icd+tdicu tdicp-tdicd+tdicu+1.2 ns ip18 data setup time tdsu tdicd-1.24 tdicu ? ns ip19 data holdup time tdhd tdicp-tdicd-1.24 tdicp-tdicu ? ns ip20o control signals offset times (defines for each pin) tocsu tocsu-1.24 tocsu tocsu+1.24 ns ip20 control signals setup time to display interface clock (defines for each pin) tcsu tdicd-1.24-tocsu%tdicp tdicu ? ns ip19 ip18 ip20 vsync ip17 ip16 drdy hsync other controls ip20o local start point tdicd tdicu ipp_disp_clk ipp_data tdicd 1 2 -- -t diclk ceil ? 2 disp_clk_down ? di_clk_period ----------------------------------------------------------- ?? ?? = tdicu 1 2 -- -t diclk ceil ? 2 disp_clk_up ? di_clk_period ------------------------------------------------ ?? ?? =
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 108 freescale semiconductor electrical characteristics 4.11.11 lvds display bridge (ldb) module parameters the lvds interface complies with tia/eia 644-a standard. for more details, see tia/eia standard 644-a, ?electrical ch aracteristics of low voltage differenti al signaling (lvds) in terface circuits?. 4.11.12 mipi d-phy timing parameters this section describes mipi d-ph y electrical specificati ons, compliant with mipi csi-2 version 1.0, d-phy specification rev. 1.0 (for mipi sensor por t x2 lanes) and mipi dsi version 1.01, and d-phy specification rev. 1.0 (and also dpi version 2.0, dbi ve rsion 2.0, dsc version 1.0a at protocol layer) (for mipi display port x2 lanes). 4.11.12.1 electrical and timing information table 73. lvds display bridge (ldb) electrical specification parameter symbol test condition min max units differential voltage output voltage v od 100 ? differential load 250 450 mv output voltage high voh 100 ? differential load (0 v diff?output high voltage static) 1.25 1.6 mv output voltage low vol 100 ? differential load (0 v diff?output low voltage static) 0.9 1.25 mv offset static voltage v os two 49.9 ? resistors in series between n-p terminal, with output in either zero or one state, the voltage measured between the 2 resistors. 1.15 1.375 v vos differential v osdiff difference in v os between a one and a zero state -50 50 mv output short circuited to gnd isa isb with the output common shorted to gnd -24 24 ma vt full load test vtload 100 ? differential load with a 3.74 k ? load between gnd and io supply voltage 247 454 mv table 74. electrical and timing information symbol parameters test conditions min typ max unit input dc specifications - apply to dsi_clk_ p/dsi_clk_n and dsi_data_p/dsi_data_n inputs v i input signal voltage range transient voltage range is limited from -300 mv to 1600 mv -50 ? 1350 mv v leak input leakage current vgndsh(min) = vi = vgndsh(max) + voh(absmax) lane module in lp receive mode -10 ? 10 ma v gndsh ground shift ? -50 ? 50 mv v oh(absmax) maximum transient output voltage level ???1.45v
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 109 t voh(absmax) maximum transient time above voh(absmax) ???20ns hs line drivers dc specifications |v od | hs transmit differential output voltage magnitude 80 ?? = rl< = 125 ? 140 200 270 mv ? |v od | change in differential output voltage magnitude between logic states 80 ?? = rl< = 125 ? ??10mv v cmtx steady-state common-mode output voltage. 80 ?? = rl< = 125 ? 150 200 250 mv ? v cmtx (1,0) changes in steady-state common-mode output voltage between logic states 80 ?? = rl< = 125 ? ?? 5mv v ohhs hs output high voltage 80 ?? = rl< = 125 ? ??360mv z os single-ended output impedance. ?405062.5 ? ? z os single-ended output impedance mismatch. ???10% lp line drivers dc specifications v ol output low-level se voltage ? -50 50 mv v oh output high-level se voltage ? 1.1 1.2 1.3 v z olp single-ended output impedance. ? 110 ? ? ? ? z olp(01-10) single-ended output impedance mismatch driving opposite level ???20% ? z olp(0-11) single-ended output impedance mismatch driving same level ???5% hs line receiver dc specifications v idth differential input high voltage threshold ???70mv v idtl differential input low voltage threshold ?-70? mv v ihhs single ended input high voltage ??460mv v ilhs single ended input low voltage ?-40? mv v cmrxdc input common mode voltage ? 70 ? 330 mv table 74. electrical and timing information (continued) symbol parameters test conditions min typ max unit
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 110 freescale semiconductor electrical characteristics 4.11.12.2 mipi d-phy signaling levels the signal levels are different for differential hs m ode and single-ended lp mode. figure 72 shows both the hs and lp signal levels on the left and right sides, respectivel y. the hs signaling levels are below the lp low-level input threshold such that lp receiver always detects low on hs signals. figure 72. d-phy signaling levels z id differential input impedance ? 80 ? 125 ? lp line receiver dc specifications v il input low voltage ? ? ? 550 mv v ih input high voltage ? 920 ? mv v hyst input hysteresis ? 25 ? mv contention line rece iver dc specifications v ilf input low fault threshold ? 200 ? 450 mv table 74. electrical and timing information (continued) symbol parameters test conditions min typ max unit hs vout range hs vcm range max v od min v od v cmtx,min v olhs v cmtx,max v ohhs lp v il lp v ol lp v ih v oh,max v oh,min v ih v il lp threshold region v gndsh,ma x v gndsh,min gnd lp v ol hs differential signaling lp single-ended signaling
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 111 4.11.12.3 mipi hs line driver characteristics figure 73. ideal single-ended and re sulting differential hs signals 4.11.12.4 possible ? vcmtx and ? vod distortions of the single-ended hs signals figure 74. possible ? vcmtx and ? vod distortions of the single-ended hs signals 4.11.12.5 mipi d-phy switching characteristics table 75. electrical and timing information symbol parameters test conditions min typ max unit hs line drivers ac specifications ? maximum serial data rate (forward direction) on datap/n outputs. 80 ? <= rl <= 125 ? 80 ? 1000 mbps v od(1) v od(1) v od(0) v od(0) v od = v dp - v dn v cmtx = (v dp + v dn )/2 0v (differential) v dn v dp ideal single-ended high speed signals ideal differential high speed signals ? v od(0) v od (1) v od /2 v od /2 v od (se hs signals) static v cmt x (se hs signals) dynamic v cmt x (se hs signals) v dn v cm tx v dp v dn v cmtx v dp v dn v cm tx v dp v od(0) ? ? ? ? ?
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 112 freescale semiconductor electrical characteristics f ddrclk ddr clk frequency on datap/n outputs. 40 ? 500 mhz p ddrclk ddr clk period 80 ?? = rl< = 125 ? 2 ? 25 ns t cdc ddr clk duty cycle t cdc ???? t cph ??? p ddrclk ?50? % t cph ddr clk high time ? ? 1 ? ui t cpl ddr clk low time ? ? 1 ? ui ? ddr clk / data jitter ? ? 75 ? ps pk?pk t skew[pn] intra-pair (pulse) skew ? ? 0.075 ? ui t skew[tx] data to clock skew ? 0.350 ? 0.650 ui t setup[rx] data to clock receiver setup time ? 0.15 ? ? ui t hold[rx] clock to data receiver hold time ? 0.15 ? ? ui t r differential output signal rise time 20% to 80%, rl = 50 ? 150 ? 0.3ui ps t f differential output signal fall time 20% to 80%, rl = 50 ? 150 ? 0.3ui ps ? v cmtx(hf) common level variation above 450 mhz 80 ? <= rl< = 125 ? ??15mv rms ? v cmtx(lf) common level variation between 50 mhz and 450 mhz. 80 ? <= rl< = 125 ? ??25mv p lp line drivers ac specifications t rlp, t flp single ended output rise/fall time 15% to 85%, c l <70 pf ? ? 25 ns t reo 30% to 85%, c l <70 pf ? ? 35 ns ? v/ ? t sr signal slew rate 15% to 85%, c l <70 pf ? ? 120 mv/ns c l load capacitance ? 0 ? 70 pf hs line receiver ac specifications ? v cmrx(hf) common mode interference beyond 450 mhz ? ? 200 mvpp ? v cmrx(lf) common mode interference between 50 mhz and 450 mhz. ?-50?50mvpp c cm common mode termination ? ? 60 pf lp line receiver ac specifications e spike input pulse rejection ? ? 300 vps t min minimum pulse response ? 50 ? ns v int pk-to-pk interference voltage ? ? 400 mv f int interference frequency ? 450 ? ? mhz model parameters used for driver load switching performance evaluation table 75. electrical and timing information (continued) symbol parameters test conditions min typ max unit
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 113 4.11.12.6 high-speed clock timing figure 75. ddr clock definition 4.11.12.7 forward high-speed data transmission timing the timing relationship of the ddr cl ock differential signal to the data differential signal is shown in figure 76 : figure 76. data to clock timing definitions c pa d equivalent single ended i/o pad capacitance. ???1pf c pin equivalent single ended package + pcb capacitance. ???2pf l s equivalent wire bond series inductance ? ? ? 1.5 nh r s equivalent wire bond series resistance ? ? ? 0.15 ? r l load resistance ? 80 100 125 ? table 75. electrical and timing information (continued) symbol parameters test conditions min typ max unit #,+p #,+n $ata"it4ime5) 5) ).34 $$2#lock0eriod 5) ).34 5) ).34 5) ).34 $ata"it4ime5) #,+p 2eference4ime 4 #,+p 4 3%450 4 (/,$ 5) ).34 4 3+%7 5) ).34 #,+n
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 114 freescale semiconductor electrical characteristics 4.11.12.8 reverse high-speed data transmission timing figure 77. reverse high-speed data transmission timing at slave side 4.11.12.9 low-power receiver timing figure 78. input glitch rejection of low-power receivers 4.11.13 hsi host contro ller timing parameters this section describes the timing parameters of the hsi host cont roller which are compliant with high-speed synchronous serial interface (h si) physical layer specification version1.01. 4.11.13.1 synchronous data flow figure 79. synchronized data flow ready signa l timing (frame and stream transmission) .2:$ata #,+?. #,+?0 #lockto$ata 5) 5) 3kew 4 4$ 2*t lpx 2*t lpx t min-rx t min-rx e spike e spike input output v ih v il &irstbitof frame . bits&rame (3)?$!4! (3)?&,!' (3)?2%!$9 . bits&rame 2eceiverhas detectedthestart ofthe&rame 2eceiverhascaptured andstoredacomplete&rame ,astbitof frame &irstbitof frame ,astbitof frame t .om"it
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 115 4.11.13.2 pipelined data flow figure 80. pipelined data flow ready signal timing (frame transmission mode) 4.11.13.3 receiver real-time data flow figure 81. receiver real-time data flow ready signal timing 4.11.13.4 synchronized data flow transmission with wake figure 82. synchronized data flow transmission with wake &irstbitof frame $!4! &,!' 2%!$9 !2eadycanchange "2eadyshallnot changetozero #2eadycanchange $2eadyshall maintainzeroif receiverdoesnot havefreespace %2eady can change &2eady shall maintain itsvalue '2eady canchange ,astbitof frame &irstbitof frame ,astbitof frame ,astbitof frame . bits&rame . bits&rame t .om"it &irstbitof frame . bits&rame $!4! &,!' 2%!$9 . bits&rame 2eceiverhasdetectedthe startofthe&rame 2eceiverhascaptureda complete&rame ,astbitof frame &irstbitof frame ,astbitof frame t .om"it 48state $!4! &,!' 2%!$9 7!+% 28state !3leepstate non operational "7ake upstate #!ctivestate fulloperational $$isable3tate .ocommunicationability 4ransmitterhas datatotransmit ! " 2eceiverinactive startstate &irstbit received 2eceived framestored transmitterhas nomoredatato transmit 2eceivercanno longerreceivedate ! " 0(9&rame # 0(9&rame ! $ ! $ #
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 116 freescale semiconductor electrical characteristics 4.11.13.5 stream transmission mode frame transfer figure 83. stream transmission mode frame transfer (synchronized data flow) 4.11.13.6 frame transmission mo de (synchronized data flow) figure 84. frame transmission mode transfer of two frames (synchronized data flow) 4.11.13.7 frame transmission mode (pipelined data flow) figure 85. frame transmission mode transfer of two frames (pipelined data flow) 4.11.13.8 data and flag signal timi ng requirement for a 15 pf load table 76. data and flag timing parameter description 1 mbit/s 100 mbit/s 200 mbit/s t bit, nom nominal bit time 1000 ns 10.0 ns 5.00 ns t rise, min and t fall, min minimum allowed rise and fall time 2.00 ns 2.00 ns 1.00 ns t txtorxskew, maxfq maximum skew between transmitter and re ceiver package pins 50.0 ns 0.5.0 ns 0.25 ns #hannel $escription bits 0ayload$ata"its #omplete. bits&rame $!4! &,!' 2%!$9 #omplete. bits&rame &rame startbit #hannel $escription bits 0ayload$ata"its #omplete. bits&rame $!4! &,!' 2%!$9 #omplete. bits&rame &rame startbit #hannel $escription bits 0ayload $ata"its #omplete. bits&rame $!4! &,!' 2%!$9 #omplete. bits&rame
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 117 figure 86. data and flag signal timing note: 1 this case shows that the data signal has slowed down more compared to the flag signal 2 this case shows that the flag signal has slowed down more compared to the data signal. 4.11.14 medialb (mlb) characteristics 4.11.14.1 medialb (mlb) dc characteristics table 77 lists the medialb 3-pin interf ace electrical characteristics. t eageseptx, min minimum allowed separation of signal transitions at transmitter package pins, including all timing defects, for example, jitter and skew, inside the transmitter. 400 ns 4.00 ns 2.00 ns t eageseprx, min minimum separation of signal transitions, measured at the receiver package pins, including all timing defects, for example, jitter and skew, inside the receiver. 350 ns 3.5 ns 1.75 ns table 77. medialb 3-pin interface electrical dc specifications parameter symbol test conditions min max unit maximum input voltage ? ? ? 3.6 v low level input threshold v il ??0.7v high level input threshold v ih see note 1 1 higher v ih thresholds can be used; however, the risks associ ated with less noise marg in in the system must be evaluated and assumed by the customer. 1.8 ? v low level output threshold v ol i ol = 6 ma ? 0.4 v high level output threshold v oh i oh = -6 ma 2.0 ? v input leakage current i l 0 < v in < vdd ? 10 ? a table 76. data and flag timing (continued) parameter description 1 mbit/s 100 mbit/s 200 mbit/s $!4! 48 &,!' 48 $!4! 28 &,!' 28 .ote .ote .ote .ote t "it t 4x4o2x3kew t %dge3ep4x t %dge3ep2x t &all t 2ise
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 118 freescale semiconductor electrical characteristics table 78 lists the medialb 6-pin interf ace electrical characteristics. table 78. medialb 6-pin interface electrical dc specifications parameter symbol test conditions min max unit driver characteristics differential output voltage (steady-state): i v o+ - v o- i v od see note 1 1 the signal-ended output voltage of a driver is defined as v o+ on mlb_clk_p, mlb_sig_ p, and mlb_data_p. the signal-ended output voltage of a driver is defined as v o- on mlb_clk_n, mlb_s ig_n, and mlb_data_n. 300 500 mv difference in differential output voltage between (high/low) steady-states: i v od, high - v od, low i ? v od ? -50 50 mv common-mode output voltage: (v o+ - v o- ) / 2 v ocm ?1.01.5v difference in common-mode output between (high/low) steady-states: i v ocm, high - v ocm, low i ? v ocm ? -50 50 mv variations on common-mode output during a logic state transitions v cmv see note 2 2 variations in the common-mode voltage can occur between logic st ates (for example, during state transitions) as a result of differences in the transition rate of v o+ and v o- . ?150mvpp short circuit current |i os | see note 3 3 short circuit current is applicable when v o+ and v o- are shorted together and/or shorted to ground. ?43ma differential output impedance z o ?1.6?k ? receiver characteristics differential clock input: ? logic low steady-state ? logic high steady-state ? hysteresis v ilc v ihc v hsc see note 4 4 the logic state of the receiv er is undefined when -50 mv < v id < 50 mv. ? 50 -25 -50 ? 25 mv mv mv differential signal/data input: ? logic low steady-state ? logic high steady-state v ils v ihs ? ? 50 -50 ? mv mv signal-ended input voltage (steady-state): ? mlb_sig_p, mlb_data_p ? mlb_sig_n, mlb_data_n v in+ v in- ? 0.5 0.5 2.0 2.0 v v
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 119 4.11.14.2 medialb (mlb) controller ac timing electrical specifications this section describes the timing electrical information of the medialb module. figure 87 show the timing of medialb 3- pin interface, and table 79 and table 80 lists the medialb 3-pin interface timing characteristics. figure 87. medialb 3-pin timing ground = 0.0 v; load capacitance = 60 pf; medi alb speed = 256/512 fs; fs = 48 khz; all timing parameters specified from the valid voltage thre shold as listed below; unless otherwise noted. table 79. mlb 256/512 fs timing parameters parameter symbol min max unit comment mlb_clk operating frequency 1 f mck 11.264 25.6 mhz 256xfs at 44.0 khz 512xfs at 50.0 khz mlb_clk rise time t mckr ?3 ns v il to v ih mlb_clk fall time t mckf ?3 ns v ih to v il mlb_clk low time 2 t mckl 30 14 ? ns 256xfs 512xfs mlb_clk high time t mckh 30 14 ? ns 256xfs 512xfs mlb_sig/mlb_data receiver input valid to mlb_clk falling t dsmcf 1?ns ? mlb_sig/mlb_data receiver input hold from mlb_clk low t dhmcf t mdzh ?ns ? mlb_sig/mlb_data output high impedance from mlb_clk low t mcfdz 0t mckl ns 3 bus hold from mlb_clk low t mdzh 4?ns ? -,"?#,+ -,"?3)' -,"?$!4! -,"?3)' -,"?$!4! transmitter -,"?3)' -,"?$!4! busstate valid receiver valid t mckr t delay t mckh t prop t dsmcf valid t dhmcf t mckf t mckl t mcfdz t mdzh
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 120 freescale semiconductor electrical characteristics ground = 0.0 v; load capacitance = 40 pf; medi alb speed = 1024 fs; fs = 48 khz; all timing parameters specified from the vali d voltage threshold as listed in table 80 ; unless otherwise noted. mlb_sig/mlb_data output valid from transition of mlb_clk (low to high) t delay ?10 ns ? transmitter mlbsig (mlbdat) output valid from transition of mlbclk (low-to-high) t delay ? 10.75 ns ? 1 the controller can shut off mlb_clk to place medialb in a low-powe r state. depending on the time the clock is shut off, a runt pulse can occur on mlb_clk. 2 mlb_clk low/high time includes the pulse width variation. 3 the medialb driver can release the mlb_data /mlb_sig line as soon as mlb_clk is low; however, the logic state of the final driven bit on the line must remain on the bus for t mdzh . therefore, coupling must be minimized while meeting the maximum load capacitance listed. table 80. mlb 1024 fs timing parameters parameter symbol min max unit comment mlb_clk operating frequency 1 1 the controller can shut off mlb_clk to place medialb in a low-po wer state. depending on the time the clock is shut off, a runt pulse can occur on mlb_clk. f mck 45.056 51.2 mhz 1024xfs at 44.0 khz 1024xfs at 50.0 khz mlb_clk rise time t mckr ?1ns v il to v ih mlb_clk fall time t mckf ?1ns v ih to v il mlb_clk low time t mckl 6.1 ? ns 2 2 mlb_clk low/high time includes the pulse width variation. mlb_clk high time t mckh 9.3 ? ns ? mlb_sig/mlb_data receiver input valid to mlb_clk falling t dsmcf 1?ns ? mlb_sig/mlb_data receiver input hold from mlb_clk low t dhmcf t mdzh ?ns ? mlb_sig/mlb_data output high impedance from mlb_clk low t mcfdz 0t mckl ns 3 bus hold from mlb_clk low t mdzh 2?ns ? mlb_sig/mlb_data output valid from transition of mlb_clk (low to high) t delay ?7ns ? transmitter mlbsig (mlbdat) output valid from transition of mlbclk (low-to-high) t delay ?6ns ? table 79. mlb 256/512 fs timing parameters (continued) parameter symbol min max unit comment
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 121 table 81 lists the medialb 6-pin interf ace timing characteristics, and figure 88 shows the mlb 6-pin delay, setup, and hold times. figure 88. mlb 6-pin delay, setup, and hold times 3 the medialb driver can release the mlb_data/mlb_sig line as soon as mlb_clk is low; however, the logic state of the final driven bit on the line must remain on the bus for t mdzh . therefore, coupling must be minimized while meeting the maximum load capacitance listed. table 81. mlb 6-pin interface timing parameters parameter symbol min max unit comment cycle-to-cycle system jitter t jitter ?600ps ? transmitter mlb_sig_p/_n (mlb_data_p/_n) output valid from transition of mlb_clk_p/_n (low-to-high) 1 1 t delay , t phz , t plz , t su , and t hd may also be referenced from a low-to-high transition of the recovered clock for 2:1 and 4:1 recov- ered-to-external clock ratios. t delay 0.6 1.3 ns ? disable turnaround time from transition of mlb_clk_p/_n (low-to-high) t phz 0.6 3.5 ns ? enable turnaround time from transition of mlb_clk_p/_n (low-to-high) t plz 0.6 5.6 ns ? mlb_sig_p/_n (mlb_data_p/_n ) valid to transition of mlb_clk_p/_n (low-to-high) t su 0.05 ? ns ? mlb_sig_p/_n (mlb_data_p/_n ) hold from transition of mlb_clk_p/_n (low-to-high) 2 2 the transmitting device must ensure valid data on mlb_sig_p/_n (mlb_data _p/_n) for at least t hd(min) following the rising edge of mlb_clk_p/n; receivers must latc h mlb_sig_p/_n (mlb_data_p/_n) data within t hd(min) of the rising edge of mlb_clk_p/_n. t hd 0.6 ? 0hysical#hannel boundary -,"?#,+?0. 2ecovered clock -,"?3)'?0. transmitter #ontroller #hannel!ddress #ontroller #hannel!ddress transmitter enabled $ata notvalid -,"?3)'?0. receiver #! ;= #! ;= #md ;= #md ;= #md ;= #md ;= #md ;= #md ;= t prop t prop t prop t prop t su t hd t su t hd t su t hd t su t hd x4 #md ;= #md ;= #md ;= #md ;= #md ;= #md ;= t delay t delay t delay t delay t delay 4 x4 x4 4x$evice #ommand 4x$evice #ommand
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 122 freescale semiconductor electrical characteristics 4.11.15 pcie phy parameters the pcie interface complies with pcie specification gen2 x1 lane and supports the pci express 1.1/2.0 standard. 4.11.15.1 pcie_rext reference resistor connection the impedance calibration pr ocess requires connection of reference resistor 200 ?? 1% precision resistor on pcie_rext pads to ground. it is used for termination imp edance calibration. 4.11.16 pulse width modulato r (pwm) timing parameters this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the selected clock signal is passed through a prescaler before being input to the counter. the output is available at the pulse-width modulator output (pwmo) external pin. figure 89 depicts the timing of the pwm, and table 82 lists the pwm timing parameters. figure 89. pwm timing 4.11.17 scan jtag controller (sjc) timing parameters figure 90 depicts the sjc test clock input timing. figure 91 depicts the sjc boundary scan timing. figure 92 depicts the sjc test access port. signal parameters are listed in table 83 . figure 90. test clock input timing diagram table 82. pwm output timing parameters id parameter min max unit pwm module clock frequency 0 ipg_clk mhz p1 pwm output pulse width high 15 ns p2 pwm output pulse width low 15 ns 07-n?/54 0 0 jtag_tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 123 figure 91. boundary scan (jtag) timing diagram figure 92. test access port timing diagram jtag_tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6 jtag_tck (input) jtag_tdi (input) jtag_tdo (output) jtag_tdo (output) jtag_tdo (output) vih vil input data valid output data valid output data valid jtag_tms sj8 sj9 sj10 sj11 sj10
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 124 freescale semiconductor electrical characteristics figure 93. jtag_trst_b timing diagram 4.11.18 spdif timing parameters the sony/philips digital interconnect format (spdif) data is sent usi ng the bi-phase marking code. when encoding, the spdif data signal is modulated by a clock that is twice the bit ra te of the data signal. table 84 and figure 94 and figure 95 show spdif timing parameters for the sony/philips digital interconnect format (spdif), including the timing of the modulating rx clock (spdif_sr_clk) for spdif in rx mode and the timing of the modulating tx clock (spdif _st_clk) for spdif in tx mode. table 83. jtag timing id parameter 1,2 all frequencies unit min max sj0 jtag_tck frequency of operation 1/(3?t dc ) 1 1 t dc = target frequency of sjc 0.001 22 mhz sj1 jtag_tck cycle time in crystal mode 45 ? ns sj2 jtag_tck clock pulse width measured at v m 2 2 v m = mid-point voltage 22.5 ? ns sj3 jtag_tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 5 ? ns sj5 boundary scan input data hold time 24 ? ns sj6 jtag_tck low to output data valid ? 40 ns sj7 jtag_tck low to output high impedance ? 40 ns sj8 jtag_tms, jtag_tdi data set-up time 5 ? ns sj9 jtag_tms, jtag_tdi data hold time 25 ? ns sj10 jtag_tck low to jtag_tdo data valid ? 44 ns sj11 jtag_tck low to jtag_tdo high impedance ? 44 ns sj12 jtag_trst_b assert time 100 ? ns sj13 jtag_trst_b set-up time to jtag_tck low 40 ? ns jtag_tck (input) jtag_trst_b (input) sj13 sj12
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 125 figure 94. spdif_sr_clk timing diagram figure 95. spdif_st_clk timing diagram table 84. spdif timing parameters characteristics symbol timing parameter range unit min max spdif_in skew: asynchronous inputs, no specs apply ?? 0.7ns spdif_out output (load = 50pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 24.2 31.3 ns spdif_out output (load = 30pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns modulating rx clock (spdif_sr_clk) period srckp 40.0 ? ns spdif_sr_clk high period srckph 16.0 ? ns spdif_sr_clk low period srckpl 16.0 ? ns modulating tx clock (spdif_st_clk) period stclkp 40.0 ? ns spdif_st_clk high period stclkph 16.0 ? ns spdif_st_clk low pe riod stclkpl 16.0 ? ns spdif_sr_clk (output) v m v m srckp srckph srckpl spdif_st_clk (input) v m v m stclkp stclkph stclkpl
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 126 freescale semiconductor electrical characteristics 4.11.19 ssi timing parameters this section describes the timing parameters of the ssi module. the connectivity of the serial synchronous interfaces are summarized in table 85 . note the terms wl and bl used in the ti ming diagrams and tables see word length (wl) and bit length (bl). 4.11.19.1 ssi transmitter timing with internal clock figure 96 depicts the ssi transmitter internal clock timing and table 86 lists the timing parameters for the ssi transmitter internal clock. . figure 96. ssi transmitter internal clock timing diagram table 85. audmux port allocation port signal nomenclature type and access audmux port 1 ssi 1 internal audmux port 2 ssi 2 internal audmux port 3 aud3 external? aud3 i/o audmux port 4 aud4 external? eim or cspi1 i/o through iomuxc audmux port 5 aud5 external? eim or sd1 i/o through iomuxc audmux port 6 aud6 external? eim or disp2 through iomuxc audmux port 7 ssi 3 internal ss19 ss1 ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: audx_rxd input in synchronous mode only audx_txc (output) audx_txfs (wl) (output) audx_txfs (bl) (output) audx_rxd (input) audx_txd (output)
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 127 note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (tsckp/rsckp = 0) a nd a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal audx_txc/audx_rxc and/or the frame sync audx_txfs/audx_rxfs shown in th e tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? the terms, wl and bl, refer to word length (wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the frame sync timing is same as that of transmit data (for ex ample, during ac97 mode of operation). table 86. ssi transmitter timing with internal clock id parameter min max unit internal clock operation ss1 audx_txc/audxrxc clock period 81.4 ? ns ss2 audx_txc/audxrxc clock high period 36.0 ? ns ss4 audx_txc/audxrxc clock low period 36.0 ? ns ss6 audx_txc high to audx_txfs (bl) high ? 15.0 ns ss8 audx_txc high to audx_txfs (bl) low ? 15.0 ns ss10 audx_txc high to audx_txfs (wl) high ? 15.0 ns ss12 audx_txc high to audx_txfs (wl) low ? 15.0 ns ss14 audx_txc/audxrxc internal audx_txfs rise time ? 6.0 ns ss15 audx_txc/audxrxc internal audx_txfs fall time ? 6.0 ns ss16 audx_txc high to audx_txd valid from high impedance ? 15.0 ns ss17 audx_txc high to audx_txd high/low ? 15.0 ns ss18 audx_txc high to audx_txd high impedance ? 15.0 ns synchronous internal clock operation ss42 audx_rxd setup before audx_txc falling 10.0 ? ns ss43 audx_rxd hold after audx_txc falling 0.0 ? ns
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 128 freescale semiconductor electrical characteristics 4.11.19.2 ssi receiver timing with internal clock figure 97 depicts the ssi receiver internal clock timing and table 87 lists the timing parameters for the receiver timing with the internal clock. figure 97. ssi receiver internal clock timing diagram table 87. ssi receiver timing with internal clock id parameter min max unit internal clock operation ss1 audx_txc/audx_rxc clock period 81.4 ? ns ss2 audx_txc/audx_rxc clock high period 36.0 ? ns ss3 audx_txc/audx_rxc clock rise time ? 6.0 ns ss4 audx_txc/audx_rxc clock low period 36.0 ? ns ss5 audx_txc/audx_rxc clock fall time ? 6.0 ns ss7 audx_rxc high to audx_txfs (bl) high ? 15.0 ns ss9 audx_rxc high to audx_txfs (bl) low ? 15.0 ns ss11 audx_rxc high to audx_txfs (wl) high ? 15.0 ns ss13 audx_rxc high to audx_txfs (wl) low ? 15.0 ns ss20 audx_rxd setup time before audx_rxc low 10.0 ? ns ss21 audx_rxd hold time after audx_rxc low 0.0 ? ns ss50 ss48 ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 ss3 ss5 audx_txc (output) audx_txfs (bl) (output) audx_txfs (wl) (output) audx_rxd (input) audx_rxc (output)
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 129 note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (tsckp/rsckp = 0) a nd a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal audx_txc/audx_rxc and/or the frame sync audx_txfs/audx_rxfs shown in th e tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? the terms, wl and bl, refer to word length (wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the frame sync timing is same as that of transmit data (for ex ample, during ac97 mode of operation). oversampling cl ock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6.0 ? ns ss49 oversampling clock rise time ? 3.0 ns ss50 oversampling clock low period 6.0 ? ns ss51 oversampling clock fall time ? 3.0 ns table 87. ssi receiver timing with internal clock (continued) id parameter min max unit
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 130 freescale semiconductor electrical characteristics 4.11.19.3 ssi transmitter timing with external clock figure 98 depicts the ssi transmitte r external clock timing and table 88 lists the timing parameters for the transmitter timing wi th the external clock. figure 98. ssi transmitter exte rnal clock timing diagram table 88. ssi transmitter timing with external clock id parameter min max unit external clock operation ss22 audx_txc/audx_rxc clock period 81.4 ? ns ss23 audx_txc/audx_rxc clock high period 36.0 ? ns ss24 audx_txc/audx_rxc clock rise time ? 6.0 ns ss25 audx_txc/audx_rxc clock low period 36.0 ? ns ss26 audx_txc/audx_rxc clock fall time ? 6.0 ns ss27 audx_txc high to audx_txfs (bl) high -10.0 15.0 ns ss29 audx_txc high to audx_txfs (bl) low 10.0 ? ns ss31 audx_txc high to audx _txfs (wl) high -10.0 15.0 ns ss33 audx_txc high to audx_txfs (wl) low 10.0 ? ns ss37 audx_txc high to audx_txd valid from high impedance ? 15.0 ns ss38 audx_txc high to audx_txd high/low ? 15.0 ns ss39 audx_txc high to audx_txd high impedance ? 15.0 ns ss45 ss33 ss24 ss26 ss25 ss23 ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 audx_txc (input) audx_txfs (bl) (input) audx_txfs (wl) (input) audx_txd (output) audx_rxd (input) note: audx_rxd input in synchronous mode only
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 131 note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (tsckp/rsckp = 0) a nd a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal audx_txc/audx_rxc and/or the frame sync audx_txfs/audx_rxfs shown in th e tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? the terms wl and bl refer to wo rd length (wl) and bit length (bl). ? for internal frame sync operation us ing external clock, the frame sync timing is same as that of transmit data (for ex ample, during ac97 mode of operation). 4.11.19.4 ssi receiver timing with external clock figure 99 depicts the ssi receiver external clock timing and table 89 lists the timing parameters for the receiver timing with the external clock. figure 99. ssi receiver exte rnal clock timing diagram synchronous external clock operation ss44 audx_rxd setup before audx_txc falling 10.0 ? ns ss45 audx_rxd hold after audx_txc falling 2.0 ? ns ss46 audx_rxd rise/fall time ? 6.0 ns table 88. ssi transmitter timing with external clock (continued) id parameter min max unit ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ss40 ss22 ss32 ss36 ss41 audx_txc (input) audx_txfs (bl) (input) audx_txfs (wl) (input) audx_rxd (input)
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 132 freescale semiconductor electrical characteristics note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (tsckp/rsckp = 0) a nd a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal audx_txc/audx_rxc and/or the frame sync audx_txfs/audx_rxfs shown in th e tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? the terms, wl and bl, refer to word length (wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the frame sync timing is same as that of transmit data (for ex ample, during ac97 mode of operation). table 89. ssi receiver timing with external clock id parameter min max unit external clock operation ss22 audx_txc/audx_rxc clock period 81.4 ? ns ss23 audx_txc/audx_rxc clock high period 36 ? ns ss24 audx_txc/audx_rxc clock rise time ? 6.0 ns ss25 audx_txc/audx_rxc clock low period 36 ? ns ss26 audx_txc/audx_rxc clock fall time ? 6.0 ns ss28 audx_rxc high to audx_txfs (bl) high -10 15.0 ns ss30 audx_rxc high to audx_txfs (bl) low 10 ? ns ss32 audx_rxc high to audx_txfs (wl) high -10 15.0 ns ss34 audx_rxc high to audx_txfs (wl) low 10 ? ns ss35 audx_txc/audx_rxc external audx_txfs rise time ? 6.0 ns ss36 audx_txc/audx_rxc external audx_txfs fall time ? 6.0 ns ss40 audx_rxd setup time before audx_rxc low 10 ? ns ss41 audx_rxd hold time after audx_rxc low 2 ? ns
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 133 4.11.20 uart i/o configurat ion and timing parameters 4.11.20.1 uart rs-232 i/o configuration in different modes the i.mx 6solo/6duallite uart interfaces can serve both as dt e or dce device. this can be configured by the dcedte contro l bit (default 0?dce mode). table 90 shows the uart i/o configuration based on the enabled mode. 4.11.20.2 uart rs-232 serial mode timing the following sections describe the electrical information of the uart module in the rs-232 mode. 4.11.20.2.1 uart transmitter figure 100 depicts the transmit timing of uart in the rs-232 serial m ode, with 8 data bit/1 stop bit format. table 91 lists the uart rs-232 serial mode transmit timing characteristics. figure 100. uart rs-232 serial mode transmit timing diagram table 90. uart i/o configuration vs. mode port dte mode dce mode direction description direction description uartx_rts_b output rts from dte to dce input rts from dte to dce uartx_cts_b input cts from dce to dte output cts from dce to dte uartx_dtr_b output dtr from dte to dce input dtr from dte to dce uartx_dsr_b input dsr from dce to dte output dsr from dce to dte uartx_dcd_ b input dcd from dce to dte output dcd from dce to dte uartx_ri_b input ring from dce to dte output ring from dce to dte uartx_tx_data input serial data from dce to dte output serial data from dce to dte uartx_rx_data output serial data from dte to dce input serial data from dte to dce table 91. rs-232 serial mode transmit timing parameters id parameter symbol min max unit ua1 transmit bit time t tbit 1/f baud_rate 1 - t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? start bit bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_tx_data (output) bit 3 stop bit next start bit possible pa r i t y bit par bit ua1 ua1 ua1 ua1
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 134 freescale semiconductor electrical characteristics 4.11.20.2.2 uart receiver figure 101 depicts the rs-232 serial mode receive timing with 8 data bit/1 stop bit format. table 92 lists serial mode receive timing characteristics. figure 101. uart rs-232 serial mode receive timing diagram 4.11.20.2.3 uart irda mode timing the following subsections give the uart transmit and receive ti mings in irda mode. uart irda mode transmitter figure 102 depicts the uart irda mode transmit timing, with 8 da ta bit/1 stop bit format. table 93 lists the transmit timin g characteristics. figure 102. uart irda mode transmit timing diagram table 92. rs-232 serial mode receive timing parameters id parameter symbol min max unit ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16 x f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 x f baud_rate ). t rbit 1/f baud_rate 2 - 1/(16 x f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16 x f baud_rate ) ? table 93. irda mode transmit timing parameters id parameter symbol min max unit ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 - t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + t ref_clk ? ua4 transmit ir pulse duration t tirpulse (3/16) x (1/f baud_rate ) - t ref_clk (3/16) x (1/f baud_rate ) + t ref_clk ? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_rx_data (input) bit 3 start bit stop bit next start bit possible pa r i t y bit par bit ua2 ua2 ua2 ua2 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_tx_data (output) bit 3 start bit stop bit possible parity bit ua3 ua3 ua3 ua3 ua4
electrical characteristics i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 135 uart irda mode receiver figure 103 depicts the uart irda mode receive ti ming, with 8 data bit/1 stop bit format. table 94 lists the receive timing characteristics. figure 103. uart irda mode receive timing diagram 4.11.21 usb hsic timings this section describes the electrical information of the usb hsic port. note hsic is ddr signal, following timing spec is for both rising and falling edge. 4.11.21.1 transmit timing figure 104. usb hsic transmit waveform 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). table 94. irda mode receive timing parameters id parameter symbol min max unit ua5 receive bit time 1 in irda mode 1 the uart receiver can tolerate 1/(16 x f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 x f baud_rate ). t rirbit 1/f baud_rate 2 - 1/(16 x f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16 x f baud_rate ) ? ua6 receive ir pulse duration t rirpulse 1.41 ? s (5/16) x (1/f baud_rate )? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_rx_data (input) bit 3 start bit stop bit possible parity bit ua5 ua5 ua5 ua5 ua6 usb_h_strobe usb_h_data todelay tstrobe todelay
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 136 freescale semiconductor electrical characteristics 4.11.21.2 receive timing figure 105. usb hsic receive waveform 4.11.22 usb phy parameters this section describes the usb-otg phy and the usb host port phy parameters. the usb phy meets the electrical compliance requireme nts defined in the univer sal serial bus revision 2.0 otg, usb host with the amendments below (on- the-go and embedded host supplement to the usb revision 2.0 specification is no t applicable to host port). ? usb engineering change notice ? title: 5v short circuit withstand requirement change ? applies to: universal serial bus specification, revision 2.0 ? errata for usb revision 2.0 april 27, 2000 as of 12/7/2000 ? usb engineering change notice ? title: pull-up/pull-down resistors ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice table 95. usb hsic transmit parameters name parameter min max unit comment tstrobe strobe period 4.166 4.167 ns ? todelay data output delay time 550 1350 ps measured at 50% point tslew strobe/data rising/falling time 0.7 2 v/ns averaged from 30% ? 70% points table 96. usb hsic receive parameters 1 1 the timings in the table are guaranteed when: ?ac i/o voltage is between 0.9x to 1x of the i/o supply ?ddr_sel configuration bits of the i/o are set to (10)b name parameter min max unit comment tstrobe strobe period 4.166 4.167 ns ? thold data hold time 300 ps measured at 50% point tsetup data setup time 365 ps measured at 50% point tslew strobe/data rising/falling time 0.7 2 v/ns averaged from 30% ? 70% points usb_h_strobe usb_h_data thold tstrobe tsetup
boot mode configuration i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 137 ? title: suspend current limit changes ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice ? title: usb 2.0 phase locked sofs ? applies to: universal serial bus specification, revision 2.0 ? on-the-go and embedded host supplement to the usb revision 2.0 specification ? revision 2.0 plus errata and ecn june 4, 2010 ? battery charging specificati on (available from usb-if) ? revision 1.2, december 7, 2010 ? portable device only 5 boot mode configuration this section provides information on boot mode configuration pins allo cation and boot devices interfaces allocation. 5.1 boot mode configuration pins table 97 provides boot options, functionalit y, fuse values, and associated pi ns. several input pins are also sampled at reset and can be used to override fuse values, depending on the va lue of bt_fuse_sel fuse. the boot option pins are in effect when bt_fuse_sel fuse is ?0? (cleared, which is the case for an unblown fuse). for detailed boot mode options configured by th e boot mode pins, see the i.mx 6solo/6duallite fuse map document and the system boot chapter in i.mx 6solo/6duallite reference manual (imx6sdlrm) . table 97. fuses and associated pins used for boot pin direction at reset efuse name boot mode selection boot_mode1 input n/a boot_mode0 input n/a boot options 1 eim_da0 input boot_cfg1[0] eim_da1 input boot_cfg1[1] eim_da2 input boot_cfg1[2] eim_da3 input boot_cfg1[3] eim_da4 input boot_cfg1[4] eim_da5 input boot_cfg1[5] eim_da6 input boot_cfg1[6] eim_da7 input boot_cfg1[7]
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 138 freescale semiconductor boot mode configuration eim_da8 input boot_cfg2[0] eim_da9 input boot_cfg2[1] eim_da10 input boot_cfg2[2] eim_da11 input boot_cfg2[3] eim_da12 input boot_cfg2[4] eim_da13 input boot_cfg2[5] eim_da14 input boot_cfg2[6] eim_da15 input boot_cfg2[7] eim_a16 input boot_cfg3[0] eim_a17 input boot_cfg3[1] eim_a18 input boot_cfg3[2] eim_a19 input boot_cfg3[3] eim_a20 input boot_cfg3[4] eim_a21 input boot_cfg3[5] eim_a22 input boot_cfg3[6] eim_a23 input boot_cfg3[7] eim_a24 input boot_cfg4[0] eim_wait input boot_cfg4[1] eim_lba input boot_cfg4[2] eim_eb0 input boot_cfg4[3] eim_eb1 input boot_cfg4[4] eim_rw input boot_cfg4[5] eim_eb2 input boot_cfg4[6] eim_eb3 input boot_cfg4[7] 1 pin value overrides fuse settings for bt_fuse_sel = ?0?. signal configuration as fuse override input at power up. these are special i/o lines that control the boot up co nfiguration during product development. in production, the boot configuration can be controlled by fuses. table 97. fuses and associated pins used for boot (continued) pin direction at reset efuse name
boot mode configuration i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 139 5.2 boot device interface allocation table 98 lists the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. the table also describes the interface?s specif ic modes and iomuxc allocation, which are configured during boot when appropriate. table 98. interface allocation during boot interface ip instance allocated pads during boot comment spi ecspi-1 eim_d17, eim_d18, eim_d16, eim_eb2, eim_d19, eim_d24, eim_d25 ? spi ecspi-2 csi0_dat10, csi0_dat 9, csi0_dat8, csi0_dat11, eim_lba, eim_d24, eim_d25 ? spi ecspi-3 disp0_dat2, di sp0_dat1, disp0_dat0, disp0_dat3, disp0_dat4, disp0_dat5, disp0_dat6 ? spi ecspi-4 eim_d22, eim_d28, ei m_d21, eim_d20, eim_a25, eim_d24, eim_d25 ? eim eim eim_da[15:0], eim_d[31:16], csi0_dat[19:4], csi0_data_en, csi0_vsync used for nor, onenand boot only cs0 is supported nand flash gpmi nandf_cle, nandf_ale, nandf_wp_b, sd4_cmd, sd4_clk, nandf_rb0, sd4_dat0, nandf_cs0, nandf_cs1, nandf_cs2, nandf_cs3, nandf_d[7:0] 8 bit only cs0 is supported sd/mmc usdhc-1 sd1_clk, sd1_cmd, sd1_dat0, sd1_dat1, sd1_dat2, sd1_dat3, gpio_1, nandf_d0, nandf_d1, nandf_d2, nandf_d3, key_col1 1, 4, or 8 bit sd/mmc usdhc-2 sd2_clk, sd2_cmd, sd2_dat0, sd2_dat1, sd2_dat2, sd2_dat3, gpio_4, nandf_d4, nandf_d5, nandf_d6, nandf_d7, key_row1 1, 4, or 8 bit sd/mmc usdhc-3 sd3_clk, sd3_cmd, sd3_dat0, sd3_dat1, sd3_dat2, sd3_dat3, sd3_dat4, sd3_dat5, sd3_dat6, sd3_dat7, sd3_rst, gpio_18 1, 4, or 8 bit sd/mmc usdhc-4 sd4_clk, sd4_cmd, sd4_dat0, sd4_dat1, sd4_dat2, sd4_dat3, sd4_dat4, sd4_dat5, sd4_dat6, sd4_dat7, nandf_ale, nandf_cs1 1, 4, or 8 bit i 2 ci 2 c-1 eim_d28, eim_d21 ? i 2 ci 2 c-2 eim_d16, eim_eb2 ? i 2 ci 2 c-3 eim_d18, eim_d17 ? usb usb-otg phy usb_otg_dp usb_otg_dn usb_otg_vbus ?
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 140 freescale semiconductor package information and contact assignments 6 package information and contact assignments this section includes the contact assignment information and mechanical package drawing. 6.1 updated signal naming convention the signal names of the i.mx6 series of products have been standardized to bett er align the signal names within the family and across the documentation. some of the benefits of thes e changes are as follows: ? the names are unique within the scope of an soc and within the series of products ? searches will return all occurrences of the named signal ? the names are consistent be tween i.mx 6 series products implementing the same modules ? the module instance is incorporated into the signal name this change applies only to signal na mes. the original ball names have been preserved to prevent the need to change schematics, bsdl models, ibis models, etc. throughout this document, the updated signal names are used except where referenced as a ball name (such as the functional contact assignm ents table, ball map table, and so on). a master list of the signal name changes is in the document, imx 6 series signal name mapping (eb792). this list can be used to map the signal names used in older documentati on to the new standardized naming conventions. 6.2 21x21 mm package information 6.2.1 case 2240, 21 x 21 mm, 0. 8 mm pitch, 25 x 25 ball matrix figure 106 shows the top, bottom, and side views of the 2121 mm bga package.
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 141 figure 106. 21 x 21 mm bga, case 2240 package top, bottom, and side views
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 142 freescale semiconductor package information and contact assignments table 99 shows the 21 ? 21 mm bga package details. table 99. 21 x 21, 0.8 mm bga package details parameter symbol common dimensions minimum normal maximum total thickness a ? ? 1.5 stand off a1 0.36 ? 0.46 substrate thickness a2 0.26 ref mold thickness a3 0.7 ref body size d 21 bsc e 21 bsc ball diameter ? 0.5 ball opening ? 0.4 ball width b 0.44 ? 0.64 ball pitch e 0.8 bsc ball count n 624 edge ball center to center d1 19.2 bsc e1 19.2 bsc body center to contact ball sd ? se ? package edge tolerance aaa 0.1 mold flatness bbb 0.2 coplanarity ddd 0.15 ball offset (package) eee 0.15 ball offset (ball) fff 0.08
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 143 6.2.2 21 x 21 mm supplies contact assi gnments and functional contact assignments table 100 shows supplies contact assignmen ts for the 21 x 21 mm package. table 100. 21 x 21 mm supplies contact assignments supply rail name ball (s) position(s) remark csi_rext d4 ? dram_vref ac2 ? dsi_rext g4 ? gnd a4, a8, a13, a25, b4, c1, c4, c6, c10, d3, d6, d8, e5, e6, e7, f5, f6, f7, f8, g3, g10, g19, h8, h12, h15, h18, j2, j8, j12, j15, j18, k8, k10, k12, k15, k18, l2, l5, l8, l10, l12, l15, l18, m8, m10, m12, m15, m18, n8, n10, n15, n18, p8, p10, p12, p15, p18, r8, r12, r15, r17, t8, t11, t12, t15, t17, t19, u8, u11, u12, u15, u17, u19, v8, v19, w3, w7, w8, w9, w10, w11, w12, w13, w15, w16, w17, w18, w19, y5, y24, aa7, aa10, aa13, aa16, aa19, aa22, ab3, ab24, ad4, ad7, ad10, ad13, ad16, ad19, ad22, ae1, ae25 ? hdmi_ref j1 ? hdmi_vp l7 ? hdmi_vph m7 ? nvcc_csi n7 supply of the camera sensor interface nvcc_dram r18, t18, u18, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18 supply of the ddr interface nvcc_eim k19, l19, m19 supply of the eim interface nvcc_enet r19 supply of the enet interface nvcc_gpio p7 supply of the gpio interface nvcc_jtag j7 supply of the jtag tap controller interface nvcc_lcd p19 supply of the lcd interface nvcc_lvds2p5 v7 supply of the lvds display interface and ddr pre-drivers nvcc_mipi k7 supply of the mipi interface nvcc_nandf g15 supply of the raw nand flash memories interface nvcc_pll_out e8 ? nvcc_rgmii g18 supply of the enet interface nvcc_sd1 g16 supply of the sd card interface nvcc_sd2 g17 supply of the sd card interface nvcc_sd3 g14 supply of the sd card interface
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 144 freescale semiconductor package information and contact assignments pcie_rext a2 ? pcie_vp h7 ? pcie_vph g7 pci phy supply pcie_vptx g8 pci phy supply vdd_snvs_cap g9 secondary supply for the snvs (internal regulator output?requires capacitor if internal regulator is used) vdd_snvs_in g11 primary supply for the snvs regulator vddarm_cap h11, h13, j11, j13, k 11, k13, l11, l13, m11, m13, n11, n13, p11, p13, r11, r13 secondary supply for core (internal regulator output?requires capacitor if internal regulator is used) vddarm_in h14, j14, k9, k14, l9, l14, m9, m14, n9, n14, p9, p14, r9, r14, t9, u9 primary supply for the arm core?s regulator vddhigh_cap h10, j10 secondary supply for the 2.5 v domain (internal regulator output?requires capacitor if internal regulator is used) vddhigh_in h9, j9 primary supply for the 2.5 v regulator vddpu_cap h17, j17, k17, l17, m17, n17, p17 secondary supply for vpu and gpus (internal regulator output?requires capacitor if internal regulator is used) vddsoc_cap r10, t10, t13, t14, u10, u13, u14 secondary supply for soc and pu regulators (internal regulator output?requires capacitor if internal regulator is used) vddsoc_in h16, j16, k16, l16, m16, n16, p16, r16, t16, u16 primary supply for soc and pu regulators vddusb_cap f9 secondary supply for the 3 v domain (internal regulator output?requires capacitor if internal regulator is used) usb_h1_vbus d10 primary supply for the 3 v regulator usb_otg_vbus e9 primary supply for the 3 v regulator hdmi_ddccec k2 analog ground (ground reference for the hot plug detect signal) fa_ana a5 ? gpanaio c8 ? vdd_fa b5 ? table 100. 21 x 21 mm supplies contact assignments (continued) supply rail name ball (s) position(s) remark
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 145 table 101 shows an alpha-sorted list of functional cont act assignments for the 21 x 21 mm package. zqpad ae17 ? nc for i.mx 6duallite: a1, a12, a14, b12, b14, c14, e1, e2, f1, f2, g12, g13, n12 for i.mx 6solo: a1, a12, a14, b12, b14, c14, e1, e2, f1, f2, g12, g13, n12, w25, y17, y18, y19, y20, y21, y22, y23, y25, aa17, aa18, aa20, aa21, aa23, aa24, aa25, ab18, ab19, ab20, ab21, ab22, ab23, ab25, ac18, ac19, ac20, ac21, ac22, ac23, ac24, ac25, ad18, ad20, ad21, ad23, ad24, ad25, ae18, ae19, ae20, ae21, ae22, ae23, ae24 ? table 101. 21 x 21 mm functional contact assignments ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2 boot_mode0 c12 vdd_snvs_in gpio al t0 src_boot_mode0 input 100 k ? pull-down boot_mode1 f12 vdd_snvs_in gpio al t0 src_boot_mode1 input 100 k ? pull-down clk1_n c7 vddhigh_cap ? ? clk1_n ? ? clk1_p d7 vddhigh_cap ? ? clk1_p ? ? clk2_n c5 vddhigh_cap ? ? clk2_n ? ? clk2_p d5 vddhigh_cap ? ? clk2_p ? ? csi_clk0m f4 nvcc_mipi analog ? csi_clk_n ? ? csi_clk0p f3 nvcc_mipi analog ? csi_clk_p ? ? csi_d0m e4 nvcc_mipi analog ? csi_data0_n ? ? csi_d0p e3 nvcc_mipi analog ? csi_data0_p ? ? csi_d1m d1 nvcc_mipi analog ? csi_data1_n ? ? csi_d1p d2 nvcc_mipi analog ? csi_data1_p ? ? csi0_dat10 m1 nvcc_csi gpio alt5 gpio5_io28 input 100 k ? pull-up csi0_dat11 m3 nvcc_csi gpio alt5 gpio5_io29 input 100 k ? pull-up csi0_dat12 m2 nvcc_csi gpio alt5 gpio5_io30 input 100 k ? pull-up csi0_dat13 l1 nvcc_csi gpio alt5 gpio5_io31 input 100 k ? pull-up csi0_dat14 m4 nvcc_csi gpio alt5 gpio6_io00 input 100 k ? pull-up csi0_dat15 m5 nvcc_csi gpio alt5 gpio6_io01 input 100 k ? pull-up csi0_dat16 l4 nvcc_csi gpio alt5 gpio6_io02 input 100 k ? pull-up csi0_dat17 l3 nvcc_csi gpio alt5 gpio6_io03 input 100 k ? pull-up csi0_dat18 m6 nvcc_csi gpio alt5 gpio6_io04 input 100 k ? pull-up table 100. 21 x 21 mm supplies contact assignments (continued) supply rail name ball (s) position(s) remark
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 146 freescale semiconductor package information and contact assignments csi0_dat19 l6 nvcc_csi gpio alt5 gpio6_io05 input 100 k ? pull-up csi0_dat4 n1 nvcc_csi gpio alt5 gpio5_io22 input 100 k ? pull-up csi0_dat5 p2 nvcc_csi gpio alt5 gpio5_io23 input 100 k ? pull-up csi0_dat6 n4 nvcc_csi gpio alt5 gpio5_io24 input 100 k ? pull-up csi0_dat7 n3 nvcc_csi gpio alt5 gpio5_io25 input 100 k ? pull-up csi0_dat8 n6 nvcc_csi gpio alt5 gpio5_io26 input 100 k ? pull-up csi0_dat9 n5 nvcc_csi gpio alt5 gpio5_io27 input 100 k ? pull-up csi0_data_en p3 nvcc_csi gpio alt5 gpio5_io20 input 100 k ? pull-up csi0_mclk p4 nvcc_csi gpio alt5 gpio5_io19 input 100 k ? pull-up csi0_pixclk p1 nvcc_csi gpio alt5 gpio5_io18 input 100 k ? pull-up csi0_vsync n2 nvcc_csi gpio alt5 gpio5_io21 input 100 k ? pull-up di0_disp_clk n19 nvcc_lcd gpio alt5 gpio4_io16 input 100 k ? pull-up di0_pin15 n21 nvcc_lcd gpio alt5 gpio4_io17 input 100 k ? pull-up di0_pin2 n25 nvcc_lcd gpio alt5 gpio4_io18 input 100 k ? pull-up di0_pin3 n20 nvcc_lcd gpio alt5 gpio4_io19 input 100 k ? pull-up di0_pin4 p25 nvcc_lcd gpio alt5 gpio4_io20 input 100 k ? pull-up disp0_dat0 p24 nvcc_lcd gpio alt5 gpio4_io21 input 100 k ? pull-up disp0_dat1 p22 nvcc_lcd gpio alt5 gpio4_io22 input 100 k ? pull-up disp0_dat10 r21 nvcc_lcd gpio alt5 gpio4_io31 input 100 k ? pull-up disp0_dat11 t23 nvcc_lcd gpio alt5 gpio5_io05 input 100 k ? pull-up disp0_dat12 t24 nvcc_lcd gpio alt5 gpio5_io06 input 100 k ? pull-up disp0_dat13 r20 nvcc_lcd gpio alt5 gpio5_io07 input 100 k ? pull-up disp0_dat14 u25 nvcc_lcd gpio alt5 gpio5_io08 input 100 k ? pull-up disp0_dat15 t22 nvcc_lcd gpio alt5 gpio5_io09 input 100 k ? pull-up disp0_dat16 t21 nvcc_lcd gpio alt5 gpio5_io10 input 100 k ? pull-up disp0_dat17 u24 nvcc_lcd gpio alt5 gpio5_io11 input 100 k ? pull-up disp0_dat18 v25 nvcc_lcd gpio alt5 gpio5_io12 input 100 k ? pull-up disp0_dat19 u23 nvcc_lcd gpio alt5 gpio5_io13 input 100 k ? pull-up disp0_dat2 p23 nvcc_lcd gpio alt5 gpio4_io23 input 100 k ? pull-up disp0_dat20 u22 nvcc_lcd gpio alt5 gpio5_io14 input 100 k ? pull-up disp0_dat21 t20 nvcc_lcd gpio alt5 gpio5_io15 input 100 k ? pull-up disp0_dat22 v24 nvcc_lcd gpio alt5 gpio5_io16 input 100 k ? pull-up disp0_dat23 w24 nvcc_lcd gpio alt5 gpio5_io17 input 100 k ? pull-up disp0_dat3 p21 nvcc_lcd gpio alt5 gpio4_io24 input 100 k ? pull-up disp0_dat4 p20 nvcc_lcd gpio alt5 gpio4_io25 input 100 k ? pull-up disp0_dat5 r25 nvcc_lcd gpio alt5 gpio4_io26 input 100 k ? pull-up table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 147 disp0_dat6 r23 nvcc_lcd gpio alt5 gpio4_io27 input 100 k ? pull-up disp0_dat7 r24 nvcc_lcd gpio alt5 gpio4_io28 input 100 k ? pull-up disp0_dat8 r22 nvcc_lcd gpio alt5 gpio4_io29 input 100 k ? pull-up disp0_dat9 t25 nvcc_lcd gpio alt5 gpio4_io30 input 100 k ? pull-up dram_a0 ac14 nvcc_dram ddr alt0 dram_addr00 output low dram_a1 ab14 nvcc_dram ddr alt0 dram_addr01 output low dram_a10 aa15 nvcc_dram ddr alt0 dram_addr10 output low dram_a11 ac12 nvcc_dram ddr alt0 dram_addr11 output low dram_a12 ad12 nvcc_dram ddr alt0 dram_addr12 output low dram_a13 ac17 nvcc_dram ddr alt0 dram_addr13 output low dram_a14 aa12 nvcc_dram ddr alt0 dram_addr14 output low dram_a15 y12 nvcc_dram ddr alt0 dram_addr15 output low dram_a2 aa14 nvcc_dram ddr alt0 dram_addr02 output low dram_a3 y14 nvcc_dram ddr alt0 dram_addr03 output low dram_a4 w14 nvcc_dram ddr alt0 dram_addr04 output low dram_a5 ae13 nvcc_dram ddr alt0 dram_addr05 output low dram_a6 ac13 nvcc_dram ddr alt0 dram_addr06 output low dram_a7 y13 nvcc_dram ddr alt0 dram_addr07 output low dram_a8 ab13 nvcc_dram ddr alt0 dram_addr08 output low dram_a9 ae12 nvcc_dram ddr alt0 dram_addr09 output low dram_cas ae16 nvcc_dram ddr alt0 dram_cas output low dram_cs0 y16 nvcc_dram ddr alt0 dram_cs0 output low dram_cs1 ad17 nvcc_dram ddr alt0 dram_cs1 output low dram_d0 ad2 nvcc_dram ddr alt0 dram_data00 input 100 k ? pull-up dram_d1 ae2 nvcc_dram ddr alt0 dram_data01 input 100 k ? pull-up dram_d10 aa6 nvcc_dram ddr alt0 dram_data10 input 100 k ? pull-up dram_d11 ae7 nvcc_dram ddr alt0 dram_data11 input 100 k ? pull-up dram_d12 ab5 nvcc_dram ddr alt0 dram_data12 input 100 k ? pull-up dram_d13 ac5 nvcc_dram ddr alt0 dram_data13 input 100 k ? pull-up dram_d14 ab6 nvcc_dram ddr alt0 dram_data14 input 100 k ? pull-up dram_d15 ac7 nvcc_dram ddr alt0 dram_data15 input 100 k ? pull-up dram_d16 ab7 nvcc_dram ddr alt0 dram_data16 input 100 k ? pull-up dram_d17 aa8 nvcc_dram ddr alt0 dram_data17 input 100 k ? pull-up dram_d18 ab9 nvcc_dram ddr alt0 dram_data18 input 100 k ? pull-up dram_d19 y9 nvcc_dram ddr alt0 dram_data19 input 100 k ? pull-up dram_d2 ac4 nvcc_dram ddr alt0 dram_data02 input 100 k ? pull-up table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 148 freescale semiconductor package information and contact assignments dram_d20 y7 nvcc_dram ddr alt0 dram_data20 input 100 k ? pull-up dram_d21 y8 nvcc_dram ddr alt0 dram_data21 input 100 k ? pull-up dram_d22 ac8 nvcc_dram ddr alt0 dram_data22 input 100 k ? pull-up dram_d23 aa9 nvcc_dram ddr alt0 dram_data23 input 100 k ? pull-up dram_d24 ae9 nvcc_dram ddr alt0 dram_data24 input 100 k ? pull-up dram_d25 y10 nvcc_dram ddr alt0 dram_data25 input 100 k ? pull-up dram_d26 ae11 nvcc_dram ddr alt0 dram_data26 input 100 k ? pull-up dram_d27 ab11 nvcc_dram ddr alt0 dram_data27 input 100 k ? pull-up dram_d28 ac9 nvcc_dram ddr alt0 dram_data28 input 100 k ? pull-up dram_d29 ad9 nvcc_dram ddr alt0 dram_data29 input 100 k ? pull-up dram_d3 aa5 nvcc_dram ddr alt0 dram_data03 input 100 k ? pull-up dram_d30 ad11 nvcc_dram ddr alt0 dram_data30 input 100 k ? pull-up dram_d31 ac11 nvcc_dram ddr alt0 dram_data31 input 100 k ? pull-up note: dram_d32 to dram_d63 are only available for i.mx 6d uallite chip; for i.mx 6sol o chip, these pins are nc. dram_d32 aa17 nvcc_dram ddr alt0 dram_data32 input 100 k ? pull-up dram_d33 aa18 nvcc_dram ddr alt0 dram_data33 input 100 k ? pull-up dram_d34 ac18 nvcc_dram ddr alt0 dram_data34 input 100 k ? pull-up dram_d35 ae19 nvcc_dram ddr alt0 dram_data35 input 100 k ? pull-up dram_d36 y17 nvcc_dram ddr alt0 dram_data36 input 100 k ? pull-up dram_d37 y18 nvcc_dram ddr alt0 dram_data37 input 100 k ? pull-up dram_d38 ab19 nvcc_dram ddr alt0 dram_data38 input 100 k ? pull-up dram_d39 ac19 nvcc_dram ddr alt0 dram_data39 input 100 k ? pull-up dram_d4 ac1 nvcc_dram ddr alt0 dram_data04 input 100 k ? pull-up dram_d40 y19 nvcc_dram ddr alt0 dram_data40 input 100 k ? pull-up dram_d41 ab20 nvcc_dram ddr alt0 dram_data41 input 100 k ? pull-up dram_d42 ab21 nvcc_dram ddr alt0 dram_data42 input 100 k ? pull-up dram_d43 ad21 nvcc_dram ddr alt0 dram_data43 input 100 k ? pull-up dram_d44 y20 nvcc_dram ddr alt0 dram_data44 input 100 k ? pull-up dram_d45 aa20 nvcc_dram ddr alt0 dram_data45 input 100 k ? pull-up dram_d46 ae21 nvcc_dram ddr alt0 dram_data46 input 100 k ? pull-up dram_d47 ac21 nvcc_dram ddr alt0 dram_data47 input 100 k ? pull-up dram_d48 ac22 nvcc_dram ddr alt0 dram_data48 input 100 k ? pull-up dram_d49 ae22 nvcc_dram ddr alt0 dram_data49 input 100 k ? pull-up dram_d5 ad1 nvcc_dram ddr alt0 dram_data05 input 100 k ? pull-up dram_d50 ae24 nvcc_dram ddr alt0 dram_data50 input 100 k ? pull-up dram_d51 ac24 nvcc_dram ddr alt0 dram_data51 input 100 k ? pull-up table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 149 dram_d52 ab22 nvcc_dram ddr alt0 dram_data52 input 100 k ? pull-up dram_d53 ac23 nvcc_dram ddr alt0 dram_data53 input 100 k ? pull-up dram_d54 ad25 nvcc_dram ddr alt0 dram_data54 input 100 k ? pull-up dram_d55 ac25 nvcc_dram ddr alt0 dram_data55 input 100 k ? pull-up dram_d56 ab25 nvcc_dram ddr alt0 dram_data56 input 100 k ? pull-up dram_d57 aa21 nvcc_dram ddr alt0 dram_data57 input 100 k ? pull-up dram_d58 y25 nvcc_dram ddr alt0 dram_data58 input 100 k ? pull-up dram_d59 y22 nvcc_dram ddr alt0 dram_data59 input 100 k ? pull-up dram_d6 ab4 nvcc_dram ddr alt0 dram_data06 input 100 k ? pull-up dram_d60 ab23 nvcc_dram ddr alt0 dram_data60 input 100 k ? pull-up dram_d61 aa23 nvcc_dram ddr alt0 dram_data61 input 100 k ? pull-up dram_d62 y23 nvcc_dram ddr alt0 dram_data62 input 100 k ? pull-up dram_d63 w25 nvcc_dram ddr alt0 dram_data63 input 100 k ? pull-up dram_d7 ae4 nvcc_dram ddr alt0 dram_data07 input 100 k ? pull-up dram_d8 ad5 nvcc_dram ddr alt0 dram_data08 input 100 k ? pull-up dram_d9 ae5 nvcc_dram ddr alt0 dram_data09 input 100 k ? pull-up dram_dqm0 ac3 nvcc_dram ddr alt0 dram_dqm0 output low dram_dqm1 ac6 nvcc_dram ddr alt0 dram_dqm1 output low dram_dqm2 ab8 nvcc_dram ddr alt0 dram_dqm2 output low dram_dqm3 ae10 nvcc_dram ddr alt0 dram_dqm3 output low dram_dqm4 ab18 nvcc_dram ddr alt0 dram_dqm4 output low dram_dqm5 ac20 nvcc_dram ddr alt0 dram_dqm5 output low dram_dqm6 ad24 nvcc_dram ddr alt0 dram_dqm6 output low dram_dqm7 y21 nvcc_dram ddr alt0 dram_dqm7 output low dram_ras ab15 nvcc_dram ddr alt0 dram_ras output low dram_reset y6 nvcc_dram ddr alt0 dram_reset output low dram_sdba0 ac15 nvcc_dram ddr alt0 dram_sdba0 output low dram_sdba1 y15 nvcc_dram ddr alt0 dram_sdba1 output low dram_sdba2 ab12 nvcc_dram ddr alt0 dram_sdba2 output low dram_sdcke0 y11 nvcc_dram ddr alt0 dram_sdcke0 output low dram_sdcke1 aa11 nvcc_dram ddr alt0 dram_sdcke1 output low dram_sdclk_0 ad15 nvcc_dram ddrclk alt0 dram_sdclk0_p output low dram_sdclk_0_b ae15 nvcc_dram ? ? dram_sdclk0_n ? ? dram_sdclk_1 ad14 nvcc_dram ddrclk alt0 dram_sdclk1_p output low dram_sdclk_1_b ae14 nvcc_dram ? ? dram_sdclk1_n ? ? dram_sdodt0 ac16 nvcc_dram ddr alt0 dram_odt0 output low table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 150 freescale semiconductor package information and contact assignments dram_sdodt1 ab17 nvcc_dram ddr alt0 dram_odt1 output low dram_sdqs0 ae3 nvcc_dram ddrclk alt0 dram_sdqs0_p input hi-z dram_sdqs0_b ad3 nvcc_dram ? ? dram_sdqs0_n ? ? dram_sdqs1 ad6 nvcc_dram ddrclk alt0 dram_sdqs1_p input hi-z dram_sdqs1_b ae6 nvcc_dram ? ? dram_sdqs1_n ? ? dram_sdqs2 ad8 nvcc_dram ddrclk alt0 dram_sdqs2_p input hi-z dram_sdqs2_b ae8 nvcc_dram ? ? dram_sdqs2_n ? ? dram_sdqs3 ac10 nvcc_dram ddrclk alt0 dram_sdqs3_p input hi-z dram_sdqs3_b ab10 nvcc_dram ? ? dram_sdqs3_n ? ? dram_sdqs4 ad18 nvcc_dram ddrclk alt0 dram_sdqs4_p input hi-z dram_sdqs4_b ae18 nvcc_dram ? ? dram_sdqs4_n ? ? dram_sdqs5 ad20 nvcc_dram ddrclk alt0 dram_sdqs5_p input hi-z dram_sdqs5_b ae20 nvcc_dram ? ? dram_sdqs5_n ? ? dram_sdqs6 ad23 nvcc_dram ddrclk alt0 dram_sdqs6_p input hi-z dram_sdqs6_b ae23 nvcc_dram ? ? dram_sdqs6_n ? ? dram_sdqs7 aa25 nvcc_dram ddrclk alt0 dram_sdqs7_p input hi-z dram_sdqs7_b aa24 nvcc_dram ? ? dram_sdqs7_n ? ? dram_sdwe ab16 nvcc_dram ddr alt0 dram_sdwe output low dsi_clk0m h3 nvcc_mipi analog ? dsi_clk_n ? ? dsi_clk0p h4 nvcc_mipi analog ? dsi_clk_p ? ? dsi_d0m g2 nvcc_mipi analog ? dsi_data0_n ? ? dsi_d0p g1 nvcc_mipi analog ? dsi_data0_p ? ? dsi_d1m h2 nvcc_mipi analog ? dsi_data1_n ? ? dsi_d1p h1 nvcc_mipi analog ? dsi_data1_p ? ? eim_a16 h25 nvcc_eim gpio alt0 eim_addr16 output low eim_a17 g24 nvcc_eim gpio alt0 eim_addr17 output low eim_a18 j22 nvcc_eim gpio alt0 eim_addr18 output low eim_a19 g25 nvcc_eim gpio alt0 eim_addr19 output low eim_a20 h22 nvcc_eim gpio alt0 eim_addr20 output low eim_a21 h23 nvcc_eim gpio alt0 eim_addr21 output low eim_a22 f24 nvcc_eim gpio alt0 eim_addr22 output low eim_a23 j21 nvcc_eim gpio alt0 eim_addr23 output low eim_a24 f25 nvcc_eim gpio alt0 eim_addr24 output low eim_a25 h19 nvcc_eim gpio alt0 eim_addr25 output low eim_bclk n22 nvcc_eim gpio alt0 eim_bclk output low eim_cs0 h24 nvcc_eim gpio alt0 eim_cs0 output high table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 151 eim_cs1 j23 nvcc_eim gpio alt0 eim_cs1 output high eim_d16 c25 nvcc_eim gpio alt5 gpio3_io16 input 100 k ? pull-up eim_d17 f21 nvcc_eim gpio alt5 gpio3_io17 input 100 k ? pull-up eim_d18 d24 nvcc_eim gpio alt5 gpio3_io18 input 100 k ? pull-up eim_d19 g21 nvcc_eim gpio alt 5 gpio3_io19 input 100 k ? pull-up eim_d20 g20 nvcc_eim gpio alt 5 gpio3_io20 input 100 k ? pull-up eim_d21 h20 nvcc_eim gpio alt5 gpio3_io21 input 100 k ? pull-up eim_d22 e23 nvcc_eim gpio alt5 gpio3_io22 input 100 k ? pull-down eim_d23 d25 nvcc_eim gpio alt5 gpio3_io23 input 100 k ? pull-up eim_d24 f22 nvcc_eim gpio alt5 gpio3_io24 input 100 k ? pull-up eim_d25 g22 nvcc_eim gpio alt 5 gpio3_io25 input 100 k ? pull-up eim_d26 e24 nvcc_eim gpio alt5 gpio3_io26 input 100 k ? pull-up eim_d27 e25 nvcc_eim gpio alt5 gpio3_io27 input 100 k ? pull-up eim_d28 g23 nvcc_eim gpio alt 5 gpio3_io28 input 100 k ? pull-up eim_d29 j19 nvcc_eim gpio alt 5 gpio3_io29 input 100 k ? pull-up eim_d30 j20 nvcc_eim gpio alt 5 gpio3_io30 input 100 k ? pull-up eim_d31 h21 nvcc_eim gpio alt5 gpio3_io31 input 100 k ? pull-down eim_da0 l20 nvcc_eim gpio alt0 eim_ad00 input 100 k ? pull-up eim_da1 j25 nvcc_eim gpio alt0 eim_ad01 input 100 k ? pull-up eim_da10 m22 nvcc_eim gpio alt0 eim_ad10 input 100 k ? pull-up eim_da11 m20 nvcc_eim gpio alt0 eim_ad11 input 100 k ? pull-up eim_da12 m24 nvcc_eim gpio alt0 eim_ad12 input 100 k ? pull-up eim_da13 m23 nvcc_eim gpio alt0 eim_ad13 input 100 k ? pull-up eim_da14 n23 nvcc_eim gpio alt0 eim_ad14 input 100 k ? pull-up eim_da15 n24 nvcc_eim gpio alt0 eim_ad15 input 100 k ? pull-up eim_da2 l21 nvcc_eim gpio alt0 eim_ad02 input 100 k ? pull-up eim_da3 k24 nvcc_eim gpio alt0 eim_ad03 input 100 k ? pull-up eim_da4 l22 nvcc_eim gpio alt0 eim_ad04 input 100 k ? pull-up eim_da5 l23 nvcc_eim gpio alt0 eim_ad05 input 100 k ? pull-up eim_da6 k25 nvcc_eim gpio alt0 eim_ad06 input 100 k ? pull-up eim_da7 l25 nvcc_eim gpio alt0 eim_ad07 input 100 k ? pull-up eim_da8 l24 nvcc_eim gpio alt0 eim_ad08 input 100 k ? pull-up eim_da9 m21 nvcc_eim gpio alt0 eim_ad09 input 100 k ? pull-up eim_eb0 k21 nvcc_eim gpio a lt0 eim_eb0 output high eim_eb1 k23 nvcc_eim gpio a lt0 eim_eb1 output high eim_eb2 e22 nvcc_eim gpio alt 5 gpio2_io30 input 100 k ? pull-up table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 152 freescale semiconductor package information and contact assignments eim_eb3 f23 nvcc_eim gpio alt 5 gpio2_io31 input 100 k ? pull-up eim_lba k22 nvcc_eim gpio alt0 eim_lba output high eim_oe j24 nvcc_eim gpio alt0 eim_oe output high eim_rw k20 nvcc_eim gpio alt0 eim_rw output high eim_wait m25 nvcc_eim gpio a lt0 eim_wait input 100 k ? pull-up enet_crs_dv u21 nvcc_enet gpio alt5 gpio1_io25 input 100 k ? pull-up enet_mdc v20 nvcc_enet gpio alt5 gpio1_io31 input 100 k ? pull-up enet_mdio v23 nvcc_enet gpio a lt5 gpio1_io22 input 100 k ? pull-up enet_ref_clk 3 v22 nvcc_enet gpio alt5 gpio1_io23 input 100 k ? pull-up enet_rx_er w23 nvcc_enet gpio alt5 gpio1_io24 input 100 k ? pull-up enet_rxd0 w21 nvcc_enet gpio alt5 gpio1_io27 input 100 k ? pull-up enet_rxd1 w22 nvcc_enet gpio alt5 gpio1_io26 input 100 k ? pull-up enet_tx_en v21 nvcc_enet gpio alt5 gpio1_io28 input 100 k ? pull-up enet_txd0 u20 nvcc_enet gpio alt5 gpio1_io30 input 100 k ? pull-up enet_txd1 w20 nvcc_enet gpio alt5 gpio1_io29 input 100 k ? pull-up gpio_0 t5 nvcc_gpio gpio alt5 gpio1_io00 input 100 k ? pull-down gpio_1 t4 nvcc_gpio gpio alt5 gpio1_io01 input 100 k ? pull-up gpio_16 r2 nvcc_gpio gpio alt5 gpio7_io11 input 100 k ? pull-up gpio_17 r1 nvcc_gpio gpio alt5 gpio7_io12 input 100 k ? pull-up gpio_18 p6 nvcc_gpio gpio alt5 gpio7_io13 input 100 k ? pull-up gpio_19 p5 nvcc_gpio gpio alt5 gpio4_io05 input 100 k ? pull-up gpio_2 t1 nvcc_gpio gpio alt5 gpio1_io02 input 100 k ? pull-up gpio_3 r7 nvcc_gpio gpio alt5 gpio1_io03 input 100 k ? pull-up gpio_4 r6 nvcc_gpio gpio alt5 gpio1_io04 input 100 k ? pull-up gpio_5 r4 nvcc_gpio gpio alt5 gpio1_io05 input 100 k ? pull-up gpio_6 t3 nvcc_gpio gpio alt5 gpio1_io06 input 100 k ? pull-up gpio_7 r3 nvcc_gpio gpio alt5 gpio1_io07 input 100 k ? pull-up gpio_8 r5 nvcc_gpio gpio alt5 gpio1_io08 input 100 k ? pull-up gpio_9 t2 nvcc_gpio gpio alt5 gpio1_io09 input 100 k ? pull-up hdmi_clkm j5 hdmi ? ? hdmi_tx_clk_n ? ? hdmi_clkp j6 hdmi ? ? hdmi_tx_clk_p ? ? hdmi_d0m k5 hdmi ? ? hdmi_tx_data0_n ? ? hdmi_d0p k6 hdmi ? ? hdmi_tx_data0_p ? ? hdmi_d1m j3 hdmi ? ? hdmi_tx_data1_n ? ? hdmi_d1p j4 hdmi ? ? hdmi_tx_data1_p ? ? hdmi_d2m k3 hdmi ? ? hdmi_tx_data2_n ? ? table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 153 hdmi_d2p k4 hdmi ? ? hdmi_tx_data2_p ? ? hdmi_hpd k1 hdmi ? ? hdmi_tx_hpd ? ? jtag_mod h6 nvcc_jtag gpio alt0 jtag_mode input 100 k ? pull-up jtag_tck h5 nvcc_jtag gpio alt0 jtag_tck input 47 k ? pull-up jtag_tdi g5 nvcc_jtag gpio alt0 jtag_tdi input 47 k ? pull-up jtag_tdo g6 nvcc_jtag gpio alt0 jtag_tdo output low jtag_tms c3 nvcc_jtag gpio alt0 jtag_tms input 47 k ? pull-up jtag_trstb c2 nvcc_jtag gpio alt0 jtag_trstb input 47 k ? pull-up key_col0 w5 nvcc_gpio gpio alt5 gpio4_io06 input 100 k ? pull-up key_col1 u7 nvcc_gpio gpio alt5 gpio4_io08 input 100 k ? pull-up key_col2 w6 nvcc_gpio gpio alt5 gpio4_io10 input 100 k ? pull-up key_col3 u5 nvcc_gpio gpio alt5 gpio4_io12 input 100 k ? pull-up key_col4 t6 nvcc_gpio gpio alt5 gpio4_io14 input 100 k ? pull-up key_row0 v6 nvcc_gpio gpio alt5 gpio4_io07 input 100 k ? pull-up key_row1 u6 nvcc_gpio gpio alt5 gpio4_io09 input 100 k ? pull-up key_row2 w4 nvcc_gpio gpio alt5 gpio4_io11 input 100 k ? pull-up key_row3 t7 nvcc_gpio gpio alt5 gpio4_io13 input 100 k ? pull-up key_row4 v5 nvcc_gpio gpio alt5 gpio4_io15 input 100 k ? pull-down lvds0_clk_n v4 nvcc_lvds2p5 ? ? lvds0_clk_n ? ? lvds0_clk_p v3 nvcc_lvds2p5 ? alt0 lvds0_clk_p input keeper lvds0_tx0_n u2 nvcc_lvds2p5 ? ? lvds0_tx0_n ? ? lvds0_tx0_p u1 nvcc_lvds2p5 ? alt0 lvds0_tx0_p input keeper lvds0_tx1_n u4 nvcc_lvds2p5 ? ? lvds0_tx1_n ? ? lvds0_tx1_p u3 nvcc_lvds2p5 ? alt0 lvds0_tx1_p input keeper lvds0_tx2_n v2 nvcc_lvds2p5 ? ? lvds0_tx2_n ? ? lvds0_tx2_p v1 nvcc_lvds2p5 ? alt0 lvds0_tx2_p input keeper lvds0_tx3_n w2 nvcc_lvds2p5 ? ? lvds0_tx3_n ? ? lvds0_tx3_p w1 nvcc_lvds2p5 ? alt0 lvds0_tx3_p input keeper lvds1_clk_n y3 nvcc_lvds2p5 ? ? lvds1_clk_n ? ? lvds1_clk_p y4 nvcc_lvds2p5 ? alt0 lvds1_clk_p input keeper lvds1_tx0_n y1 nvcc_lvds2p5 ? ? lvds1_tx0_n ? ? lvds1_tx0_p y2 nvcc_lvds2p5 ? alt0 lvds1_tx0_p input keeper lvds1_tx1_n aa2 nvcc_lvds2p5 ? ? lvds1_tx1_n ? ? lvds1_tx1_p aa1 nvcc_lvds2p5 ? alt0 lvds1_tx1_p input keeper lvds1_tx2_n ab1 nvcc_lvds2p5 ? ? lvds1_tx2_n ? ? lvds1_tx2_p ab2 nvcc_lvds2p5 ? alt0 lvds1_tx2_p input keeper table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 154 freescale semiconductor package information and contact assignments lvds1_tx3_n aa3 nvcc_lvds2p5 ? ? lvds1_tx3_n ? ? lvds1_tx3_p aa4 nvcc_lvds2p5 ? alt0 lvds1_tx3_p input keeper mlb_cn a11 vddhigh_cap mlb_clk_n mlb_cp b11 vddhigh_cap mlb_clk_p mlb_dn b10 vddhigh_cap mlb_data_n mlb_dp a10 vddhigh_cap mlb_data_p mlb_sn a9 vddhigh_cap mlb_sig_n mlb_sp b9 vddhigh_cap mlb_sig_p nandf_ale a16 nvcc_nandf gpio alt5 gpio6_io08 input 100 k ? pull-up nandf_cle c15 nvcc_nandf gpio alt5 gpio6_io07 input 100 k ? pull-up nandf_cs0 f15 nvcc_nandf gpio alt5 gpio6_io11 input 100 k ? pull-up nandf_cs1 c16 nvcc_nandf gpio alt5 gpio6_io14 input 100 k ? pull-up nandf_cs2 a17 nvcc_nandf gpio alt5 gpio6_io15 input 100 k ? pull-up nandf_cs3 d16 nvcc_nandf gpio alt5 gpio6_io16 input 100 k ? pull-up nandf_d0 a18 nvcc_nandf gpio alt5 gpio2_io00 input 100 k ? pull-up nandf_d1 c17 nvcc_nandf gpio alt5 gpio2_io01 input 100 k ? pull-up nandf_d2 f16 nvcc_nandf gpio alt5 gpio2_io02 input 100 k ? pull-up nandf_d3 d17 nvcc_nandf gpio alt5 gpio2_io03 input 100 k ? pull-up nandf_d4 a19 nvcc_nandf gpio alt5 gpio2_io04 input 100 k ? pull-up nandf_d5 b18 nvcc_nandf gpio alt5 gpio2_io05 input 100 k ? pull-up nandf_d6 e17 nvcc_nandf gpio alt5 gpio2_io06 input 100 k ? pull-up nandf_d7 c18 nvcc_nandf gpio alt5 gpio2_io07 input 100 k ? pull-up nandf_rb0 b16 nvcc_nandf gpio alt5 gpio6_io10 input 100 k ? pull-up nandf_wp_b e15 nvcc_nandf gpio alt5 gpio6_io09 input 100 k ? pull-up onoff d12 vdd_snvs_in gpio alt0 src_onoff input 100 k ? pull-up pcie_rxm b1 pcie_vph ? ? pcie_rx_n ? ? pcie_rxp b2 pcie_vph ? ? pcie_rx_p ? ? pcie_txm a3 pcie_vph ? ? pcie_tx_n ? ? pcie_txp b3 pcie_vph ? ? pcie_tx_p ? ? pmic_on_req d11 vdd_snvs_in gpio alt0 sn vs_pmic_on_req output open drain with pu(100k) enable pmic_stby_req f11 vdd_snvs_in gpio alt0 ccm_pmic_stby_req output low por_b c11 vdd_snvs_in gpio alt0 src_por_b input 100 k ? pull-up rgmii_rd0 c24 nvcc_rgmii ddr alt5 gpio6_io25 input 100 k ? pull-up rgmii_rd1 b23 nvcc_rgmii ddr alt5 gpio6_io27 input 100 k ? pull-up rgmii_rd2 b24 nvcc_rgmii ddr alt5 gpio6_io28 input 100 k ? pull-up table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 155 rgmii_rd3 d23 nvcc_rgmii ddr alt5 gpio6_io29 input 100 k ? pull-up rgmii_rx_ctl d22 nvcc_rgmii ddr alt5 gpio6_io24 input 100 k ? pull-down rgmii_rxc b25 nvcc_rgmii ddr alt5 gpio6_io30 input 100 k ? pull-down rgmii_td0 c22 nvcc_rgmii ddr alt5 gpio6_io20 input 100 k ? pull-up rgmii_td1 f20 nvcc_rgmii ddr alt5 gpio6_io21 input 100 k ? pull-up rgmii_td2 e21 nvcc_rgmii ddr alt5 gpio6_io22 input 100 k ? pull-up rgmii_td3 a24 nvcc_rgmii ddr alt5 gpio6_io23 input 100 k ? pull-up rgmii_tx_ctl c23 nvcc_rgmii ddr alt5 gpio6_io26 input 100 k ? pull-down rgmii_txc d21 nvcc_rgmii ddr alt5 gpio6_io19 input 100 k ? pull-down rtc_xtali d9 vdd_snvs_cap ? ? rtc_xtali ? ? rtc_xtalo c9 vdd_snvs_cap ? ? rtc_xtalo ? ? sd1_clk d20 nvcc_sd1 gpio alt5 gpio1_io20 input 100 k ? pull-up sd1_cmd b21 nvcc_sd1 gpio alt 5 gpio1_io18 input 100 k ? pull-up sd1_dat0 a21 nvcc_sd1 gpio alt5 gpio1_io16 input 100 k ? pull-up sd1_dat1 c20 nvcc_sd1 gpio alt5 gpio1_io17 input 100 k ? pull-up sd1_dat2 e19 nvcc_sd1 gpio alt5 gpio1_io19 input 100 k ? pull-up sd1_dat3 f18 nvcc_sd1 gpio alt5 gpio1_io21 input 100 k ? pull-up sd2_clk c21 nvcc_sd2 gpio alt5 gpio1_io10 input 100 k ? pull-up sd2_cmd f19 nvcc_sd2 gpio alt5 gpio1_io11 input 100 k ? pull-up sd2_dat0 a22 nvcc_sd2 gpio alt5 gpio1_io15 input 100 k ? pull-up sd2_dat1 e20 nvcc_sd2 gpio alt5 gpio1_io14 input 100 k ? pull-up sd2_dat2 a23 nvcc_sd2 gpio alt5 gpio1_io13 input 100 k ? pull-up sd2_dat3 b22 nvcc_sd2 gpio alt5 gpio1_io12 input 100 k ? pull-up sd3_clk d14 nvcc_sd3 gpio alt5 gpio7_io03 input 100 k ? pull-up sd3_cmd b13 nvcc_sd3 gpio alt 5 gpio7_io02 input 100 k ? pull-up sd3_dat0 e14 nvcc_sd3 gpio alt5 gpio7_io04 input 100 k ? pull-up sd3_dat1 f14 nvcc_sd3 gpio alt5 gpio7_io05 input 100 k ? pull-up sd3_dat2 a15 nvcc_sd3 gpio alt5 gpio7_io06 input 100 k ? pull-up sd3_dat3 b15 nvcc_sd3 gpio alt5 gpio7_io07 input 100 k ? pull-up sd3_dat4 d13 nvcc_sd3 gpio alt5 gpio7_io01 input 100 k ? pull-up sd3_dat5 c13 nvcc_sd3 gpio alt5 gpio7_io00 input 100 k ? pull-up sd3_dat6 e13 nvcc_sd3 gpio alt5 gpio6_io18 input 100 k ? pull-up sd3_dat7 f13 nvcc_sd3 gpio alt5 gpio6_io17 input 100 k ? pull-up sd3_rst d15 nvcc_sd3 gpio alt5 gpio7_io08 input 100 k ? pull-up sd4_clk e16 nvcc_nandf gpio alt5 gpio7_io10 input 100 k ? pull-up sd4_cmd b17 nvcc_nandf gpio alt5 gpio7_io09 input 100 k ? pull-up table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 156 freescale semiconductor package information and contact assignments sd4_dat0 d18 nvcc_nandf gpio alt5 gpio2_io08 input 100 k ? pull-up sd4_dat1 b19 nvcc_nandf gpio alt5 gpio2_io09 input 100 k ? pull-up sd4_dat2 f17 nvcc_nandf gpio alt5 gpio2_io10 input 100 k ? pull-up sd4_dat3 a20 nvcc_nandf gpio alt5 gpio2_io11 input 100 k ? pull-up sd4_dat4 e18 nvcc_nandf gpio alt5 gpio2_io12 input 100 k ? pull-up sd4_dat5 c19 nvcc_nandf gpio alt5 gpio2_io13 input 100 k ? pull-up sd4_dat6 b20 nvcc_nandf gpio alt5 gpio2_io14 input 100 k ? pull-up sd4_dat7 d19 nvcc_nandf gpio alt5 gpio2_io15 input 100 k ? pull-up tamper e11 vdd_snvs_in gpio alt0 snvs_tamper input 100 k ? pull-down test_mode e12 vdd_snvs_in gpio alt0 tcu_test_mode input 100 k ? pull-down usb_h1_dn f10 vddusb_cap ? ? usb_h1_dn ? ? usb_h1_dp e10 vddusb_cap ? ? usb_h1_dp ? ? usb_otg_chd_b b8 vddusb_cap ? ? usb_otg_chd_b ? ? usb_otg_dn b6 vddusb_cap ? ? usb_otg_dn ? ? usb_otg_dp a6 vddusb_cap ? ? usb_otg_dp ? ? xtali a7 nvcc_pll_out ? ? xtali ? ? xtalo b7 nvcc_pll_out ? ? xtalo ? ? 1 the state immediately after reset and before rom firmware or software has executed. 2 variance of the pull-up and pull-down strengt hs are shown in the tables as follows: ? table 24, "gpio dc parameters," on page 40 ? table 25, "lpddr2 i/o dc electrical parameters," on page 41 ? table 26, "ddr3/ddr3l i/o dc electrical characteristics," on page 41 3 enet_ref_clk is used as a clock source for mii and rgmii modes only. rmgii mode uses either gpio_16 or rgmii_tx_ctl as a clock source. for more information on thes e clocks, see the device reference manual and the hardware development guide for i.mx 6quad, 6dual, 6duallite, 6sol o families of applications processors (imx6dq6sdlhdg). table 102. signals with differing before reset and after reset states ball name before reset state input/output value eim_a16 input pd (100k) eim_a17 input pd (100k) eim_a18 input pd (100k) eim_a19 input pd (100k) eim_a20 input pd (100k) eim_a21 input pd (100k) table 101. 21 x 21 mm functional contact assignments (continued) ball name ball power group ball type out of reset condition 1 default mode (reset mode) default function input/ output value 2
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 157 eim_a22 input pd (100k) eim_a23 input pd (100k) eim_a24 input pd (100k) eim_a25 input pd (100k) eim_da0 input pd (100k) eim_da1 input pd (100k) eim_da2 input pd (100k) eim_da3 input pd (100k) eim_da4 input pd (100k) eim_da5 input pd (100k) eim_da6 input pd (100k) eim_da7 input pd (100k) eim_da8 input pd (100k) eim_da9 input pd (100k) eim_da10 input pd (100k) eim_da11 input pd (100k) eim_da12 input pd (100k) eim_da13 input pd (100k) eim_da14 input pd (100k) eim_da15 input pd (100k) eim_eb0 input pd (100k) eim_eb1 input pd (100k) eim_eb2 input pd (100k) eim_eb3 input pd (100k) eim_lba input pd (100k) eim_rw input pd (100k) eim_wait input pd (100k) gpio_17 output drive state unknown (x) gpio_19 output drive state unknown (x) key_col0 output drive state unknown (x) table 102. signals with differing before reset and after reset states (continued) ball name before reset state input/output value
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 158 freescale semiconductor package information and contact assignments 6.2.3 21 x 21 mm, 0.8 mm pitch ball map table 103 shows the 21 x 21 mm, 0.8 mm pitch ball map for the i.mx 6solo. table 103. 21 x 21 mm, 0.8 mm pitch ball map i.mx 6solo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a nc pcie_rext pcie_txm gnd fa_ana usb_otg_dp xtali gnd mlb_sn mlb_dp mlb_cn nc gnd nc sd3_dat2 nandf_ale nandf_cs2 nandf_d0 nandf_d4 sd4_dat3 sd1_dat0 sd2_dat0 sd2_dat2 rgmii_td3 gnd a b pcie_rxm pcie_rxp pcie_txp gnd vdd_fa usb_otg_dn xtalo usb_otg_chd_b mlb_sp mlb_dn mlb_cp nc sd3_cmd nc sd3_dat3 nandf_rb0 sd4_cmd nandf_d5 sd4_dat1 sd4_dat6 sd1_cmd sd2_dat3 rgmii_rd1 rgmii_rd2 rgmii_rxc b c gnd jtag_trstb jtag_tms gnd clk2_n gnd clk1_n gpanaio rtc_xtalo gnd por_b boot_mode0 sd3_dat5 nc nandf_cle nandf_cs1 nandf_d1 nandf_d7 sd4_dat5 sd1_dat1 sd2_clk rgmii_td0 rgmii_tx_ctl rgmii_rd0 eim_d16 c d csi_d1m csi_d1p gnd csi_rext clk2_p gnd clk1_p gnd rtc_xtali usb_h1_vbus pmic_on_req onoff sd3_dat4 sd3_clk sd3_rst nandf_cs3 nandf_d3 sd4_dat0 sd4_dat7 sd1_clk rgmii_txc rgmii_rx_ctl rgmii_rd3 eim_d18 eim_d23 d e nc nc csi_d0p csi_d0m gnd gnd gnd nvcc_pll_out usb_otg_vbus usb_h1_dp tamper test_mode sd3_dat6 sd3_dat0 nandf_wp_b sd4_clk nandf_d6 sd4_dat4 sd1_dat2 sd2_dat1 rgmii_td2 eim_eb2 eim_d22 eim_d26 eim_d27 e f nc nc csi_clk0p csi_clk0m gnd gnd gnd gnd vddusb_cap usb_h1_dn pmic_stby_req boot_mode1 sd3_dat7 sd3_dat1 nandf_cs0 nandf_d2 sd4_dat2 sd1_dat3 sd2_cmd rgmii_td1 eim_d17 eim_d24 eim_eb3 eim_a22 eim_a24 f g dsi_d0p dsi_d0m gnd dsi_rext jtag_tdi jtag_tdo pcie_vph pcie_vptx vdd_snvs_cap gnd vdd_snvs_in nc nc nvcc_sd3 nvcc_nandf nvcc_sd1 nvcc_sd2 nvcc_rgmii gnd eim_d20 eim_d19 eim_d25 eim_d28 eim_a17 eim_a19 g
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 159 h dsi_d1p dsi_d1m dsi_clk0m dsi_clk0p jtag_tck jtag_mod pcie_vp gnd vddhigh_in vddhigh_cap vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd eim_a25 eim_d21 eim_d31 eim_a20 eim_a21 eim_cs0 eim_a16 h j hdmi_ref gnd hdmi_d1m hdmi_d1p hdmi_clkm hdmi_clkp nvcc_jtag gnd vddhigh_in vddhigh_cap vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd eim_d29 eim_d30 eim_a23 eim_a18 eim_cs1 eim_oe eim_da1 j k hdmi_hpd hdmi_ddccec hdmi_d2m hdmi_d2p hdmi_d0m hdmi_d0p nvcc_mipi gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_eim eim_rw eim_eb0 eim_lba eim_eb1 eim_da3 eim_da6 k l csi0_dat13 gnd csi0_dat17 csi0_dat16 gnd csi0_dat19 hdmi_vp gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_eim eim_da0 eim_da2 eim_da4 eim_da5 eim_da8 eim_da7 l m csi0_dat10 csi0_dat12 csi0_dat11 csi0_dat14 csi0_dat15 csi0_dat18 hdmi_vph gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_eim eim_da11 eim_da9 eim_da10 eim_da13 eim_da12 eim_wait m n csi0_dat4 csi0_vsync csi0_dat7 csi0_dat6 csi0_dat9 csi0_dat8 nvcc_csi gnd vddarm_in gnd vddarm_cap nc vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd di0_disp_clk di0_pin3 di0_pin15 eim_bclk eim_da14 eim_da15 di0_pin2 n p csi0_pixclk csi0_dat5 csi0_data_en csi0_mclk gpio_19 gpio_18 nvcc_gpio gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_lcd disp0_dat4 disp0_dat3 disp0_dat1 disp0_dat2 disp0_dat0 di0_pin4 p r gpio_17 gpio_16 gpio_7 gpio_5 gpio_8 gpio_4 gpio_3 gnd vddarm_in vddsoc_cap vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in gnd nvcc_dram nvcc_enet disp0_dat13 disp0_dat10 disp0_dat8 disp0_dat6 disp0_dat7 disp0_dat5 r table 103. 21 x 21 mm, 0.8 mm pitch ball map i.mx 6solo (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 160 freescale semiconductor package information and contact assignments t gpio_2 gpio_9 gpio_6 gpio_1 gpio_0 key_col4 key_row3 gnd vddarm_in vddsoc_cap gnd gnd vddsoc_cap vddsoc_cap gnd vddsoc_in gnd nvcc_dram gnd disp0_dat21 disp0_dat16 disp0_dat15 disp0_dat11 disp0_dat12 disp0_dat9 t u lvds0_tx0_p lvds0_tx0_n lvds0_tx1_p lvds0_tx1_n key_col3 key_row1 key_col1 gnd vddarm_in vddsoc_cap gnd gnd vddsoc_cap vddsoc_cap gnd vddsoc_in gnd nvcc_dram gnd enet_txd0 enet_crs_dv disp0_dat20 disp0_dat19 disp0_dat17 disp0_dat14 u v lvds0_tx2_p lvds0_tx2_n lvds0_clk_p lvds0_clk_n key_row4 key_row0 nvcc_lvds2p5 gnd nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram gnd enet_mdc enet_tx_en enet_ref_clk enet_mdio disp0_dat22 disp0_dat18 v w lvds0_tx3_p lvds0_tx3_n gnd key_row2 key_col0 key_col2 gnd gnd gnd gnd gnd gnd gnd dram_a4 gnd gnd gnd gnd gnd enet_txd1 enet_rxd0 enet_rxd1 enet_rx_er disp0_dat23 nc w y lvds1_tx0_n lvds1_tx0_p lvds1_clk_n lvds1_clk_p gnd dram_reset dram_d20 dram_d21 dram_d19 dram_d25 dram_sdcke0 dram_a15 dram_a7 dram_a3 dram_sdba1 dram_cs0 nc nc nc nc nc nc nc gnd nc y aa lvds1_tx1_p lvds1_tx1_n lvds1_tx3_n lvds1_tx3_p dram_d3 dram_d10 gnd dram_d17 dram_d23 gnd dram_sdcke1 dram_a14 gnd dram_a2 dram_a10 gnd nc nc gnd nc nc gnd nc nc nc aa ab lvds1_tx2_n lvds1_tx2_p gnd dram_d6 dram_d12 dram_d14 dram_d16 dram_dqm2 dram_d18 dram_sdqs3_b dram_d27 dram_sdba2 dram_a8 dram_a1 dram_ras dram_sdwe dram_sdodt1 nc nc nc nc nc nc gnd nc ab ac dram_d4 dram_vref dram_dqm0 dram_d2 dram_d13 dram_dqm1 dram_d15 dram_d22 dram_d28 dram_sdqs3 dram_d31 dram_a11 dram_a6 dram_a0 dram_sdba0 dram_sdodt0 dram_a13 nc nc nc nc nc nc nc nc ac table 103. 21 x 21 mm, 0.8 mm pitc h ball map i.mx 6solo (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
document number: imx6sdlcec rev. 3 03/2014 how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provid ed solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm, the arm logo, and cortex are registered trademarks of arm limited. mpcore and neon are trademarks of arm limited. ? 2012-2014 freescale semiconductor, inc. all rights reserved. ad dram_d5 dram_d0 dram_sdqs0_b gnd dram_d8 dram_sdqs1 gnd dram_sdqs2 dram_d29 gnd dram_d30 dram_a12 gnd dram_sdclk_1 dram_sdclk_0 gnd dram_cs1 nc gnd nc nc gnd nc nc nc ad table 103. 21 x 21 mm, 0.8 mm pitc h ball map i.mx 6solo (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 162 freescale semiconductor package information and contact assignments table 104 shows the 21 x 21 mm, 0.8 mm pitch ball map for the i.mx 6duallite. ae gnd dram_d1 dram_sdqs0 dram_d7 dram_d9 dram_sdqs1_b dram_ dram_sdqs2_b dram_d24 dram_dqm3 dram_d26 dram_a9 dram_a5 dram_sdclk_1_b dram_sdclk_0_b dram_cas zqpad nc nc nc nc nc nc nc gnd ae 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 table 104. 21 x 21 mm, 0.8 mm pitch ball map i.mx 6duallite 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a nc pcie_rext pcie_txm gnd fa_ana usb_otg_dp xtali gnd mlb_sn mlb_dp mlb_cn nc gnd nc sd3_dat2 nandf_ale nandf_cs2 nandf_d0 nandf_d4 sd4_dat3 sd1_dat0 sd2_dat0 sd2_dat2 rgmii_td3 gnd a b pcie_rxm pcie_rxp pcie_txp gnd vdd_fa usb_otg_dn xtalo usb_otg_chd_b mlb_sp mlb_dn mlb_cp nc sd3_cmd nc sd3_dat3 nandf_rb0 sd4_cmd nandf_d5 sd4_dat1 sd4_dat6 sd1_cmd sd2_dat3 rgmii_rd1 rgmii_rd2 rgmii_rxc b c gnd jtag_trstb jtag_tms gnd clk2_n gnd clk1_n gpanaio rtc_xtalo gnd por_b boot_mode0 sd3_dat5 nc nandf_cle nandf_cs1 nandf_d1 nandf_d7 sd4_dat5 sd1_dat1 sd2_clk rgmii_td0 rgmii_tx_ctl rgmii_rd0 eim_d16 c d csi_d1m csi_d1p gnd csi_rext clk2_p gnd clk1_p gnd rtc_xtali usb_h1_vbus pmic_on_req onoff sd3_dat4 sd3_clk sd3_rst nandf_cs3 nandf_d3 sd4_dat0 sd4_dat7 sd1_clk rgmii_txc rgmii_rx_ctl rgmii_rd3 eim_d18 eim_d23 d e nc nc csi_d0p csi_d0m gnd gnd gnd nvcc_pll_out usb_otg_vbus usb_h1_dp tamper test_mode sd3_dat6 sd3_dat0 nandf_wp_b sd4_clk nandf_d6 sd4_dat4 sd1_dat2 sd2_dat1 rgmii_td2 eim_eb2 eim_d22 eim_d26 eim_d27 e table 103. 21 x 21 mm, 0.8 mm pitc h ball map i.mx 6solo (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 163 f nc nc csi_clk0p csi_clk0m gnd gnd gnd gnd vddusb_cap usb_h1_dn pmic_stby_req boot_mode1 sd3_dat7 sd3_dat1 nandf_cs0 nandf_d2 sd4_dat2 sd1_dat3 sd2_cmd rgmii_td1 eim_d17 eim_d24 eim_eb3 eim_a22 eim_a24 f g dsi_d0p dsi_d0m gnd dsi_rext jtag_tdi jtag_tdo pcie_vph pcie_vptx vdd_snvs_cap gnd vdd_snvs_in nc nc nvcc_sd3 nvcc_nandf nvcc_sd1 nvcc_sd2 nvcc_rgmii gnd eim_d20 eim_d19 eim_d25 eim_d28 eim_a17 eim_a19 g h dsi_d1p dsi_d1m dsi_clk0m dsi_clk0p jtag_tck jtag_mod pcie_vp gnd vddhigh_in vddhigh_cap vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd eim_a25 eim_d21 eim_d31 eim_a20 eim_a21 eim_cs0 eim_a16 h j hdmi_ref gnd hdmi_d1m hdmi_d1p hdmi_clkm hdmi_clkp nvcc_jtag gnd vddhigh_in vddhigh_cap vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd eim_d29 eim_d30 eim_a23 eim_a18 eim_cs1 eim_oe eim_da1 j k hdmi_hpd hdmi_ddccec hdmi_d2m hdmi_d2p hdmi_d0m hdmi_d0p nvcc_mipi gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_eim eim_rw eim_eb0 eim_lba eim_eb1 eim_da3 eim_da6 k l csi0_dat13 gnd csi0_dat17 csi0_dat16 gnd csi0_dat19 hdmi_vp gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_eim eim_da0 eim_da2 eim_da4 eim_da5 eim_da8 eim_da7 l m csi0_dat10 csi0_dat12 csi0_dat11 csi0_dat14 csi0_dat15 csi0_dat18 hdmi_vph gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_eim eim_da11 eim_da9 eim_da10 eim_da13 eim_da12 eim_wait m n csi0_dat4 csi0_vsync csi0_dat7 csi0_dat6 csi0_dat9 csi0_dat8 nvcc_csi gnd vddarm_in gnd vddarm_cap nc vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd di0_disp_clk di0_pin3 di0_pin15 eim_bclk eim_da14 eim_da15 di0_pin2 n table 104. 21 x 21 mm, 0.8 mm pitch ball map i.mx 6duallite (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 164 freescale semiconductor package information and contact assignments p csi0_pixclk csi0_dat5 csi0_data_en csi0_mclk gpio_19 gpio_18 nvcc_gpio gnd vddarm_in gnd vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in vddpu_cap gnd nvcc_lcd disp0_dat4 disp0_dat3 disp0_dat1 disp0_dat2 disp0_dat0 di0_pin4 p r gpio_17 gpio_16 gpio_7 gpio_5 gpio_8 gpio_4 gpio_3 gnd vddarm_in vddsoc_cap vddarm_cap gnd vddarm_cap vddarm_in gnd vddsoc_in gnd nvcc_dram nvcc_enet disp0_dat13 disp0_dat10 disp0_dat8 disp0_dat6 disp0_dat7 disp0_dat5 r t gpio_2 gpio_9 gpio_6 gpio_1 gpio_0 key_col4 key_row3 gnd vddarm_in vddsoc_cap gnd gnd vddsoc_cap vddsoc_cap gnd vddsoc_in gnd nvcc_dram gnd disp0_dat21 disp0_dat16 disp0_dat15 disp0_dat11 disp0_dat12 disp0_dat9 t u lvds0_tx0_p lvds0_tx0_n lvds0_tx1_p lvds0_tx1_n key_col3 key_row1 key_col1 gnd vddarm_in vddsoc_cap gnd gnd vddsoc_cap vddsoc_cap gnd vddsoc_in gnd nvcc_dram gnd enet_txd0 enet_crs_dv disp0_dat20 disp0_dat19 disp0_dat17 disp0_dat14 u v lvds0_tx2_p lvds0_tx2_n lvds0_clk_p lvds0_clk_n key_row4 key_row0 nvcc_lvds2p5 gnd nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram nvcc_dram gnd enet_mdc enet_tx_en enet_ref_clk enet_mdio disp0_dat22 disp0_dat18 v w lvds0_tx3_p lvds0_tx3_n gnd key_row2 key_col0 key_col2 gnd gnd gnd gnd gnd gnd gnd dram_a4 gnd gnd gnd gnd gnd enet_txd1 enet_rxd0 enet_rxd1 enet_rx_er disp0_dat23 dram_d63 w y lvds1_tx0_n lvds1_tx0_p lvds1_clk_n lvds1_clk_p gnd dram_reset dram_d20 dram_d21 dram_d19 dram_d25 dram_sdcke0 dram_a15 dram_a7 dram_a3 dram_sdba1 dram_cs0 dram_d36 dram_d37 dram_d40 dram_d44 dram_dqm7 dram_d59 dram_d62 gnd dram_d58 y aa lvds1_tx1_p lvds1_tx1_n lvds1_tx3_n lvds1_tx3_p dram_d3 dram_d10 gnd dram_d17 dram_d23 gnd dram_sdcke1 dram_a14 gnd dram_a2 dram_a10 gnd dram_d32 dram_d33 gnd dram_d45 dram_d57 gnd dram_d61 dram_sdqs7_b dram_sdqs7 aa table 104. 21 x 21 mm, 0.8 mm pitch ball map i.mx 6duallite (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
package information and contact assignments i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 165 ab lvds1_tx2_n lvds1_tx2_p gnd dram_d6 dram_d12 dram_d14 dram_d16 dram_dqm2 dram_d18 dram_sdqs3_b dram_d27 dram_sdba2 dram_a8 dram_a1 dram_ras dram_sdwe dram_sdodt1 dram_dqm4 dram_d38 dram_d41 dram_d42 dram_d52 dram_d60 gnd dram_d56 ab ac dram_d4 dram_vref dram_dqm0 dram_d2 dram_d13 dram_dqm1 dram_d15 dram_d22 dram_d28 dram_sdqs3 dram_d31 dram_a11 dram_a6 dram_a0 dram_sdba0 dram_sdodt0 dram_a13 dram_d34 dram_d39 dram_dqm5 dram_d47 dram_d48 dram_d53 dram_d51 dram_d55 ac ad dram_d5 dram_d0 dram_sdqs0_b gnd dram_d8 dram_sdqs1 gnd dram_sdqs2 dram_d29 gnd dram_d30 dram_a12 gnd dram_sdclk_1 dram_sdclk_0 gnd dram_cs1 dram_sdqs4 gnd dram_sdqs5 dram_d43 gnd dram_sdqs6 dram_dqm6 dram_d54 ad ae gnd dram_d1 dram_sdqs0 dram_d7 dram_d9 dram_sdqs1_b dram_d11 dram_sdqs2_b dram_d24 dram_dqm3 dram_d26 dram_a9 dram_a5 dram_sdclk_1_b dram_sdclk_0_b dram_cas zqpad dram_sdqs4_b dram_d35 dram_sdqs5_b dram_d46 dram_d49 dram_sdqs6_b dram_d50 gnd ae 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 table 104. 21 x 21 mm, 0.8 mm pitch ball map i.mx 6duallite (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 166 freescale semiconductor revision history 7 revision history table 105 provides a revision history for this data sheet. table 105. i.mx 6solo/6duallite data sheet document revision history rev. number date substantive changes rev. 3 02/2014 ? updates throughout for silicon revision c, including: - figure 1 part number nomenclature diagram - ta b l e 1 example orderable part numbers ? feature descriptions updated for: - camera sensors: updated from one to two ports at up to 240 mhz peak. - miscellaneous ips and interfaces; ssi and esai. ? ta bl e 3 , modules list, usdhc 1?4 description change: including sdxc cards up to 2 tb. ? ta bl e 3 , modules list, uart 1?5 description change: programmable baud rate up to 5 mhz. ? ta bl e 4 , special signal considerations: xtalosc_rtc_xtali/rtc_xtalo: ending paragraph removed. was: ?in case when high accuracy real time clock are not required system may use internal low frequency ring oscillator. it is recommended to connect xtalosc_rtc_xtali to gnd and keep rtc_xtalo floating.? ? ta bl e 9 , operating ranges for run mode ldo bypassed: added footnote regarding alternate maximum voltage on vdd_soc_in ? this maximum can be 1.3v. ? ta bl e 9 , operating ranges standby/dsm mode: added f ootnote regarding alternate maximum voltage on vdd_soc_in ? this maximum can be 1.3v. ? ta bl e 9 , operating ranges gpio supply voltages: corrected supply name to nvcc_nandf ? ta bl e 9 , operating ranges: updated table footnotes for clarity. ? removed table ?on-chip ldos and their on-chip loads.? ? section 4.1.4 , external clock sources; added note, ?the internal rtc oscillator does not ...?. ? section 4.1.5 , maximum supply currents: reworded second paragraph about the power management ic to explain that a robust thermal design is re quired for the increased system power dissipation. ? ta bl e 1 1 , maximum supply currents: nvcc_rgmii condition value corrected to n=6. ? ta bl e 1 1 , maximum supply currents: corrected supply name nvcc_nandf. ? ta bl e 1 1 , maximum supply currents: added row nvcc_lvds2p5 ? section 4.2.1 , power-up sequence: clarified wording of th ird bulleted item regarding por control. ? section 4.2.1 , power-up sequence: removed note. ? section 4.2.1 , power-up sequence: corrected bullet regarding vdd_arm_cap / vdd_soc_cap difference from 50 mv to 100 mv. ? section 4.5.2 , osc32k, second paragraph reworded to describe osc32k automatic switching. ? section 4.5.2 , osc32k, added note following second paragraph to caution use of internal oscillator. ? ta bl e 2 3 , xtali and rtc_xtali dc parameters; changed rtc_xtali vih minimum value to 0.8. ? ta bl e 2 3 , xtali and rtc_xtali dc parameters; changed rtc_xtali vih maximum value to 1.1. ? ta bl e 3 9 , reset timing parameters; removed rise/fall time requirement ? section 4.9.3 , external interface module; enhanced wording to first paragraph to describe operating frequency for data transfers, and to explain regist er settings are valid for entire range of frequencies.
revision history i.mx 6solo/6duallite applications proces sors for consumer products, rev. 3 freescale semiconductor 167 rev. 3 continued 2/2014 ? ta bl e 4 2 , eim bus timing parameters; reworded footnotes for clarity. ? ta bl e 4 2 , eim asynchronous timing parameters; removed comment from the max heading cell. ? figure 65 , gated clock mode timing diagram: corrected hsync trace behavior ? ta bl e 7 0 , video signal cross-reference: corrected naming of hsync and vsync ? section 4.11.22 , usb phy parameters: updated battery charging specification bullet ? ta bl e 9 9 , bga package details: corrected to read ?21 x 21, 0.8 mm?. ? ta bl e 1 0 0 , supplies contact assignments: corrected supply name nvcc_nandf ? ta bl e 1 0 0 , supplies contact assignments: updated nc rows to show i.mx 6duallite vs. i.mx 6solo ? ta bl e 1 0 1 , functional contact assignments: alt5 default function signal names corrected ? ta bl e 1 0 1 , functional contact assignments: pmic_on_re q out of reset value corrected to ?open drain with pu (100k) enabled? ? ta bl e 1 0 1 , functional contact assignments: test_mode row included ? ta bl e 1 0 1 , functional contact assignments: vdd_arm_in and zqpad row removed rev. 2.2 8/2013 ? 21x21 functional contac t table: changed from nand to nandf ? system timing parameters ta bl e 3 9 , reset timing parameter , cc1 description, change from: "duration of src_por_b to be qualified as valid ( <= 5 ns)" to: "duration of src_por_b to be qualified as valid" and added a footnote to the parameter with the following text: "src_por_b rise and fall times must be 5 ns or less." rev. 2.1 5/2013 substantive changes thro ughout this document are as follows: ? incorporated standardized signal names. this change is extensive throughout. ? added reference to eb792, i.mx signal name mapping. ? figures updated to align to standardized signal names. ? updated references to emmc standard to include 4.41. ? added medialb (mlb) feature and dtcp module to the commercial temperature grade version. ? figure 1 part number nomenclature: updates to part differentiator section to align with table 1. ? ta bl e 1 ?orderable part numbers,? added arm core information to the options column: 2x ?arm cortex-a9? 64-bit to 6duallite 1x ?arm cortex -a9? 32-bit to 6solo ? ta bl e 3 changed reference to global power controller to read general power controller. ? ta bl e 9 ?operating ranges,? added reference for info rmation on product lifetime: i.mx 6dual/6quad product usage lifetime estimates application note, an4725. ? ta bl e 1 1 ?maximum supply currents,? updated footnote 2. ? ta bl e 1 2 stop mode current and power cons umption: added snvs only mode ? ta bl e 6 4 rgmii parameter tskewt minimum and maximum values corrected. ? ta bl e 6 4 rgmii parameter tskewr units corrected. ? ta bl e 1 0 1 clarification of enet_ref_clk naming. ? added table 102, "signals with differing before reset and after reset states," on page 156 . ? removed section, eim signal cross reference. si gnal names are now aligned with reference manual. ? removed table from section 3.2, ?recommended connections for unused analog interfaces and referenced the hardware development guide. ? section 1.2, ?features added bulleted item regarding the soc-level memory system. ? section 1.2, ?features camera sensors: changed camera port to be up to 180 mhz peak. ? added section 1.3, ?updated signal naming convention ? section 4.2.1, ?power-up sequence ? updated wording. ? section 4.3.2, ?regulators for analog modules ? section updates. ? added section 4.6.1, ?xtali and rtc_xtali (clock inputs) dc parameters .? ? section 4.10, ?general-purpose media interface (gpmi) timing ? figures replaced, tables revised. rev. 2 05/2013 ? revision 2 was not published. table 105. i.mx 6solo/6duallite data sh eet document revision history (continued) rev. number date substantive changes
document number: imx6sdlcec rev. 3 03/2014 how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provid ed solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm, the arm logo, and cortex are registered trademarks of arm limited. mpcore and neon are trademarks of arm limited. ? 2012-2014 freescale semiconductor, inc. all rights reserved.

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