integrated circuit systems, inc. general description features ics9159c-02 the ics9159c-02 generates all clocks required for high speed risc or cisc microprocessor systems such as 486, pentium, powerpc,? etc. four different reference frequency multiplying factors are externally selectable with smooth frequency transitions. these multiplying factors can be customized for specific applications. a test mode is provided to drive all clocks directly. high drive bclk outputs provide typically greater than 1v/ns slew rate into 30pf loads. pclk outputs provide typically better than 1v/ns slew rate into 20pf loads while maintaining +/- 5% duty cycle. ? generates up to four processor and six bus clocks, plus disk, keyboard and reference clocks ? synchronous clocks skew matched to 250ps window on pclks and 500ps window on bclks ? test clock mode eases system design ? custom configurations available: output frequency ranges to 100 mhz on options selectable multiplying and processor/bus ratios stop clock control stops clock glitch-free; available as mask option ? 3.0v - 5.5v supply range ? 28-pin soic package applications ? ideal for high-speed risc or cisc systems such as 486, pentium, powerpc, etc. xtal osc bclk(0:5) pclk(0:3) oen ref(0:1) keybd disk sync reg pll clock gen pll clock gen x2 x1 fs0 fs1 9159 -02 rev d 062397 block diagram pentium is a trademark of intel corporation powerpc is a trademark of motorola corporation frequency generator and integrated buffer for pentium tm ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9159c-02 pin configuration pin descriptions functionality *vco range is limited from 60 - 200 mhz pclk(0,3) bclk(0,5) disk keybd vco/2 pclk/2 24 mhz 12 mhz tclk/2 tclk/4 tclk/4 tclk/8 pin number pin name type description 1, 8, 14, 20, 26 vdd pwr power for logic, pclk and fixed frequency output buffers. 2x1in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 12 - 16 mhz crystal, nominally 14.31818 mhz. 3 x2 out xtal output which includes xtal load capacitance. 4, 11, 17, 23 vss pwr ground for logic, pclk and fixed frequency output buffers. 6, 7, 9, 10 pclk(0:3) out processor clock outputs which are a multiple of the input reference frequency as shown in the table above. 13, 12 fs(0:1) in frequency multiplier select pins. see table above. these inputs have internal pull-up devices. 15, 16, 18 19, 21, 22 bclk(0:5) out bus clock outputs are fixed at one half the pclk frequency. 5oenin oen tristates all outputs when low. this input has an internal pull- up device. 24 disk out the disk controller clock is fixed at 24 mhz (with 14.318 mhz input). 25 keybd out the keybd clock is fixed at 12 mhz (with 14.318 mhz input). 28, 27 ref(0:1) out ref is a buffered copy of the crystal oscillator or reference input clock nominally 14.31818 mhz. note: bclk buffers cannot be supplied with 5 volts (pins 14 and 20) if cpu and fixed frequencies (pins 1, 8, and 26) are being supplied with 3.3 volts 28-pin soic fs1 fs0 *vco x1, ref (mhz) cpu (mhz) 0 0 118/17xx1 14.318 50(49.7) 0 1 65/7xx1 14.318 66.6(66.5) 1 0 92/11xx1 14.318 60(59.9) 1 1 test mode tclk tclk/2
3 ics9159c-02 absolute maximum ratings electrical characteristics at 3.3 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stess specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply v oltage ......................................................................................... 7.0 v logic inputs ..................................................... gnd - 0.5 v to vdd + 0.5 v ambient .................................................... operating t emperature0 to +70 c storage temperature .................................................................. 65 to +150 c v dd = 3.0 - 3.7 v, t a = 0 - 70 o c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. dc characteristics parameter symbol test conditions min typ max units input low voltage v il - -0.2v dd v input high voltage v ih 0.7v dd - - v input low current i il v in =0v -28.0 -10.5 - ma input high current i ih v in =v dd -5.0 - 5.0 ma output low current 1 i ol v ol =0.8v for pclks & bclks 30.0 47.0 - ma output high current 1 i oh vol=2.0v for pclks & bclks - -66.0 -42.0 ma output low current 1 i ol vol=0.8v for fixed clks 25.0 38.0 - ma output high current 1 i oh vol=2.0v for fixed clks - -47.0 -30.0 ma output low voltage 1 v ol i ol =15ma for pclks & bclks - 0.3 0.4 v output high voltage 1 v oh i oh =-30ma for pclks & bclks 2.4 2.8 - v output low voltage 1 v ol i ol =12.5ma for fixed clks - 0.3 0.4 v output high voltage 1 v oh i oh =-20ma for fixed clks 2.4 2.8 - v supply current i dd @66.5 mhz all outputs unloaded - 55 110 ma
4 ics9159c-02 electrical characteristics at 3.3 v v dd = 3.0 - 3.7 v, t a = 0 - 70 o c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v pclk & bclk - 0.9 1.5 ns fall time 1 t f1 20pf load, 2.0 to 0.8v pclk & bclk - 0.8 1.4 ns rise time 1 t r2 20pf load, 20% to 80% pclk & bclk - 1.5 2.5 ns fall time 1 t f2 20pf load, 80% to 20% pclk & bclk - 1.4 2.4 ns duty cycle 1 d t 20pf load @ vout=1.4v 45 50 55 % jitter, one sigma 1 t j1s1 pclk & bclk clocks; load=20pf, fout>25 mhz - 50 150 ps jitter, absolute 1 t jab1 pclk & bclk clocks; load=20pf, fout >25 mhz -250 - 250 ps jitter, one sigma 1 t j1s2 fixed clk; load=20pf - 1 3 % jitter, absolute 1 t jab2 fixed clk; load=20pf -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator 1 capacitance1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1st crossing of 66.5 mhz v dd supply ramp<40ms - 2.5 4.5 ms frequency settling time 1 t s from 1st crossing of acquisition to <1% settling - 2.0 4.0 ms clock skew window 1 t sk1 pclk to pclk; load=20pf; @1.4v - 150 250 ps clock skew window t sk2 bclk to bclk; load=20pf; @1.4v - 300 500 ps clock skew window 1 t sk3 pclk to bclk; load=20pf; @1.4v 1 2.6 5 ns
5 ics9159c-02 electrical characteristics at 5.0 v note 1: parameter is guaranteed by design and characterization. not 100% tested in production. dc characteristics parameter symbol test conditions min typ max units input low voltage v il - - 0.8 v input high voltage v ih 2.4 - - v input low current i il v in =0v -45 -15 - ma input high current i ih v in =v dd -5.0 - 5.0 ma output low current 1 i ol v ol =0.8v; for pclks & bclks 36.0 62.0 - ma output high current 1 i oh v oh =2.0v; for pclks & bclks - -152 -90.0 ma output low current 1 i ol v ol =0.8v; for fixed clks 30.0 50.0 - ma output high current 1 i oh vol=2.0v; for fixed clks - -110.0 -65.0 ma output low voltage 1 v ol i ol =20ma; for pclks & bclks - 0.25 0.4 v output high voltage 1 v oh i oh =-70ma; for pclks & bclks 2.4 4.0 - v output low voltage 1 v ol i ol =15ma; for fixed clks - 0.2 0.4 v output high voltage 1 v oh i oh =-50ma; for fixed clks 2.4 4.7 - v supply current i dd @66.5 mhz; all outputs unloaded - 80.0 160.0 ma v dd = 4.5 - 5.5 v, t a = 0 - 70 o c unless otherwise stated
6 ics9159c-02 electrical characteristics at 5.0 v v dd = 4.5 - 5.5 v, t a = 0 - 70 o c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v pclk & bclk - 0.55 0.95 ns fall time 1 t f1 20pf load, 2.0 to 0.8v pclk & bclk - 0.52 0.90 ns rise time 1 tr2 20pf load, 20% to 80% pclk & bclk - 1.2 2.1 ns fall time 1 t f2 20pf load, 80% to 20% pclk & bclk - 1.1 2.0 ns duty cycle 1 d t 20pf load @ vout=50% 45 50 55 % duty cycle 1 d t2 20pf load @ vout=1.4v % jitter, one sigma 1 t j1s1 pclk & bclk clocks; load=20pf, rs=33 fout>25 mhz - 50 150 ps jitter, absolute 1 t jab1 pclk & bclk clocks; load=20pf, rs=33 fout>25 mhz -250 - 250 ps jitter, one sigma 1 t j1s2 fixed clk; load=20pf rs=33 - 1 3 % jitter, absolute 1 t jab2 fixed clk; load=20pf rs=33 -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator capacitance1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1st crossing of 66.5 mhz v dd supply ramp<40ms - 2.5 4.5 ms frequency settling time 1 t s from 1st crossing of acquisition to <1% settling - 2.0 4.0 ms clock skew window 1 t sk1 pclk to pclk; load=20pf; @1.4v - 150 250 ps clock skew window 1 t sk2 bclk to bclk; load=20pf; @1.4v - 300 500 ps clock skew window 1 t sk3 pclk to bclk; load=20pf; @1.4v 1 2.6 5 ns
7 ics9159c-02 soic package ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ics xxxx - ppp xx ## ordering information ics9159c-02cw28 example: package type cw = 0.3" body soic, cs = 0.15 body soic device type (consists of 3 or 4 digit numbers and one alpha code on some parts.) ics, av=s tandard device; gsp=genlock device prefix pattern number(2 or 3 digit number for parts with rom code patterns) lead count lead count=1,2 or 3 digits
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