, and . 9.1.4 global status byte table 29. global status byte bit global status byte 7 6543 2 1 0 name gl_er co_er nrece tsd tw_ol uv_ov_oc v cc _fail passive reset 1 0 0 0 0 0 0 0 gl_er global error flag. failures of bits 0-6 are always linked to the global error flag. this flag is generated by an or combination of all failure events of the device. if the tw_ol_msk bit is set in the configuration register, tw_ol is not used as an input to this bit. gl_er is reflected via the do pin while csn is he ld low and no clock signal is available. the flag remains as long as csn is low. this operation does not cause the communication error bit in the to be set. co_er communication error. if the number of clock pulses within the previous frame is not 24, the frame is ignored, and this bit is set. co_er is not set, if csn is held low without any clock to check the gl_er bit. nrece = not (c_reset or co_er) chip reset (c_reset) = registers have be en set to default. after power on nrece is ?0? and is set to ?1? by a valid spi communication. nrece is also ?0? if there was a communication erro r or if there was a reset due to stuck-at-0 or stuck-at-1 at the spidi input. when nrece is active (?0?), the gate drivers are switched off (resistive path to source). the gate drivers can only be activated after nrece has been reset with an spi command. tsd thermal shut down due to an internal sensor. all the gate drivers and the charge pump are switched off (resistive path to source). the tsd bit has to be cleared through a software reset to reactivate the gate drivers and the charge pump. tw_ol thermal warning or open-load. uv_ov_oc under voltage or overvoltage or overcurrent v cc_fail v cc fail pa s s i v e device in passive mode. this bit is set if the device enters passive mode (due to watchdog failure, v cc under voltage, thermal shutdown tsd2 or spi data in stuck at 0 or 1) the bit is reset when the micro sends the firs t correct spi frame after entering passive mode.
L99MM70XP spi control and status registers doc id 022637 rev 2 53/68 9.1.5 address mapping table 30. ram memory map address name access content 01h control register 1 read/write bridge control, watchdog trigger 02h control register 2 read/write high/low-side control, ec control 03h control register 3 read/write bridge recovery mode, bridge pwm mode, lin 04h control register 4 read/write hs recovery and pwm mode, ls recovery and pwm mode, current monitor 11h status register 1 read/clear overcurrent diagnosis 12h status register 2 read/clear open-load diagnosis 13h status register 3 read/clear wd status, supply voltage and ec diagnosis, 14h status register 4 read/clear lin diagnosis, thermal status 3fh configuration register read/write table 31. rom memory map address name access content 00h id header read only 4300h (assp st_spi) 01h version read only 0000h (engineering sample) 02h product code 1 read only 4800h (dec. 72) 03h product code 2 read only 4800h (ascii ?h?) 3eh spi frame id read only 4200h (watchdog available, 24 bit st-spi)
spi control and status registers L99MM70XP 54/68 doc id 022637 rev 2 9.1.6 control registers table 32. control registers 1 control register 1 (01h) bit 151413121110 9 8 7 6 5 4 3 2 1 0 reset state0000000000100000 name out5 hs out5 ls out4 hs out4 ls out3 hs out3 ls out2 hs out2 ls out1 hs out1 ls nint en rst lev icmp stby sel go stby wd tr i g table 33. control registers 1, bits bit name comment out5hs if a bit is set, the selected output driver is swit ched on. if the corresponding pwm enable bit is set also, the driver is activated only if the associated pwm input signal is high. the outputs of out1 ? out5 are half bridges. if the bits of the hs and ls drivers of the same half bridge are set, both drivers are deactivated and the output is set to high impedance. out5ls out4hs out4ls out3hs out3ls out2hs out2ls out1hs out1ls ninten enable nint output 0: rxd output has only rxd functionality 1: rxd output can work also as nint output rstlev select v cc reset level 0: 4.7 v 1: 3.5 v i cmp monitor the i cc current consumption during v cc-standby mode 0: watchdog disabled only if i cc < i cmp 1: watchdog disabled stbysel standby select 0: v bat-standby 1: v cc-standby this bit is a one-shot bit, it is read always 0 gostby 1: execute standby mode this bit is a one-shot bit, it is read always 0 wdtrig watchdog trigger this bit has to be toggled regularly if the watchdog is active. the watchdog can be triggered either by this bit or by bit 0 of the configuration register.
L99MM70XP spi control and status registers doc id 022637 rev 2 55/68 table 34. control registers 2 control register 2 (02h) bit 15 14 13 12 11 10 9 8 7 654321 0 reset state0 0 0 0 0 0 0 0 0 000000 0 name reserved ecfdls ecvls out9 out8hs2 out8hs1 out7 out6 ecnd ec5 ec4 ec3 ec2 ec1 ec0 econ table 35. control registers 2, bits bit name comment reserved reserved bit, has always to be written to 0 and reads always 0 ecfdls 1: switch on the ecfd ls driver 0: switch off the ecfd ls driver ecvls 1: switch on the ecv ls driver 0: switch off the ecv ls driver if the ecvpwm1 bit (cr4/bit4) is also set, then the ecv output is controlled by the pwm1 input out9 1: switch on the out9 hs driver 0: switch off the out9 hs driver if the out9pwm1 bit (cr4/bit11) is also set, th en the out9 output is controlled by the pwm1 input out8hs2 11: switch o ff the out8 hs driver 10: switch on the out8 hs driver (high current mode) 01: switch on the out8 hs driver (low current mode) 00: switch off the out8 hs driver if the out8pwm3 bit (cr4/bit10) is also set, th en the out8 output is controlled by the pwm3 input out8hs1 out7 1: switch on the out7 hs driver 0: switch off the out7 hs driver if the out7pwm1 bit (cr4/bit9) is also set, then the out7 output is controlled by the pwm1 input this bit is disabled if ec on = 1. in this case out7 is switched on permanently. out6 1: switch on the out6 hs driver 0: switch off the out6 hs driver if the out6pwm2 bit (cr4/bit8) is also set, then the out6 output is controlled by the pwm2 input ecnd ec negative discharge: 0: ec negative discharge off 1: ec negative discharge on ec5 reference value for difference voltage amplifier at pin ecv, binary coded. the full scale value is set in ecvl (cr3/bit5). if all ec bits are se t to zero, the reference value is 0v. ec4 ec3 ec2 ec1 ec0 econ 1: ec control enabled 0: ec control disabled if the ec control is enabled, the out put out7 is switched on permanently.
spi control and status registers L99MM70XP 56/68 doc id 022637 rev 2 table 36. control register 3 control register 3 (03h) bit 1514131211109876543210 reset state0 00 0000001000000 name reserved ocr freq ovuvr out5 or out4 or out3 or out2 or out1 or lin flash lin txd tout ecvl out5 pwm1 out4 pwm1 out3 pwm1 out2 pwm1 out1 pwm1 table 37. control register 3, bits bit name comment reserved reserved bit, has always to be written to 0 and reads always 0 ocrfreq ocr frequency: this bit defines the overcurrent recovery frequen cy of a driver in overcurrent recovery mode 0: 1.7 khz 1: 3 khz ovuvr overvoltage/undervoltage recovery: 1: clear status register to enable the outputs after an overvoltage/undervoltage event 0: outputs are enabled automatically after an overvoltage/undervoltage event out5or overcurrent recovery enable: 1: the output is automatically reactivated af ter a delay time with programmable duty cycle (cr3/bit14) 0: clear status register to enable the output after an overcurrent event out4or out3or out2or out1or linflash lin flash mode: 0: 20 kbit/s 1: 100 kbit/s lintxdtout dominant txd time-out for the lin interface: 1: enable the dominant txd time -out for the lin interface 0: disable the dominant txd time-out for the lin interface ecvl ec voltage limit: 0: max ec voltage = 1.2v 1: max ec voltage = 1.5v out5pwm1 if the pwm enable bit is set and the output is enab led, the output is switc hed on only if the pwm1 input is high, and switched off if the pwm1 input is low. out4pwm1 out3pwm1 out2pwm1 out1pwm1
L99MM70XP spi control and status registers doc id 022637 rev 2 57/68 table 38. control register 4 control register 4 (04h) bit 151413121110 9 8 7 6 5 4 3210 reset state00000000 0 0 0 00000 name out9 or out8 or out7 or out6 or out9 pwm1 out8 pwm3 out7 pwm1 out6 pwm2 reserved ecv or reserved ecv pwm1 cm3 cm2 cm1 cm0 table 39. control register 4, bits bit name comment out9or overcurrent recovery enable: 1: the output is automatically reactivated after a dela y time with programmable duty cycle (cr3/bit14) 0: clear status register to enable the output after an overcurrent event out8or out7or out6or out9pwm1 if the pwm1/2/3 enable bit is set and the output is enabled, the output is switched on only if the pwm1/2/3 input is high, and switched off if the pwm1/2/3 input is low. out8 is controlled by pwm3, out7 is controlled by pwm1 and out6 is controlled by pwm2. out8pwm3 out7pwm1 out6pwm2 reserved reserved bit, has always to be written to 0 and reads always 0 ecvor overcurrent recovery enable: 1: the output is automatically reactivated after a dela y time with programmable duty cycle (cr3/bit14) 0: clear status register to enable the output after an overcurrent event reserved reserved bit, has always to be written to 0 and reads always 0 ecvpwm1 if the pwm1 enable bit is set and the output is en abled, the output is switched on only if the pwm1 input is high, and switched off if the pwm1 input is low.
spi control and status registers L99MM70XP 58/68 doc id 022637 rev 2 cm3 cm2 cm1 cm0 current monitor: the current image of the selected high-side output is multiplexed to the cm output (see table below). table 39. control register 4, bits (continued) bit name comment cm3 cm2 cm1 cm0 current image of 0 0 0 0 cm deactivated 0 0 0 1 cm hs1 active 0 0 1 0 cm hs2 active 0 0 1 1 cm hs3 active 0 1 0 0 cm hs4 active 0 1 0 1 cm hs5 active 0 1 1 0 cm hs6 active 0 1 1 1 cm hs7 active 1 0 0 0 cm hs8 active 1 0 0 1 cm hs9 active 10 1 0 reserved 10 1 1 reserved 11 0 0 reserved 11 0 1 reserved 11 1 0 reserved 11 1 1 reserved
L99MM70XP spi control and status registers doc id 022637 rev 2 59/68 table 40. configuration register configuration register (3fh) bit76543210 reset state00000000 name ecv ecfd out7 olmask out1hs olmask out1ls olmask tw_ol mask wd trig table 41. configuration register, bits bit name comment the bits 15 to 8 of the configuration regist er have to be written to 0, and read always 0 ecv ecfd out7 olmask mask the ecv, ecfd (hs and ls) and out7 open-load diagnostics bits (status reg. 2, bits 11, 14, 15): an open-load event is not considered in the open- load bit (tw_ol) of the global status register out1hs olmask mask the ouths1 open-load diagnostic bit (status reg. 1/bit 1): an open-load event (under-current status bit of out1hs) is not considered in open-load bit (tw_ol) of the global status register. out1ls olmask mask the outls1 open-load diagnostic bit (status reg. 1/bit 0): an open-load event (under-current status bit of out1ls) is not c onsidered in open-load bit (tw_ol) of the global status register. tw_ol mask mask the tw_ol bit in global status byte: a temperature warning or open-load event is not considered in the ?global error flag? wdtrig trigger the watchdog. this bit has to be toggled regularly if the watchdog is active. the watchdog can be triggered either by this bit or by bit 0 of the control register 1.
spi control and status registers L99MM70XP 60/68 doc id 022637 rev 2 9.1.7 status registers table 42. status register 1 status register 1 (11h) bit 15 1413121110 9 8 7 6 5 4 3 2 1 0 reset state 0 00000 0 000000000 name ecfdls ecv ls out 9hs out 8hs out 7hs out 6hs out5 hs out5 ls out4 hs out4 ls out3 hs out3 ls out2 hc out2 ls out1 hs out1 ls table 43. status register 1, bits bit name comment ecfdlsoc overcurrent diagnosis: in case of an overcurrent event the corresponding st atus bit is set and the output driver is disabled. if the overcurrent recovery enable bit is set, the out put is automatically reactivated after a delay time resulting in a pwm modulated cu rrent with a programmable duty cycle. if the overcurrent recovery bit is not set, the mi crocontroller has to clear the overcurrent bit to reactivate the output driver. ecvlsoc out9hsoc out8hsoc out7hsoc out6hsoc out5hsoc out5lsoc out4hsoc out4lsoc out3hsoc out3lsoc out2hsoc out2lsoc out1hsoc out1lsoc
L99MM70XP spi control and status registers doc id 022637 rev 2 61/68 table 44. status register 2 status register 2 (12h) bit 151413121110 9 8 7 6 5 4 3 2 1 0 reset state0000000000000000 name ecfd ls ecv ls out9 out8 out7 out6 out5 hs out5 ls out4 hs out4 ls out3 hs out3 ls out2 hs out2 ls out1 hs out1 ls table 45. status register 2, bits bit name comment ecfdlsol the open-load detection monitors the load current in each activated output stage. if the load current is below the under current dete ction threshold for at least t dol = 2ms, the corresponding open-load bit is set. due to the mechanical / electrical inerti a of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open-load stat us without changing the mechanical / electrical state of the loads. the open-load detection of out1 hs and out1 ls can be masked by the configuration register (bit 4/5). the open-load detection of ecfdls, ecvls an d out7 can be masked by the configuration register (bit 6). ecvlsol out9ol out8ol out7ol out6ol out5hsol out5lsol out4hsol out4lsol out3hsol out3lsol out2hsol out2lsol out1hsol maskable by the configuration register: an open-load event is not considered in open- load bit (tw_ol) of global status register. out1lsol
spi control and status registers L99MM70XP 62/68 doc id 022637 rev 2 table 46. status register 3 status register 3 (13h) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0000000 0 0 0000000 name lin perm dom lin txd dom lin prem rec vcc fail uv ov wd timer state wd timer state ecfd hsoc ecfd hsol ecv nr ecvo tsd2 tsd1 tw table 47. status register 3, bits bit name comment lin perm dom if the bus state is dominant (low) for more than 12 ms a permanent dominant status is detected. the status bit is set. lin txd dom if txd is in dominant state (low) for more than 12 ms, the transmitter is disabled and this bit is set. lin perm rec if txd changes to dominant (low) state but rxd signal does not follow within 40 s, the transmitter is disabled and this bit is set. v ccfail v ccfail : v cc < 2 v for more than 2 s uv v s undervoltage detected if an over/under volt age event is detected, the outputs are disabled and one of these bits is set. if the ovuvr bit is 0, the output s are enabled automatically after an over/under voltage event and the uv/ov bit is reset. if the ovuvr bit is 1, the output s are enabled after clearing the uv/ov bit by spi command (read and clear operation) ov v s overvoltage detected wdtim1 watchdog state: display which part of the total wd time (100 ms) has been elapsed: wdtim0 ecfdhsoc overcurrent diagnosis: in case of an overcurrent event on ecfdhs the status bit is set and the output driver is disabled. ecfdhsol the open-load detection monitors the load current in the ecfdhs. if the load current is below the under current detection threshold for at least t dol = 2 ms, the open-load bit is set. ecvnr ecv voltage not reached two comparators mo nitor the voltage at pin ecv in electrochrome mode. if this voltage is below / above the programmed target, these bits signal the difference after at least 32 s. the bits are not latched and may toggle after at least 32 s, if the ecv voltage has not yet reached the target. ecvo ecv voltage too high tsd2 thermal shutdown 2 (> 160 c) tsd1 thermal shutdown 1 (> 150 c) tw thermal warning (> 140 c) wdtim1 wdtim0 elapsed time 0 0 < 1/3 of the total wd time 0 1 < 2/3 of the total wd time 1 1 < 3/3 of the total wd time
L99MM70XP spi control and status registers doc id 022637 rev 2 63/68 all bits except the wdtim1, wdtim0, ecvnr and ecvo bits can be reset by a read and clear operation on sr4. table 48. status register 4 status register 4 (14h) bit 15141312 11 10 9 8 7 6 5 4 3210 reset state0000 0 0 0 0 0 0 0 0 10 0 0 name wd fail wd fail wd fail wd fail forced sleepwd forced sleeptsd dev state dev state vcc restart vcc restart vcc restart not rdy spi wake lin wake inh wake table 49. status register 4, bits bit name comment wdfail3 nr of watchdog fails these bits are not clearable, are cleared with a proper watchdog trigger or if the chip is sent to v bat-standby by the watchdog. wdfail2 wdfail1 wdfail0 forced sleep wd this bit is set if the chip has been set to v bat-standby mode by the watchdog these bits are latched until a ?read and clear? access on sr4. forced sleep tsd this bit is set if the chip has been set to v bat-standby mode by a thermal shutdown devstate1 signal device state: the device state is updated with any state transition and with a read and clear command on status register 4. therefore, the first read oper ation after entering active mode or flash mode reads the last device state. read operations after a read and clear operation reads the current device stat e. after power-on reset, the device state is v bat-standby . these bits are latched until a ?read and clear? access on sr 4. devstate0 vccrestart2 nr of tsd restart trials these bits are latched until a ?read and clear access? on sr 4. vccrestart1 vccrestart0 notrdy not ready: this bit is set for 200s after switching from standby to active mode. it is cleared automatically. while the bit is set, the output drivers are disabled. this bit is not clearable, it is cleared automatically. dev state1 dev state2 state 00 active 01 v cc-standby 10v bat standby or por 11 flash
spi control and status registers L99MM70XP 64/68 doc id 022637 rev 2 spiwake indicates wake-up from v cc-standby mode via spi these bits are latched until a ?read and clear? access on sr4. linwake indicates wake-up from v cc-standby mode via lin inhwake indicates wake-up from v cc-standby mode via inh table 49. status register 4, bits (continued) bit name comment
L99MM70XP package and packaging information doc id 022637 rev 2 65/68 10 package and packaging information 10.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 10.2 powersso-36 package information figure 19. powersso-36 package dimensions a g00066v1
package and packaging information L99MM70XP 66/68 doc id 022637 rev 2 note: ?d? and ?e? do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. table 50. powersso-36 mechanical data symbol millimeters min. typ. max. a 2.15 - 2.45 a2 2.15 - 2.35 a1 0 - 0.10 b 0.18 - 0.36 c 0.23 - 0.32 d 1 10.10 - 10.50 e 1 7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 g1 - - 0.06 h 10.1 - 10.5 h- -0.4 k0-8 l 0.55 - 0.85 m-4.3- n- -10 o-1.2- q-0.8- s-2.9- t - 3.65 - u-1- x4.3 - 5.2 y6.9 - 7.5
L99MM70XP revision history doc id 022637 rev 2 67/68 11 revision history table 51. document revision history date revision changes 04-jan-2012 1 initial release. 19-sep-2013 2 updated disclaimer.
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