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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 2 1 publication order number: NCV70514/d NCV70514 micro-stepping motor driver description the NCV70514 is a micro?stepping stepper motor driver for bipolar stepper motors. the chip is connected through i/o pins and an spi interface with an external microcontroller. the NCV70514 contains a current?translation table and takes the next micro?step depending on the clock signal on the ?nxt? input pin and the status of the ?dir? (= direction) register or input pin. the chip provides an error message if stall, an electrical error, an under?voltage or an elevated junction temperature is detected. it is using a proprietary pwm algorithm for reliable current control. NCV70514 is fully compatible with the automotive voltage requirements and is ideally suited for general?purpose stepper motor applications in the automotive, industrial, medical, and marine environment. due to the technology, the device is especially suited for use in applications with fluctuating battery supplies. features ? dual h?bridge for 2?phase stepper motors ? programmable peak?current up to 800 ma ? on?chip current translator ? spi interface with daisy chain capability ? 7 step modes from full?step up to 32 micro?steps ? fully integrated current?sensing and current?regulation ? on chip stall detection ? pwm current control with automatic selection of fast and slow decay ? fixed pwm frequency ? active fly?back diodes ? full output protection and diagnosis ? thermal warning and shutdown ? compatible with 3.3 v microcontrollers, 5 v tolerant inputs, 5 v tolerant open drain outputs ? reset function ? overcurrent protection ? enhanced under voltage management ? step mode selection inputs ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? small positioning applications ? automotive (headlamp alignment, hvac, idle control, cruise control) ? industrial equipment (lighting, fluid control, labeling, process control, xyz tables, robots) ? building automation (hvac, surveillance, satellite dish, renewable energy systems) see detailed ordering and shipping information in the package dimensions section on page 30 of this data sheet. ordering information marking diagram n70514 = specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb?free package 32 1 qfn32, 5x5 case 488am n70514?3 awlyyww 1 www. onsemi.com
NCV70514 www. onsemi.com 2 typical application schematic the application schematic below shows typical connections for applications with low axis counts and/or with software spi implementation. for applications with many stepper motor drivers, some ?minimal wiring? examples are shown at the last sections of this datasheet. NCV70514 errb gnd csb clk di do nxt dir motxp motxn motyp motyn m v bat vbb 100 uf c2 c1 100 nf uc d1 v dd r1 r2 rhb c3 100 nf step1 step0 c4 100 nf vbb vdd tst2 tst1 c5 c6 c7 c8 r3 r4 r11 r5 r6 r7 r8 r9 r12 r10 figure 1. typical application schematic table 1. external components component function typ. value max tolerance unit c1 v bb buffer capacitor (note 1) 22 ... 100 20% f c2, c3 v bb decoupling capacitor (note 2) 100 20% nf c4 v dd decoupling capacitor (note 3) 100 20% nf c5, c6, c7, c8 optional emc filtering capacitor (note 4) 1 ... 3.3 max 20% nf r1, r2 pull up resistor 1..5 10% k r3 ? r10 optional resistors 1 10% k r11, r12 optional resistors (note 5) 100 10% d1 optional reverse protection diode e.g. murd530 1. low esr < 4 , mounted as close as possible to the NCV70514. total decoupling capacitance value has to be chosen properly to reduce the supply voltage ripple and to avoid em emission. 2. c2 and c3 must be close to pins vbb and coupled gnd directly. 3. c4 must be a ceramic capacitor to assure low esr. 4. optional capacitors for improvement of emc and system esd performance. the slope times on motor pins can be longer than speci fied in the ac table. 5. value depends on characteristics of c inputs for do and errb signals.
NCV70514 www. onsemi.com 3 tsd spi otp timebase por di do csb clk nxt dir errb band? gap NCV70514 logic & registers t r a n s l a t o r rhb vbb p w m i?sense emc p w m i?sense emc gnd motxp motxn motyp motyn stall open/ short tst1 internal voltage regulator 3.3 v vdd step0 step1 uv detect tst2 figure 2. block diagram
NCV70514 www. onsemi.com 4 package and pin description motxp vbb step0 step1 csb nc 2 3 4 1 6 7 8 5 motxn gndp 29 30 31 32 25 26 27 28 nc dir rhb nxt 21 22 23 24 19 20 17 18 di do errb vdd gnd clk tst2 tst1 10 11 12 9 14 15 16 13 qfn32 5x5 motxp vbb gndp motxn motyn motyn gndp gndp motyp motyp vbb vbb figure 3. pin connections ? qfn32 5x5 table 2. pin description pin no. qfn32 5x5 pin name description i/o type 1, 2 motxp positive end of phase x coil driver output 3, 4, 21, 22 vbb battery voltage supply supply 5, 20 nc not connected 6 step0 step mode selection input 0 digital input 7 step1 step mode selection input 1 digital input 8 csb spi chip select input digital input 9 di spi data input digital input 10 do spi data output (open drain) digital output 11 errb error output (open drain) digital output 12 vdd internal supply (needs external decoupling capacitor) supply 13 gnd ground supply 14 tst1 test pin input (to be tied to ground in normal operation) digital input 15 tst2 test pin input (to be tied to ground in normal operation) digital input 16 clk spi clock input digital input 17 nxt next micro?step input digital input 18 rhb run/hold current selection input digital input 19 dir direction input digital input 23, 24 motyp positive end of phase y coil driver output 25, 26, 31, 32 gndp ground supply 27, 28 motyn negative end of phase y coil driver output 29, 30 motxn negative end of phase x coil driver output
NCV70514 www. onsemi.com 5 table 3. absolute maximum ratings characteristic symbol min max unit supply voltage (note 6) v bb ?0.3 +40 v digital input/outputs voltage v io ?0.3 +6.0 v junction temperature range (note 7 ) t j ?45 +175 c storage temperature (note 8) t strg ?55 +160 c hbm electrostatic discharge voltage (note 9) v esd_hbm ?2 +2 kv system electrostatic discharge voltage (note 10) v syst_esd ?8 +8 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 6. v bb max is +43 v for limited time <0.5 s. 7. the circuit functionality is not guaranteed. 8. for limited time up to 100 hours. otherwise the max storage temperature is 85 c. 9. hbm according to aec?q100: eia?jesd22?a114?b (100 pf via 1.5 k ). 10. system esd, 150 pf, 330 , contact discharge on the connector pin, unpowered. operating ranges define the limits for functional operation and parametric characteristics of the device. a mission profile (note 11) is a substantial part of the operation conditions; hence the customer must contact on semiconductor in order to mutually agree in writing on the allowed missions profile(s) in the application. table 4. recommended operating ranges characteristic symbol min typ max unit battery supply voltage v bb +6 +29 v digital input/outputs voltage v io 0 +5.5 v parametric operating junction temperature range (notes 12) t jp ?40 +145 c functional operating junction temperature range (notes 13) t jf ?40 +160 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 11. a mission profile describes the application specific conditions such as, but not limited to, the cumulative operating condi tions over life time, the system power dissipation, the system?s environmental conditions, the thermal design of the customer?s system, the modes, in which the device is operated by the customer, etc. no more than 100 cumulated hours in life time above t tw . 12. the parametric characteristics of the circuit are not guaranteed outside the parametric operating junction temperature range . 13. the maximum functional operating temperature range can be limited by thermal shutdown t tsd . package thermal characteristic the NCV70514 is available in thermally optimized qfn32 5x5 package. for the optimizations, the package has an exposed thermal pad which has to be soldered to the pcb ground plane. the ground plane needs thermal vias to conduct the heat to the bottom layer. for precise thermal cooling calculations the major thermal resistances of the devices are given. the thermal media to which the power of the devices has to be given are: ? static environmental air (via the case) ? pcb board copper area (via the device pins and exposed pad) the major thermal resistances of the device are the rth from the junction to the ambient (rthja) and the rth from the junction to the exposed pad (rthjp). using an exposed die pad on the bottom surface of the package is mainly contributing to this performance. in order to take full advantage of the exposed pad, it is most important that the pcb has features to conduct heat away from the package. in the table below, one can find the values for the rthja and rthjp: table 5. thermal resistance package rth, junction?to?exposed pad, rthjp rth, junction?to?ambient, rthja (note 14) qfn32 5x5 15 k/w 39 k/w 14. the rthja for 2s2p simulated for worst case power and following conditions: ? a 4?layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used ? board thickness is 1.46 mm (fr4 pcb material) ? all four layers: 30 um thick copper with an area of 2500 mm 2 where: ? top layer with 70% copper coverage in 20x20 mm around device, rest 40% copper coverage ? in layer 1 with 70% copper coverage ? in layer 2 with 98% copper coverage ? bottom layer with 90% copper coverage ? the 12 vias in exposed pad area, via diameter 0.4 mm ? gap?filler max 400 m between pcb and heat sink non conductive with worst case thermal conductivity of 1.5 w/mk
NCV70514 www. onsemi.com 6 equivalent schematics the following figure gives the equivalent schematics of the user relevant inputs and outputs. the diagrams are simplified representations of the circuits used. vdd vbb digital in ipd mot out digital out errb, do di, clk, nxt, dir, rhb, step0, step1, (csb) motxp, motxn, motyn, motyp figure 4. input and output equivalent diagrams electrical characteristics dc parameters the dc parameters are guaranteed over junction temperature from ?40 to 145 c and vbb in the operating range from 6 to 29 v, unless otherwise specified. convention: currents flowing into the circuit are defined as positive. table 6. dc parameters symbol pin(s) parameter test conditions min typ max unit motordriver i ms - max,peak motxp motxn motyp motyn max current through motor coil in normal operation v bb = 14 v 800 ma i msabs absolute error on coil current (note 15) v bb = 14 v, t j = 145 c ?10 10 % i msrel matching of x & y coil currents (note 15) v bb = 14 v ?7 7 % r ds(on) on resistance of high side + low side driver at the highest current range t j 25 c 1.8 t j = 145 c 2.4 r mpd motor pin pull?down resistance hiz mode 70 k logic inputs v inl di, clk, nxt, dir, rhb, step0, step1 logic low input level, max t j = 145 c 0.8 v v inh logic high input level, min t j = 145 c 2.4 v i inl logic low input level, max t j = 145 c ?1 a i inh logic high input level, max t j = 145 c 1 2 4 a 15. tested in production for 800 ma, 400 ma, 200 ma and 100 ma current settings for both x and y coil. 16. csb has an internal weak pull?up resistor of 100 k . 17. thermal warning is derived from thermal shutdown (t tw = t tsd ? 20 c). 18. no more than 100 cumulated hours in life time above t tw . 19. parameter guaranteed by trimming relevant otps in production test at 160 c and v bb = 14 v. 20. dynamic current is with oscillator running, all analogue cells active. coil currents 0 ma, spi active, errb inactive, no floating input s, tst input tied to gnd. 21. all analog cells in power down. logic powered, no clocks running. all outputs unloaded, no floating inputs. 22. pin vdd must not be used for any external supply. 23. the spi registers content will not be altered above this voltage. 24. maximum allowed drain current that the output can withstand without getting damaged. not tested in production.
NCV70514 www. onsemi.com 7 table 6. dc parameters symbol unit max typ min test conditions parameter pin(s) logic inputs v inl csb logic low input level, max t j = 145 c 0.8 v v inh logic high input level, min t j = 145 c 2.4 v i inl logic low input level, max (note 16) t j = 145 c ?50 ?30 ?10 a i inh logic high input level, max (note 16) t j = 145 c 1 a r pd tst1 internal pull?down resistor 3 9 k logic outputs v olmax do, errb output voltage when 8 ma sink current 0.4 v v ohmax maximum drain voltage 5.5 v i olmax maximum allowed drain current (note 24) 12 ma thermal warning & shutdown t tw thermal warning (notes 17 and 18) 136 145 154 c t tsd thermal shutdown (note 19) 156 165 174 c supply and voltage regulator uv 3 v bb h?bridge off voltage low threshold 5.98 v uv 1 uv 2 under voltage low threshold uvxthr[3:0] = 0000 5.98 v uvxthr[3:0] = 1111 10.96 v uv 1_step uv 2_step under voltage low threshold step between two uvxthr codes 0.33 v uv x_acc under voltage low threshold accuracy ?4 4 % uv x_hyst under voltage hysteresis 30 150 310 mv i bat total current consumption (note 20) unloaded outputs v bb = 29 v 4 15 ma i bat_s sleep mode current consumption (note 21) v bb = 5.5 v & 18 v 90 150 a v dd v dd regulated internal supply (note 22) 5.5 v < v bb < 29 v 3.0 3.3 3.6 v v ddreset digital supply reset level @ power down (note 23) 3.0 v i ddlim current limitation pin shorted to ground v bb = 14 v 80 ma 15. tested in production for 800 ma, 400 ma, 200 ma and 100 ma current settings for both x and y coil. 16. csb has an internal weak pull?up resistor of 100 k . 17. thermal warning is derived from thermal shutdown (t tw = t tsd ? 20 c). 18. no more than 100 cumulated hours in life time above t tw . 19. parameter guaranteed by trimming relevant otps in production test at 160 c and v bb = 14 v. 20. dynamic current is with oscillator running, all analogue cells active. coil currents 0 ma, spi active, errb inactive, no floating input s, tst input tied to gnd. 21. all analog cells in power down. logic powered, no clocks running. all outputs unloaded, no floating inputs. 22. pin vdd must not be used for any external supply. 23. the spi registers content will not be altered above this voltage. 24. maximum allowed drain current that the output can withstand without getting damaged. not tested in production.
NCV70514 www. onsemi.com 8 figure 5. on resistance of high side + low side driver at the highest current range ac parameters the ac parameters are guaranteed over junction temperature from ?40 to 145 c and vbb in the operating range from 6 to 29 v, unless otherwise specified. table 7. ac parameters symbol pin(s) parameter test conditions min typ max unit internal oscillator f osc frequency of internal oscillator v bb = 14 v 7.2 8 8.8 mhz motordriver f pwm motxx pwm frequency (note 25) 20.5 22.8 25.1 khz t ocdet open coil detection with pwm=100% (note 25) spi bit opendet[1:0] = 00 5 ms spi bit opendet [1:0] = 01 25 spi bit opendet [1:0] = 10 50 spi bit opendet [1:0] = 11 200 t brise turn?on transient time, between 10% and 90%, i md = 200 ma, v bb = 14 v, 1 nf at motor pins spi bit emc[1:0] = 00 80 ns spi bit emc[1:0] = 01 120 spi bit emc[1:0] = 10 190 t bfall turn?off transient time, between 10% and 90%, i md = 200 ma, v bb = 14 v, 1 nf at motor pins spi bit emc[1:0] = 00 70 ns spi bit emc[1:0] = 01 110 spi bit emc[1:0] = 10 180 digital outputs t h2l do, errb output fall?time (90% to 10%) from v inh to v inl capacitive load 200 pf and pull?up 1.5 k 50 ns hard reset function t hr_trig dir hard reset trigger time (note 25) see hard reset function 20 200 s t hr_dir hard reset dir pulse width (note 25) 2.5 t hr_trig ?2.5 s t hr_set rhb rhb set?up time (note 25) 5 ms t hr_err errb hard reset error indication (note 25) 2 ms t csb_width csb csb wake?up low pulse width (note 25) 1 150 s t wu wake?up time see sleep mode 250 s 25. derived from the internal oscillator
NCV70514 www. onsemi.com 9 table 7. ac parameters symbol unit max typ min test conditions parameter pin(s) nxt/dir/step0/step1 inputs t nxt_hi nxt nxt minimum, high pulse width 2 s t nxt_lo nxt minimum, low pulse width 2 s f nxt nxt nxt max repetition rate f pwm /2 khz t csb_lo_width nxt pin trigger after spi nxt command 1 s t dir_set nxt, dir, step0 , step1 nxt hold time, following change of dir, step0 or step1 25 s t dir_hold nxt hold time, before change of dir, step0 or step1 25 s 25. derived from the internal oscillator product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. table 8. spi interface symbol parameter min typ max unit t clk spi clock period 1 s t hi_clk spi clock high time 200 ns t clkrise spi clock rise time 1 s t clkfall spi clock fall time 1 s t lo_clk spi clock low time 200 ns t set_di di set up time, valid data before rising edge of clk 50 ns t hold_di di hold time, hold data after rising edge of clk 50 ns t hi_csb csb high time 2.5 s t set_csb_lo csb set up time, csb low before rising edge of clk (note 26) 1 s t clk_csb_hi csb set up time, csb high after rising edge of clk 200 ns t del_csb_do do delay time, do settling time after csb low (note 27) 250 ns t del_clk_do do delay time, do settling time after clk low (note 27) 100 ns 26. after leaving sleep mode an additional wait time of 250 s is needed before pulling csb low. 27. specified for a capacitive load 10 pf and a pull?up resistor of 1.5 k .
NCV70514 www. onsemi.com 10 di valid 0.8 vcc t set_di t hold _di t hi_clk t clk clk cs t set_csb_lo t clk_csb _hi t hi_csb valid ????? ????? ?????? ?????? ????? ????? ????? ????? ????? ????? figure 6. spi timing 0.8 vcc 0.2 vcc 0.8 vcc
NCV70514 www. onsemi.com 11 detailed operating description h?bridge drivers with pwm control two h?bridges are integrated to drive a bipolar stepper motor. each h?bridge consists of two low?side n?type mosfet switches and two high?side p?type mosfet switches. one pwm current control loop with on?chip current sensing is implemented for each h?bridge. depending on the desired current range and the micro?step position at hand, the r ds(on) of the low?side transistors will be adapted to maintain current?sense accuracy. a comparator compares continuously the actual winding current with the requested current and feeds back the information to generate a pwm signal, which turns on/off the h?bridge switches. the switching points of the pwm duty?cycle are synchronized to the on?chip pwm clock. for each output bridge the pwm duty cycle is measured and stored in two appropriate status registers of the motor controller. the pwm frequency will not vary with changes in the supply voltage. also variations in motor?speed or load? conditions of the motor have no ef fect. there are no external components required to adjust the pwm frequency. in order to avoid large currents through the h?bridge switches, it is guaranteed that the top? and bottom?switches of the same half?bridge are never conductive simultaneously (interlock delay). in order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. two bits in spi control register 3 allow adjustment of the voltage slopes. a protection against shorts on motor lines is implemented. when excessive voltage is sensed across a mosfet for a time longer than the required transition time, then the mosfet is switched?off. motor enable?disable the h?bridges and pwm control can be disabled (high?impedance state) by means of a bit in the spi control registers. =0 will only disable the drivers and will not impact the functions of nxt, dir, rhb, spi bus, etc. the h?bridges will resume normal pwm operation by writing =1 in the spi register. pwm current control is then enabled again and will regulate current in both coils corresponding with the position given by the current translator. automatic forward and slow?fast decay the pwm generation is in steady?state using a combination of forward and slow?decay. for transition to lower current levels, fast?decay is automatically activated to allow high?speed response. the selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. icoil 0 t forward & slow decay forward & slow decay fast decay & forward actual value set value figure 7. forward and slow/fast decay pwm t pwm
NCV70514 www. onsemi.com 12 pwm duty cycle measurement for both motor windings the actual pwm duty cycle is measured and stored in two status registers. the duty cycle values are a representation of the applied average voltage to the motor windings to achieve and maintain the actual set point current. figure 8 gives an example of the duty cycle representation. pwm voltage icoil 0 t set value 40% 40% 40% ?4 8% ? 38% ? 40% pwm value figure 8. pwm duty cycle measurement automatic duty cycle adaptation if during regulation the set point current is not reached before 75% of t pwm , the duty cycle of the pwm is adapted automatically to > 50% (top regulation) to maintain the requested average current in the coils. this process is completely automatic and requires no additional parameters for operation. the state of the duty cycle adaptation mode is represented in the t/b bits of the appropriate status registers for both motor windings x and y. figure 9 gives a representation of the duty cycle adaptation. actual value duty cycle < 50% duty cycle > 50% duty cycle < 50% |icoil| set value bit t/b top reg. bit t/b = 1 bottom reg. bit t/b = 0 0 figure 9. automatic duty cycle adaptation bottom reg. bit t/b = 0 t pwm
NCV70514 www. onsemi.com 13 step translator step mode the step translator provides the control of the motor by means of spi register step mode: sm[2:0], spi bits dirp, rhbp and input pins step0, step1, dir (direction of rotation), rhb (run/hold of motor) and nxt (next pulse). it is translating consecutive steps in corresponding currents in both motor coils for a given step mode. one out of seven possible stepping modes can be selected through spi?bits sm[2:0] and pins step0, step1. device takes the value from spi?bits sm[2:0] and increases stepmode value with adding binary information from step0, step1 pins. after power?on or hard reset, the coil?current translator is set to the default to 1/32 micro?stepping at position ?16*?. when remaining in the default step mode, subsequent translator positions are all in the same column and increased or decreased with 1. t able 9 lists the output current versus the translator position. when the micro?step resolution is reduced, then the corresponding least?significant bits of the translator position are set to ?0?. this means that the position in the current table moves to the right and in the case that micro?step position of desired new resolution does not overlap the micro?step position of current resolution, the closest value up or down in required column is set depending on the direction of rotation. when the micro?step resolution is increased, then the corresponding least?significant bits of the translator position are added as ?0?: the micro?step position moves to the left on the same row. in general any change of spi bits or step0 and step1 pins have no effect on current micro?step position without consequent occurrence of nxt pulse or spi command. (see nxt input timing below). when nxt pulse or spi command arrives, the motor moves into next micro?step position according to the current spi bits value and step0, step1 pins level set.
NCV70514 www. onsemi.com 14 table 9. circular translator table msp[6:0 ] step mode sm[2:0] % of imax msp[6:0 ] step mode sm[2:0] % of imax 000 001 010 011 100 coil y coil x 000 001 010 011 100 coil y coil x 1/32 1/16 1/8 1/4 1/2 1/32 1/16 1/8 1/4 1/2 000 0000 0 0 0 0 0 0 100 100 0000 64 32 16 8 4 0 ?100 000 0001 1 ? ? ? ? 4.9 99.9 100 0001 65 ? ? ? ? ?4.9 ?99.9 000 0010 2 1 ? ? ? 9.8 99.5 100 0010 66 33 ? ? ? ?9.8 ?99.5 000 0011 3 ? ? ? ? 14.7 98.9 100 0011 67 ? ? ? ? ?14.7 ?98.9 000 0100 4 2 1 ? ? 19.5 98.1 100 0100 68 34 17 ? ? ?19.5 ?98.1 000 0101 5 ? ? ? ? 24.3 97 100 0101 69 ? ? ? ? ?24.3 ?97 000 0110 6 3 ? ? ? 29 95.7 100 0110 70 35 ? ? ? ?29 ?95.7 000 0111 7 ? ? ? ? 33.7 94.2 100 0111 71 ? ? ? ? ?33.7 ?94.2 000 1000 8 4 2 1 ? 38.3 92.4 100 1000 72 36 18 9 ? ?38.3 ?92.4 000 1001 9 ? ? ? ? 42.8 90.4 100 1001 73 ? ? ? ? ?42.8 ?90.4 000 1010 10 5 ? ? ? 47.1 88.2 100 1010 74 37 ? ? ? ?47.1 ?88.2 000 1011 11 ? ? ? ? 51.4 85.8 100 1011 75 ? ? ? ? ?51.4 ?85.8 000 1100 12 6 3 ? ? 55.6 83.1 100 1100 76 38 19 ? ? ?55.6 ?83.1 000 1101 13 ? ? ? ? 59.6 80.3 100 1101 77 ? ? ? ? ?59.6 ?80.3 000 1110 14 7 ? ? ? 63.4 77.3 100 1110 78 39 ? ? ? ?63.4 ?77.3 000 1111 15 ? ? ? ? 67.2 74.1 100 1111 79 ? ? ? ? ?67.2 ?74.1 001 0000 16 (*) 8 4 2 1 70.7 70.7 101 0000 80 40 20 10 5 ?70.7 ?70.7 001 0001 17 ? ? ? ? 74.1 67.2 101 0001 81 ? ? ? ? ?74.1 ?67.2 001 0010 18 9 ? ? ? 77.3 63.4 101 0010 82 41 ? ? ? ?77.3 ?63.4 001 0011 19 ? ? ? ? 80.3 59.6 101 0011 83 ? ? ? ? ?80.3 ?59.6 001 0100 20 10 5 ? ? 83.1 55.6 101 0100 84 42 21 ? ? ?83.1 ?55.6 001 0101 21 ? ? ? ? 85.8 51.4 101 0101 85 ? ? ? ? ?85.8 ?51.4 001 0110 22 11 ? ? ? 88.2 47.1 101 0110 86 43 ? ? ? ?88.2 ?47.1 001 0111 23 ? ? ? ? 90.4 42.8 101 0111 87 ? ? ? ? ?90.4 ?42.8 001 1000 24 12 6 3 ? 92.4 38.3 101 1000 88 44 22 11 ? ?92.4 ?38.3 001 1001 25 ? ? ? ? 94.2 33.7 101 1001 89 ? ? ? ? ?94.2 ?33.7 001 1010 26 13 ? ? ? 95.7 29 101 1010 90 45 ? ? ? ?95.7 ?29 001 1011 27 ? ? ? ? 97 24.3 101 1011 91 ? ? ? ? ?97 ?24.3 001 1100 28 14 7 ? ? 98.1 19.5 101 1100 92 46 23 ? ? ?98.1 ?19.5 001 1101 29 ? ? ? ? 98.9 14.7 101 1101 93 ? ? ? ? ?98.9 ?14.7 001 1110 30 15 ? ? ? 99.5 9.8 101 1110 94 47 ? ? ? ?99.5 ?9.8 001 1111 31 ? ? ? ? 99.9 4.9 101 1111 95 ? ? ? ? ?99.9 ?4.9 010 0000 32 16 8 4 2 100 0 110 0000 96 48 24 12 6 ?100 0 010 0001 33 ? ? ? ? 99.9 ?4.9 110 0001 97 ? ? ? ? ?99.9 4.9 010 0010 34 17 ? ? ? 99.5 ?9.8 110 0010 98 49 ? ? ? ?99.5 9.8 010 0011 35 ? ? ? ? 98.9 ?14.7 110 0011 99 ? ? ? ? ?98.9 14.7 010 0100 36 18 9 ? ? 98.1 ?19.5 110 0100 100 50 25 ? ? ?98.1 19.5 010 0101 37 ? ? ? ? 97 ?24.3 110 0101 101 ? ? ? ? ?97 24.3 010 0110 38 19 ? ? ? 95.7 ?29 110 0110 102 51 ? ? ? ?95.7 29 *default position after reset of the translator position.
NCV70514 www. onsemi.com 15 table 9. circular translator table msp[6:0] % of imax step mode sm[2:0] msp[6:0] % of imax step mode sm[2:0] msp[6:0] coil x coil y 100 011 010 001 000 msp[6:0] coil x coil y 100 011 010 001 000 msp[6:0] coil x coil y 1/2 1/4 1/8 1/16 1/32 msp[6:0] coil x coil y 1/2 1/4 1/8 1/16 1/32 010 0111 39 ? ? ? ? 94.2 ?33.7 110 0111 103 ? ? ? ? ?94.2 33.7 010 1000 40 20 10 5 ? 92.4 ?38.3 110 1000 104 52 26 13 ? ?92.4 38.3 010 1001 41 ? ? ? ? 90.4 ?42.8 110 1001 105 ? ? ? ? ?90.4 42.8 010 1010 42 21 ? ? ? 88.2 ?47.1 110 1010 106 53 ? ? ? ?88.2 47.1 010 1011 43 ? ? ? ? 85.8 ?51.4 110 1011 107 ? ? ? ? ?85.8 51.4 010 1100 44 22 11 ? ? 83.1 ?55.6 110 1100 108 54 27 ? ? ?83.1 55.6 010 1101 45 ? ? ? ? 80.3 ?59.6 110 1101 109 ? ? ? ? ?80.3 59.6 010 1110 46 23 ? ? ? 77.3 ?63.4 110 1110 110 55 ? ? ? ?77.3 63.4 010 1111 47 ? ? ? ? 74.1 ?67.2 110 1111 111 ? ? ? ? ?74.1 67.2 011 0000 48 24 12 6 3 70.7 ?70.7 111 0000 112 56 28 14 7 ?70.7 70.7 011 0001 49 ? ? ? ? 67.2 ?74.1 111 0001 113 ? ? ? ? ?67.2 74.1 011 0010 50 25 ? ? ? 63.4 ?77.3 111 0010 114 57 ? ? ? ?63.4 77.3 011 0011 51 ? ? ? ? 59.6 ?80.3 111 0011 115 ? ? ? ? ?59.6 80.3 011 0100 52 26 13 ? ? 55.6 ?83.1 111 0100 116 58 29 ? ? ?55.6 83.1 011 0101 53 ? ? ? ? 51.4 ?85.8 111 0101 117 ? ? ? ? ?51.4 85.8 011 0110 54 27 ? ? ? 47.1 ?88.2 111 0110 118 59 ? ? ? ?47.1 88.2 011 0111 55 ? ? ? ? 42.8 ?90.4 111 0111 119 ? ? ? ? ?42.8 90.4 011 1000 56 28 14 7 ? 38.3 ?92.4 111 1000 120 60 30 15 ? ?38.3 92.4 011 1001 57 ? ? ? ? 33.7 ?94.2 111 1001 121 ? ? ? ? ?33.7 94.2 011 1010 58 29 ? ? ? 29 ?95.7 111 1010 122 61 ? ? ? ?29 95.7 011 1011 59 ? ? ? ? 24.3 ?97 111 1011 123 ? ? ? ? ?24.3 97 011 1100 60 30 15 ? ? 19.5 ?98.1 111 1100 124 62 31 ? ? ?19.5 98.1 011 1101 61 ? ? ? ? 14.7 ?98.9 111 1101 125 ? ? ? ? ?14.7 98.9 011 1110 62 31 ? ? ? 9.8 ?99.5 111 1110 126 63 ? ? ? ?9.8 99.5 011 1111 63 ? ? ? ? 4.9 ?99.9 111 1111 127 ? ? ? ? ?4.9 99.9 *default position after reset of the translator position. besides the micro?step modes listed above, also two full step modes are implemented. full step mode 1 activates always only one coil at a time, whereas mode 2 always keeps 2 coils active. the table below lists the output current versus the translator positions for these cases and figure 10 shows the projection on a square. changing between micro?step mode and full step modes follows a similar scheme as changes between micro?step modes. changing from one full step mode to another full step mode will always result in a ?45deg step?back or forward? depending on the dir bit. for example: in the table below, when changing full step mode (positioner is on a particular row and full step column), then the new full step location will be one row above or below in the adjacent ?full step column?. the step?back and forward is executed after the nxt pulse.
NCV70514 www. onsemi.com 16 table 10. square translator table for full step msp[6:0] step mode ( sm[2:0] ) % of imax 101 or 110 111 coil x coil y full step1 full step2 000 0000 0 ? 100 0 001 0000 ? 0 71 71 010 0000 1 ? 0 100 011 0000 ? 1 ?71 71 100 0000 2 ? ?100 0 101 0000 ? 2 ?71 ?71 110 0000 3 ? 0 ?100 111 0000 ? 3 71 ?71 i y i x 1/4 th micro ?step sm[2:0] = 011 1 full step 1 sm [2:0] = 101 i y i x full step 2 sm [2:0] = 111 i y i x 0 2 3 0 1 2 3 1 23 0 figure 10. translator table: circular and square translator position the translator position can be read in the spi register . this is a 7?bit number equivalent to the 1/32 th micro?step from : circular translator table. the translator position is updated immediately following a next micro?step trigger (see below). nxt update translator position update translator position figure 11. translator position timing diagram direction the direction of rotation is selected by means of input pin dir and its ?polarity bit? (spi register). the polarity bit allows changing the direction of rotation by means of only spi commands instead of the dedicated input pin. direction = dir?pin exor positive direction of rotation means counter?clockwise rotation of electrical vector ix + iy. also when the motor is disabled (=0), both the dir pin and will have an effect on the positioner. the logic state of the dir pin is visible as a flag in spi status register. next micro?step trigger positive edges on the nxt input ? or activation of the ?nxt pushbutton? in the spi input register ? will move the motor current one step up/down in the translator table. the bit in spi is used to move positioner one (micro?)step by means of only spi commands. if the bit is set to ?1?, it is reset automatically to ?0? after having advanced the positioner with one micro?step. trigger ?next micro?step? = (positive edge on nxt?pin) or (=1) ? also when the motor is disabled (=0), nxt/dir/rhb functions will move the positioner according to the logic. ? in order to be sure that both the nxt pin and the spi command are individually attended, the following non overlapping zone has to be respected. in this case it is guaranteed that both triggers will have effect (2 steps are taken).
NCV70514 www. onsemi.com 17 ???? ???? nxt csb t csb _lo_width 0.8 v cc 0.2 v cc figure 12. nxt input non overlapping zone with the spi command dir nxt valid t nxt_hi t nxt_lo t dir_set t dir_hold 0.5v cc figure 13. nxt input timing diagram for control by means of i/o?s, the nxt pin operation with respect to dir, step0 and step1 pins should be in a non?overlapped way . see also the timing diagram below (refer to the ac table for the timing values). the step0 and step1 pins or spi bits setting, when changed, is accepted upon the consequent either nxt pin rising edge or spi command only. on the other hand, the spi bits , and can change state at the same time in the same spi command: the next micro?step will be applied with the new settings. irun, ihold and ?run / not hold? mode the rhb input pin and it?s ?polarity bit? (spi register) allow to switch the driver between ?run mode? and ?hold mode?. ?run mode? = not(?hold mode?) = rhb?pin exor ? in ?run mode?, the current translator table is stepped through based on the ?nxt & dir? commands. the amplitude of the motor current (=imax) is set by spi control register . ? in ?hold mode?, nxt & dir will have no effect and the position in the current translator table is maintained. the motor current amplitude is set by spi control register . the run and hold current settings correspond to the following current levels: table 11. irun and ihold values (4bit) register value peak motor current irun (ma) peak motor current ihold (ma) 0 59 0 1 71 59 2 84 71 3 100 84 4 119 100 5 141 119 6 168 141 7 200 168 8 238 200 9 283 238 a 336 283 b 400 336 c 476 400 d 566 476 e 673 566 f 800 673 note: during hold with a hold current of 0 ma the stall and motion detection and the open coil detection are disabled. the pwm d uty cycle registers will present 0% duty cycle.
NCV70514 www. onsemi.com 18 whenever or is changed, the new coil currents will be updated immediately at the next pwm period. in case the motor is disabled (=0), the logic is functional and both rhb pin and bit will have effect on nxt/dir operation (not on the h?bridges). when the chip is in sleep mode, the logic is not functional and as a result, the rhb pin will have no effect. the logic state of the rhb pin is visible as a flag in spi status register. note: the hard?reset function is embedded in the ?hold mode? by means of a special sequence on the dir pin, see also hard?reset function chapter. under?voltage detection the NCV70514 has three uv threshold levels. two higher threshold levels are programmable over spi register uvxthr, third threshold level is fixed. each uv level has its own flag readable via spi and can create interrupt to microcontroller when dedicated bit of interrupt enable register is set. all interrupt sources uv?s, bemf, etc. are grouped into single interrupt line (pin) errb. when supply voltage vbb drops under dedicated uvx level, several actions are performed. ? uv1 level ? no action inside device regarding to h?bridges ? only when uv1inten interrupt enable bit is set, errb pin is pulled down. microcontroller needs to do action like soft stop, etc based on this interrupt. ? uv2 level ? when uv2inten interrupt enable bit is set, errb pin is pulled down. when uv2minten interrupt enable bit is set, the errb pin is pulled down in the moment nxp pulse comes, the device then stops executing nxt pulses and starts counting them in step loss counter . ? uv3 level ? device each time disables h?bridge drivers ( = 0). when uv3inten interrupt enable bit is set, errb pin is pulled down. when uv3minten interrupt enable bit is set, the errb pin is pulled down in the moment nxp pulse comes, the device then stops executing nxt pulses and starts counting them in step loss counter . only if the =0 the motor can be enabled again by writing =1 in the control register 1. note: the change of dir and step mode will not be taken into account in step loss counter. step loss register range is 7 bits => 0 to 127 nxt pulses, no overflow, keeping the counter at maximum value of 127 if more than 127 nxt pulses are received. table 12. uv1/2 thresholds settings (4bit) uvxthr index uv1/2 threshold level (v) 0 5.98 1 6.31 2 6.65 3 6.98 4 7.31 5 7.64 6 7.97 7 8.31 8 8.64 9 8.97 a 9.3 b 9.63 c 9.97 d 10.3 e 10.63 f 10.96 stall and motion detection motion detection is based on the back electromotive force (bemf or back emf) generated into the running motor. when the motor is blocked, e.g. when it hits the end?position, the velocity and as a result also the generated back emf, is disturbed. the NCV70514 measures the back emf during the current zero crossing phase and makes it available in the spi status register 4. the back emf voltage is measured several times in each pwm cycle during zero crossing phase. samples taken during pwm on phase of the switches in the second coil are discarded not to add noise to measurement (see figure 14). results are then converted into a 5?bits word with the following formula: bemf_code(dec) v_mot_xory_diff(v) gain 5 4 2 5 2.41 when the result is ready, it is indicated by bit in status register. when using normal mode of back emf measurement ( = 0), last sample before end of current zero crossing phase becomes available in register (see the red circle on figure 14). when the enhanced back emf measurement mode is set by bit, all non discarded results are continuously available in register (see red and all black circles on figure 14). this allows microcontroller
NCV70514 www. onsemi.com 19 (when reading content of the register fast enough) to follow back emf signal and its shape during zero crossing phase and use more complex algorithms to optimize the work of driven stepper motor. i coil x nxt nxt zero crossing position (0;64) pins mxp/mxn in hiz state mxn mxn mxp mxp mxp myp myp myp myp myp bemf sampling v myp/myn v mxp/mxn 0 t t t myp ideal coil current real coil current current decay vbb + 0.6 v voltage transient vbemf t figure 14. back emf sampling for slow speed or when a motion ends at a full step position (there is an absence of next nxt trigger), the end of the zero crossing is taking too long or is non?existing. in this case, the back emf voltage is taken the latest at ?stall time?out? time and this value is used also for comparison with stall threshold to detect stall situation in run mode or movement in hold mode. the ?stall time?out? is set in spi by means of register and is expressed in counts of 4/f pwm (see ac table), roughly in steps of 0.2 ms. if = 0, time?out is not active. at the end of the current zero crossing phase the internal circuitry compares measured back emf voltages with register, which determines threshold for stall detection. the last sample of back emf taken before end of zero crossing phase is used for stall detection in normal mode as well as in enhanced back emf mode. when = 0 then stall detection is disabled. when value of is dif ferent from 0 and measured back emf signal is lower than threshold for 2 succeeding coil current zero?crossings (including both x and y coil), then the bit in spi status register 1 is set, the current translator table goes 135 degrees in opposite direction and the errb pin is pulled down, irun is maintained. the stall bit is cleared by reading the status register 1, also the errb pin becomes inactive again. with stall bit cleared, the chip reacts on ?next micro?step triggers? only after direction has changed its state at least once. an additional feature of the NCV70514 is the detection of uncontrolled motion during hold. if the stall detection is enabled and the hold position is at full steps (full step mode1, 0 , 90 , 180 , 270 ) with only excitation of one coil, the NCV70514 is checking upon back emf voltages higher than or equal to the threshold. if this voltage is detected, it indicates there is a motor movement. the stall bit in the spi register is set and the errb pin is pulled down. the motion detection during hold does not work for ihold 0 a. notes: 1. used stall detection is covered by patent us 8,058,894b2 2. as the stall threshold register is 4 bits wide, the 4 msbs of 5?bit register are taken for comparison. stall detection and bemf measurement are performed only when speed register value is less than or equal to speed threshold register value . range and resolution of speed register and speed threshold register are 0 to 5100 s and 20 s/digit for half stepping mode. accuracy of speed (time) measurement is given by the accuracy of the internal oscillator. if measured back emf voltage has not expected polarity, the back emf sign flag is set. motor pin, where lower voltage is expected, is tied to gnd by pull down current. sign is determined by comparator, which compares the polarity of voltage measured over the coil with expected polarity of voltage. nxt xp xn 2ma expected polarity bemf polarity bemfs nxt v bemf h-bridge hiz state v xp v xn xor figure 15. back emf sign value the last measured back emf value , sign flag and coil where the last back emf sample was taken can be read out via spi.
NCV70514 www. onsemi.com 20 table 13. stall thresholds settings (4bit) stthr index stthr level (v) stthr level (v) bemfgain = 1 bemfgain = 0 0 disable disable 1 0.48 0.24 2 0.96 0.48 3 1.44 0.72 4 1.92 0.96 5 2.4 1.2 6 2.88 1.44 7 3.36 1.68 8 3.84 1.92 9 4.32 2.16 a 4.8 2.4 b 5.28 2.64 c 5.76 2.88 d 6.24 3.12 e 6.72 3.36 f 7.2 3.6 warning, error detection and diagnostics feedback open & short circuit diagnostic the NCV70514 stepper driver features an enhanced diagnostic detection and feedback, to be read by the external microcontroller unit (mcu). among the main items of interest for the application and typical failures, are open coil and the short circuit condition, which may be to ground (chassis), or to supply (battery line). to serve this purpose two diagnostic modes are available in the device. the first is called ?automatic diagnostic? and is executed after each power?up sequence. in addition, by a specific bit setting, it can be enabled after any output (h?bridge) activation. the other mode is defined as ?user diagnostic? or ?normal mode diagnostic? and consists in applying activation sequences directly from the mcu and read back the consequent status via the proper device registers. open & short circuit automatic diagnostic the auto?diagnostic is executed after each power up, or when enabling the h?bridge (=0 =1) in case the bit would be programmed to one (see spi table, control register 0x03, bit 6). during the auto?diagnostic sequence, the device makes use of internal pull?ups and pull?downs (see figure 16) to test the connections at the xp, xn, yp, yn pins with weak currents. this mechanism guarantees a very wide coverage; however, some conditions are reported as multiple failure source detections. this is due to the impossibility to discern between the two cases from electrical point of view. details of failures combination coverage by the automatic diagnostic for the x coil are shown in figure 14. the same is applicable for y coil. any short circuit detection disables the output h?bridges ( = 0) and does not allow the device to automatically proceed to ?normal mode?. to permit entering normal mode, the registers involved must be cleared out by spi reading and the error condition removed prior enabling again the outputs ( set to ?1?). the dead time for automatic diagnostic routine is 2 ms (*). the automatic diagnostic is interrupted when the supply voltage drops below uv3 level. note: (*): for a controlled start of the automatic diagnostics, the user has to place the motor driver in high impedance state by setting the bit to ?0?. after setting the bit to ?1?, there is a need for an additional delay time. this is needed for recirculation of the motor current. an average time of approximately 2 ms is needed. this time has to be taken into account by the user. pt nt ref. x or y h-bridge nb pb ref. pn figure 16. automatic diagnostic
NCV70514 www. onsemi.com 21 table 14. diagnostics open/short detection fault condition sr1[5:4] = {short, open} sr7a[6] = {openx,l} sr7a[3] = {shrtxpb} sr7a[2] = {shrtxnb} sr7a[1] = {shrtxpt} sr7a[0] = {shrtxnt} no short, no open coil ? unique detection 0, 0 0 0 0 0 0 short xp and/or xn top side, no open coil; short xp and xn top side and open coil 1, 0 0 0 0 1 1 short xp and/or xn bottom side, no open coil; short xp and xn bottom side and open coil 1, 1 1 1 1 0 0 no short or short xn bottom side, open coil 1, 1 1 0 1 0 0 short xp top side, open coil 1, 1 1 0 0 1 0 short xn top side and short xp bottom side, open coil 1, 1 1 1 0 0 1 short xn top side, open coil 1, 1 1 0 0 0 1 open & short circuit user diagnostic when in normal mode, the device will continuously check upon errors with respect to the expected behavior. the open load condition is determined by the fact that the pwm duty cycle keeps 100% value for a time longer than set by register . this is valid of course only for the x/y coil where the current is supposed to circulate, meaning that in full step positions (msp[6:0] = {0; 32; 64; 96} (dec)) the open load can be detected only for one of the coil at a time (respectively {x; y; x; y}). the same reasoning applies for the short circuits detection. due to the timeout value set by , the open coil detection is dependent on the motor speed. in more detail, there is a maximum speed at which it can be done. table 15 specifies these maxima for the different step modes. for practical reasons, all values are given in full steps per second. table 15. maximum velocities for open coil detection step mode speed [fs/s] for given 00 01 10 11 full step1 200 40 20 5 full step2 400 80 40 10 1/2 300 60 30 7.5 1/4 350 70 35 8.8 1/8 375 75 37.5 9.4 1/16 387.5 77.5 38.8 9.7 1/32 393.8 78.8 39.4 9.8 when open coil condition is detected, the appropriate bit ( or ) together with bit in the spi status register are set. reaction of the h?bridge to open coil condition depends on the settings of and bits. when both and bits are 0, bit stays in 1 and only h?bridge where open coil is detected is disabled. when bit is set, both h?bridges are disabled (=0) in case of open coil detection. when bit is set, drivers remain active for both coils independently of bit. the short circuit detection monitors the load current in each activated output stage. the current is measured in terms of voltage drop over the mosfets? r ds(on) . if the load current exceeds the over?current detection threshold, then the over?current flag is set and the drivers are switched off to protect the integrated circuit. each driver stage has an individual detection bit for the n side and the p side. when short circuit is detected, is set to 0. the positioner, the nxt, rhb, step0, step1 and dir stay operational. the flag (result of or?ing the latched flags: or or or or or or or ) is reset when the microcontroller reads out the short circuit status flags in status registers 7a and 8a. to enable the motor again after reading out of the status flags, =1 has to be written. depending on the bit, automatic diagnostic can be performed after enabling the outputs (h?bridges) prior to going to normal mode operation. notes: 1. successive reading of the flags and re?enabling the motor in case of a short circuit condition may lead to damage of the drivers. 2. example: shrtxpt means: short at x coil, positive output pin, top transistor. 3. in case of the short from any stepper motor pin to the top side during switching event from bottom to top on motor pin, the flag ?short to bottom side? is set instead of the expected ?short to top side? flag. thermal warning and shutdown when junction temperature is above t tw , the thermal warning bit is set (spi register) and the errb pin is
NCV70514 www. onsemi.com 22 pulled down (*). if junction temperature increases above thermal shutdown level, then also the flag is set, the errb pin is pulled down, the motor is disabled ( = 0) and the hardware reset is disabled. if t j < t tw level and bit has been read?out, the status of is cleared and the errb pin is released. only if the ==0, the motor can be enabled again by writing =1 in the control register 1. during the over temperature condition the hardware reset will not work until t j < t tw and the readout is done. in this way it is guaranteed that after a =1 event, the die?temperature decreases back to the level of . note: (*): during the situation the motor is not disabled while the errb is pulled down. to be informed about other error situations it is recommended to poll the status registers on a regular base (time base driven by application software in the millisecond domain). spi framing error the spi transmission is continuously monitored for correct amounts of incoming data bits. if within one frame of data the number of spi clk high transitions is not equal to a multiple of 16 (16,32,48,...), then the spi error bit in the status register is set and the errb pin goes low to indicate this error to the micro controller. during this fault condition the incoming data are not loaded into the internal registers and the transmit shift register is not loaded with the requested data. the status of the spi framing error is reset by an errorless received frame requesting for the motor controller status register 0. this request will reset the spi error bit and releases the errb pin (high). error output this is an open drain output to flag a problem to the external microcontroller. the signal on this output is active low and the logic combination of: not(errb) = ( or or or or or or or (bemfinten and bemfres) or (uv1inten and uv1) or (uv2inten and uv2) or (uv2minten and uv2m) or (uv3inten and uv3) or (uv3minten and uv3m) or (*)reset state) and not (**)sleep mode note: (*) reset state: after a power?on or a hard?reset, the errb is pulled low during t hr_err (table 7 ? ac parameters). note: (**) sleep mode: in sleep mode the errb is always inactive (high). sleep mode the motor driver can be put in a low?power consumption mode (sleep mode). the sleep mode is entered automatically after a power?on or hard reset and can also be activated by means of spi bit . in sleep?mode, all analog circuits are suspended in low?power and all digital clocks are stopped: spi communication is impossible. the motor driver is disabled (even if =1), the content of all logic registers is maintained (including , and ), all logic output pins are disabled (errb has no function) and none of the input pins are functional with the exception of pin csb. only this pin can wake?up the chip to normal mode (i.e. clear bit ) by means of a ?high?to?low voltage? transition. after wake?up, time t wu (see ac t able) is needed to restore analog and digital clocks and to bring spi communication within specification. notes: ? the hard?reset function is disabled in sleep mode. ? the thermal shutdown function will be ?frozen? during sleep mode and re?activated at wake?up. this is important in case bit =1 was cleared already by the micro and was not ?0? yet. ? the csb low pulse width has to be within t csb_with , (see ac table) to guarantee a correct wake?up. power?on reset, hard?reset function after a power?on or a hard?reset, a flag

in the spi status register is set and the errb is pulled low. the errb stays low during this reset state. the typical power?on reset time is given by t hr_err (table 7 ? ac p arameters). after the reset state the device enters sleep mode and the errb pin goes high to indicate the motor controller is ready for operation. by means of a specific pattern on the dir pin during the ?hold mode?, the complete digital part of driver can be reset without a power?cycle. this hard?reset function is activated when the input pin dir changes logic state ?0 1 0 1? within t hr_trig in five consecutive patterns during ?hold mode?. see figure below and table 7 ? ac parameters. the operation of all analog circuits is suspended during the reset state of the digital. similar as for a normal power?on, the flag

is set in the spi register after a hard?reset and the errb pin is pulled low during t hr_err (table 7 ? ac parameters). to enable the motor controller to perform a proper self diagnosis, it is recommended that the motor is in ?hold mode? before the hard reset is generated. the minimum time (t hr_set ) between the beginning of ?hold mode? and the first rising edge of the dir pin is given in table 7 ? ac parameters.
NCV70514 www. onsemi.com 23 t hr_set dir rhb hold mode t hr_trig t hr_dir errb t hr_err figure 17. hard reset timing diagram spi interface the serial peripheral interface (spi) is used to allow an external microcontroller (mcu) to communicate with the device. NCV70514 acts always as a slave and it cannot initiate any transmission. the operation of the device is configured and controlled by means of spi registers, which are observable for read and/or write from the master. the NCV70514 spi transfer size is 16 bits. during an spi transfer, the data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (clk) synchronizes shifting and sampling of the information on the two serial data lines: do and di. the do signal is the output from the slave (NCV70514), and the di signal is the output from the master. a slave or chip select line (csb) allows individual selection of a slave spi device in a time multiplexed multiple?slave system. the csb line is active low. if an NCV70514 is not selected, do is in high impedance state and it does not interfere with spi bus activities. since the NCV70514 always clocks data out on the falling edge and samples data in on rising edge of clock, the mcu spi port must be configured to match this operation. byte 1 byte 2 di data [7:0] di addr [7:4] di addr [3:0] msb 6 lsb 5 4 3 2 1 msb 6 lsb 54321 msb cs clk di do 6 lsb 5 4 3 2 1 msb 6 lsb 54321 figure 18. spi frame structure the implemented spi allows connection to multiple slaves by means of both time?multiplexing (csb per slave) and daisy?chain (csb per group of slaves). multi?axis connections schemes are discussed in a separate chapter below. spi transfer format and pin signals all spi commands (to di pin of NCV70514) from the micro controller consist of one ?address byte? and one ?data byte?. the address byte contains up to two addresses of each 4 bit long. these addresses are pointing to a command or requested action in a spi slave. three command?types can be distinguished: ?write to a control register?, ?read from a control register? and ?read from a status register?. ? writing to a control register is accomplished only if the address of the target register appears in the first half of the address byte. the contents of the data?byte will be copied in the control register. the contents of the addressed control register will be sent back by the NCV70514 in the next spi access. ? reading from a control register is accomplished by putting its address in the second half of the address byte. the data byte has no function for this command. ? reading from a status register is accomplished by putting its address either in the first or in the second half of the address byte. the data byte has no function for this command. the response (from do pin of NCV70514) on these commands is always 2 bytes long. the possible combinations of di/do and their use are summarized in the following table 16. figure 19 gives examples of the data streaming:
NCV70514 www. onsemi.com 24 table 16. spi command address, data and response structure di addr[7:4] di addr[3:0] di data[7:0] do byte1 do byte2 comment on use acr1 acr2 dicr1 docr1 docr2 control and status of cr acr1 asr1 dicr1 docr1 dosr1 control and status of sr acr1 nop dicr1 docr1 00h control and no status asr1 acr1 xxh dosr1 docr1 status of sr and cr asr1 asr2 xxh dosr1 dosr2 status of sr and sr asr1 nop xxh dosr1 00h status of sr nop acr1 xxh 00h docr1 status of cr nop asr1 xxh 00h dosr1 status of sr nop nop xxh 00h 00h dummy/placeholder with: acrx = address of control register x asrx = address of status register x dicrx = data input of control register x doxy = data output of corresponding register contents transmitted in the next spi access nop = register address outside range : 0h xxh = any byte master ?> slave cs acr1 ??? acr2 data for acr1 previous data slave ? > master example 1: write cr1, read cr1 and cr2 previous data command this is the data from command before or not valid after power up or reset data from acr1 data from acr2 next command next data data master ? > slave cs acr3 ??? asr5 data for acr3 previous data slave ?> master example 2: write cr3, read cr3 and sr5 previous data command this is the data from command before or not valid after power up or reset data from acr3 data from asr5 next command next data data master ? > slave cs asr5 ??? asr7 dummy previous data slave ?> master example 3: read sr5 and sr7 previous data command this is the data from command before or not valid after power up or reset data from asr5 data from asr7 next command next data data the written control registers are updated by the NCV70514 at the rising edge of csb the contents of the previously addressed registers are copied into the transmission shift registers at the falling edge of csb figure 19. command and data streaming of spi spi control registers (cr) all spi control registers have read/write access.
NCV70514 www. onsemi.com 25 table 17. spi control registers (cr) 4?bit address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default after reset 01h or 11h (cr1) dirp rhbp nxtp moten stthr3 stthr2 stthr1 stthr0 0000 0000 02h or 12h (cr2) ihold3 ihold2 ihold1 ihold0 irun3 irun2 irun1 irun0 0000 0000 03h or 13h (cr3) enhbemf en diagen emc1 emc0 slp sm2 sm1 sm0 0010 0000 04h (cr4) stto7 stto6 stto5 stto4 stto3 stto2 stto1 stto0 0001 0000 05h or 15h (cr5) spthr7 spthr6 spthr5 spthr4 spthr3 spthr2 spthr1 spthr0 0000 0000 06h or 16h (cr6) uv1thr3 uv1thr2 uv1thr1 uv1thr0 uv2thr3 uv2thr2 uv2thr1 uv2thr0 0000 0000 07h or 17h (cr7) ad4 bemfgain bemf resinten uv1inten uv2inten uv2minten uv3inten uv3minten 0000 0000 14h (cr4a) notused notused notused notused opendet1 opendet0 opendis openhiz 0000 0100 NCV70514 responds on every incoming byte by shifting out the data stored on the last address sent via the bus. after por the initial address is unknown, so the first data shifted out are undefined.
NCV70514 www. onsemi.com 26 table 18. bit definition symbol map position description dirp bit 7 ? addr_0x01 or 0x11 (cr1) polarity of dir pin, which controls direction status; dirp = 1 inverts the logic polarity of the dir pin) rhbp bit 6 ? addr_0x01 or 0x11 (cr1) polarity of rhb pin, which controls run/hold status; rhbp = 1 inverts logic polarity of the rhb pin (hold = not(rhb xor )) nxtp bit 5 ? addr_0x01 or 0x11 (cr1) push button pin, generating next step in position table moten bit 4 ? addr_0x01 or 0x11 (cr1) enables the h?bridges (motor activated in run or hold mode) stthr[3:0] bits [3:0] ? addr_0x01 or 0x11 (cr1) threshold level for stall detection, when ?0?, stall detection is disabled ihold[3:0] bits [7:4] ? addr_0x02 or 0x12 (cr2) current amplitude in hold mode irun[3:0] bits [3:0] ? addr_0x02 or 0x12 (cr2) current amplitude in run mode enhbemfen bit 7 ? addr_0x03 or 0x13 (cr3) enhanced bemf measurement functionality is activated when bit is set diagen bit 6 ? addr_0x03 or 0x13 (cr3) enables automatic diagnostic at rising edge of bit emc[1:0] bits [5:4] ? addr_0x03 or 0x13 (cr3) voltage slope defining bits for motor driver switching slp bit 3 ? addr_0x03 or 0x13 (cr3) places device in sleep mode with low current consumption (when 1) sm[2:0] bits [2:0] ? addr_0x03 or 0x13 (cr3) step mode selection stto[7:0] bits [7:0] ? addr_0x04 (cr4) max difference between two successive full step next pulse periods (time- out), after this time the bemf sample is taken to verify stall spthr[7:0] bits [7:0] ? addr_0x05 or 0x15 (cr5) speed threshold register, bemf measurement and stall detection is acti- vated when speed register value is less than or equal to value uv1thr[3:0] bits [7:4] ? addr_0x06 or 0x16 (cr6) setting of under voltage level uv1. see chapter uv detection uv2thr[3:0] bits [3:0] ? addr_0x06 or 0x16 (cr6) setting of under voltage level uv2. see chapter uv detection ad4 bit 7 ? addr_0x07 or 0x17 (cr7) address selection bit, alternating register ?banks?. when ad = 1, all addresses will be interpreted with a ?1? in the first nibble (allowing to access registers cr4a, sr7a, sr8a). when ad = 0, all addresses will be interpreted with a ?0? in the first nibble (allowing to access registers cr4, sr7, sr8). bemfgain bit 6 ? addr_0x07 or 0x17 (cr7) gain of bemf measurement channel ? ?0?: gain 0.5, ?1?: gain 0.25 bemfresinten bit 5 ? addr_0x07 or 0x17 (cr7) bemf result interrupt enable uv1inten bit 4 ? addr_0x07 or 0x17 (cr7) under voltage 1 detection interrupt enable uv2inten bit 3 ? addr_0x07 or 0x17 (cr7) under voltage 2 detection interrupt enable uv2minten bit 2 ? addr_0x07 or 0x17 (cr7) under voltage 2 detection and motion interrupt enable uv3inten bit 1 ? addr_0x07 or 0x17 (cr7) under voltage 3 detection interrupt enable uv3minten bit 0 ? addr_0x07 or 0x17 (cr7) under voltage 3 detection and motion interrupt enable opendet[1:0] bits [3:2] ? addr_0x14 (cr4a) open coil detection time setting bits (see table 7 ? ac parameters ) opendis bit 1 ? addr_0x14 (cr4a) when bit is set, open coil detection status is flagged, but drivers control remain active for both coils, bit setting has higher priority than bit openhiz bit 0 ? addr_0x04 (cr4a) when bit is set, during open coil detection both drivers are deactivated (moten=0)
NCV70514 www. onsemi.com 27 spi status registers (sr) all spi status registers have read only access, with the odd parity on bit7. parity bit makes the numbers of 1 in the byte odd. table 19. spi status registers (sr) 4?bit address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comment default after reset 08h or 18h (sr1) par spi,l short,r* open,r* tsd,l tw,r stall,l hr,l errors 0xx 0001 09h or 19h (sr2) par orerr, r bemfres uv1,l uv2,l uv2m,l uv3,l uv3m,l intst 101 1010 0ah or 1ah (sr3) par msp6,r msp5,r msp4,r msp3,r msp2,r msp1,r msp0,r micro?step position 001 0000 0bh or 1bh (sr4) par bemfcoil, r bemfs, r bemf4, r bemf3, r bemf2, r bemf1, r bemf0, r bemf x00 0000 0ch or 1ch (sr5) sp7,r sp6,r sp5,r sp4,r sp3 ,r sp2,r sp1,r sp0,r speed 1111 1111 0dh or 1dh (sr6) par sl6,l sl5,l sl4,l sl3,l sl2,l sl1,l sl0,l steploss 000 0000 0eh (sr7) par t/bx,r signx,r pwmx4,r pwmx3,r pwmx2,r pwmx1,r pwmx0,r pwmx 000 0000 0fh (sr8) par t/by,r signy,r pwmy4,r pwmy3,r pwmy2,r pwmy1,r pwmy0,r pwmy 000 0000 1eh (sr7a) par openx,l step0pin,r step1pin,r shrtxpb,l shrtxnb,l shrtxpt,l shrtxnt,l input pins & shortsx xxx 0000 1fh (sr8a) par openy,l rhbpin,r dirpin, r shrtypb,l shrtynb,l shrtypt,l shrtynt,l input pins & shortsy xxx 0000 flags have ?,l? for latched information or ?,r? for real time information. all latched flags are ?cleared upon read?. x = value after reset is defined during reset phase (diagnostics) r* = real time read out of values of other latches. reading out this r* value does not reset the bit, and does not reset the va lues of the latches this bit reads out. table 20. bit definition symbol map position description par bit 7 ? addr_0x08 or 0x18 (sr1) parity bit for sr1 spi bit 6 ? addr_0x08 or 0x18 (sr1) spi error: no multiple of 16 rising clock edges between falling and rising edge of csb line short bit 5 ? addr_0x08 or 0x18 (sr1) an over current detected (common: set if at least one of the shortij indi- vidual bits is set) open bit 4 ? addr_0x08 or 0x18 (sr1) open coil x or y detected (common: set if at least one of the two specific x/y open coil bits is set) tsd bit 3 ? addr_0x08 or 0x18 (sr1) thermal shutdown tw bit 2 ? addr_0x08 or 0x18 (sr1) thermal warning stall bit 1 ? addr_0x08 or 0x18 (sr1) stall detected by the internal algorithm hr bit 0 ? addr_0x08 or 0x18 (sr1) hard reset flag: 1 indicates a hard reset has occurred par bit 7 ? addr_0x09 or 0x19 (sr2) parity bit for sr2 orerr bit 6 ? addr_0x09 or 0x19 (sr2) logic or of all bits of sr1 (error bits) bemfres bit 5 ? addr_0x09 or 0x19 (sr2) bemf result ready at register uv1 bit 4 ? addr_0x09 or 0x19 (sr2) under voltage 1 detection uv2 bit 3 ? addr_0x09 or 0x19 (sr2) under voltage 2 detection uv2m bit 2 ? addr_0x09 or 0x19 (sr2) under voltage 2 detection and nxt pulse arrive during uv2 state (motion) uv3 bit 1 ? addr_0x09 or 0x19 (sr2) under voltage 3 detection uv3m bit 0 ? addr_0x09 or 0x19 (sr2) under voltage 3 detection and nxt pulse arrive during uv3 state (motion) par bit 7 ? addr_0x0a or 0x1a (sr3) parity bit for sr3
NCV70514 www. onsemi.com 28 table 20. bit definition symbol description map position msp[6:0] bits [6:0] ? addr_0x0a or 0x1a (sr3) translator micro?step position par bit 7 ? addr_0x0b or 0x1b (sr4) parity bit for sr4 bemfcoil bit 6 ? addr_0x0b or 0x1b (sr4) last bemf measurement was done on coil: 0 = x, 1 = y bemfs bit 5 ? addr_0x0b or 0x1b (sr4) bemf measured voltage has expected polarity (yes = 0, no = 1) bemf[4:0] bits [4:0] ? addr_0x0b or 0x1b (sr4) bemf value measured during zero crossing sp[7:0] bits [7:0] ? addr_0x0c or 0x1c (sr5) speed register par bit 7 ? addr_0x0d or 0x1d (sr6) parity bit for sr6 sl[6:0] bits [6:0] ? addr_0x0d or 0x1d (sr6) step loss register counts number of nxt pulses arrived after activation of under?voltage event or other failure state when nxt pulses are ignored (e.g. tsd, ovc, stall). counter keeps maximum value of 127 after more pulses have been received (no overflow) par bit 7 ? addr_0x0e (sr7) parity bit for sr7 t/bx bit 6 ? addr_0x0e (sr7) pwm regulation mode on x coil (top = 1 or bottom = 0 regulation) signx bit 5 ? addr_0x0e (sr7) pwm sign for x coil regulation (?0? = positive, ?1? = negative) pwmx[4:0] bits [4:0] ? addr_0x0e (sr7) actual pwm duty cycle value for coil x par bit 7 ? addr_0x0f (sr8) parity bit for sr8 t/by bit 6 ? addr_0x0f (sr8) pwm regulation mode on y coil (top = 1 or bottom = 0 regulation) signy bit 5 ? addr_0x0f (sr8) pwm sign for y coil regulation (?0? = positive, ?1? = negative) pwmy[4:0] bits [4:0] ? addr_0x0f (sr8) actual pwm duty cycle value for coil y par bit 7 ? addr_0x1e (sr7a) parity bit for sr7a openx bit 6 ? addr_0x1e (sr7a) open coil x detected step0pin bit 5 ? addr_0x1e (sr7a) read out of step0 pin logic status step1pin bit 4 ? addr_0x1e (sr7a) read out of step1 pin logic status shrtxpb bit 3 ? addr_0x1e (sr7a) short circuit detected at xp pin towards ground (bottom) shrtxnb bit 2 ? addr_0x1e (sr7a) short circuit detected at xn pin towards ground (bottom) shrtxpt bit 1 ? addr_0x1e (sr7a) short circuit detected at xp pin towards supply (top) shrtxnt bit 0 ? addr_0x1e (sr7a) short circuit detected at xn pin towards supply (top) par bit 7 ? addr_0x1f (sr8a) parity bit for sr8a openy bit 6 ? addr_0x1f (sr8a) open coil y detected rhbpin bit 5 ? addr_0x1f (sr8a) read out of rhb pin logic status dirpin bit 4 ? addr_0x1f (sr8a) read out of dir pin logic status shrtypb bit 3 ? addr_0x1f (sr8a) short circuit detected at yp pin towards ground (bottom) shrtynb bit 2 ? addr_0x1f (sr8a) short circuit detected at yn pin towards ground (bottom) shrtypt bit 1 ? addr_0x1f (sr8a) short circuit detected at yp pin towards supply (top) shrtynt bit 0 ? addr_0x1f (sr8a) short circuit detected at yn pin towards supply (top)
NCV70514 www. onsemi.com 29 application examples for multi?axis control the wiring diagrams below show possible connections of multiple slaves to one microcontroller. in these examples, all movements of the motors are synchronized by means of a common nxt wire. the direction and run/hold activation is controlled by means of an spi bus. further i/o reduction is accomplished in case the errb is not connected. this would mean that the microcontroller operates while polling the error flags of the slaves. ultimately, one can operate multiple slaves by means of only 4 spi connections: even the nxt pin can be avoided if the microcontroller operates the motors by means of the ?nxtp? bit. nxt csb1 csb2 csb3 di/do/clk errb nxt csb di/do/clk errb nxt csb errb nxt csb di/do/clk errb 3 3 3 ic1 NCV70514 ic2 NCV70514 ic3 NCV70514 microcontroller ?multiplexed spi? vcc rpu csb/clk/nxt do di errb csb/clk/nxt di do errb csb/clk/nxt di do errb csb/clk/nxt di do errb 3 3 3 ic1 NCV70514 ic2 NCV70514 ic3 NCV70514 microcontroller ?daisy?chained spi? vcc rpu figure 20. examples of wiring diagrams for multi?axis control* di/do/clk csb/clk do di csb/clk di do csb/clk di do csb/clk di do 2 2 2 ic1 NCV70514 ic2 NCV70514 ic3 NCV70514 microcontroller full spi, minimal wiring figure 21. minimal wiring diagram for multi?axis control* *this drawing does not present the hard reset interconnection. for the functionality of the hard reset function the rhb and dir pins have to be connected to the micro controller.
NCV70514 www. onsemi.com 30 electro magnetic compatibility the NCV70514 has been developed using state?of?the?art design techniques for emc. the overall system performance depends on multiple aspects of the system (ic design & lay?out, pcb design and layout ...) of which some are not solely under control of the ic manufacturer. therefore, meeting system emc requirements can only happen in collaboration with all involved parties. special care has to be taken into account with long wiring to motors and inductors. a modern methodology to regulate the current in inductors and motor windings is based on controlling the motor voltage by pwm. this low frequency switching of the battery voltage is present at the wiring towards the motor or windings. to reduce possible radiated transmission, it is advised to use twisted pair cable and/or shielded cable. pcb layout recommendations recommended pcb layout for the NCV70514 is shown on the following figure. the vdd capacitor c4 must be placed close to the device and with gnd straight to the device and not the common gnd. this is crucial for optimum emc performance. figure 22. recommended pcb layout ordering information device marking peak current boost peak current end market/version package* shipping ? NCV70514mw003g n70514?3 800 ma n.a. automotive high temperature version qfn32 5x5 with wettable flanks (pb?free) 60 units / tube NCV70514mw003r2g n70514?3 5000 / tape & reel *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and m ounting techniques reference manual, solderrm/d. ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCV70514 www. onsemi.com 31 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ?? ?? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCV70514/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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