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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. system management microcontroller 19-5327; rev 2; 1/12 typical operating circuit appears at end of data sheet. general description the max31782 provides a complete solution for the monitoring and controlling of complex system physical health characteristics based on a high-performance, maxq20, 16-bit microcontroller core with generous amounts of flash program/data and ram data memory. i/o resources include an accurate measurement sys - tem for temperature and voltage, pwm outputs, timer inputs, and gpio to support monitoring and controlling critical system parameters such as temperature, volt - age, fan speed, and chassis intrusion. direct connection of diode-connected transistors used as remote tem - perature sensors is supported as well as expansion to a virtually unlimited number of external digital temperature sensor ics using the on-chip master i 2 c interface. an independent slave i 2 c interface facilitates communica - tion to a host microprocessor in addition to password- protected in-system reprogramming of the on-chip flash. ease of development is supported with highly versatile c-compilers and development software that programs flash and performs in-circuit debug through the inte - grated jtag interface and associated hardware. all these features combined make the device a highly flexible platform, allowing the designer to easily create a customized complex system management solution. applications network switches/routers base stations servers smart grid network systems features s maxq20, high-performance, 16-bit c s efficient c-language programming s 36kwords total program memory 32kwords flash program memory 4kwords rom program memory s 1kwords data ram s 12-bit adc with 7-input mux for temperature and voltage monitoring s temperature measurement analog front-end 0.125 n c resolution diode series resistance cancellation s six timer/fan tachometer inputs s six 16-bit pwm outputs for fan speed or d/a applications s 5-bit gpio ports s smbus/i 2 c-compatible slave interface for host communication with password-protected flash programming s i 2 c-compatible master interface for slave expansion s power-on reset and brownout monitors s jtag port supports in-system debug and flash programming s internal oscillator requires no crystal s 2.7v to 5.5v operating voltage range ordering information + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . part temp range pin-package MAX31782ETL+ -40 n c to +85 n c 40 tqfn-ep* MAX31782ETL+t -40 n c to +85 n c 40 tqfn-ep* max31782
system management microcontroller 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to v ss ........................................................... -0.5v to +5.5v adxn to v ss ......................................................... -0.3v to +0.3v all other pins to v ss except reg18 and reg25 .............................. -0.5v to (v dd + 0.5v)* scl, sda, msda, mscl, p6.0Cp6.4 continuous sink current .................... 20ma each, 50ma total p6.0Cp6.4 continuous source current ... 20ma each, 50ma total operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c continuous power dissipation (t a = +70 n c) tqfn (derate 35.7mw/ n c above +70 n c) ............... 2857.1mw recommended operating conditions (t a = -40 n c to +85 n c, unless otherwise noted.) dc electrical characteristics (v dd = 2.7v to 5.5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25 n c, unless otherwise noted.) absolute maximum ratings * subject to not exceeding +5.5v. parameter symbol conditions min typ max units v dd operating voltage range v dd (note 1) 2.7 5.5 v input logic 1 v ih 0.7 x v dd v dd + 0.3 v input logic 0 v il 0 0.3 x v dd v input logic-high: scl, sda, msda, mscl v i2c_ih 2.7v p v dd p 3.6v (note 1) 2.1 v dd + 0.3 v 3.6v p v dd p 5.5v 0.7 x v dd v dd + 0.3 input logic-low: scl, sda, msda, mscl v i2c_il 2.7v p v dd p 3.6v (note 1) 0 0.8 v 3.6v p v dd p 5.5v 0 0.3 x v dd parameter symbol conditions min typ max units supply current i cpu assuming 100% cpu duty cycle (note 2) 1.73 2.34 ma i stop (note 2) 830 1250 a i program 7 ma brownout voltage v bo monitors v dd (note 1) 2.40 2.46 2.55 v brownout hysteresis v boh monitors v dd (note 1) 30 mv internal system clock f mosc 4.0 mhz system clock error (note 3) f err:mosc initial tolerance, t a = +25 n c, v dd = 5.5v -1 +1 % +25 n c p t a p +85 n c -2 +1 -40 n c p t a p +25 n c -5.5 +0.6 max31782
system management microcontroller 3 dc electrical characteristics (continued) (v dd = 2.7v to 5.5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25 n c, unless otherwise noted.) parameter symbol conditions min typ max units system clock startup t su:mosc from por, mosc inactive 1000 mosc cycles output logic-low v ol i ol = 4ma (note 1) 0.4 v output logic-high (all pins except sda, sll, msda, mscl) v oh i oh = -2ma (note 1) v dd - 0.5 v gpio mode pullup current i pu v pin = v ss, v dd = 3.3v 38 55 107 f a adc voltage conversion time t conv_v (note 4) 137 150 s adc temperature conversion time t conv_t (note 4) 7 ms adc internal reference 1.225 v adc voltage measurement error v err -1 +1 % adc internal reference temperature drift -0.5 +0.5 % adc internal reference initial accuracy (+25 n c) -1 +1 mv adc external reference buffer accuracy (note 5) q 0.25 % adc operating current i adc this current is in addition to i cpu 2.2 ma adc full-scale input voltage (note 6) v fs adgain = 0, factory set, internal reference 1.213 1.225 1.237 v adgain = 1, factory set, internal reference 5.445 5.5 5.555 adc measurement resolution v lsb adgain = 0 300 f v adgain = 1 1343 adc bit resolution 12 bits ad0pCad5p input resistance r in 15 m i adc integral nonlinearity inl (note 7) q 8 lsb adc offset v offset q 2 lsb internal temperature measurement error t a = -40 n c to +85 n c -3 +3 n c remote temperature measurement error (max31782 error only) t a = 0 n c to +60 n c, t diode = +60 n c to +120 n c -1.5 +1.5 n c t a = 0 n c to +60 n c, t diode = -45 n c to +120 n c -1.75 +1.75 t a = -40 n c to +85 n c, t diode = + 60 to +120 n c -2.75 +2.75 t a = -40 n c to +85 n c, t diode = -45 n c to +120 n c -3.0 +3.0 max31782
system management microcontroller 4 dc electrical characteristics (continued) (v dd = 2.7v to 5.5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25 n c, unless otherwise noted.) electrical characteristics: i 2 c-compatible interface (v dd = 2.7v to 5.5v, t a = -40 n c to +85 n c, unless otherwise noted.) (figure 1) parameter symbol conditions min typ max units flash erase time t me mass erase 20 40 ms t pe page erase 20 40 flash programming time per word t prog 20 40 f s flash endurance n flash t a = +50 n c 20,000 write cycles data retention t a = +50 n c 100 years parameter symbol conditions min typ max units scl clock frequency f scl timeout not enabled (note 8) 10 400 khz bus free time between a stop and start condition t buf 1.3 f s hold time (repeated) start condition t hd:sta (note 9) 0.6 f s low period of scl clock t low 1.3 f s high period of scl clock t high 0.6 f s setup time for a (repeated) start condition t su:sta 0.6 f s data hold time (note 10) t hd:dat receive 0 ns transmit 300 data setup time t su:dat 100 ns rise time of both sda and scl signals t r (note 11) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 11) 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 f s spike pulse width that can be suppressed by input filter t sp (note 12) 0 50 ns scl, sda capacitive loading c b 400 pf smbus timeout 25 30 35 ms max31782
system management microcontroller 5 electrical characteristics: jtag interface (v dd = 2.7v to 5.5v, t a = -40 n c to +85 n c, unless otherwise noted.) (figure 2) note 1: all voltages are referenced to ground (v ss ). currents entering the ic are specified positive and currents exiting the ic are negative. note 2: this value does not include current in sda, scl, and p6.0Cp6.4. note 3: guaranteed by design. note 4: adcclk = sysclk/16. this is following an initial startup time of approximately 80s. note 5: base line accuracy of reference source + 0.25% introduced by the max31782. note 6: the voltage applied to the pins must not exceed their corresponding absolute maximum voltages. note 7: adc has no missing codes. note 8: minimum scl frequency applies only when in i 2 c master mode. note 9: after this period, the first clock pulse can be generated. note 10: this device internally provides a hold time of at least 25ns for the sda signal (referenced to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 11: c b total capacitance of one bus line in pf. note 12: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instant. figure 1. i 2 c-compatible bus timing diagram scl note: timing is referenced to v ilmax and v ihmin . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low parameter symbol conditions min typ max units jtag logic reference v ref v dd /2 v tck high time t th 1 f s tck low time t tl 1 f s tck low to tdo output t tlq 0.125 f s tms, tdi input setup to tck high t dvth 0.30 f s tms, tdi input hold after tck high t thdx 0.25 f s max31782
system management microcontroller 6 figure 2. jtag timing diagram typical operating characteristics (v dd = 3.3v, t a = +25c, unless otherwise noted.) tck tms/tdi tdo v ref t th t tlq t tl t thdx t dvth adc dnl max31782 toc01 adc code adc dnl (lsb) 3584 3072 2560 2048 1536 1024 512 -0.5 0 0.5 1.0 1.5 -1.0 0 4096 no missing codes observed max31782
system management microcontroller 7 pin configuration pin description tqfn (6mm 6mm 0.75mm) max31782 top view 35 36 34 33 12 11 13 v ss ad3n ad3p ad0p ad0n 14 ad4n tach.1 tach.2 pwm.2 pwm.0 reg25 tach.0 tach.3 reg18 12 p6.3/tdo 45 67 27 28 29 30 26 24 23 22 p6.2/tms/tbb v ss pwm.4 tach.5 pwm.5 mscl ad4p pwm.1 3 25 37 p6.1/tdi msda 38 39 40 p6.0/tck ad5n ad5p rst ad2n ad2p p6.4/tba 32 15 tach.4 scl 31 16 17 18 19 20 pwm.3 ad1p v dd ad1n v ss 89 10 21 sda ep + pin name function 1 ad4n ground reference for adc.4 voltage measurement 2, 21, 36 v ss supply return node 3 ad4p adc voltage-sense input, measurement relative to ad4n 4 ad3n ground reference for adc.3 voltage measurement. connected to external reference pin when enabled. 5 ad3p adc voltage-sense input, measurement relative to ad3n 6 ad0p adc voltage-sense input, measurement relative to ad0n 7 ad0n ground reference for adc.0 voltage measurement 8 ad1p adc voltage-sense input, measurement relative to ad1n 9 v dd input supply. +2.7v to +5.5v input range. bypass v dd to v ss with a 0.1 f f capacitor. 10 ad1n ground reference for adc.1 voltage measurement 11 ad2p adc voltage-sense input, measurement relative to ad2n 12 ad2n ground reference for adc.2 voltage measurement 13 rst active-low reset. a low-level voltage at this pin resets the ic. 14 msda master i 2 c-compatible bidirectional data line. when disabled, this pin can be used as gpio p2.7. 15 mscl master i 2 c-compatible clock. when disabled, this pin can be used as gpio p2.6. 16 pwm.5 pwm output no. 5. when disabled, this pin can be used as gpio. 17 tach.5 tachometer input no. 5. when disabled, this pin can be used as gpio. 18 pwm.4 pwm output no. 4. when disabled, this pin can be used as gpio. 19 tach.4 tachometer input no. 4. when disabled, this pin can be used as gpio. max31782
system management microcontroller 8 pin description (continued) pin name function 20 pwm.3 pwm output no. 3. when disabled, this pin can be used as gpio. 22 reg18 bypass reg18 to v ss with 1 f f and high-frequency 10nf capacitors. do not use for external circuitry. 23 tach.3 tachometer input no. 3. when disabled, this pin can be used as gpio. 24 pwm.2 pwm output no. 2. when disabled, this pin can be used as gpio. 25 tach.2 tachometer input no. 2. when disabled, this pin can be used as gpio. 26 pwm.1 pwm output no. 1. when disabled, this pin can be used as gpio. 27 tach.1 tachometer input no. 1. when disabled, this pin can be used as gpio. 28 pwm.0 pwm output no. 0. when disabled, this pin can be used as gpio. 29 reg25 bypass reg25 to v ss with 1 f f and high-frequency 10nf capacitors. do not use for external circuitry. 30 tach.0 tachometer input no. 0. when disabled, this pin can be used as gpio. 31 sda slave i 2 c-compatible bidirectional data line. when disabled, this pin can be used as gpio. 32 scl slave i 2 c-compatible clock. when disabled, this pin can be used as gpio. 33 p6.4/tba programmable i/o pin. alternate function: timer/counter tba 34 p6.3/tdo programmable i/o pin. alternate function: jtag tdo 35 p6.2/tms/tbb programmable i/o pin. alternate functions: timer/counter tbb, jtag tms 37 p6.1/tdi programmable i/o pin. alternate function: jtag tdi 38 p6.0/tck programmable i/o pin. alternate function: jtag tck 39 ad5n ground reference for adc.5 voltage measurement 40 ad5p adc voltage-sense input, measurement relative to ad5n ep exposed pad. not electrically connected to ic. connect to v ss . max31782
system management microcontroller 9 block diagram clock control, watchdog timer, and power monitor ckcn rst wdcn ic ic ip loop counters data pointers dpc maxq20 core system modules/ registers 4k x 16 utility rom ffffh 8fffh 8000h 7fffh 0000h program memory space lc[n] ap apc psf imr iir interrupt logic address generation dp[0], dp[1], fp = (bp+offs) 32k x 16 user program memory accumulators (16) cpu clock boolean variable manipulation instruction decode (src, dst transport determination) 4k x 16 utility rom ffffh 8fffh 8000h 03ffh 0000h data memory space 1k x 16 sram sp stack memory 16 x 16 msda mscl i 2 c master p6.n n = 0?4 gpio scl sda i 2 c slave multiply accumulate unit (mac) 6-channel tachometer tach.0 tach.1 tach.2 tach.3 tach.4 tach.5 memory management unit (mmu) 12-bit adc adch v dd mux current sources ad0p ad1p ad2p ad3p ad4p ad5p internal temp 6-channel pulse-width modulator pwm.0 pwm.1 pwm.2 pwm.3 pwm.4 pwm.5 max31782 max31782
system management microcontroller 10 detailed description the max31782 incorporates the 16-bit maxq20 micro - controller core with 16 accumulators and 16-level hard - ware stack. three memory blocks provide flash applica - tion code space, utility rom code space, and ram mem - ory. specialized peripherals are integrated to perform pwm control of fan speed, read fan tachometers, and perform temperature monitoring using diode-connected transistors. the device also features two i 2 c-compatible communication peripherals. the slave i 2 c-compatible peripheral is included to allow communication between a host system and the device. an i 2 c-compatible master interface is also included to allow communication with remote i 2 c digital temperature sensors or other i 2 c devices. general-purpose i/o pins (gpios) are also provided to allow interrupt functions and control of other circuitry using the system management microprocessor. the maxq20 core, along with the specialized peripher - als, provides a flexible solution for system and thermal management. flexibility is further enhanced as the solu - tion allows for upgrading the program and data flash contents over the i 2 c-compatible interface. updates to the program flash are protected against unauthorized writes by a 256-bit user password. the following sections are an introduction to the pri - mary features of the max31782 system management microcontroller. more detailed descriptions of the device features can be found in the max31782 users guide . maxq20 core architecture the device employs a maxq20 low-cost, high-perfor - mance, cmos, fully static, 16-bit risc microcontroller with flash memory. it is structured on a highly advanced, 16-accumulator-based, 16-bit risc architecture. fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data. the highly efficient core is sup - ported by 16 accumulators and a 16-level hardware stack, enabling fast subroutine calling and task switch - ing. data can be quickly and efficiently manipulated with three internal data pointers. multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. the data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. instruction set the instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca - tions. the instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. special-function registers control the peripherals and are subdivided into register modules. the family architecture is modular, so that new devices and modules can reuse code developed for existing products. the architecture is transport-triggered. this means that writes or reads from certain register locations can also cause side effects to occur. these side effects form the basis for higher level op codes defined by the assembly, such as addc, or, jump, etc. the op codes are imple - mented as move instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. the 16-bit instruction word is designed for efficient execution. bit 15 indicates the format for the source field of the instruction. bits 0C7 of the instruction represent the source for the transfer. depending on the value of the format field, this can either be an immediate value or a source register. if this field represents a register, the lower 4 bits contain the module specifier and the upper 4 bits contain the register index in that module. bits 8C14 represent the destination for the transfer. this value always represents a destination register, with the lower 4 bits containing the module specifier and the upper 3 bits containing the register subindex within that module. any time it is necessary to directly select one of the upper 24 registers as a destination, the prefix regis - ter, pfx, is needed to supply the extra destination bits. this prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. refer to the max31782 users guide for complete instruction set information. memory organization the device incorporates several memory areas, including: ? 32kwords of flash memory for application program storage ? 1kwords of sram for storage of temporary variables ? 4kwords of utility rom contain a debugger and pro - gram loader ? 16-level stack memory for storage of program return addresses and general-purpose use max31782
system management microcontroller 11 the memory is implemented using the harvard archi - tecture, with separate address spaces for program and data memory. a pseudo-von neumann memory map is also used placing rom, application code, and data memory into a single contiguous memory map. the pseudo-von neumann memory map allows data memory to be mapped into program space, permitting code execution from data memory. in addition, program memory can be mapped into data space, permitting code constants to be accessed as data memory. figure 3 shows the devices memory map when executing from program memory space. refer to the max31782 users guide for memory map information when executing from data or rom space. the incorporation of flash memory allows field upgrade of the firmware. flash memory is password protected with a 16-word key, denying access to program memory by unauthorized individuals. utility rom the utility rom is a 4kword block of internal rom memory that defaults to a starting address of 8000h. the utility rom consists of subroutines that can be called from application software. these include the following: ? in-system programming (bootstrap loader) over jtag or i 2 c-compatible interfaces ? in-circuit debug routines ? callable routines for in-application flash programming following any reset, execution begins in the utility rom. the rom software determines whether the program execution should immediately jump to location 0000h, the start of application code, or to one of the special routines mentioned. routines within the utility rom are firmware-accessible and can be called as subroutines by the application software. more information on the util - ity rom contents is contained in the max31782 users guide . figure 3. memory map system registers peripheral registers dp 16 x 16 stack m5 m4 m3 m2 m1 m0 5h 0fh 00h 4h 3h 2h 1h 0h ffffh ffffh ffffh 8fffh 9fffh 8fffh 7fffh 001fh 0010h 0000h 0000h 0000h 4k x 16 utility rom 8k x 8 utility rom 4k x 16 utility rom 2k x 8 sram data 1k x 16 sram data 32k x 16 user program memory password 8000h 8000h 8000h 07ffh 03ffh dpc sp ip pfx a ap fh 00h 0fh 00h 1fh eh dh ch bh 9h 8h program memory space data memory (byte mode) data memory (word mode) max31782
system management microcontroller 12 password the device is programmed with a default password prior to being shipped. the password is defined as the 16 words of physical program memory at addresses 0010hC001fh. a single password lock bit (pwl) is implemented in the sc register. once a new device is programmed, a password is defined (password is other than all zeros or all ones) and the pwl bit is set. if the pwl is zero, the device is deemed unprogrammed. the password is automatically set to all ones following a mass erase. stack memory a 16-bit, 16-level internal stack provides storage for program return addresses and general-purpose use. the stack is used automatically by the processor when the call, ret, and reti instructions are executed and interrupts serviced. the stack can also be used explicitly to store and retrieve data by using the push, pop, and popi instructions. on reset, the stack pointer, sp, initializes to the top of the stack (0fh). the call, push, and interrupt-vectoring operations increment sp, and then store a value at the location pointed to by sp. the ret, reti, pop, and popi operations retrieve the value at sp and then decrement sp. programming the flash memory of the microcontroller can be pro - grammed by one of three methods: in-system pro - gramming, in-application programming, and production programming. all three methods provide great flexibility in system design and reduce the life-cycle cost of the embedded system. in-system programming an internal bootstrap loader allows the device to be pro - grammed over the jtag or i 2 c-compatible interfaces. as a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. programming source select (pss) bits in the icdf register determine which interface is used for bootload - ing operation. the device supports jtag and i 2 c as an interface corresponding to 00 and 01 bits of pss, respectively. in-application programming the in-application programming feature allows the microcontroller to modify its own flash program memory. this allows on-the-fly software updates in mission-critical applications that cannot afford downtime. alternatively, it allows the application to develop custom loader software that can operate under the control of the application soft - ware. the utility rom contains firmware-accessible flash programming functions that erase and program flash memory. these functions are described in detail in the max31782 users guide . system timing the device generates its 4mhz instruction clock (mosc) internally using a ring oscillator. on power-up, the output of the oscillator (which cannot be accessed externally) is disabled until v dd rises above v bo . once this threshold is reached, 1000 cycles are counted (~ 250 f s) and then the output is enabled, clocking the device. system reset the device features several sources that can be used to reset the device. power-on reset an internal power-on-reset (por) circuit is used to enhance system reliability. this circuit forces the device to perform a por whenever a rising voltage on v dd climbs above v por . when this happens the following events occur: ? all registers and circuits enter their reset state ? the por flag (wdcn.7) is set to indicate the source of the reset ? code execution begins at location 8000h when the reset condition is released brownout detect/reset the device features a brownout-detect/reset function. whenever the power monitor detects a brownout condi - tion (when v dd < v bo ), it immediately issues a reset and stays in that state as long as v dd remains below v bo . once v dd voltage rises above v bo , the device waits for t su:mosc before returning to normal opera - tion, also referred to as cpu state. if a brownout occurs during t su:mosc , it again goes back to the brownout state. otherwise, it enters into cpu state. in cpu state, the brownout detector is also enabled. on power-up, the device always enters into brownout state first and then follows the previously mentioned sequence. the reset issued by brownout is the same as por. whatever action happens on por also happens on brownout reset. all the registers that are cleared on por are also cleared on brownout reset. max31782
system management microcontroller 13 watchdog timer reset the watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. the watchdog timer is a hardware timer designed to be periodically reset by the application software. if the software operates correctly, the timer is reset before it reaches its maximum count. however, if undesirable code execution prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor. the watchdog timer is controlled through 2 bits in the wdcn register (wdcn[5:4]: wd[1:0]). its timeout period can be set to one of the four programmable intervals ranging from 2 12 to 2 21 system clock (mosc) periods (1.024ms to 0.524s). the watchdog interrupt occurs at the end of this timeout period, which is 512 mosc clock periods, or 128s, before the reset. the reset generated by the watchdog timer lasts for four system clock cycles, which is 1s. software can determine if a watchdog time caused a reset by checking the watchdog timer reset flag (wtrf) in the wdcn register. execution resumes at location 8000h following a watchdog timer reset. external reset asserting the rst pin low causes the device to enter the reset state. the external reset function is described in the max31782 users guide . execution resumes at loca - tion 8000h after the rst pin is released. internal system reset in i 2 c bootload mode, the host can issue a bbh com - mand to reset the communicating device using an i 2 c slave address of 34h. this reset has the same effect as the external reset as far as the reset values of all registers are concerned. also, an internal system reset can occur when the in-system programming is done (rod = 1). power modes the device supports two modes of operation: cpu mode and stop mode. the device enters stop mode state after a cpu stop (ckcn.stop) is asserted. on entering stop mode, the digital core is inactive as its clock is turned off. all the analog circuits, except adc (including svm, ldos, and monitor circuits), are still active. stop mode is exited by any of the following: an external interrupt on port 6, an i 2 c start interrupt, an svm interrupt, or an external reset. for one of the mentioned interrupts to get the device out of stop mode, it must be enabled. the system returns to cpu mode within 10 system clocks. if an interrupt causes the system to come out of stop mode, the program execution starts from the point where stop mode was asserted. however, if an external reset is used to come out of stop mode, the program execution begins from org (starting point). table 1 explains the state of analog/digital circuits during different modes. register set most functions of the device are controlled by sets of registers. these registers provide a working space for memory operations as well as configuring and address - ing peripheral registers on the device. registers are divided into two major types: system registers (sprs) and peripheral registers (sfrs). the common register set, also known as the system registers, includes the alu, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. the peripheral registers define additional functionality and the function - ality is broken up into discrete modules. both the system registers and the peripheral registers are illustrated in detail in the max31782 users guide . table 1. power modes ckcn. stop svm. svmen svm. svmstop cpu ldo (1.8v) internal oscillator brownout detect svm monitor ldo (1.8v) monitor adc power mode ldo (2.5v) 0 0 x on on on on off on on/off cpu mode on 0 1 x on on on on on on on/off cpu mode on 1 0 x off on on on off on off stop mode on 1 1 0 off on on on off on off stop mode on 1 1 1 off on on on on on off stop mode on max31782
system management microcontroller 14 hardware multiplier the hardware multiplier (a multiply-accumulate, or mac module) is a very powerful tool, especially for applica - tions that require heavy calculations. this multiplier can execute the multiply, multiply-negate, or multiply- accumulate, multiply-subtract operation for signed or unsigned operands in a single machine cycle, and even faster for special cases. the mac module uses eight sfrs, mapped as register 0hC07h in module m5. system interrupts multiple interrupt sources are available to respond to internal and external events. the maxq20 architecture uses a single interrupt vector (iv) and single interrupt- service routine (isr) design. for maximum flexibility, interrupts can be enabled globally, individually, or by module. when an interrupt condition occurs, its indi - vidual flag is set, even if the interrupt source is disabled at the local, module, or global level. interrupt flags must be cleared within the firmware-interrupt routine to avoid repeated interrupts from the same source. application software must ensure a delay between the write to the flag and the reti instruction to allow time for the inter - rupt hardware to remove the internal interrupt condition. asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two- instruction delay. when an enabled interrupt is detected, execution jumps to a user-programmable interrupt vec - tor location. the iv register defaults to 0000h on reset or power-up, so if it is not changed to a different address, application firmware must determine whether a jump to 0000h came from a reset or interrupt source. once control has been transferred to the isr, the interrupt identification register (iir) can be used to deter - mine if a system register or peripheral register was the source of the interrupt. in addition to iir, miir registers are implemented to indicate which particular function under a peripheral module has caused the interrupt. the device contains six peripheral modules, m0Cm5. an miir register is implemented under each module. the miir registers are 16-bit read-only registers and all of them default to all 0 on system reset. once the module that causes the interrupt is singled out, it can then be inter - rogated for the specific interrupt source and software can take appropriate action. interrupts are evaluated by application code allowing the definition of a unique interrupt priority scheme for each application. interrupt sources are available from the watchdog timer, the adc, the tach.n pins, the programmable timer/counter, the i 2 c-compatible master and slave interface, the svm, and the port 6 i/o pins. programmable timer/counter the device features a general-purpose programmable timer/counter commonly referred to as a timer b mod - ule. the specification for this timer/counter block is the same as the timer b specification. there are four reg - isters associated with this timer/counter block: tb0cn (control register), tb0v (value register), tb0c (compare register), and tb0r (capture/reload value register). the timer/counter has two pins, tba and tbb, that are multi - plexed with pins p6.4 and p6.2, respectively. when tba or tbb is enabled, the corresponding pin functions as a timer/counter pin instead of a gpio. see the i/o port section for more details. detailed information regarding the timer/counter block can be found in the max31782 users guide . i/o port the device includes a simple input/output (i/o) data port, port 6. pins p6.0Cp6.4 are primary gpio pins with alter - nate functions. each pin is multiplexed with at least one special function, such as interrupts, timer/counter i/o pins, or jtag pins. table 2 summarizes the functionality of the i/o pins. figure 4 shows a block diagram of the i/o port. port 6 pins have schmitt trigger receivers and full cmos output drivers, and can support alternate functions. the port is accessed through six sfrs (po6, pi6, pd6, eie6, eif6, and eies6) in module 1 and each pin can be indi - vidually configured. the pin is either high impedance or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. in addition, each pin can function as external interrupt with individual enable, flag, and active edge selection, when programmed as input. on power-up, pins p6.0Cp6.3 default to jtag. clearing sc.tap to 0 (1 is the power-up state) configures them as gpio. setting eie6.n (n = 0C4, 6, 7) to 1 configures p6.n to an interrupt. pins p6.2 and p6.4 have special functions that are the timer/counters tbb and tba pins, respectively. when tbb or tba or both are enabled, p6.2 or p6.4 or both are used as their special functions. p6.2 and p6.4 are independent when used as timer/counter pins, i.e., when either of them is used as a timer/counter pin, the other can still be used as gpio if the corresponding special function is not enabled. max31782
system management microcontroller 15 pwm outputs the device provides six independent pwm outputs. each pwm output is associated with four sfrs: pwmcnn, pwmvn, pwmrn, and pwmcn, where n = 0C5 is the channel number. the pwm clock is derived from the system clock with a division ratio defined by pwmcnn. the pwmcnn register also enables/disables the pwm output and selects the pwm polarity. the user can set the frequency and the duty cycle of each pwm output individually by configuring the corresponding pwmrn register and the pwmcn register, respectively. when the pwm output functionality of a pwm.n pin is disabled, that pin can be used as a gpio. when used as gpio pins, pwm.n pins are accessed as port 1 and through three sfrs: po1, pi1, and pd1. each pwm.n pin can be independently configured, and can be defined as an input with weak pullup, an input without pullup, or an output. table 2. i/o port pins figure 4. port 6 i/o block diagram pd6.n sf direction sf enable mux mux po6.n v dd sf output v dd weak i/o pad p6.n interrupt flag flag pi6.n or sf input n = 0?4 eies6.n detect circuit eie6.n max31782 port index primary function alternate function interrupts tap (jtag) reset state p6.0 gpio, p6.0 int0 tck tck p6.1 gpio, p6.1 int1 tdi tdi p6.2 gpio, p6.2 timer b tbb pin int2 tms tms p6.3 gpio, p6.3 int3 tdo tdo p6.4 gpio, p6.4 timer b tba pin int4 gpio input with weak pullup max31782
system management microcontroller 16 tachometer inputs the device provides six pins for reading fan tachometer pulses. each tach.n pin functions independently and is associated with three sfrs: tachcnn (the control reg - ister), tachvn (the timer value register), and tachrn (the timer capture register), where n = 0C5 is the channel number. there is an internal timer for each tach.n pin. the clock for the tach.n timer is derived from the system clock with a division ratio defined by tachcnn. the tach.n timer, when initially enabled, begins counting up from the tachvn value and upon overflow subsequently contin - ues counting from 0000h to the ffffh overflow, i.e., rolls over from ffffh to 0000h if left enabled and running. if the capture function is enabled by configuring the tachcnn register, a 1-to-0 transition on the prescaled tachometer pulses causes the value in the tachvn reg - ister to be transferred into the tachrn register and set the external trigger flag. upon capture, tachvn reloads 0000h and continues counting. the user can calculate the tachometer pulse period and the fan speed by read - ing the tachrn register. when the tachometer input functionality of a tach.n pin is disabled, that pin can be used as a gpio. when used as gpio pins, tach.n pins are accessed as port 2 and through three sfrs: po2, pi2, and pd2. each tach.n pin can be independently configured, and can be defined as an input with weak pullup, an input without pullup, or an output. i 2 c-compatible interface modules the device provides two independent i 2 c-compatible interfaces; one is a master and the other is a slave. i 2 c-compatible master interface the device features an internal i 2 c-comaptible mas - ter interface for communication with a wide variety of external i 2 c devices. the i 2 c-compatible master bus is a bidirectional bus using two bus lines, the serial-data line (msda) and the serial-clock line (mscl). for the i 2 c-compatible master, the device has ownership of the i 2 c bus, and drives the clock and generates the start and stop signals. this allows the device to send data to a slave or receive data from a slave as required. both the msda and mscl lines must be driven as open-drain outputs. external pullup resistors are required to pull the lines to a logic-high state. when the i 2 c-compatible master interface is disabled, msda and mscl can be used as gpio pins. when used as gpio pins, msda and mscl can be used as pins p2.7 and p2.6, respectively, and are accessed through three sfrs: po2, pi2, and pd2. because these pins are open drain, external pullups are required to realize a logic-high. i 2 c-compatible slave interface the device also features an internal i 2 c-comaptible slave interface for communication with a host. furthermore, the device can be in-system programmed (bootloaded) through the i 2 c-compatible slave interface. for the i 2 c-compatible slave interface, the device relies on an externally generated clock to drive scl and responds to data and commands only when requested by the i 2 c master device. smbus timeout both the i 2 c-compatible master and slave interfaces can work in smbus-compatible mode for communication with other smbus devices. to achieve this, a 30ms timer has been implemented on the i 2 c-compatible slave interface to make the interface smbus compatible. the purpose of this timer is to issue a timeout interrupt and thus the firmware can reset the i 2 c-compatible slave interface when the scl is held low for longer than 30ms. the timer only starts when none of the following conditions is true: ? the i 2 c-compatible slave interface is in the idle state and there is no communication on the bus. ? the i 2 c-compatible slave interface is not working in smbus-compatible mode. ? the scl logic level is high. ? the i 2 c-compatible slave interface is disabled. when a timeout occurs, the timeout bit is set and an interrupt is generated, if enabled. if a timeout interrupt is generated, the firmware disables and reenables the i 2 c- compatible slave interface. after this process, the scl and sda pins are set to high impedance. all the relevant i 2 c slave sfrs should be reloaded by firmware. analog-to-digital converter (adc) the device contains a 12-bit analog-to-digital converter (adc) with a 7-input mux (figure 5). the mux selects the adc input from six external channels and one internal channel. the six external channels can operate in fully differential voltage mode or in single-ended voltage mode. in addition, any of the six external channels can be configured to measure the temperature of an external diode. the internal channel is used exclusively to mea - sure the die temperature. the adc is controlled by sfr registers. max31782
system management microcontroller 17 the adc can be set up to continuously poll the input channels (continuous-sequence mode) or run a short burst of conversions and enter a shutdown mode to con - serve power (single-sequence mode). the six external channels can be individually configured to operate in external temperature mode. in external tem - perature mode, current is forced into an external diode that is connected between user-specified channel pins. the diode temperature is obtained by measuring the diode voltages at multiple bias currents. the device fea - tures a 3-point series resistance-cancellation algorithm to provide high-temperature measurement accuracy. the adc is able to measure the external diode tempera - ture immune to the loop resistance. for both external and internal temperature measurements, the internal ref - erence is automatically selected and the full-scale (fs) value is fixed at 1.225v. the temperature measurement resolution is 0.125 n c. when the external channels are configured to operate in voltage mode, the voltage applied on the correspond - ing channel (differential or single-ended) is converted to a digital readout. in voltage mode, the reference can be either internal or external. if the internal reference is used, the fs can be set to 1.225v or 5.5v. these fs values can be trimmed by modifying the associated reg - isters (adcg1 and adcg5), respectively. in voltage mode, an adc conversion takes 34 adcclk cycles to complete. the adcclk is derived from the system clock with division ratio defined by the adc control register. the fastest adc sampling rate is sysclk/544. with a 4mhz system clock, this is theo - retically equivalent to 7.35ksps. in applications where extending the acquisition time is desired, the sample can be acquired over a prolonged period determined by the adc control register. the adc has eight configuration registers. each channel can have its own configuration, such as differential mode select, data alignment select, acquisition extension enable, adc reference select, and external temperature mode select, etc. the adc also has sixteen 13-bit circu - lar data buffers for conversion result storage. the adc data available interrupt flag (addai) can be configured to trigger an interrupt following a predetermined number of samples. once set, addai can be cleared by soft - ware or at the start of a conversion process. when the device is put into stop mode, any in-progress adc conversion is aborted and the adc start conver - sion bit (adconv) is reset to 0. the adc is shut down completely to conserve power. on exiting stop mode, the adc waits on adconv = 1. when adconv is set to 1, it counts 20 adcclk cycles before acquisition commences. figure 5. adc block diagram mux ad0p scaler for temperature sensing channels ad0n ad5p ad5n internal channel 12-bit adc core adc data voltage offset temperature offset adcg1 adcg5 internal reference external reference max31782 max31782
system management microcontroller 18 in-circuit debug embedded debugging capability is available through the jtag-compatible test access port (tap). embedded debug hardware and embedded rom firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. figure 6 shows a block diagram of the in-circuit debug - ger. the in-circuit debug features include the following: ? hardware debug engine ? set of registers able to set breakpoints on register, code, or data accesses (icda, icdb, icdc, icdd, icdf, icdt0, and icdt1) ? set of debug service routines stored in the utility rom the embedded hardware debug engine is an indepen - dent hardware block in the microcontroller. the debug engine can monitor internal activities and interact with selected internal registers while the cpu is executing user code. collectively, the hardware and software features allow two basic modes of in-circuit debugging: background and debug. background mode allows the host to configure and set up the in-circuit debugger while the cpu continues to execute the application software at full speed. debug mode can be invoked from background mode. debug mode allows the debug engine to take control of the cpu, providing read/write access to internal regis - ters and memory, and single-step trace operation. applications information power-supply decoupling to achieve the best results when using the device, decouple the v dd power supply with a 0.1 f f capacitor. use a high-quality, ceramic, surface-mount capacitor if possible. surface-mount components minimize lead inductance, which improves performance, and ceram - ic capacitors tend to have adequate high-frequency response for decoupling applications. decouple reg25 and reg18 using 1 f f and 10nf capacitors (one each per output). note: do not use either of these pins for external circuitry. additional documentation designers must have four documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and electrical specifica - tions. errata sheets contain deviations from published specifications. the users guides offer detailed information about device features and operation. the following docu - ments can be downloaded from www.maxim-ic.com . ? the max31782 data sheet, which contains electrical/ timing specifications and pin descriptions. ? the max31782 revision-specific errata sheet ( www.maxim-ic.com/errata ). ? the max31782 users guide , which contains detailed information on core features and operation, including programming. ___________________ development and technical support maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: ? compilers (c and assembly) ? in-circuit debugger ? integrated development environments (ides) ? serial-to-jtag converters for programming and debugging ? usb-to-jtag converters for programming and debugging technical support is available through email at mixedsignal.apps@maxim-ic.com . figure 6. in-circuit debugger tap controller cpu debug engine debug service routines (utility rom) control breakpoint address data max31782 tms tck tdi tdo max31782
system management microcontroller 19 typical operating circuit package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. max31782 ds75 msda mscl v dd reg25 reg18 scl to host p gpio/special functions pwm for d/a; other tach/timer inputs or gpio sda rst tach pwm p6.0/tck p6.1/tdi i 2 c temp sensor 3.3v v ss (3) pwm.5 pwm.4 pwm.3 to load v in pwm.2 pwm.1 pwm.0 tach.5 tach.4 tach.3 tach.2 tach.1 p6.2/tms/tbb p6.3/tdo p6.4/tba tach.0 additional adc channels for monitoring remote temperature sensor ad3p ad3n ad2p ad2n ad1p ad1n ad0p ad0n ad5p ad5n ad4p ad4n in power supply trim en out 3.3v 3.3v v 4-wire fan package type package code outline no. land pattern no. 40 tqfn-ep t4066+2 21-0141 90-0053 max31782
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. system management microcontroller revision history revision number revision date description pages changed 0 6/10 initial release 1 11/11 changed the lead temperature and added the adxn to v ss voltage range and continuous power dissipation numbers to the absolute maximum ratings section; updated the v i2c_ih , v i2c_il conditions, changed the v il(min) number, and removed the v ih1 , v il1 parameters in the recommended operating conditions table; updated the v ol , v oh parameters and t conv_v(typ) and inl(max) numbers in the dc electrical characteristics table 2, 3 2 1/12 added new note 7 to the inl parameter and removed the dnl parameter in the dc electrical characteristics table; added the typical operating characteristics section 3, 5, 6 max31782

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