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1 ? fn6333.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcp are registered trademarks of intersil americas inc. copyright intersil americas inc. 2006, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL22449 quad digitally controlled potentiometer (xdcp?) low noise, low power, spi ? bus, 128 taps, wiper only the ISL22449 integrates fo ur digitally controlled potentiometers (dcp) and non-volatile memory on a monolithic cmos integrated circuit. the digitally controlled potenti ometers are implemented with a combination of resistor elements and cmos switches. the position of the wipers are contro lled by the user through the spi serial interface. each po tentiometer has an associated volatile wiper register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr controls the position of the wiper. at power-up the device recalls the contents of the dcp?s ivr to the corresponding wr. the dcp can be used as a voltage divider in a wide variety of applications including contro l, parameter adjustments, ac measurement and signal processing. pinout features ? four potentiometers in one package ? 128 resistor taps ? spi serial interface ? non-volatile storag e of wiper position ? wiper resistance: 70 typical ? shutdown mode ? shutdown current 6.5a max ? power supply: 2.7v to 5.5v ?50k or 10k total resistance ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ t < +55 c ? 14 lead tssop ? pb-free (rohs compliant) ISL22449 (14 ld tssop) top view rw0 shdn v cc nc sdi cs nc 14 13 12 11 10 9 8 1 2 3 4 5 6 7 rw3 nc sck sdo gnd rw2 rw1 ordering information part number (note) part marking resistance option (k ) temp. range (c) package (pb-free) pkg. dwg. # ISL22449ufv14z* 22449 ufvz 50 -40 to +125 14 ld tssop m14.173 ISL22449wfv14z* 22449 wfvz 10 -40 to +125 14 ld tssop m14.173 *add ?-tk? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. data sheet july 17, 2009 o b s o l e t e p r o d u c t p o s s i b l e s u b s t i t u t e p r o d u c t i s l 2 2 4 4 6
2 fn6333.3 july 17, 2009 block diagram spi interface v cc gnd rw0 rw1 rw2 rw3 sck sdi sdo cs wr3 wr2 wr1 wr0 shdn v cc power up interface, control and status logic non- volatile registers v cc v cc v cc pin descriptions tssop pin symbol description 1 rw3 ?wiper? terminal of dcp3 2nc 3 sck spi clock input 4 sdo spi open drain data output 5 gnd device ground pin and the rl connection for each dcp 6 rw2 ?wiper? terminal of dcp2 7 rw1 ?wiper? terminal of dcp1 8nc 9cs spi chip select active low input 10 sdi spi data input 11 nc 12 vcc power supply pin and the rh connection for each dcp 13 shdn shutdown active low input 14 rw0 ?wiper? terminal of dcp0 ISL22449
3 fn6333.3 july 17, 2009 absolute maximum rati ngs thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . -0.3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v voltage at any dcp pin with respect to gnd . . . . . . . -0.3v to v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup (note 2) . . . . . . . . . . . . . . . . . . class ii, level b @ +125c esd (hbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kv (cdm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kv thermal resistance (typical, note 1) ja (c/w) 14 ld tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +100 maximum junction temperature (plast ic package) . . . . . . . .+150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v cc voltage for dcp operation . . . . . . . . . . . . . . . . . . 2.7v to 5.5v wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3ma to 3ma power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mw caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective t hermal conductivity test board in free air. see tech brief tb379 f or details. 2. jedec class ii pulse conditions and failure criterion used. level b exceptions are: us ing a max positive pulse of 6.5v on the shdn pin, and using a max negative pulse of -0.8v for all pins. analog specifications over recommended operat ing conditions unless otherwis e stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temper ature limits established by characterization and are not production tested. symbol parameter test conditions min typ (note 3) max unit r total end-to-end resistance w option 10 k u option 50 k end-to-end resistance tolerance w and u option -20 +20 % end-to-end temperature coefficient w option 50 ppm/c (note 13) u option 80 ppm/c (note 13) r w wiper resistance v cc = 3.3v @ +25c, wiper current = v cc /r total 70 200 c w (note 13) wiper capacitance 25 pf voltage divider mode (measured at r w i, unloaded; i = 0, 1, 2 or 3) inl (note 8) integral non-linearity -1 1 lsb (note 4) dnl (note 7) differential non-linearity monotonic over all tap positions -0.5 0.5 lsb (note 4) zserror (note 5) zero-scale error w option 0 1 5 lsb (note 4) u option 0 0.5 2 lsb (note 4) fserror (note 6) full-scale error w option -5 -1 0 lsb (note 4) u option -2 -1 0 lsb (note 4) v match (note 9) dcp to dcp matching any two dcps at same tap position -2 2 lsb (note 4) tc v (note 10) ratiometric temperature coefficient dcp register set to 40 hex 4 ppm/c ISL22449
4 fn6333.3 july 17, 2009 operating specifications over the recommended operating conditi ons unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits est ablished by characterization and are not production tested. symbol parameter test conditions min typ (note 3) max unit i cc1 v cc supply current (volatile write/read) v cc = +3.6v, 10k dcp, f spi = 5mhz; (for spi active, read and write states) 2.5 ma v cc supply current (volatile write/read) v cc = +3.6v, 50k dcp, f spi = 5mhz; (for spi active, read and write states) 0.65 ma i cc2 v cc supply current ( non-volatile write/read) v cc = +5.5v, 10k dcp, f spi = 5mhz; (for spi active, read and write states) 4.0 ma v cc supply current ( non-volatile write/read) v cc = +5.5v, 50k dcp, f spi = 5mhz; (for spi active, read and write states) 3.0 ma i sb v cc current (standby) v cc = +5.5v, 10k dcp, spi interface in standby state 2.4 ma v cc = +5.5v, 50k dcp, spi interface in standby state 525 a v cc = +3.6v, 10k dcp, spi interface in standby state 1.6 ma v cc = +3.6v, 50k dcp, spi interface in standby state 350 a i sd v cc current (shutdown) v cc = +5.5v @ +85c, spi interface in standby state 5a v cc = +5.5v@ +125c, spi interface in standby state 6.5 a v cc = +3.6v @ +85c, spi interface in standby state 4a v cc = +3.6v @ +125c, spi interface in standby state 5.5 a i lkgdig leakage current, at pins shdn , sck, sdi, sdo and cs voltage at pin from gnd to v cc -1 1 a t wrt (note 13) dcp wiper response time sck falling edge of last bit of dcp data byte to wiper new position 1.5 s t shdnrec (note 13) dcp recall time from shutdown mode from rising edge of shdn signal to wiper stored position and rh connection 1.5 s sck rising edge of last bit of acr data byte to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum v cc at which memory recall occurs 2.0 2.6 v vccramp vcc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed, and spi interface in standby state 3ms eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature t < +55 c 50 years t wc (note 11) non-volatile write cycle time 12 20 ms serial interface specifications v il shdn , sck, sdi, and cs input buffer low voltage -0.3 0.3*v cc v ISL22449
5 fn6333.3 july 17, 2009 v ih shdn , sck, sdi, and cs input buffer high voltage 0.7*v cc v cc +0.3 v hysteresis shdn , sck, sdi, and cs input buffer hysteresis 0.05* v cc v v ol sdo output buffer low voltage i ol = 4ma 0 0.4 v r pu (note 12) sdo pull-up resistor off-chip maximum is determined by t ro and t fo with maximum bus load cbus = 30pf, f sck = 5mhz 2k cpin (note 13) shdn , sck, sdi, sdo and cs pin capacitance 10 pf f sck spi frequency 5mhz t cyc spi clock cycle time 200 ns t wh spi clock high time 100 ns t wl spi clock low time 100 ns t lead lead time 250 ns t lag lag time 250 ns t su sdi, sck and cs input setup time 50 ns t h sdi, sck and cs input hold time 50 ns t ri sdi, sck and cs input rise time 10 ns t fi sdi, sck and cs input fall time 10 20 ns t dis sdo output disable time 0 100 ns t v sdo output valid time 350 ns t ho sdo output hold time 0 ns t ro sdo output rise time r pu = 2k, cbus = 30pf 60 ns t fo sdo output fall time r pu = 2k, cbus = 30pf 60 ns t cs cs deselect time 2s t wrt wiper response time after spi write to wr register 1.5 s notes: 3. typical values are for t a = +25c and 3.3v supply voltage. 4. lsb: [v(r w ) 127 ? v(r w ) 0 ] / 127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 5. zs error = v(rw) 0 / lsb. 6. fs error = [v(rw) 127 ? v cc ] / lsb. 7. dnl = [v(rw) i ? v(rw) i-1 ] / lsb-1, for i = 1 to 127. i is the dcp register setting. 8. inl = [v(rw) i ? i ? lsb ? v(rw)]/lsb for i = 1 to 127 9. v match = [v(rwx) i ? v(rwy) i ] / lsb, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. 10. for i = 16 to 112 decimal, t = -40c to +125 c. max( ) is the maximum value of the wiper voltage and min ( ) is the minimum value of the wiper voltage over the temperature range. 11. t wc is the time from the end of a write sequence of spi serial inte rface, to the end of the self-timed internal non-volatile write cycle. 12. r pu is specified for the highest data rate transfer for the device. higher value pullup can be used at lower data rates. 13. this parameter is not 100% tested. operating specifications over the recommended operating conditi ons unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits est ablished by characterization and are not production tested. (continued) symbol parameter test conditions min typ (note 3) max unit tc v max v rw () i () min v rw () i () ? max v rw () i () min v rw () i () + [] 2 ? --------------------------------------------------------------------------------------------- - 10 6 165c ---------------- - = ISL22449
6 fn6333.3 july 17, 2009 timing diagrams input timing output timing xdcp timing (for all load instructions) ... cs sck sdi sdo msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck sdo sdi addr msb lsb t dis t ho t v ... ... cs sck sdi msb lsb v w t wrt ... sdo high impedance ISL22449
7 fn6333.3 july 17, 2009 typical performance curves figure 1. wiper resistance vs tap position [i(rw) = v cc /r total ] for 10k (w) figure 2. standby i cc vs v cc figure 3. dnl vs tap position in voltage divider mode for 10k (w) figure 4. inl vs tap position in voltage divider mode for 10k (w) figure 5. zs error vs temperature figure 6. fs error vs temperature 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 tap position (decimal) v cc = 3.3v, t = +125c v cc = 3.3v, t = +20c v cc = 3.3v, t = -40c wiper resisitance ( ) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.7 3.2 3.7 4.2 4.7 5.2 v cc (v) i sb (a) t = +25c t = +125c dnl (lsb) -0.2 -0.1 0 0.1 0.2 0 20406080100120 tap position (decimal) t = +25c v cc = 5.5v v cc = 2.7v -0.2 -0.1 0 0.1 0.2 020406080100120 tap position (decimal) inl (lsb) t = +25c v cc = 5.5v v cc = 2.7v -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 -40 -20 0 20 40 60 80 100 120 temperature (c) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k -1.5 -1.2 -0.9 -0.6 -0.3 0.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k ISL22449
8 fn6333.3 july 17, 2009 pin description potentiometers pins rwi (i = 0, 1, 2, 3) rwi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the wri register. shdn the shdn pin forces the resistors to end-to-end open circuit condition and shorts all rws to gnd. when shdn is returned to logic high, the previous latch settings put rwi at the same resistance setting pr ior to shutdown. this pin is logically anded with the shdn bit in the acr register. spi interface is still available in shutdown mode and all registers are accessible. this pin must remain high for normal operation. bus interface pins serial clock (sck) this is the serial clock input of the spi serial interface. serial data output (sdo) the sdo is an open drain serial data output pin. during a read cycle, the data bits are shifted out at the falling edge of the serial clock sck, while the cs input is low. sdo requires an external pull-up resistor for proper operation. figure 7. end to end r total % change vs temperature figure 8. tc for voltag e divider mode in ppm figure 9. midscale glitch, code 80h to 7fh figure 10. large signal settling time typical performance curves (continued) -1.0 -0.5 0.0 0.5 1.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) end to end r total change (%) 50k 10k v cc = 5.5v v cc = 2.7v 0 15 30 45 60 75 90 105 16 36 56 76 96 tap position (decimal) tcv (ppm/c) 50k 10k signal at wiper (wiper unloaded) signal at wiper (wiper unloaded movement from 7fh to 00h) scl rw figure 11. dcp connection in shutdown mode ISL22449
9 fn6333.3 july 17, 2009 serial data input (sdi) the sdi is the serial data input pin for the spi interface. it receives device address, operation code, wiper address and data from the spi external host device. the data bits are shifted in at the rising edge of the serial clock sck, while the cs input is low. chip select (cs ) cs low enables the ISL22449, placing it in the active power mode. a high to low transition on cs is required prior to the start of any operation after power up. when cs is high, the ISL22449 is deselected and the sdo pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. principles of operation the ISL22449 is an integrated ci rcuit incorporating four dcps with its associated registers, non-volatile memory and the spi serial interface providing direct communication between host and potentiometers and memory. the resistor array is comprised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on th e device operate in a ?make before break? mode when the wiper changes tap positions. when the device is powered down, the last value stored in ivri will be maintained in the non-volatile memory. when power is restored, the contents of the ivri is recalled and loaded into the corresponding wri to set the wiper to the initial value. dcp description each dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fixed terminals of a mechanical potentiometer and internally connected to vcc and gnd. the rw pin of each dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by volatile wiper register (wr). each dcp has its own wr. when the wr of a dcp contains all zeroes (wr[6:0]= 00h), its wi per terminal (rw) is closest to gnd. when the wr register of a dcp contains all ones (wr[6:0]= 7fh), its wiper terminal (rw) is closest to v cc . as the value of the wr increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to gnd to the closest to v cc . while the ISL22449 is being powered up, all four wrs are reset to 40h (64 decimal), which locates rw roughly at the center between gnd and v cc . after the power supply voltage becomes large enough for reliable non-volatile memory reading, all wrs will be reload with the value stored in corresponding non-volatile initial value registers (ivrs). the spi interface register address bits have to be set to 0000b, 0001b, 0010b or 0011b to access the wr of dcp0, dcp1, dcp2 or dcp3 respectively. the wri and ivri can be read or written to directly using the spi serial interface as described in the following sections. memory description the ISL22449 contains seven non-volatile and five volatile 8- bit registers. the memory map of ISL22449 is on table 1. the four non-volatile registers (ivr i) at address 0, 1, 2 and 3, contain initial wiper value and vo latile registers (wri) contain current wiper position. in addition, three non-volatile general purpose registers from addres s 4 to address 6 are available. the non-volatile ivri and volatile wri registers are accessible with th e same address. the access control register (acr) contains information and control bits described below in table 2. the vol bit (acr[7]) determines whether the access is to wiper registers wr or initial value registers ivr. if vol bit is 0, the non-volatile ivr register is accessible. if vol bit is 1, only the volatile wri is accessible. note, value is written to ivri register al so is written to the wri. the default value of this bit is 0. the shdn bit (acr[6]) disables or enables shutdown mode. this bit is logically and with shdn pin. when this bit is 0, dcps are in shutdown mode. default value of shdn bit is 1. the wip bit (acr[5]) is read only bit. it indicates that non- volatile write operation is in progress. the wip bit can be read repeatedly after a non-volati le write to determine if the write has been completed. it is impossible to write to the ivri, wri or acr while wip bit is 1. shutdown mode the device can be put in shutdown mode either by pulling the shdn pin to gnd or setting the shdn bit in the acr register to 0. the truth table for shutdown mode is in table 3. table 1. memory map address non-volatile volatile 8? acr 7 reserved 6 5 4 general purpose general purpose general purpose not available not available not available 3 2 1 0 ivr3 ivr2 ivr1 ivr0 wr3 wr2 wr1 wr0 table 2. access control register (acr) bit #7654321 0 bit name vol shdn wip 0000 0 ISL22449
10 fn6333.3 july 17, 2009 spi serial interface the ISL22449 supports an spi serial protocol, mode 0. the device is accessed via the sdi input and sdo output with data clocked in on the rising edge of sck, and clocked out on the falling edge of sck. cs must be low during communication with the ISL22449. sck and cs lines are controlled by the host or master. the ISL22449 operates only as a slave device. all communication over the spi interface is conducted by sending the msb of each byte of data first. protocol conventions the first byte sent to the ISL22449 from the spi host is the identification byte. a valid ident ification byte contains 0101 as the four msbs, with the fo llowing four bits set to 0. table 4. identification byte format the next byte sent to the ISL22449 contains the instruction and register pointer information. the four msbs are the instruction and four lsbs are register address (see table 5). table 5. identification byte format there are only two valid instruction sets: 1011(binary) - is a read operation 1100(binary) - is a write operation write operation a write operation to the ISL22449 is a three-byte operation. it requires first, the cs transition from high to low, then a valid identification byte, then a valid instruction byte following by data byte is sent to sdi pi n. the host terminates the write operation by pulling the cs pin from low to high. for a write to addresses 0000b to 0011b, the msb at address 8 (acr[7]) determines if the data byte is to be written to volatile or both volatile and non-volatile registers. refer to ?memory description? on page 9 and figure 12. device can receive more than one byte of data by auto incrementing the address after each received byte. note after reaching the address 0110b, the internal pointer ?rolls over? to address 0000b. the internal non-volatile write cycle starts after rising edge of cs and takes up to 20ms. thus, non-volatile registers must be written individually. read operation a read operation to the ISL22449 is a three-byte operation. it requires first, the cs transition from high to low, then a valid identification byte, then a valid instruction byte following by ?dummy? data byte is sent to sdi pin. the spi host reads the data from sdo pin on falling edge of sck. the host terminates the read operation by pulling the cs pin from low to high (see figure 13). the ISL22449 will provide the data bytes to the sdo pin as long as sck is provided by the host from the registers indicated by an internal pointer. this pointer initial value is determined by the register address in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory location 0110b, the pointer ?rolls over? to 0000b, and the device continues to output the data for each received sck clock. in order to read back the non-volatile ivr, it is recommended that the application reads the a cr first to verify the wip bit is 0. if the wip bit (acr[5]) is not 0, the host should repeat its reading sequence again. table 3. shdn pin shdn bit mode high 1 normal operation low 1 shutdown high 0 shutdown low 0 shutdown 01010000 (msb) (lsb) 76543210 i3 i2 i1 i0 r3 r2 r1 r0 ISL22449
11 fn6333.3 july 17, 2009 figure 12. three byte write sequence figure 13. three byte read sequence applications information communicating with ISL22449 communication with ISL22449 pr oceeds using spi interface through the acr (address 1000b), ivri (addresses 0000b, 0001b, 0010b and 0011b) and wri (addresses 0000b, 0001b, 0010b and 0011b) registers. the wiper of the potentiomete r is controlled by the wri register. writes and reads can be made directly to these registers to control and monito r the wiper position without any non-volatile memory changes . this is done by setting msb bit at address 1000b to 1. the non-volatile ivri stores the power up value of the wiper. ivrs are accessible when msb bit at address 1000b is set to 0. writing a new value to the ivri register will set a new power up position for the wiper. also, writing to this register will load the same value into the corresponding wri as the ivri. reading from the ivri will not change the wri, if its contents are different. 0 1 0 1 0 0 i3 i2 i1 i0 r3 r2 r1 r0 sck sdi 0 d6 d5d4 d3 d2 d1d0 cs 00 0 0 101 00 i3 i2 i1 i0 r3 r2 r1 r0 sck sdi cs 00 sdo 0 d6 d5d4 d3 d2 d1d0 don?t care 0 ISL22449
12 fn6333.3 july 17, 2009 examples: a . writing to the ivr: this sequence will write a new value (77h) to the ivr2(non-volatile): set the acr (addr 1000b) for nv write (40h) send the id byte, instruction byte, then the data byte 0 1 0 1 0 0 0 0 1 1 0 0 1 00001000000 (sent to sdi) set the ivr (addr 0010b) to 77h send the id byte, instruction byte, then the data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 01001110111 (sent to sdi) b. reading from the wr: this sequence will read the value from the wr3 (volatile): write to acr first to access the volatile wrs send the id byte, instructio n byte, then the data byte 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 (sent to sdi) read the data from wr3 (addr 0011b) send the id byte, instruction byte, then read the data byte 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 1 x x x x x x x x (out on sdo) ISL22449
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6333.3 july 17, 2009 ISL22449 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06

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