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document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 1 of 15 peregrine?s PE97632 is a high performance fractional-n pll capable of frequency synthesis up to 3.5 ghz. the device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space plls. the PE97632 features a 10/11 dual modulus prescaler, counters, a delta sigma modulator, and a phase comparator as shown in figure 1 . counter values are programmable through a serial or direct hardwired mode. the PE97632 is optimized for commercial space applications. single event latch up (sel) is physically impossible and single event upset (seu) is better than 10 -9 errors per bit / day. fabricated in peregrine?s patented ultracmos ? technology, the PE97632 offers excellent rf performance and intrinsic radiation tolerance. product specification 3.5 ghz delta-sigma modulated fractional-n frequency synthesizer for low phase noise applications product description figure 1. block diagram PE97632 features ?? 3.5 ghz operation ?? 10/11 dual modulus prescaler ?? phase detector output ?? serial or direct hardwired mode ?? frequency selectivity: comparison frequency / 2 18 ?? low power - 40 ma at 3.3 v ?? rad-hard ?? ultra-low phase noise ?? 68-lead cqfj ?? pin compatible with the pe9763 (reference application note an24 at www.psemi.com)
product specification PE97632 page 2 of 15 ?2006-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0205-07 ultracmos? rfic solutions 14 k 5 direct input k counter bit5. 15 k 6 direct input k counter bit6. v dd 51 gnd 52 pd_ u 53 v dd 54 v dd 55 56 57 58 gnd 59 60 21 fin 49 nc 50 20 24 26 25 23 22 14 13 17 19 18 16 15 10 12 11 46 47 48 44 45 k 2 k 3 k 4 k 5 k 6 k 7 k 8 k 9 k 10 k 11 k 12 k 13 k 14 k 15 k 16 k 17 gnd pd_ d v dd ld d out c ext v dd fin v dd gnd table 1. pin descriptions pin no. pin name valid mode type description 1 r 0 direct input r counter bit0 (lsb). 2 r 1 direct input r counter bit1. 3 r 2 direct input r counter bit2. 4 r 3 direct input r counter bit3. 5 r 4 direct input r counter bit4. 6 r 5 direct input r counter bit5 (msb). 7 k 0 direct input k counter bit0 (lsb). 8 k 1 direct input k counter bit1. 9 gnd downbond ground 10 v dd (note 1) digital core v dd . 11 k 2 direct input k counter bit2. 12 k 3 direct input k counter bit3. 13 k 4 direct input k counter bit4. figure 2. pin configurations (top view) 68-lead cqfj figure 3. package type
product specification PE97632 document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 3 of 15 16 k 7 direct input k counter bit7. 17 k 8 direct input k counter bit8. 18 k 9 direct input k counter bit9. 19 k 10 direct input k counter bit10. 20 k 11 direct input k counter bit11. 21 k 12 direct input k counter bit12. 22 k 13 direct input k counter bit13. 23 k 14 direct input k counter bit14. 24 k 15 direct input k counter bit15. 25 k 16 direct input k counter bit16. 26 k 17 direct input k counter bit17 (msb). 27 v dd (note 1) digital core v dd . 28 gnd downbond ground 29 m 0 direct input m counter bit0 (lsb). 30 m 1 direct input m counter bit1. 31 m 2 direct input m counter bit2 32 m 3 direct input m counter bit3. 33 m 4 direct input m counter bit4. s_wr serial input serial load enable input. while s_wr is ?low?, sdata can be serially clocked. primary register data are transferred to the secondary register on s_wr rising edge. 34 m 5 direct input m counter bit5. sdata serial input binary serial data input. input data entered msb first. 35 m 6 direct input m counter bit6. sclk serial input serial clock input. sdata is clocked serially in to the 21-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e_w r ?high?) on the rising edge of sclk. 36 m 7 direct input m counter bit7. 37 m 8 direct input m counter bit8 (msb). 38 a 0 direct input a counter bit0 (lsb). 39 a 1 direct input a counter bit1. e_wr serial input enhancement register write enable. while e_wr is ?high?, sdata can be serially clocked into the enhancement register on the rising edge of sclk. 40 a 2 direct input a counter bit2. 41 a 3 direct input a counter bit3 (msb). 42 direct both input direct mode select. ?high? enables di rect mode. ?low? enables serial mode. 43 pre_en direct input prescaler enable, active ?low?. when ?high?, fin bypasses the prescaler. 44 v dd (note 1) digital core v dd . 45 gnd downbond ground pin no. pin name valid mode type description
product specification PE97632 page 4 of 15 ?2006-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0205-07 ultracmos? rfic solutions 47 f in both input prescaler input from the vco, 3.5 ghz max frequency. a 22 pf coupling capacitor should be placed as close as possible to this pin and terminated with a 50 ? resistor to ground. 48 f in both input prescaler complementary input. a 22pf bypa ss capacitor should be placed as close as possible to this pin and be c onnected in series with a 50 ? resistor to ground. 49 gnd downbond ground 50 cext both output logical ?nand? of pd_ u and pd_ d terminated through an on chip, 2 k ? series resistor. connecting cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld. 51 ld both output lock detect and open drain logical inversion of c ext. when the loop is in lock, ld is high impedance, otherwise ld is a logic low (?0?). 52 d out both output data out function, enabled in enhancement mode. 53 v dd (note 1) output driver/v dd . 54 gnd downbond ground 55 pd_ d both output pd_ d pulses down when f p leads f c . 56 nc both (note 3) no connect 57 pd_ u both output pd_ u pulses down when f c leads f p . 58 gnd downbond ground 59 v dd (note 1) output driver/v dd . 60 v dd (note 1) phase detector v dd . 61 gnd downbond ground 62 f r both input reference frequency input. 63 v dd (note 1) reference v dd . 64 v dd (note 1) digital core v dd . gnd downbond ground 65 enh both input enhancement mode. when asserted low (?0?), enh ancement register bits are functional. 66 nc both (note 3) no connect 67 ms2_sel both input mash 1-1 select. ?high? selects mash 1- 1 mode. ?low? selects the mash 1-1-1 mode. 68 rnd_sel both input k register lsb toggle enable. ?1? enables the toggl ing of lsb. this is equivalent to having an additional bit for the lsb of k register. the frequency offset as a result of enabling this bit is the phase detector comparison frequency / 2 19 . notes 1. all v dd pins are connected by diodes and must be supplied with the same positive voltage level. 2. all digital input pins have 70 k ? pull-down resistors to ground. 3. no connect pins can be left open or floating. 46 v dd (note 1) prescaler v dd . pin no. pin name valid mode type description
product specification PE97632 document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 5 of 15 table 2. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 4 . latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. notes 1. periodically sampled, not 100% tested. tested per mil-std-883, m3015 c2. 2. pin 52 is a test pin only. it is not used in normal operation. table 3. operating ratings symbol parameter/conditions min max units v dd supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v i i dc into any input -10 +10 ma i o dc into any output -10 +10 ma t stg storage temperature range -65 150 c jc theta jc 12 c/w symbol parameter/conditions min max units v dd supply voltage 2.85 3.45 v t a operating ambient temperature range -40 85 c table 4. esd ratings symbol parameter/conditions level units v esd esd voltage human body model on all pins except pin 52 1 1000 v esd voltage human body model on pin 52 1,2 300 v table 5. dc characteristics: v dd = 3.30 v -40 c < ta < 85 c, unless otherwise specified symbol parameter conditions min typ max units i dd operational supply current; v dd = 2.85 to 3.45 v prescaler enabled 40 ma i dd operational supply current; v dd = 2.85 to 3.45 v 15 ma prescaler disabled all digital inputs: k[17:0], r[5:0], m[8:0], a[3:0], direct, pre_en , rnd_sel, ms2_sel, enh (contains a 70 k ? pull-down resistor) v ih high level input voltage v dd = 2.85 to 3.45 v 0.7 x v dd v v il low level input voltage v dd = 2.85 to 3.45 v 0.3 x v dd v i ih high level input current v ih = v dd = 3.45 v 100 a i il low level input current v il = 0, v dd = 3.45 v -1 a reference divider input: f r i ihr high level input current v ih = v dd = 3.45 v 100 a i ilr low level input current v il = 0, v dd = 3.45 v -100 a counter and phase detector outputs: pd_ d , pd_ u v old output voltage low i out = 6 ma 0.4 v v ohd output voltage high i out = -3 ma v dd - 0.4 v digital test outputs: dout v old output voltage low i out = 200 ? a 0.4 v v ohd output voltage high i out = -200 ? a v dd - 0.4 v lock detect outputs: (cext, ld) v olc output voltage low, cext i out = 0.1 ma 0.4 v v ohc output voltage high, cext i out = -0.1 ma v dd - 0.4 v v olld output voltage low, ld i out = 1 ma 0.4 v
product specification PE97632 page 6 of 15 ?2006-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0205-07 ultracmos? rfic solutions table 6. ac characteristics v dd = 3.30 v -40 c < ta < 85 c, unless otherwise specified notes: 1. f clk is verified during the functional pattern test. serial programmi ng sections of the functional pa ttern are clocked at 10 mhz to verify f clk specification. 2. cmos logic levels can be used to drive the reference input. if the v dd of the cmos driver matches the v dd of the pll ic, then the reference input can be dc coupled. otherwise, the reference input should be ac coupled. for sin wave inputs, the minimum amplitude needs to be 0.5vpp. the maximum level should be limited to prevent esd diodes at the pin input from turning on. di odes will turn on at one forward-bias diode drop above vdd o r below gnd. the dc voltage at the reference input is v dd /2. 3. parameter is guaranteed through characterization only and is not tested. 4. parameter below are not tested for die sales. these parameters are verified during the element symbol parameter conditions min typ max units control interface and latches (see figure 10 ) f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t dsu sdata set-up time to sclk rising edge 10 ns t dhld sdata hold time after sclk rising edge 10 ns t pw s_wr pulse width 30 ns t cwr sclk rising edge to s_wr rising edge 30 ns t ce sclk falling edge to e_wr transition 30 ns t wrc s_wr falling edge to sclk rising edge 30 ns t ec e_wr transition to sclk rising edge 30 ns main divider (prescaler enabled) 4 p fin input level range external ac coupling 275 mhz freq 3200 mhz -5 5 dbm external ac coupling 3.2 ghz < freq 3.5 ghz 3.15 v v dd 3.45 v 0 5 dbm main divider (prescaler bypassed) 4 f in operating frequency 50 300 mhz p fin input level range external ac coupling -5 5 dbm reference divider f r operating frequency (note 3) 100 mhz p fr reference input power 2 single ended input -2 dbm phase detector f c comparison frequency (note 3) 50 mhz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.3 v, temp = 25 ? c ) 4 ? n phase noise 100 hz offset -89 dbc/hz ? n phase noise 1 khz offset -96 dbc/hz ? n phase noise 10 khz offset -101 dbc/hz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.0 v, temp = 25 ? c ) 4 ? n phase noise 100 hz offset -84 dbc/hz ? n phase noise 1 khz offset -92 dbc/hz ? n phase noise 10 khz offset -100 dbc/hz
product specification PE97632 document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 7 of 15 -30 -25 -20 -15 -10 -5 0 5 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) rf sensitivity (dbm) 2.85v 3.15v 3.30v figure 4. typical spurious plot test conditions: mash 1-1 mode. f out = 1.9204 ghz, f comparison = 20 mhz, frequency step = 400 khz, v dd = 3.3 v, temp = 25c , loop bandwidth = 50 khz. figure 5. rf sensitivity versus frequency (typical device at temperature = 25 c)
product specification PE97632 document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 8 of 15 figure 6. equivalent input diagram: reference input figure 7. equivalent input diagram: main input figure 8. equivalent output diagram: pd_ d & pd_ u outputs pin 62 pin 47 pin 48 pin 55 pin 57 71-0034-02 71-0033-01 71-0032-01 r f f ref r f = 112k ? c eq = 12pf c eq r f c eq r f in r f r f r f r f r f = 50k c eq = 0.8pf l bw = 3nh l bw r f = 50k ? c eq = 0.8pf l bw = 3nh l bw c eq r f l bw l bw f f in f f in 3nh 3nh l bw l bw l bw l bw
product specification PE97632 page 9 of 15 ?2006-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0205-07 ultracmos? rfic solutions functional description the PE97632 consists of a prescaler, counters, an 18-bit delta-sigma modulator (dsm) and a phase detector. the dual modulus prescaler divides the vco frequency by either 10 or 11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. an additional counter (?a?) is used in the modulus select logic. the dsm modulates the ?a? counter outputs in order to achieve the desired fractional step. the phase-frequency detector generates up and down frequency control signals. data is written into the internal registers via the three wire serial bus. there are also various operational and test modes and a lock detect output. figure 9. functional block diagram control logic modulus select 10/11 prescaler m counter (9-bit) r counter (6-bit) phase detector r(5:0) m(8:0) a(3:0) sdata control pins f r f in 2 k ? ld cext f in f c f p dsm + logic pd_ u pd_ d k(17:0)
product specification PE97632 document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 10 of 15 main counter chain normal operating mode the PE97632 can be operated in integer-n mode or either fractional-n mode. the main counter chain divides the rf input frequency (fin) by an integer or fractional number derived from the values in the ?m?, ?a? counters and the dsm input word k. setting the pre_en control bit ?high? operates the part only in integer-n mode. in addition, even if pre_en is "low" if k=0 the part is operated in integer-n mode. the fractional-n modes use a mash ( m ulti-st a ge noise sh aping) decimation structure. the ms2_sel pin sets the mash mode. mash-1-1 mode is a 2nd order fractional dithering using four (2 2 ) n values: n-1, n, n+1, n+2. mash 1-1-1 mode is a 3rd order fractional dithering using eight (2 3 ) n values: n-3, n-2, n-1, n, n+1, n+2, n+3, n+4. using the part in mash-1-1 or mash-1-1-1 mode will yield spurs at frequency offsets equal to fspur = [(2k + rnd_sel)/(2 19 )] x f c 1 k 131072 (1) [1-(2k + rnd_sel)/(2 19 )] x f c 131073 k 262143 where f c is the phase detector (comparison) frequency, k is the dsm input word, and rnd_sel is the k register lsb toggle enable. mash-1-1-1 mode reduces these spurs for an increase in the phase noise and a decrease in the number of valid programming frequencies. the 18-bit dsm accumulator fixes the fractional value of n from the ratio k/2 18 and the frequency step size as f c /2 18 . there is an additional bit in the dsm that acts like an extra bit (19th bit). this bit is enabled by asserting the pin rnd_sel to ?high?. enabling this bit has the benefit of reducing the spur levels. this is especially beneficial for large k-counter values that do not use any lower bits, causing an accumulation of random values in these bits and additional spurs. the side effect of asserting rnd_sel is that a small frequency offset will occur. this positive frequency offset is calculated with the following equation: f offset = (f r / (r + 1)) / 2 19 (2) all of the following equations do not take into account this frequency offset. if this offset is important to a specific frequency plan, it should be taken into account accordingly. in addition, k-counter values at the minimum, maximum and midpoint have higher spur levels that may not be reduced by enabling rnd_sel. if the pd comparison frequency is slightly shifted, the k value can be experimented with to move away from the suboptimal values. during normal operation, the output from the main counter chain (f p ) is related to the vco frequency (f in ) by the following equation: f p = f in / n (3) where n = 10 x (m+1) + a + (2k + rnd_sel)/2 19 a m + 1, 1 m 511 when the loop is locked, f in is related to the reference frequency (f r ) by the following equation: f in = n x (f r / (r+1)) (4) where n = 10 x (m+1) + a + (2k + rnd_sel)/2 19 a m + 1, 1 m 511
product specification PE97632 document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 11 of 15 a consequence of the upper limit on a is that: in integer-n mode, f in must be 90 x (f r / (r+1)) to obtain contiguous channels. in mash-1-1 mode, f in must be 91 x (f r / (r+1)) to obtain contiguous channels. in mash-1-1-1 mode, f in must be 93 x (f r / (r+1)) to obtain contiguous channels. the a counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 in increments of m. programming the m counter with the minimum allowed value of ?1? will result in a minimum m counter divide ratio of ?2?. prescaler bypass mode (*) setting the frequency control register bit pre_en ?high? allows f in to bypass the 10/11 prescaler. in this mode, the prescaler and a c ounter are powered down, and the input vco frequency is divided by the m counter directly. the following equation relates f in to the reference frequency f r : f in = (m + 1) x (f r / (r+1)) (5) where 1 m 511 (*) only integer-n mode in frequency bypass mode, neither a counter or k counter is used. therefore, only integer-n operation is possible. reference counter the reference counter chain divides the reference frequency f r down to the phase detector comparison frequency f c . the output frequency of the 6-bit r counter is related to the reference frequency by the following equation: f c = f r / (r + 1) (6) where 0 r 63 note that programming r with ?0? will pass the reference frequency (f r ) directly to the phase detector.
product specification PE97632 page 12 of 15 ?2006-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0205-07 ultracmos? rfic solutions while the e_wr input is ?high? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 7 , are clocked serially into the enhancement register on the rising edge of sclk, msb (b 0 ) first. the enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of e_wr according to the timing diagram shown in figure 10 . after the falling edge of e_wr, the data provide control bits as shown in table 9 on page 10 will have their bit functionality enabled by asserting the enh input ?low?. direct interface mode direct interface mode is selected by setting the ?direct? input ?high?. counter control bits are set directly at the pins as shown in table 7 and table 8 . table 7. secondary register programming table 8. auxiliary register programming table 9. enhancement register programming interface mode enh r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 addr direct 1 r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 x serial* 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 0 *serial data clocked serially on sclk rising edge while e_wr ?l ow? and captured in secondary register on s_wr rising edge. interface mode enh k 17 k 16 k 15 k 14 k 13 k 12 k 11 k 10 k 9 k 8 k 7 k 6 k 5 k 4 k 3 k 2 k 1 k 0 rsrv rsrv addr direct 1 k 17 k 16 k 15 k 14 k 13 k 12 k 11 k 10 k 9 k 8 k 7 k 6 k 5 k 4 k 3 k 2 k 1 k 0 x x x serial* 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 1 *serial data clocked serially on sclk rising edge while e_wr ?l ow? and captured in secondary register on s_wr rising edge. interface mode enh reserved reserved f p output power down counter load msel output f c output ld disable serial* 0 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 *serial data clocked serially on sclk rising edge while e_wr ?high? and captured in the double buffer on e_wr falling edge . msb (first in) msb (first in) (last in) lsb (last in) lsb (last in) lsb msb (first in) register programming serial interface mode while the e_wr input is ?low? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 20 , are clocked serially into the primary register on the rising edge of sclk, msb (b 0 ) first. the lsb is used as an address bit. when ?0?, the contents from the primary register are transferred into the secondary register on the rising edge of either s_wr according to the timing diagrams shown in figure 10 . when ?1?, data is transferred to the auxiliary register according to the same timing diagram. the secondary register is used to program the various counters, while the auxiliary register is used to program the dsm. data are transferred to the counters as shown in table 8 .
product specification PE97632 document no. 70-0205-07 www.psemi.com ?2006-2011 peregrine semiconductor corp. all rights reserved. page 13 of 15 enhancement register figure 10. serial interface mode timing diagram the functions of the enhancement register bits ar e shown below with all bits active ?high?. table 10. enhancement register bit functionality bit function description bit 0 reserve ** reserved. bit 1 reserve ** reserved. bit 2 f p output drives the m counter output onto the dout output. bit 3 power down power down of all functions except programming interface. bit 4 counter load immediate and cont inuous load of counter programming. bit 5 msel output drives the intern al dual modulus prescaler modulus select (msel) onto the dout output. bit 6 f c output drives the reference counter output onto the dout output. bit 7 ld disable disables the ld pin for quieter operation. ** program to 0 t dhld t dsu t clkh t clkl t cwr t pw t wrc t ec t ce e_wr sdata sclk s_wr
product specification PE97632 page 14 of 15 ?2006-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0205-07 ultracmos? rfic solutions figure 11. typical phase noise phase detector the phase detector is triggered by rising edges from the main counter (f p ) and the reference counter (f c ). it has two outputs, namely pd_ u , and pd_ d . if the divided vco leads the divided refer- ence in phase or frequency (f p leads f c ), pd_ d pulses ?low?. if the divided reference leads the di- vided vco in phase or frequency (f c leads f p ), pd_ u pulses ?low?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . for the up and down mode, pd_ u and pd_ d drive an active loop filter which controls the vco tune voltage. the phase detector gain is equal to vdd / 2 . pd_ u pulses cause an increase in vco frequency and pd_ d pulses cause a decrease in vco frequency, for a positive kv vco. a lock detect output, ld is also provided, via the pin cext. cext is the logical ?nand? of pd_ u and pd_ d waveforms, which is driven through a series 2 k ? resistor. connecting cext to an external shunt capacitor provides low pass filtering of this signal. cext also drives the input of an internal inverting comparator with an open drain output. thus ld is an ?and? function of pd_ u and pd_ d . a typical phase noise plot is shown below. ?trace 1? is the smoothed average, and ?trace 2? is the raw data . test conditions: mash-1-1 mode. f out = 1.9204 ghz, f comparison = 20 mhz, v dd = 3.3 v, temp = 25 c, loop bandwidth = 50 khz.
product specification PE97632 page 15 of 15 ?2006-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0205-07 ultracmos? rfic solutions figure 12. package drawing package dimensions: 68-lead cqfj table 11. ordering information order code part marking description packaging shipping method 97632-01 PE97632 es engineering samples 68-lead cqfj tray 97632-11 PE97632 flight units 68-lead cqfj tray 97632-00 PE97632 ek evaluation kit 1/box 97632-99 fa97632 die waffle pack 100 units / waffle pack advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in dev ices or systems int ended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for dam ages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com.

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