1 www.pericom.com 03/1 1/16 features ?? supports sata gen 3i. ?? two 6gbps diferential signal pairs ?? 100? diferential cml i/os ?? input signal level detect and squelch for each channel ?? oob support ?? automatic hdd rate detection for output swing/emphasis setting ?? termination detect indication p ower saving mode control to host or hdd ?? adjustable receiver equalization ?? selectable output pre-emphasis and swing control ?? high impedance i/o termination in standby mode ?? esd +/-8kv ?? low power operation: 254mw typical ?? auto-slumber mode: 36mw typical ?? hdd unplugged: 3.6mw ?? power down stand-by mode: 0.7mw max ?? supply voltage: 3.3v 10% ?? industrial temperature range: -40 o c to 85 o c ?? packaging: 20-tqfn (4x4mm) description pericoms pi3eqx6741st is a low power, signal sata gen 3i 6gbps redriver?. te device provides programmable equal - ization and output emphasis, to optimize performance over a variety of physical mediums by reducing inter-symbol interfer - ence. pi3eqx6741st supports two 100? diferential cml data i/os between the protocol asic to a switch fabric, across a back - plane, or to extend the signals across other distant data pathways on the users platform. te integrated equalization circuitry provides fexibilitywith signal integrity of the signal before the redriver. a low-level input signal detection and output squelch function is provided for each channel. each channel operates fully inde - pendently. when the channels are enabled (en=1) and operating, that channels input signal level (on xi+/-) determines whether the output is active. if the input signal level of the channel falls below the active threshold level (vth-) then the outputs are driven to the common mode voltage. termination detect indication (tdet_a# or tdet_b#) provides indication when the load is connected ie hdd or host. tis can be used as control to go into power saving mode by either the host or hdd. in addition to signal conditioning, when en = 0, the device enters a low power standby mode. block diagram en tdet_en x_ eq x_ em xl+ xl- xo+ xo- limiting amp equalizer power management cont rol circuit - repeated 2 times - cml tdet# cml v 50 50 signal detection bias = 1.05v pin diagram (top side view) 19 1 2 3 4 5 7 16 15 14 13 12 11 108 9 18 17 b_eq tdet_b# ai+ ai- bo- bo+ nc nc ao+ ao- tdet_a# bi- bi+ v dd en b_em tdet_en a_eq gnd 6 a_em 20 v dd pi3eqx6741st applications ?? notebook, desktop, docking station, set top box, server workstation, data storage 3.3v, 1-port, sata gen 3i redriver? with adjustable equalization/pre-emphasis all trademarks are property of their respective owners. 16-0050
2 www.pericom.com 03/1 1/16 pin description standard mode pin # pin name ty pe description 9 a_em input output emphasis adjustment for channel a. (see confguration table) digital control with 200k? pull-up resistor. 17 a_eq input channel a equalization adjustment is active. (see confguration table) tri-level input pin with 100k? pull-up and 100k? pull-down resistors. 1 2 ai+ ai- input cml input forward channel a with internal 50? pull-up resistors connected to vbias (100? diferential). 15 14 ao+ ao- output cml output channel a with internal 50? pull-up resistors connected to vbias (100? diferential). 8 b_em input output emphasis adjustment for channel b. (see confguration table) digital control with 200k? pull-up resistor. 19 b_eq input tri-level input pin with 100k? pull-up and 100k? pull-down resistors. (see confguration table) 11 12 bi+ bi- input cml input return channel b with internal 50k? pull-up, resistor connected to vbias (100? diferential). 5 4 bo+ bo- output positive cml output channel b with internal 50? pull-up resistor connected to vbias (100? diferential). 7 en input chip enable "high" provides normal operation. "low" for power down mode. with internal 200k? pull-up resistor. center pad gnd gnd supply ground. 10, 20 v dd power 3.3v supply voltage 10% 3 tdet_b# output termination detect output for channel b-active low, open drain. low: hdd termination present. high: hdd termination not present. 13 tdet_a# output termination detect output for channel a-active low, open drain. low: hdd termination present. high: hdd termination not present. 18 tdet_en input termination detect enable (200k? internal pull-up resistor) high: enable termination detect for esata application or hot plug device application low: disable termination detect for internal sata application. 6, 16 nc no connection internally. all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
3 www.pericom.com 03/1 1/16 configuration table - input equalizer a_eq/b_eq 1.5 gb/s 3 gb/s 6gb/s 0 1 db 2.5 db 3 db foating 2.5 db 5 db 6 db 1 4 db 7.5 db 9 db configuration table - output pre-emphasis/swing setting a_em/b_em 3 gb/s 6 gb/s 0 550mv pp 650mv pp 1 550mv pp + 3db pre-emphasis 650mv pp + 1.5db pre-emphasis termination detect feature: termination detect is a power saving feature. te user can enable tdet_en (set to high) for esata application as it would save more power when there is no external hdd connection. but for internal sata application, tdet_en should be set to low because internal hdd is always on and termination is always there. when redriver doesnt detect host or hdd termination, there will be about 12us detect pulse width with 50us detect period at the output of redriver. once the termination is detected, the detect period will change to about 40ms. anyway when the signal is detected at the input of redriver, there will not be any detect pulse at both the output side of redriver. all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
4 www.pericom.com 03/1 1/16 storage temperature ................................................ C 65c to +150c supply voltage to ground potential ........................ C0.5v to +4.6v dc sig voltage ................................................. C0.5v to v dd +0.5v output current ..................................................... -25ma to +25ma power dissipation continuous ............................................. 5 00mw operating temperature ............................................ -40c to +85c esd, human body model .............................................. -8kv to 8kv note: stresses greater than those listed under maximum rat- ings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. ex- posure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) ac/dc electrical characteristics symbol parameter conditions min. ty p. (1) max. units v dd power supply voltage 3.0 3.6 v p standby supply power, standby en = 0 0.07 0.7 mw p unplug supply power, hdd unplugged no hdd attached, tdet_en = high 3.6 11 p slumber supply power, slumber tdet_en = low 36 50 p active supply power, active en = 1 a/b_em=0 diffp-p v th-sd 254 317 i dd-standby supply current standby en = 0 0.02 0.2 ma i dd-unplug supply current, hdd unplugged no hdd attached, tdet_en = high 1 3 i dd-slumber supply current slumber tdet_en = low 11 14 i dd-active supply current active en = 1, input = 600mvppd, a/b_em=0 77 88 t pd latency from input to output 0.7 ns cml receiver input z rx-dc dc input impedance 40 50 60 ohm z rx-diff-dc dc diferential input impedance 80 100 120 v rx-diffp-p diferential input peak-to-peak voltage 0.2 1.2 v v rx-cm-acp ac peak common mode input voltage 150 mv v th-sd signal detect treshold en = 1 50 200 (2) mvppd note: 1. t ypical values are at v dd = 3.3v, t a = 25c ambient and maximum loading. 2. u sing compliance test at 1.5gbps, 3gbps and 6gbps. also using oob (oob is formed by alignp primitive or d24.3) test patterns at 1.5gbps. te align primitive (k28.5+d10.2+d27.3 = 0011111010+0101010101+0010011100). te d24.3 = 00110011001100110011. all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
5 www.pericom.com 03/1 1/16 symbol parameter conditions min. ty p. (1) max. units rl dd11_rx rx diferential mode return loss 75mhz-300mhz 300mhz-600mhz 600mhz-1.2ghz 1.2ghz-2.4ghz 2.4ghz-3.0ghz 3.0 ghz-5.0ghz 18 14 10 8 3 1 db rl cc11_rx rx common mode return loss 150mhz C 300mhz 300mhz C 600mhz 600mhz C 1.2ghz 1.2ghz C 2.4ghz 2.4ghz C 3.0ghz 3.0ghz C 5.0ghz 3 5 2 2 1 1 db rl dc11_rx rx impedance balance 150mhz C 300mhz 300mhz C 600mhz 600mhz C 1.2ghz 1.2ghz C 2.4ghz 2.4ghz C 3.0ghz 3.0ghz C 5.0ghz 30 30 20 10 4 4 db cml transmitter output (100? diferential) ( 3) z tx-diff-dc dc diferential tx impedance 80 100 120 ohm v tx-diffp-p diferential peak-to-peak output voltage v tx-diffp-p = 2 * | v tx-d sata2 450 700 sata3 550 750 mv v tx-c common-mode voltage | v tx-d+ + v tx-d-| /2 0.5 1.2 v t f , t r transition time 20% to 80% ( 3) 0db pre-emphasis 40 150 ps v amp_bal tx amplitude imbalance 3g only; hftp, mftp 10 % t skew tx diferential skew 1.5g and 3g; hftp, mftp 20 ps v cm_ac tx ac common mode voltage 3g only; mftp 50 mvpp v tx-pre-ratio-max max tx pre-emphasis level 3 db 1.5 rl dd11_tx tx diferential mode return loss 150mhz C 300mhz 300mhz C 600mhz 600mhz C 1.2ghz 1.2ghz C 2.4ghz 2.4ghz C 3.0ghz 3.0 ghz C 5.0ghz 14 8 6 6 3 1 db c tx ac coupling capacitor 2 4.7 12 nf t j total jitter fr4 input trace 18" 0.16 ui 36" 0.24 d j deterministic jitter fr4 input trace 18" 0.11 ui 36" 0.19 ac/dc electrical characteristics ( cml receiver input continued) ( 1) note: 3. recommended output coupling capacitor is 4.7nf to 12nf (on each output) all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
6 www.pericom.com 03/1 1/16 symbol parameter conditions min. ty p. (1) max. units rl cc11_tx tx common mode return loss 150mhz C 300mhz 300mhz C 600mhz 600mhz C 1.2ghz 1.2ghz C 2.4ghz 2.4ghz C 3.0ghz 3.0 ghz C 5.0ghz 5 5 2 2 1 1 db rl dc11_tx tx impedance balance 150mhz C 300mhz 300mhz C 600mhz 600mhz C 1.2ghz 1.2ghz C 2.4ghz 2.4ghz C 3.0ghz 3.0 ghz C 5.0ghz 30 20 10 10 4 4 db lvcmos control pins v ih input high voltage (bi-level) 0.65 v dd v v il input low voltage (bi-level) 0.35 v dd i ih input high current 100 a i il input low current -100 v ol dc output logic low i ol = 4 ma 0.4 v v ih input high voltage (tri-level) 0.8 v dd v v il input low voltage (tri-level) 0.2 v dd v ac/dc electrical characteristics auto slumber mode entry/exit time symbol parameter conditions min. ty p. (1) max. units t slumberon entry time to slumber mode electrical idle at input (see figure) 10 20 s t slumberoff exit time from slumber mode afer frst signal activity (see figure) 6 20 ns all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
7 www.pericom.com 03/1 1/16 test condition referenced in the electrical characteristic table auto slumber mode entry and exit timing d.u.t. signal source sma connector in out a sma connector b c fr4 30 in v d+ common mode vo lt age v_ d+ - v_ d- 0v v cm v diff v d- v dif fp -p v di ff p-p v d+ v cm v diff v d- 1 st t bit 2 nd + t bit(s) v diff-pre pre-emphasis = 20 . log (v diff -p re /v diff ) defnition of diferential voltage and diferential voltage peak-to-peak defnition of pre-emphasis all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
8 www.pericom.com 03/1 1/16 b_em device host device sata host application sata device application device en host +2.5 ~ +3.3v host vdd device vdd +2.5 ~ +3.3v +2.5 ~ +3.3v c9 c7 c4 c13 4.7nf c18 pi3eqx6741st note: * connect r1 for high connect r2 for low don?t connect r1, r2 for mid level . r1, r2 are 0 resistors. 10n 10n c12 c11 r2 100k c16 gnd pi3eqx6741st 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ai+ ai- bo- bo+ nc en a_em vdd vdd b_eq nc ao+ ao- bi- bi+ c17 4.7nf j5 watf- 07 1 2 3 4 5 6 7 1 2 3 4 5 6 7 c8 c5 c20 c14 c15 4.7nf c6 c3 c10 j2 watf-07 1 2 3 4 5 6 7 1 2 3 4 5 6 7 c19 4.7nf 4.7nf 4.7nf 4.7nf 4.7nxf 4.7nf 4.7nf 4.7nf 4.7nf 4.7nf 4.7nf 4.7nf 4.7nf r5 100k +2.5 ~ +3.3v 10n 10n c1 c1 b_em gnd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ai+ ai- bo- bo+ nc en a_em vdd vdd b_eq nc ao+ ao- bi- bi+ a_eq a_eq vdd *r2 *r1 vdd *r2 *r1 vdd *r2 *r1 vdd *r2 *r1 vdd *r2 *r1 vdd *r2 *r1 vdd *r2 *r1 vdd *r2 *r1 tdeta# tdetb# t_det_en tdetb# tdeta# t_det_en application schematic all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
9 www.pericom.com 03/1 1/16 ordering information ordering number package code package description PI3EQX6741STZDE zd 20-lead, tin fine pitch quad flat no-lead (tqfn) 4x4mm notes: ? t ermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = p b-free and green ? x s ufx = tape/reel packaging mechanical: 20-contact tqfn (zd) 1 : 20-lead, thin fine pitch quad flat no-lead (tqfn) noitpircsed :edoc egakcap 2084-dp :# lortnoc tnemucod -- :noisiver 80/11/90 :etad zd20 08-0456 note: for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php all trademarks are property of their respective owners. pi3eqx6741st 3.3v, 1-port, sata3i redriver ? 16-0050
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