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1 of 157 093002 note: some revisions of this device m ay incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim - ic.com/errata . general description the ds2196 t1 dual framer liu is designed for t1 transmission equipment. the ds2196 combines dual optimized framers together with a liu. this combination allows the users to extract and insert facility data - link (fdl) messages in the receive and transmit paths, collect line performance data, and perform basic channel conditioning and maintenance. the ds2196 contains all of the necessary functions for connection to t1 lines whether they are ds1 long haul or dsx ? 1 short haul. the clock recovery circuitry automatically adjusts to t1 lines from 0ft to over 6000ft in length. the device can generate both dsx ? 1 line buildouts as well as csu line buildouts of - 7.5db, - 15db, and - 22.5db. the on - board jitter attenuator (selectable to eith er 32 bits or 128 bits) can be placed in either the transmit or receive data paths. the framer locates the frame and multiframe boundaries and monitors the data stream for alarms. the device contains a set of internal registers that the user can access and use to control the unit?s operation of the unit. quick access through the parallel control port allows a single controller to handle many t1 lines. the device fully meets all of the latest t1 specifications. package outline features two f ull - featured framers and a short/long - haul line interface unit (liu) in one small package based on dallas semiconductor?s single - chip transceiver (sct) family two hdlc controllers with 64 - byte buffers that can be used for the fdl or ds0 channels supports nprms and sprms as per ansi t1.403 - 1998 can be combined with a short/long - haul liu or a hdsl modem chipset to create a low - cost office repeater/niu/csu, or a hdsl1/hdsl2 terminal unit with enhanced monitoring and data link control supports fractional t1 ca n convert from d4 to esf framing and esf to d4 framing 32 - bit or 128 - bit crystal - less jitter attenuator can generate and detect repeating in - band patterns from 1 to 8 bits or 16 bits in length detects and generates rai - ci and ais - ci generates ds1 idle code s on - chip programmable bert generator and detector all key signals are routed to pins to support numerous hardware configurations supports both nrz and bipolar interfaces can create errors in the f - bit position and bert interface data paths 8 - bit parallel control port that can be used directly on either multiplexed or nonmultiplexed buses (intel or motorola) ieee 1149.1 jtag boundary scan 3.3v supply with 5v tolerant inputs and outputs 100 - pin lqfp (14 mm x 14 mm) package ordering information part temp ra nge pin - package ds2196l 0oc to +70oc 100 lqfp DS2196LN - 40oc to +85oc 100 lqfp www.maxim - ic.com ds2196 t1 dual framer liu 1 100 ds2196
ds2196 2 of 157 table of contents 1 introduction.................................................................................................................. .............. 6 1.1 feature highlights......................................................................................................... ......... 6 1.2 typical applications....................................................................................................... ...... 10 1.3 functional description..................................................................................................... .. 10 2 pin description ............................................................................................................... ........... 10 3 pin function description.................................................................................................... 13 4 register map.................................................................................................................. ............. 21 5 parallel port................................................................................................................. ........... 27 6 control, id, and test registers ..................................................................................... 27 7 status and in formation registers ............................................................................ 51 8 error count registers................................................................................................... .... 64 9 signaling operation........................................................................................................... ... 68 10 ds0 monitoring function .................................................................................................. 70 11 per?channel code (idle) generation and loopback ..................................... 72 11.1 transmit side code generation .................................................................................. 72 11.2 receive side code generation...................................................................................... 73 12 programmable in?band code generation and detection ......................... 74 13 clock blocking registers.............................................................................................. 83 14 transmit transparency................................................................................................... .85 15 bert function ........................................................................................................... ............... 86 15.1 bert register description.............................................................................................. 88 16 error insertion function ............................................................................................... 9 6 17 hdlc controller ......................................................................................................... ......... 99 17.1 hdlc for ds0 s ......................................................................................................................... 100 18 fdl/fs extraction and insertion .............................................................................. 101 18.1 hdlc and boc controller for the fdl.................................................................. 101 18.1.1 general overview ......................................................................................................... ........ 101 18.1.2 status register for the hdlc............................................................................................. .. 103 18.1.3 basic operation details .................................................................................................. ...... 103 18.1.4 hdlc/boc register description ........................................................................................ 105
ds2196 3 of 157 18.2 legacy fdl support......................................................................................................... . 115 18.2.1 overview................................................................................................................. .............. 115 18.2.2 receive section.......................................................................................................... ........... 115 18.2.3 transmit section ......................................................................................................... .......... 116 18.3 d4/slc?96 operation ........................................................................................................ .. 117 19 line interface function................................................................................................ 118 19.1 receive clock and data recovery ......................................................................... 118 19.2 transmit waveshaping and line driving............................................................. 119 19.3 jitter attenuator ..................................................................................................... ..... 120 20 jtag-boundary scan architec ture and test access port...................... 124 20.1 d escription ............................................................................................................................... . 124 20.2 tap c ontroller s tate m achine ............................................................................................ 125 20.3 i nstruction r egister and i nstructions ................................................................................ 127 21 timing diagrams.............................................................................................................. .... 133 22 operating parameters ................................................................................................... 141 23 100-pin lqfp package specifications ...................................................................... 157
ds2196 4 of 157 list of figures figure 1-1: t1 dual framer liu ................................................................................................. ............. 9 figure 15-1: bert mux diagram .................................................................................................. ........ 87 figure 19-1: external analog connections ....................................................................................... ... 121 figure 19-2: jitter tolerance .................................................................................................. ............... 122 figure 19-3: transmit waveform template ........................................................................................ 122 figure 19-4: jitter attenuation................................................................................................ .............. 123 figure 20-1: boundary scan architecture ........................................................................................ ... 124 figure 20-2: tap controller state machine...................................................................................... .. 127 figure 21-1: receive side d4 timing............................................................................................ ........ 133 figure 21-2: receive side esf timing ........................................................................................... ...... 134 figure 21-3: receive si de boundary timing ...................................................................................... . 135 figure 21-4: transmit side d4 timing........................................................................................... ...... 136 figure 21-5: transmit side esf timing .......................................................................................... .... 137 figure 21-6: transmit si de boundary timing .................................................................................... 1 38 figure 21-7: transmit data flow................................................................................................ .......... 139 figure 21-8: receive data flow................................................................................................. ............ 140 figure 22-1: intel bus read ac timing (bts=0 / mux = 1) ............................................................ 146 figure 22-2: intel bus write timing (bts=0 / mux=1) .................................................................... 147 figure 22-3: motorola bus ac timing (bts = 1 / mux = 1) ............................................................ 148 figure 22-4: intel bus read ac timing (bts=0 / mux=0) .............................................................. 149 figure 22-5: intel bus write ac timing (bts=0 / mux=0) ............................................................. 150 figure 22-6: motorola bus read ac timing (bts=1 / mux=0) ...................................................... 151 figure 22-7: motorola bus write ac timing (bts=1 / mux=0) ..................................................... 152 figure 22-8: receive side ac timing............................................................................................ ....... 153 figure 22-9: receive line interface ac timing.................................................................................. 154 figure 22-10: transmit side ac timing.......................................................................................... .... 155 figure 22-11: transmit line interface side ac timing..................................................................... 156
ds2196 5 of 157 list of tables table 2-1: pin description sorted by pin number................................................................................ 10 table 4-1: register map sorted by address ...................................................................................... .... 21 table 6-1: output pin test modes ............................................................................................... ........... 36 table 6-2: receive data source mux modes...................................................................................... ... 37 table 6-3: tposb/tnegb data source select..................................................................................... 3 8 table 7-1: receive t1 level indication ......................................................................................... ......... 57 table 7-2: alarm criteria ...................................................................................................... .................. 59 table 8-1: line code violat ion counting arrangements..................................................................... 66 table 8-2: path code violation counting arrangements..................................................................... 67 table 8-3: multiframes out of sync counting arrangements............................................................ 67 table 12-1: transm it code length............................................................................................... .......... 75 table 12-2: receive code length ............................................................................................... ............ 75 table 15-1: bert pattern select options ........................................................................................ ......... 89 table 15-2: repetitive pa ttern length options .................................................................................. ... 90 table 15-3: bert rate insertion select......................................................................................... ........... 91 table 16-1: error rate options ................................................................................................. ............. 98 table 16-2: error insertion examples........................................................................................... .......... 99 table 17-1: transmit hdlc configuration ........................................................................................ .. 99 table 18-1: hdlc/boc cont roller register list............................................................................... 102 table 19-1: line build out select in licr ...................................................................................... ... 119 table 19-2: transformer specifications ......................................................................................... ...... 120 table 20-1: instruction codes for the ds21352/552 ieee 1149.1 architecture ............................ 128 table 20-2: id co de structure .................................................................................................. ............ 128 table 20-3: device id codes.................................................................................................... .............. 129 table 20-4: boundary scan register des cription................................................................................ 1 30
ds2196 6 of 157 1. introduction the ds2196 is a derivative of the ds21352 t1 sct. th e feature set has been optimized for transport applications commonly found in t1 transmission equi pment. the ds2196 register map and register bit definitions are compatible with the ds21352/ds 21552, allowing for easy migration to the ds2196. interface designs requiring per-channel code inserti on, elastic stores, and ansi 1?s density monitoring should use the ds21352 or ds21552. 1.1 feature highlights main features ? two full-featured independent framers ? short/long haul liu ? 100-pin lqfp small package ? 3.3v operation with 5v tolerant i/o 8-bit parallel control port ? multiplexed or nonmultiplexed buses ? intel or motorola formats ? polled or interrupt environments hdlc support ? two independent hdlc controllers ? 64-byte rx and tx buffers ? access fdl or single/multiple ds0 channels ansi t1.403-1998 support ? nprms ? sprms ? rai-ci detection and generation ? ais-ci detection and generation format conversion ? d4 to esf framing ? esf to d4 framing liu ? long and short-haul support ? receive sensitivity: 0db to -36db ? 32-bit or 128-bit crystal-less jitter attenuator ? dsx-1 and csu line buildout options ? provisions for custom waveform generation ds1 idle code generation ? user-defined ? fixed 7f hex ? digital milliwatt in-band repeating pattern generator and detector ? programmable pattern generator ? three programmable pattern detectors ? patterns from 1 to 8 bits or 16 bits in length programmable on-chip bit error-rate testing ? pseudorandom patterns including qrss ? user-defined repetitive patterns ? daly pattern ? error insertion ? bit and error counts payload error insertion ? error insertion in the payload portion of the t1 frame in the transmit path ? errors can be inserted over the entire frame or selected channels ? insertion options include continuous and absolute number with selectable insertion rates function isolation ? all key signals are routed to pins ? liu, framer a, and framer b can be disconnected from each other supports both nrz and bipolar interfaces f-bit corruption for line testing programmable output clocks for fractional t1 fully independent transmit and receive functionality in each framer large path and line error counters including bpv, cv, crc6, and framing bit errors ability to calculate and check crc6 according to the japanese standard ability to generate yellow alarm according to the japanese standard per channel loopback rcl, rlos, rra, and rais alarms interrupt on change of state hardware pins to indicate receive loss-of- sync and receive bipolar violations ieee 1149.1 jtag boundary scan
ds2196 7 of 157 1.2 typical applications 1.3 functional description the analog ami/b8zs waveform off of the t1 lin e is transformer coupled into the rring and rtip pins of the ds2196. the device recovers clock and da ta from the analog signal and passes it through the optional jitter attenuator to the receive side framer where the digital serial stream is analyzed to locate the framing/multiframe pattern. the ds2196 c ontains an active filter that re constructs the analog received signal for the nonlinear losses that occur in transmi ssion. the device has a usable receive sensitivity of 0 db to ?36 db, which allows the device to operate on cables up to 6000 feet in length. the receive side framer locates d4 (slc?96) or esf multiframe boundarie s as well as detects incoming alarms including, carrier loss, loss of synchronization, blue (ais) and yellow alarms. the transmit side of the ds2196 is totally indepe ndent from the receive side in both the clock requirements and characteristics. the transmit formatter will provide the necessary frame/multiframe data overhead for t1 transmission. once the data stream has been prepared fo r transmission, it is sent via the optional jitter attenuator to the wave shaping and line driver func tions. the ds2196 will drive the t1 line from the ttip and tring pins via a coupling transf ormer. the line driver can handle both long haul (csu) and short haul (dsx?1) lines. long / short haul line interface unit (liu) rx framer a rx hdlc tx hdlc tx formatter a rx framer b rx hdlc tx hdlc tx formatter b long / short haul line interface unit (liu) t1 interface a t1 interface b microcontroller ds2196 1.544 mhz long / short haul line interface unit (liu) rx framer a rx hdlc tx hdlc tx formatter a rx framer b rx hdlc tx hdlc tx formatter b t3 / sonet / optical mux t1 network interface microcontroller ds2196 1.544 mhz n rz interface office repeater/niu long / short haul line interface unit (liu) rx framer a rx hdlc tx hdlc tx formatter a rx framer b rx hdlc tx hdlc tx formatter b short haul line interface unit (liu) telco t1 interface cpe t1 interface microcontroller ds2196 1.544 mhz long / short haul line interface unit (liu) rx framer a rx hdlc tx tx formatter a rx framer b rx hdlc tx hdlc tx formatter b hdsl1 / hdsl2 modem t1 interface (remote or co located) one or two sets of twiste d pair microcontroller ds2196 1.544 mhz n rz interface csu application hdsl1/hdsl2 application t3/sonet/optical multiplexer application
ds2196 8 of 157 reader?s note: this data sheet assumes a particular nomen clature of the t1 operating environment. in each 125 s frame, there are 24 8-bit channels plus a framing bit. it is assumed that the framing bit is sent first followed by channel 1. each channel is made up of 8 bits that are numbered 1 to 8. bit number 1 is the msb and is transmitted first. bit number 8 is the lsb and is transmitted last. the following abbreviations are used throughout this data sheet: bert bit error rate tester d4 superframe (12 frames per multiframe) multiframe structure slc?96 subscriber loop carrier?96 channels esf extended superframe (24 frames per multiframe) multiframe structure b8zs bipolar with eight zero substitution crc cyclical redundancy check ft terminal framing pattern in d4 fs signaling framing pattern in d4 fps framing pattern in esf mf multiframe boc bit-oriented code hdlc high-level data-link control fdl facility data link
ds2196 9 of 157 framer loopback a payload loopback a ais & ais-ci generation b8zs encode crc generation yellow alarm generation signaling insertion clear channel f-bit insertion parallel control port (routed to all blocks) receive side framer a transmit side formatter a bpv counter alarm detection loop code generation fsync data clock msync data clock d0 to d7 / ad0 to ad7 bts int* tsynca tclka tchclka/ tlclka tsera tchblka/ tlinka wr*(r/w*) rd*(ds*) rchclka/ rlclka cs* rchblka/ rlinka rmsynca rsera rfsynca fdl extraction fdl insertion b8zs decoder synchronizer loop code detector crc/frame error count signaling extraction channel marking rlosa / lotca ale(as) / a7 a0 to a6 mux 8 rcl line drivers csu filters wave shaping local loopback tring ttip jitter attenuation (can be placed in either transmit or receive path) filter peak detect clock / data recovery rring rtip remote loopback vco / pll mclk 1.544 mhz liu ais generation rclka 7 rposlo rneglo rnegia rposia tposli tnegli tnegoa/ tfsynca tposoa/ tnrza rclklo rclkia per-channel loopback tclkli tclkoa 64-byte buffer bom detection 64-byte buffer bom generation mux (controlled via ccr4a.2) mux (controlled via ccr4a.2) msync fsync framer loopback b ais & ais-ci generation b8zs encode crc generation yellow alarm generation signaling insertion clear channel f-bit insertion transmit side formatter b bpv counter alarm detection loop code generation fsync data clock msync data clock fdl extraction fdl insertion b8zs decoder synchronizer loop code detector crc/frame error count signaling extraction channel marking per-channel loopback 64-byte buffer bom detection 64-byte buffer bom generation msync fsync tsync control tsync control clock gen clock gen clock gen tsyncb tclkb tserb tchclkb tlclkb tchblkb/ tlinkb rlosb / lotcb rchclkb/ rlclkb rchblkb/ rlinkb rclkb rmsyncb rserb rfsyncb liu ais pro- tect work- ing wps wnrz wclk pnrz pclk tneg or tfsync tclk tpos or tnrz lfsync lclk lnrz mux (controlled via ccr4b.2) rposib rnegib rclkib tposob/ tnrzb tclkob tnegob/ tfsyncb receive side framer b clock gen to bert mux jtag jtclk jtms jtdo jtdi jtrst* to bert mux insert data from bert insert data from bert power dvss(3) rvss(2) tvdd tvss rvdd dvdd(3) bert mux rxa rxb txa 4 4 5 to / from bert mux rbpva rbpvb data source mux control (controlled via ccr1a.2/3/4) back end loopback rser rmsync rclk sysclk sser sfsync ds2175 (optional) from receive framer b (only in ft1 application) msync 1.544mhz rclkb rmsyncb user output port (4 pins) uop0 uop1 uop2 uop3 flb b 2 flb b mux from bert mux lotc mux from mclk 4 4 bert clock data clock data corrupt f-bit / payload corrupt f-bit / payload sync payload loopback b mux (controlled via ccr4b.2) lotc mux from mclk lnrz ais generation figure 1-1. t1 dual framer liu
ds2196 10 of 157 2. pin description table 2-1. pin description sorted by pin number pin symbol type function 1 pclk i protect clock input. 2 pnrz i protect nrz data input. 3 wclk i working clock input. 4 wnrz i working nrz data input. 5 jtms i ieee 1149.1 test mode select. 6 jtclk i ieee 1149.1 test clock signal. 7 jtrst* i ieee 1149.1 test reset. 8 jtdi i ieee 1149.1 test data input. 9 jtdo o ieee 1149.1 test data output. 10 rcl o receive liu carrier loss. 11 lnrz o liu nrz & positive data output. 12 lclk o liu clock output. 13 lfsync o liu frame sync pulse & negative data output. 14 rposlo o receive positive & nrz data output from the liu. 15 rneglo o receive negative & nrz data output from the liu. 16 rclklo o receive clock output from the liu. 17 bts i bus type select. 0 = intel / 1 = motorola. 18 rtip i receive analog tip input. 19 rring i receive analog ring input. 20 rvdd ? receive analog positive supply. 3.3v (5%). 21 rvss ? receive analog signal ground. 22 int* o interrupt. open drain. active low signal. 23 rvss ? receive analog signal ground. 24 mclk i master clock input. 1.544 mhz (50 ppm). 25 uop3 o user defined output port bit 3. 26 uop2 o user defined output port bit 2. 27 uop1 o user defined output port bit 1. 28 uop0 o user defined output port bit 0. 29 ttip o transmit analog tip output. 30 tvss ? transmit analog signal ground. 31 tvdd ? transmit analog positive supply. 3.3v (5%). 32 tring o transmit analog ring output. 33 tposli i transmit positive & nrz data for the liu. 34 tnegli i transmit negative & nrz data for the liu. 35 tclkli i transmit clock input for the liu. 36 tchblkb/ tlinkb i/o transmit channel blocking clock output from formatter b / transmit fdl link data input for formatter b. 37 tchclkb/ tlclkb o transmit ds0 channel clock output from formatter b / transmit fdl link clock output from formatter b. 38 tsyncb i/o transmit frame & multiframe pulse for/from formatter b. 39 tclkb i transmit clock input for formatter b. 40 tserb i transmit serial data input for formatter b. 41 tposob/ tnrzb o transmit positive data output from formatter b / transmit nrz data output from formatter b. 42 tnegob / tfsyncb o transmit negative data output from formatter b / transmit frame sync pulse output from formatter b.
ds2196 11 of 157 pin symbol type function 43 tclkob o transmit clock output from formatter b. 44 dvss ? digital signal ground. 45 dvdd ? digital positive supply. 3.3v (5%). 46 tclkoa o transmit clock output from formatter a. 47 tnegoa / tfsynca o transmit negative data output from formatter a / transmit frame sync pulse output from formatter a. 48 tposoa / tnrza o transmit positive data output / transmit nrz data output from formatter a. 49 tsera i transmit serial data input for formatter a. 50 tclka i transmit clock input for formatter a. 51 tsynca i/o transmit frame & multiframe pulse for/from formatter a. 52 tchclka / tlclka o transmit ds0 channel clock output from formatter a / transmit fdl link clock output from formatter a. 53 tchblka / tlinka i/o transmit channel blocking clock output from formatter a / transmit fdl link data input for formatter a. 54 mux i bus operation. 0 = non-mux bus / 1 = mux bus operation. 55 d0 / ad0 i/o data bus bit 0 / address/data bus bit 0. lsb. 56 d1 / ad1 i/o data bus bit 1 / address/data bus bit 1. 57 d2 / ad2 i/o data bus bit 2 / address/data bus bit 2. 58 d3 / ad3 i/o data bus bit 3 / address/data bus bit 3. 59 d4 / ad4 i/o data bus bit 4 / address/data bus bit 4. 60 d5 / ad5 i/o data bus bit 5 / address/data bus bit 5. 61 d6 / ad6 i/o data bus bit 6 / address/data bus bit 6. 62 d7 / ad7 i/o data bus bit 7 / address/data bus bit 7. msb. 63 dvss ? i/o digital signal ground. 64 dvdd ? i/o digital positive supply. 3.3v (5%). 65 a0 i address bus bit 0. lsb. 66 a1 i address bus bit 1 67 a2 i address bus bit 2 68 a3 i address bus bit 3 69 a4 i address bus bit 4 70 a5 i address bus bit 5 71 a6 i address bus bit 6 72 a7 / ale(as) i address bus bit 7 / addres s latch enable (address strobe). msb. 73 rd*(ds*) i read input (data strobe). 74 cs* i chip select. active low signal. 75 wr*(r/w*) i write input (read/write). 76 rchblka / rlinka o receive channel blocking clock output from framer a / receive fdl link data output from framer a. 77 rchclka / rlclka o receive ds0 channel clock output from framer a / receive fdl link clock output from framer a. 78 rclkia i receive clock input for framer a. 79 rposia i receive positive & nrz data input for framer a. 80 rnegia i receive negative & nrz data input for framer a. 81 rclka o receive clock output from framer a. 82 rsera o receive serial data output from framer a. 83 rmsynca o receive multiframe pulse from framer a. 84 rfsynca o receive frame pulse from framer a. 85 rlosa/ lotca o receive loss of synchronization from framer a / loss of transmit clock framer a.
ds2196 12 of 157 pin symbol type function 86 rbpva o receive bipolar violation (bpv) from framer a. 87 dvss ? digital signal ground. 88 dvdd ? digital positive supply. 3.3v (5%). 89 rbpvb o receive bipolar violation (bpv) from framer b. 90 rlosb/ lotcb o receive loss of synchronization from framer b / loss of transmit clock framer b. 91 rfsyncb o receive frame pulse from framer b. 92 rmsyncb o receive multiframe pulse from framer b. 93 rserb o receive serial data output from framer b. 94 rclkb o receive clock output from framer b. 95 rnegib i receive negative & nrz data input for framer b. 96 rposib i receive positive & nrz data input for framer b. 97 rclkib i receive clock input for framer b. 98 rchclkb / rlclkb o receive ds0 channel clock output from framer b / receive fdl link clock output from framer b. 99 rchblkb / rlinkb o receive channel blocking clock output from framer b / receive fdl link data output from framer b. 100 wps i working/protect select.
ds2196 13 of 157 3. pin function description transmit side pins signal name: tclka/b signal description: transmit clock signal type: input a 1.544 mhz primary clock is applied here. used to clock data through the transmit side formatters. tclka/b can be internally connected to rclkb/a via the ccr4b.2 control bit. signal name: tsera/b signal description: transmit serial data signal type: input transmit nrz serial data. sampled on the falling ed ge of tclka or tclkb. tsera/b can be internally connected to rserb/a via the ccr4b.2 control bit. signal name: tsynca/b signal description: transmit sync signal type: input / output when programmed as an input, a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. via tcr2a.2 and tcr2b.2, the ds2196 can be programmed to output either a frame or multiframe pulse at this pin. if this pin is set to output pulses at frame boundaries, it can also be set via tcr2a.4 and tcr2b.4 to output double?wide pulses at signaling frames. see section 21 for details. tsynca/b can be internally connected to rmsyncb/a via the ccr4b.2 control bit. signal name: tchclka/b / tlclka/b signal description: transmit channel clock / transmit link clock signal type: output a dual function pin depending on the setting of the ccr4a.1 and ccr4b.1 control bits. if tchclk is selected, a 192-khz clock, which pulses high during the lsb of each channel, will be output. if tlclk is selected, either a 4 khz or 2 khz (zbtsi) demand clock for the tlink data is output. this output signal is always synchronous with tclka or tclkb. see section 21 for details. signal name: tchblka/b / tlinka/b signal description: transmit channel block / transmit link data signal type: input / output a dual function pin depending on the setting of the ccr4a.1 and ccr4b.1 control bits. if tchblk is selected, a user programmable output that can be forced high or low during any of the 24 t1 channels is output. useful for blocking clocks to a serial uart or lapd controller in applications where not all t1 channels are used such as fractional t1, 384 kbps service, 768 kbps, or isdn?pri. al so useful for locating individual channels in drop? and?insert applications, for external per?channel loopback, and for per?channel conditioning. see section 21 for details. if tlink is selected, this pin will be sampled on the falling edge of tclka or tclkb for data insertion into either the fdl stream (esf) or the fs?bit position (d4) or the z?bit position (zbtsi). see section 21 for details. this signal is always synchronous with tclka or tclkb. signal name: tposoa/b / tnrza/b signal description: transmit positive & nrz data output signal type: output updated on the rising edge of tclkoa and rising or fall ing edge of tclkob with either bipolar data or nrz data out of the transmit side formatter. this pin can be programmed to source nrz data via the output data format (ccr1a.6 and ccr1b.6) control bits.
ds2196 14 of 157 signal name: tnega/b / tfsynca/b signal description: transmit negative data & frame sync pulse output signal type: output updated on the rising edge of tclka or tclkb with either bipolar data or a frame sync pulse out of the transmit side formatter. this pin can be programmed to source the frame sync pulse via the output data format (ccr1a.6 and ccr1b.6) control bits. receive framer pins signal name: rchclka/b / rlclka/b signal description: receive channel clock / receive link clock signal type: output a dual function pin depending on the setting of the ccr4a .1 and ccr4b.1 control bits. if rchclk is selected, a 192-khz clock, which pulses high during the lsb of each channel, will be output. if rlclk is selected, either a 4 khz or 2 khz (zbtsi) clock for the rlink data is output. this output signal is always synchronous with rclka or rclkb. signal name: rchblka/b / rlinka/b signal description: receive channel block / receive link data signal type: output a dual function pin depending on the setting of the ccr4a .1 and ccr4b.1 control bits. if rchblk is selected, a user programmable output that can be forced high or lo w during any of the 24 t1 channels. useful for blocking clocks to a serial uart or lapd controller in applications where not all t1 channels are used such as fractional t1, 384 kbps service, 768 kbps, or isdn?pri. also useful for locating individual channels in drop?and?insert applications, for external per?channel loopback, and for per?channel conditioning. see section 21 for details. if rlink is selected, then either fdl data (esf) or fs bits (d4) or z bits (zbtsi) one rclka before the start of a frame are output. see section 21 for details. this signal is always synchron ous with rclka or rclkb. signal name: rsera/b signal description: receive serial data signal type: output received nrz serial data. updated on rising edges of rclka or rclkb. signal name: rfsynca/b signal description: receive frame sync signal type: output an extracted pulse, one rclka or rclkb wide, is outp ut at this pin which identifies frame boundaries. via rcr2a.5 and rcr2b.5, rfsync can also be set to output double?wide pulses on signaling frames. this signal is always synchronous with rclka or rclkb . signal name: rmsynca/b signal description: receive multiframe sync signal type: output an extracted pulse, one rclka or rclkb wide, is output at this pin which identifies multiframe boundaries. this signal is always synchronous with rclka or rclkb.
ds2196 15 of 157 signal name: rlosa/b / lotca/b signal description: receive loss of sync / loss of transmit clock signal type: output a dual function output that is controlled by the ccr3.5 cont rol bit. this pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the tclk pin has not been toggled for 5 sec. signal name: rbpva/b signal description: receive bpv signal type: output this pin will toggle high for one rclka or rclkb clock cycle for each bipolar violation (bpv) detected by the framer. signal name: rposia/b signal description: receive positive data input signal type: input sampled on the falling edge of rclkia and either rising or falling edge of rclkib for data to be clocked through the receive side framer. rposia /b and rnegia/b can be tied together for a nrz interface. rposia be internally connected to rposlo via the ccr4a.2 control bit. signal name: rnegia/b signal description: receive negative data input signal type: input sampled on the falling edge of rclki for data to be cl ocked through the receive side framer. rposia/b and rnegia/b can be tied together for a nrz interface. rnegia be internally c onnected to rneglo via the ccr4a.2 control bit. signal name: rclkia/b signal description: receive clock input signal type: input signal used to clock data through the receive side framers. rclkia can be internally connected to rclklo via the ccr4a.2 control bit. user port pins signal name: uop0/1/2/3 signal description: user output port signal type: output these output port pins can be set low or high via the ccr7b.0 to ccr7b.3 control bits. the pins are forced low on power-up.
ds2196 16 of 157 parallel control port pins signal name: int* signal description: interrupt signal type: output flags host controller during conditions and change of states as defined in the status registers. active low, open drain output. signal name: mux signal description: bus operation signal type: input set low to select non-multiplexed bus operation. set high to select multiplexed bus operation. signal name: d0 to d7 / ad0 to ad7 signal description: data bus or address/data bus signal type: input / output in non-multiplexed bus operation (mux = 0), serves as the data bus. in multiplexed bus operation (mux = 1), serves as a 8?bit multiplexed address / data bus. signal name: a0 to a6 signal description: address bus signal type: input in non-multiplexed bus operation (mux = 0), serves as the address bus. in multiplexed bus operation (mux = 1), these pins are not used and should be tied low. signal name: bts signal description: bus type select signal type: input strap high to select motorola bus timing; strap low to sele ct intel bus timing. this pin controls the function of the rd*(ds*), ale (as), and wr*(r/w*) pins. if bts = 1, then these pins assume the function listed in parenthesis (). signal name: rd* (ds*) signal description: read input (data strobe) signal type: input rd* is an active low signal. ds* polarity is determined by the mux pin setting. refer to section 21 for details. signal name: cs* signal description: chip select signal type: input must be low to read or write to the device. cs* is an active low signal. signal name: ale(as) / a7 signal description: a7 or address latch enable (address strobe) signal type: input in non-multiplexed bus operation (mux = 0), serves as the upper address bit. in multiplexed bus operation (mux = 1), serves to demultiplex the bus on a positive?going edge. signal name: wr*( r/w*) signal description: write input (read/write) signal type: input wr* is an active low signal.
ds2196 17 of 157 signal name: jtclk signal description: jtag ieee 1149.1 test serial clock signal type: input this signal is used to shift data into jtdi on the rising edge and out of jtdo on the falling edge. if not used, this pin should be pulled high. signal name: jtdi signal description: jtag ieee 1149.1 test serial data input signal type: input test instructions and data are clocked into this signal on th e rising edge of jtclk. if not used, this pin should be pulled high. this pin has an internal pull-up. signal name: jtdo signal description: jtag ieee 1149.1 test serial data output signal type: output test instructions are clocked out of this signal on the falling edge of jtclk. if not used, this pin should be left open circuited. signal name: jtrst* signal description: jtag ieee 1149.1 test reset signal type: input this signal is used to synchronously reset the test access port controller. at power up, jtrst must be set low and then high. this action will set the device into the boundary scan bypass mode allowing normal device operation. if boundary scan is not used, this pin should be held low. this pin has an internal pull-up. signal name: jtms signal description: jtag ieee 1149.1 test mode select signal type: input this signal is sampled on the rising edge of jtclk and is used to place the test port into the various defined ieee 1149.1 states. if not used, this pin should be pulled high. this signal has an internal pull-up. line interface pins signal name: mclk signal description: master clock input signal type: input a 1.544 mhz (50 ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data recovery and for jitter attenuation. this clock is also used to source ais within the liu. signal name: rtip & rring signal description: receive tip and ring signal type: input analog inputs for clock recovery circuitry. these pins c onnect via a 1:1 transformer to the t1 line. see section 19 for details. signal name: ttip & tring signal description: transmit tip and ring signal type: output analog line driver outputs. these pins connect via a 1:2 step?up transformer to the t1 line. see section 19 for details. signal name: lfsync signal description: liu frame sync
ds2196 18 of 157 signal type: output this digital output will provide either a frame synchronization pulse or the negative half of a bipolar data stream. the signal is based on what is provided at the tnegli input. signal name: lnrz signal description: liu nrz data signal type: output this digital output will provide either a nrz data stream or the positive half of a bipolar data stream. the signal is based on what is provided at the tposli input. signal name: lclk signal description: liu clock signal type: output this digital output provides the 1.544 mhz transmit liu clock. the signal is based on what is provided at the tclkli input. signal name: tnegli signal description: transmit negative data for the liu signal type: input this digital input is used to pass either the negative half of a bipolar data stream or a frame synchronization pulse via the jitter attenuator block to the transmit line driver block and the lfsync output pin. data input to this pin is sampled on the falling edge of tclkli. tnegli can be internally connected to tnegoa/tfsynca via the ccr4a.2 control bit. signal name: tposli signal description: transmit positive data for the liu signal type: input this digital input is used to pass either the positive half of a bipolar data stream or a nrz data stream via the jitter attenuator block to the transmit line driver block and the lnrz output pin. data input to this pin is sampled on the falling edge of tclkli. tposli can be internally connected to tposoa/tnrza via the ccr4a.2 control bit. signal name: tclkli signal description: transmit clock for the liu signal type: input this digital input is used to pass a 1.544 mhz clock via the jitter attenuator block to the transmit line driver block and the lclk output pin. tclkli can be internal ly connected to tclkoa via the ccr4a.2 control bit. signal name: wnrz signal description: working nrz data signal type: input this digital input is used to pass a nrz data stream via the data source selection mux and the jitter attenuator block to the rposlo and rneg lo output pins. data input to this pin is sampled on the falling or rising edge of wclk. signal name: wclk signal description: working clock signal type: input this digital input is used to pass a 1.544 mhz clock via the data source selection mux and the jitter attenuator block to the rclklo output pin.
ds2196 19 of 157 signal name: pnrz signal description: protect nrz data signal type: input this digital input is used to pass a nrz data stream via the data source selection mux and the jitter attenuator block to the rposlo and rneg lo output pins. data input to this pin is sampled on the falling or rising edge of pclk. signal name: pclk signal description: protect clock signal type: input this digital input is used to pass a 1.544 mhz clock via the data source selection mux and the jitter attenuator block to the rclklo output pin. signal name: rcl signal description: receive carrier loss signal type: output set high when the line interface (liu) detects a carrier loss. signal name: rposlo signal description: receive positive data output from the liu signal type: output updated on the rising edge of rclklo with either bipolar data out of the liu or nrz data from the wnrz or pnrz inputs. signal name: rneglo signal description: receive negative data output from the liu signal type: output updated on the rising edge of rclklo with either bipolar data out of the liu or nrz data from the wnrz or pnrz inputs. signal name: rclko signal description: receive clock output signal type: output either a buffered recovered clock from the t1 line or the clock provided at the wclk or pclk inputs. signal name: wps signal description: working or protect select signal type: input this digital input can be used to select between the wnrz/wclk (working) or pnrz/pclk (protect) data inputs. for this pin to be active the data source mux must be properly configured via the ccr1a.2, ccr1a.3, and ccr1a.4 control bits.
ds2196 20 of 157 supply pins signal name: dvdd signal description: digital positive supply signal type: supply 3.3 volts 5%. should be tied to the rvdd and tvdd pins. signal name: rvdd signal description: receive analog positive supply signal type: supply 3.3 volts 5%. should be tied to the dvdd and tvdd pins. signal name: tvdd signal description: transmit analog positive supply signal type: supply 3.3 volts 5%. should be tied to the rvdd and dvdd pins. signal name: dvss signal description: digital signal ground signal type: supply should be tied to the rvss and tvss pins. signal name: rvss signal description: receive analog signal ground signal type: supply 0.0 volts. should be tied to the dvss and tvss pins. signal name: tvss signal description: transmit analog ground signal type: supply 0.0 volts. should be tied to the dvss and tvss pins.
ds2196 21 of 157 4. register map table 4-1. register map sorted by address address r/w register name register abbreviation 00 r/w hdlc control for framer a hcra 01 r/w hdlc status fr om framer a hsra 02 r/w hdlc interrupt mask for framer a himra 03 r/w receive hdlc information for framer a rhira 04 r/w receive bit oriented code for framer a rboca 05 r receive hdlc fifo from framer a rhfa 06 r/w transmit hdlc information for formatter a thira 07 r/w transmit bit oriented code for formatter a tboca 08 w transmit hdlc fifo for formatter a thfa 09 r/w test 2 for framer a (set to 00h on power-up) ? 0a r/w common control 7 for framer a ccr7a 0b ? reserved (set to 00h on power-up) ? 0c ? reserved (set to 00h on power-up) ? 0d ? reserved (set to 00h on power-up) ? 0e r interrupt status register isr 0f r device id idr 10 r/w receive information 3 from framer a rir3a 11 r/w common control 4 for framer a ccr4a 12 r/w in?band code control for framer a ibcca 13 r/w transmit code definition 1 for framer a tcd1a 14 r/w receive up code definition 1 for framer a rupcd1a 15 r/w receive down code definition 1 for framer a rdncd1a 16 r/w transmit code definition 2 for framer a tcd2a 17 r/w receive up code definition 2 for framer a rupcd2a 18 r/w receive down code definition 2 for framer a rdncd2a 19 r/w common control 5 for framer a ccr5a 1a r transmit ds0 monitor for framer a tds0ma 1b r/w receive spare code definition 1 for framer a rscd1a 1c r/w receive spare code definition 2 for framer a rscd2a 1d r/w receive spare code control for framer a rscca 1e r/w common control 6 for framer a ccr6a 1f r receive ds0 monitor from framer a rds0ma 20 r/w status 1 from framer a sr1a 21 r/w status 2 from framer a sr2a 22 r/w receive information 1 from framer a rir1a 23 r line code violation count 1 from framer a lcvcr1a 24 r line code violation count 2 from framer a lcvcr2a 25 r path code violation count 1 from framer a multiframe out of sync count 1 from framer a pcvcr1a moscr1a 26 r path code violation count 2 from framer a pcvcr2a 27 r multiframe out of sync count 2 from framer a moscr2a 28 r receive fdl register from framer a rfdla 29 r/w receive fdl match 1 for framer a rmtch1a 2a r/w receive fdl match 2 for framer a rmtch2a 2b r/w receive control 1 for framer a rcr1a
ds2196 22 of 157 address r/w register name register abbreviation 2c r/w receive control 2 for framer a rcr2a 2d r/w receive mark 1 for framer a rmr1a 2e r/w receive mark 2 for framer a rmr2a 2f r/w receive mark 3 for framer a rmr3a 30 r/w common control 3 for framer a ccr3a 31 r/w receive information 2 for framer a rir2a 32 r/w transmit channel blocking 1 for formatter a tcbr1a 33 r/w transmit channel blocking 2 for formatter a tcbr2a 34 r/w transmit channel blocking 3 for formatter a tcbr3a 35 r/w transmit control 1 for formatter a tcr1a 36 r/w transmit control 2 for formatter a tcr2a 37 r/w common control 1 for framer a ccr1a 38 r/w common control 2 for framer a ccr2a 39 r/w transmit transparency 1 for formatter a ttr1a 3a r/w transmit transparency 2 for formatter a ttr2a 3b r/w transmit transparency 3 for formatter a ttr3a 3c r/w transmit idle 1 for formatter a tir1a 3d r/w transmit idle 2 for formatter a tir2a 3e r/w transmit idle 3 for formatter a tir3a 3f r/w transmit idle definition for formatter a tidra 40 r/w bert control register 0 bc0 41 r/w bert control register 1 bc1 42 r/w bert control register 2 bc2 43 r bert information register bir 44 r/w bert alternating word count bawc 45 r/w bert repetitive pattern set register 0 brp0 46 r/w bert repetitive pattern set register 1 brp1 47 r/w bert repetitive pattern set register 2 brp2 48 r/w bert repetitive pattern set register 3 brp3 49 r bert bit count register 0 bbc0 4a r bert bit count register 1 bbc1 4b r bert bit count register 2 bbc2 4c r bert bit count register 3 bbc3 4d r bert bit error count register 0 bec0 4e r bert bit error count register 1 bec1 4f r bert bit error count register 2 bec2 50 r/w bert interface control bic 51 ? reserved (set to 00h on power-up) ? 52 ? reserved (set to 00h on power-up) ? 53 ? reserved (set to 00h on power-up) ? 54 ? reserved (set to 00h on power-up) ? 55 ? reserved (set to 00h on power-up) ? 56 ? reserved (set to 00h on power-up) ? 57 ? reserved (set to 00h on power-up) ? 58 ? reserved (set to 00h on power-up) ? 59 ? reserved (set to 00h on power-up) ? 5a ? reserved (set to 00h on power-up) ? 5b ? reserved (set to 00h on power-up) ? 5c ? reserved (set to 00h on power-up) ?
ds2196 23 of 157 address r/w register name register abbreviation 5d ? reserved (set to 00h on power-up) ? 5e r/w liu test register 1 (set to 00h on power-up) ? 5f r/w liu test register 2 (set to 00h on power-up) ? 60 r receive signaling 1 from framer a rs1a 61 r receive signaling 2 from framer a rs2a 62 r receive signaling 3 from framer a rs3a 63 r receive signaling 4 from framer a rs4a 64 r receive signaling 5 from framer a rs5a 65 r receive signaling 6 from framer a rs6a 66 r receive signaling 7 from framer a rs7a 67 r receive signaling 8 from framer a rs8a 68 r receive signaling 9 from framer a rs9a 69 r receive signaling 10 from framer a rs10a 6a r receive signaling 11 from framer a rs11a 6b r receive signaling 12a from framer a rs12a 6c r/w receive channel blocking 1 for framer a rcbr1a 6d r/w receive channel blocking 2 for framer a rcbr2a 6e r/w receive channel blocking 3 for framer a rcbr3a 6f r/w interrupt mask 2 for framer a. imr2a 70 r/w transmit signaling 1 for formatter a ts1a 71 r/w transmit signaling 2 for formatter a ts2a 72 r/w transmit signaling 3 for formatter a ts3a 73 r/w transmit signaling 4 for formatter a ts4a 74 r/w transmit signaling 5 for formatter a ts5a 75 r/w transmit signaling 6 for formatter a ts6a 76 r/w transmit signaling 7 for formatter a ts7a 77 r/w transmit signaling 8 for formatter a ts8a 78 r/w transmit signaling 9 for formatter a ts9a 79 r/w transmit signaling 10 for formatter a ts10a 7a r/w transmit signaling 11 for formatter a ts11a 7b r/w transmit signaling 12 for formatter a ts12a 7c r/w line interface control licr 7d r/w test 1 for framer a (set to 00h on power-up) ? 7e r/w transmit fdl register for formatter a tfdla 7f r/w interrupt mask register 1 for framer a imr1a 80 r/w error rate control for framer a erca 81 w number of errors 1 for framer a noe1a 82 w number of errors 2 for framer a noe2a 83 r number of errors left 1 for framer a noel1a 84 r number of errors left 2 for framer a noel2a 85 r/w error rate control for framer b ercb 86 w number of errors 1 for framer b noe1b 87 w number of errors 2 for framer b noe2b 88 r number of errors left 1 for framer b noel1b 89 r number of errors left 2 for framer b noel2b 8a ? reserved (set to 00h on power-up) ? 8b ? reserved (set to 00h on power-up) ? 8c ? reserved (set to 00h on power-up) ? 8d ? reserved (set to 00h on power-up) ?
ds2196 24 of 157 address r/w register name register abbreviation 8e ? reserved (set to 00h on power-up) ? 8f ? reserved (set to 00h on power-up) ? 90 r/w receive hdlc ds0 control register 1 for framer a rdc1a 91 r/w receive hdlc ds0 control register 2 for framer a rdc2a 92 r/w transmit hdlc ds0 control register 1 for formatter a tdc1a 93 r/w transmit hdlc ds0 control register 2 for formatter a tdc2a 94 r/w receive hdlc ds0 control register 1 for framer b rdc1b 95 r/w receive hdlc ds0 control register 2 for framer b rdc2b 96 r/w transmit hdlc ds0 control register 1 for formatter b tdc1b 97 r/w transmit hdlc ds0 control register 2 for formatter b tdc2b 98 ? reserved (set to 00h on power-up) ? 99 ? reserved (set to 00h on power-up) ? 9a ? reserved (set to 00h on power-up) ? 9b ? reserved (set to 00h on power-up) ? 9c ? reserved (set to 00h on power-up) ? 9d ? reserved (set to 00h on power-up) ? 9e ? reserved (set to 00h on power-up) ? a0 r/w hdlc control for framer b hcrb a1 r/w hdlc status fr om framer b hsrb a2 r/w hdlc interrupt mask for framer b himrb a3 r/w receive hdlc information for framer b rhirb a4 r/w receive bit oriented code for framer b rbocb a5 r receive hdlc fifo from framer b rhfb a6 r/w transmit hdlc information for formatter b thirb a7 r/w transmit bit oriented code for formatter b tbocb a8 w transmit hdlc fifo for formatter b thfb a9 r/w test 2 for framer b (set to 00h on power-up) ? aa r/w common control 7 for framer b ccr7b ab ? reserved (set to 00h on power-up) ? ac ? reserved (set to 00h on power-up) ? ad ? reserved (set to 00h on power-up) ? ae ? reserved (set to 00h on power-up) ? af ? reserved (set to 00h on power-up) ? b0 r/w receive information 3 from framer b rir3b b1 r/w common control 4 for framer b ccr4b b2 r/w in?band code control for framer b ibccb b3 r/w transmit code definition 1 for framer b tcd1b b4 r/w receive up code definition 1 for framer b rupcd1b b5 r/w receive down code definition 1 for framer b rdncd1b b6 r/w transmit code definition 2 for framer b tcd2b b7 r/w receive up code definition 2 for framer b rupcd2b b8 r/w receive down code definition 2 for framer b rdncd2b
ds2196 25 of 157 address r/w register name register abbreviation b9 r/w common control 5 for framer b ccr5b ba r transmit ds0 monitor from formatter b tds0mb bb r/w receive spare code definition 1 for framer b rscd1b bc r/w receive spare code definition 2 for framer b rscd2b bd r/w receive spare code control for framer b rsccb be r/w common control 6 for framer b ccr6b bf r receive ds0 monitor from framer b rds0mb c0 r/w status 1 from framer b sr1b c1 r/w status 2 from framer b sr2b c2 r/w receive information 1 from framer b rir1b c3 r line code violation count 1 from framer b lcvcr1b c4 r line code violation count 2 from framer b lcvcr2b c5 r path code violation count 1 from framer b multiframe out of sync count 1 from framer b pcvcr1b moscr1b c6 r path code violation coun t 2 from framer b pcvcr2b c7 r multiframe out of sync count 2 from framer b moscr2b c8 r receive fdl register from framer b rfdlb c9 r/w receive fdl match 1 for framer b rmtch1b ca r/w receive fdl match 2 for framer b rmtch2b cb r/w receive control 1 for framer b rcr1b cc r/w receive control 2 for framer b rcr2b cd r/w receive mark 1 for framer b rmr1b ce r/w receive mark 2 for framer b rmr2b cf r/w receive mark 3 for framer b rmr3b d0 r/w common control 3 for framer b ccr3b d1 r/w receive information 2 from framer b rir2b d2 r/w transmit channel blocking 1 for formatter b tcbr1b d3 r/w transmit channel blocking 2 for formatter b tcbr2b d4 r/w transmit channel blocking 3 for formatter b tcbr3b d5 r/w transmit control 1 for framer b tcr1b d6 r/w transmit control 2 for framer b tcr2b d7 r/w common control 1 for framer b ccr1b d8 r/w common control 2 for framer b ccr2b d9 r/w transmit transparency 1 for formatter b ttr1b da r/w transmit transparency 2 for formatter b ttr2b db r/w transmit transparency 3 for formatter b ttr3b dc r/w transmit idle 1 for formatter b tir1b dd r/w transmit idle 2 for formatter b tir2b de r/w transmit idle 3 for formatter b tir3b df r/w transmit idle definition for formatter b tidrb e0 r receive signaling 1 from framer b rs1b e1 r receive signaling 2 from framer b rs2b e2 r receive signaling 3 from framer b rs3b e3 r receive signaling 4 from framer b rs4b e4 r receive signaling 5 from framer b rs5b e5 r receive signaling 6 from framer b rs6b e6 r receive signaling 7 from framer b rs7b e7 r receive signaling 8 from framer b rs8b e8 r receive signaling 9 from framer b rs9b
ds2196 26 of 157 address r/w register name register abbreviation e9 r receive signaling 10 from framer b rs10b ea r receive signaling 11 from framer b rs11b eb r receive signaling 12 from framer b rs12b ec r/w receive channel blocking 1 for framer b rcbr1b ed r/w receive channel blocking 2 for framer b rcbr2b ee r/w receive channel blocking 3 for framer b rcbr3b ef r/w interrupt mask 2 for framer b imr2b f0 r/w transmit signaling 1 for formatter b ts1b f1 r/w transmit signaling 2 for formatter b ts2b f2 r/w transmit signaling 3 for formatter b ts3b f3 r/w transmit signaling 4 for formatter b ts4b f4 r/w transmit signaling 5 for formatter b ts5b f5 r/w transmit signaling 6 for formatter b ts6b f6 r/w transmit signaling 7 for formatter b ts7b f7 r/w transmit signaling 8 for formatter b ts8b f8 r/w transmit signaling 9 for formatter b ts9b f9 r/w transmit signaling 10 for formatter b ts10b fa r/w transmit signaling 11 for formatter b ts11b fb r/w transmit signaling 12 for formatter b ts12b fc ? reserved (set to 00h on power-up) ? fd r/w test 1 for framer b (set to 00h on power-up) ? fe r/w transmit fdl register for framer b tfdlb ff r/w interrupt mask register 1 for framer b imr1b note: framer a and b test and reserved registers are used only by the factory; these registers must be cleared (set to all 0?s) on p ower-up initialization to ensure proper operation.
ds2196 27 of 157 5. parallel port the ds2196 is controlled via either a nonmultiplexed (mux = 0) or a multiplexed (mux = 1) bus by an external microcontroller or microprocessor. the ds 2196 can operate with either intel or motorola bus timing configurations. if the bts pin is tied low, intel timing will be selected; if tied high, motorola timing will be selected. all motorola bus signals are listed in parenthesis (). see the timing diagrams in the ac electrical characteristics in section 22 for more details. 6. control, id, and test registers each framer in the ds2196 is configured via a set of eleven control registers. typically, the control registers are only accessed when the system is fi rst powered up. once the ds2196 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. there are two receive control registers (rcr1 and rcr2), two transmit control registers (tcr1 and tcr2), and seven common control registers (ccr1 to ccr7). each of the eleven registers are described in this section. there is a device identif ication register (idr) at address 0fh. the msb of this read?only register is fixed to a 0 indicating that a t1 device is present. the next 3 msbs are used to indicate which t1 device is present. the lower 4 bits of the idr are used to display the die revision of the chip. power-up sequence the ds2196 does not automatically clear its register space on power?up. after the supplies are stable, the register space should be configured for operation by writing to all of the internal registers. this includes setting the test and all unused registers to 00hex. this can be accomplished using a two-pass approach. 1. clear ds2196 register space by writing 00h to the addresses 00h through 0ffh. 2. program required registers to ach ieve desired operating mode. idr: device identi fication register (address = 0f hex) (msb) (lsb) 0011id3id2id1id0 symbol position name and description 0idr.7 chip id bit 3. msb of ds2196 identifica tion code. set to 0. 0idr.6 chip id bit 2. ds2196 identification code. set to 0. 1idr.5 chip id bit 1. ds2196 identification code. set to 1. 1idr.4 chip id bit 0. lsb of ds2196 identification code. set to 1. id3 idr.3 chip revision bit 3. msb of a decimal code that represents the chip revision. id2 idr.1 chip revision bit 2. id1 idr.2 chip revision bit 1. id0 idr.0 chip revision bit 0. lsb of a decimal code that represents the chip revision.
ds2196 28 of 157 the factory in testing the ds2196 uses the two test registers at addresses 09 and 7d hex. on power?up, the test registers should be set to 00 hex in order for the ds2196 to operate properly. rcr1a: receive control register 1 framer a (address = 2b hex) (msb) (lsb) lcvcrf arc oof1 oof2 syncc synct synce resync symbol position name and description lcvcrf rcr1a.7 line code violation count register function select. 0 = do not count excessive 0?s 1 = count excessive 0?s arc rcr1a.6 auto resync criteria. 0 = resync on oof or rcl event 1 = resync on oof only oof1 rcr1a.5 out of frame select 1. 0 = 2/4 frame bits in error 1 = 2/5 frame bits in error oof2 rcr1a.4 out of frame select 2. 0 = follow rcr1.5 1 = 2/6 frame bits in error syncc rcr1a.3 sync criteria. in d4 framing mode. 0 = search for ft pattern, then search for fs pattern 1 = cross couple ft and fs pattern in esf framing mode. 0 = search for fps pattern only 1 = search for fps and verify with crc6 synct rcr1a.2 sync time. 0 = qualify 10 bits 1 = qualify 24 bits synce rcr1a.1 sync enable. 0 = auto resync enabled 1 = auto resync disabled resync rcr1a.0 resync. when toggled from low to high, a resynchronization of the receive side framer is initiated. must be cleared and set again for a subsequent resync.
ds2196 29 of 157 rcr1b: receive control register 1 framer b (address = cb hex) (msb) (lsb) lcvcrf arc oof1 oof2 syncc synct synce resync symbol position name and description lcvcrf rcr1b.7 line code violation count register function select. 0 = do not count excessive 0?s 1 = count excessive 0?s arc rcr1b.6 auto resync criteria. 0 = resync on oof or rcl event 1 = resync on oof only oof1 rcr1b.5 out of frame select 1. 0 = 2/4 frame bits in error 1 = 2/5 frame bits in error oof2 rcr1b.4 out of frame select 2. 0 = follow rcr1.5 1 = 2/6 frame bits in error syncc rcr1b.3 sync criteria. in d4 framing mode. 0 = search for ft pattern, then search for fs pattern 1 = cross couple ft and fs pattern in esf framing mode. 0 = search for fps pattern only 1 = search for fps and verify with crc6 synct rcr1b.2 sync time. 0 = qualify 10 bits 1 = qualify 24 bits synce rcr1b.1 sync enable. 0 = auto resync enabled 1 = auto resync disabled resync rcr1b.0 resync. when toggled from low to high, a resynchronization of the receive side framer is initiated. must be cleared and set again for a subsequent resync.
ds2196 30 of 157 rcr2a: receive control register 2 framer a (address = 2c hex) (msb) (lsb) rcs????rd4ymfsbemoscrf symbol position name and description rcs rcr2a.7 receive code select. see section 11 for more details. 0 = idle code (7f hex) 1 = digital milliwatt code (1e/0b/0b/1e/9e/8b/8b/9e hex) ? rcr2a.6 not assigned. should be set to 0 when written to. ? rcr2a.5 not assigned. should be set to 0 when written to. ? rcr2a.4 not assigned. should be set to 0 when written to. ? rcr2a.3 not assigned. should be set to 0 when written to. rd4ym rcr2a.2 receive side d4 yellow alarm select. 0 = 0s in bit 2 of all channels 1 = a 1 in the s?bit position of frame 12 fsbe rcr2a.1 pcvcr fs?bit error report enable. 0 = do not report bit errors in fs?bit position; only ft bit position 1 = report bit errors in fs?bit position as well as ft bit position moscrf rcr2a.0 multiframe out of sync count register function select. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync
ds2196 31 of 157 rcr2b: receive control register 2 framer b (address = cc hex) (msb) (lsb) rcs????rd4ymfsbemoscrf symbol position name and description rcs rcr2b.7 receive code select. see section 11 for more details. 0 = idle code (7f hex) 1 = digital milliwatt code (1e/0b/0b/1e/9e/8b/8b/9e hex) ? rcr2b.6 not assigned. should be set to 0 when written to. ? rcr2b.5 not assigned. should be set to 0 when written to. ? rcr2b.4 not assigned. should be set to 0 when written to. ? rcr2b.3 not assigned. should be set to 0 when written to. rd4ym rcr2b.2 receive side d4 yellow alarm select. 0 = 0?s in bit 2 of all channels 1 = a 1 in the s?bit position of frame 12 fsbe rcr2b.1 pcvcr fs?bit error report enable. 0 = do not report bit errors in fs?bit position; only ft bit position 1 = report bit errors in fs?bit position as well as ft bit position moscrf rcr2b.0 multiframe out of sync count register function select. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync
ds2196 32 of 157 tcr1a: transmit control register 1 framer a (address = 35 hex) (msb) (lsb) lotcmc tfpt tcpt rbse gb7s tfdls tbl tyel symbol position name and description lotcmc tcr1a.7 loss of transmit clock mux control. determines whether the transmit side of formatter a should switch to mclk if the tclk input should fail to transition (see figure 1.1 for details). 0 = do not switch to mclk if tclka stops 1 = switch to mclk if tclka stops tfpt tcr1a.6 transmit f?bit pass through. (see note below) 0 = f bits sourced internally 1 = f bits sampled at tsera tcpt tcr1a.5 transmit crc pass through. (see note below) 0 = source crc6 bits internally 1 = crc6 bits sampled at tsera during f?bit time rbse tcr1a.4 robbed bit signaling enable. (see note below) 0 = no signaling is inserted in any channel 1 = signaling is inserted in all channels (the ttr registers can be used to block insertion on a channel by channel basis) gb7s tcr1a.3 global bit 7 stuffing. (see note below) 0 = allow the ttr registers to determine which channels containing all 0?s are to be bit 7 stuffed 1 = force bit 7 stuffing in all zero byte channels regardless of how the ttr registers are programmed tfdls tcr1a.2 tfdl register select. (see note below) 0 = source fdl or fs bits from the internal tfdl register (legacy fdl support mode) 1 = source fdl or fs bits from the internal hdlc/boc controller or the tlinka pin tbl tcr1a.1 transmit blue alarm. (see note below) 0 = transmit data normally 1 = transmit an unframed all 1?s code at tposoa and tnegoa tyel tcr1a.0 transmit yellow alarm. (see note below) 0 = do not transmit yellow alarm 1 = transmit yellow alarm note: for a description of how the bits in tcr1a affect the transmit side formatter, see figure 21-7.
ds2196 33 of 157 tcr1b: transmit control register 1 framer b (address = d5 hex) (msb) (lsb) lotcmc tfpt tcpt rbse gb7s tfdls tbl tyel symbol position name and description lotcmc tcr1b.7 loss of transmit clock mux control. determines whether the transmit side of formatter b should switch to mclk if the tclk input should fail to transition (see figure 1.1 for details). 0 = do not switch to mclk if tclkb stops 1 = switch to mclk if tclkb stops tfpt tcr1b.6 transmit f?bit pass through. (see note below) 0 = f bits sourced internally 1 = f bits sampled at tserb tcpt tcr1b.5 transmit crc pass through. (see note below) 0 = source crc6 bits internally 1 = crc6 bits sampled at tserb during f?bit time rbse tcr1b.4 robbed bit signaling enable. (see note below) 0 = no signaling is inserted in any channel 1 = signaling is inserted in all channels (the ttr registers can be used to block insertion on a channel by channel basis) gb7s tcr1b.3 global bit 7 stuffing. (see note below) 0 = allow the ttr registers to determine which channels containing all 0?s are to be bit 7 stuffed 1 = force bit 7 stuffing in all zero byte channels regardless of how the ttr registers are programmed tfdls tcr1b.2 tfdl register select. (see note below) 0 = source fdl or fs bits from the internal tfdl register (legacy fdl support mode) 1 = source fdl or fs bits from the internal hdlc/boc controller or the tlinkb pin tbl tcr1b.1 transmit blue alarm. (see note below) 0 = transmit data normally 1 = transmit an unframed all 1?s code at tposob and tnegob tyel tcr1b.0 transmit yellow alarm. (see note below) 0 = do not transmit yellow alarm 1 = transmit yellow alarm note: for a description of how the bits in tcr1b affect the transmit side formatter, see figure 21-7.
ds2196 34 of 157 tcr2a: transmit control register 2 framer a (address = 36 hex) (msb) (lsb) test1 test0 taism tsdw tsm tsio td4ym tb7zs symbol position name and description test1 tcr2a.7 test mode bit 1 for output pins. see table 6?1. test0 tcr2a.6 test mode bit 0 for output pins. see table 6?1. taism tcr2a.5 transmit ais mode. 0 = normal ais 1 = ais-ci tsdw tcr2a.4 tsynca double?wide. (note: this bit must be set to 0 when tcr2.3=1 or when tcr2.2=0) 0 = do not pulse double?wide in signaling frames 1 = do pulse double?wide in signaling frames tsm tcr2a.3 tsynca mode select. 0 = frame mode (see the timing in section 21) 1 = multiframe mode (see the timing in section 21) tsio tcr2a.2 tsynca i/o select. 0 = tsynca is an input 1 = tsynca is an output td4ym tcr2a.1 transmit side d4 yellow alarm select. 0 = 0?s in bit 2 of all channels 1 = a 1 in the s?bit position of frame 12 tb7zs tcr2a.0 transmit side bit 7 zero suppression enable. 0 = no stuffing occurs 1 = bit 7 force to a 1 in channels with all 0?s
ds2196 35 of 157 tcr2b: transmit control register 2 framer b (address = d6 hex) (msb) (lsb) ? ? taism tsdw tsm tsio td4ym tb7zs symbol position name and description ? tcr2b.7 not assigned. should be set to 0 when written to. ? tcr2b.6 not assigned. should be set to 0 when written to. taism tcr2a.5 transmit ais mode. 0 = normal ais 1 = ais-ci tsdw tcr2b.4 tsyncb double?wide. (note: this bit must be set to 0 when tcr2.3=1 or when tcr2.2=0) 0 = do not pulse double?wide in signaling frames 1 = do pulse double?wide in signaling frames tsm tcr2b.3 tsyncb mode select. 0 = frame mode (see the timing in section 21) 1 = multiframe mode (see the timing in section 21) tsio tcr2b.2 tsyncb i/o select. 0 = tsyncb is an input 1 = tsyncb is an output td4ym tcr2b.1 transmit side d4 yellow alarm select. 0 = zeros in bit 2 of all channels 1 = a 1 in the s?bit position of frame 12 tb7zs tcr2b.0 transmit side bit 7 zero suppression enable. 0 = no stuffing occurs 1 = bit 7 force to a 1 in channels with all 0?s
ds2196 36 of 157 table 6-1: output pin test modes test 1 test 0 effect on output pins 0 0 operate normally 0 1 force all output pins into 3?sta te (including all i/o pins and parallel port pins) 1 0 force all output pins low (includi ng all i/o pins except parallel port pins) 1 1 force all output pins high (incl uding all i/o pins except parallel port pins) ccr1a: common control register 1 framer a (address = 37 hex) (msb) (lsb) traim odf rsao rds2 rds1 rds0 plb flb symbol position name and description traim ccr1a.7 transmit rai mode. only used in esf framing mode. 0 = normal rai 1 = rai-ci odf ccr1a.6 output data format. 0 = bipolar data at tposoa and tnegoa 1 = nrz data at tposoa; tnegoa = tsynca delayed by 10 tclkas rsao ccr1a.5 receive signaling all 1?s. 0 = allow robbed signaling b its to appear at rsera 1 = force all robbed signaling bits at rsera to 1 rds2 ccr1a.4 receive data source bit 2 see table 6?2. rds1 ccr1a.3 receive data source bit 1 see table 6?2. rds0 ccr1a.2 receive data source bit 0 see table 6?2. plb ccr1a.1 payload loopback. 0 = loopback disabled 1 = loopback enabled flb ccr1a.0 framer loopback. 0 = loopback disabled 1 = loopback enabled
ds2196 37 of 157 table 6-2: receive data source mux modes rds2 rds1 rds0 data source 0 0 0 ais generator 0 0 1 line interface unit 0 1 0 pnrz and pclk 0 1 1 wnrz and wclk 1 x x wps pin selects source 0 = source from pnrz/pclk pins 1 = source from wnrz/wclk pins ccr1b: common control register 1 framer b (address = d7 hex) (msb) (lsb) traim odf rsao ? tdss1 tdss0 plb flb symbol position name and description traim ccr1b.7 transmit rai mode. only used in esf framing mode. 0 = normal rai 1 = rai-ci odf ccr1b.6 output data format. 0 = bipolar data at tposob and tnegob 1 = tx nrz data at tposob; tnegob =tfsyncb= tsyncb delayed by 10 tclkbs rsao ccr1b.5 receive signaling all 1?s. 0 = allow robbed signaling b its to appear at rserb 1 = force all robbed signaling bits at rserb to 1 ? ccr1b.4 not assigned. should be set to 0 when written to. tdss1 ccr1b.3 tpos/tneg data source select 1. used to select the data source for the tposob & tn egob pins when framer loopback is active. see table 6-3. tdss0 ccr1b.2 tpos/tneg data source select 0. used to select the data source for the tposob & tn egob pins when framer loopback is active. see table 6-3. plb ccr1b.1 payload loopback. 0 = loopback disabled 1 = loopback enabled flb ccr1b.0 framer loopback. 0 = loopback disabled 1 = loopback enabled
ds2196 38 of 157 table 6-3: tposb/tnegb data source select ttdss1 ttdss0 data source 0 0 pass tpos/tclk/tneg from the framer through to the tposob/tclkob/tnegob pins. 0 1 force tposob to source data from the bert circuit. tnegob is the frame sync pulse. 1 0 force tposob high. tnegob is the frame sync pulse. 1 1 force tposob and tnegob high. payload loopback a payload loopback when ccr1a.1 is set to a 1, the framer/formatter a will be forced into payload loopback (plb). normally, this loopback is only en abled when esf framing is being performed but can be enabled also in d4 framing applications. in a plb situation, the ds2196 will loop the 192 bits of payload data (with bpvs corrected) from the receive section back to the transmit section. the fps framing pattern, crc6 calculation, and the fdl bits are not looped back, they are reinserted by the ds2196. when plb is enabled, the following will occur: 1. the tclkoa signal will become synchronous with rclka instead of tclka. 2. data will be transmitte d from the tring and ttip pins synchronous with rclka instead of tclka. 3. all of the receive side signals will continue to operate normally. 4. the tchclka and tchblka signals are forced low. 5. tx serial data into formatter a is ignored. payload loopback b when ccr1b.1 is set to a 1, the framer/formatter b will be forced into payload loopback (plb). normally, this loopback is only enab led when esf framing is being performed but can be enabled also in d4 framing applications. in a plb situation, th e ds2196 will loop the 192 bits of payload data (with bpvs corrected) from the receive section back to the transmit section. the fps framing pattern, crc6 calculation, and the fdl bits are not looped back, they are reinserted by the ds2196. when plb is enabled, the following will occur: 1. the tclkob signal will become synchronous with rclkib instead of tclkb. 2. data will be transmitted from the tposob and tnegob pins synchronous with rclkib instead of tclkb. 3. all of the receive side signals will continue to operate normally. 4. the tchclkb and tchblkb signals are forced low. 5. tx serial data into formatter b is ignored.
ds2196 39 of 157 framer loopback a when ccr1a.0 is set to a 1, the a framer/formatter will enter a framer loopback (flb) mode. this loopback is useful in testing and debugging appli cations. in flb, the ds2196 will loop data from the transmit side back to the receive side. when flb is enabled, the following will occur: 1. an unframed all 1?s code will be transmitted at tposoa and tnegoa outputs 2. data at rposia and rnegia will be ignored 3. all receive side signals will take on timing sy nchronous with tclkoa instead of rclkia. note: the signals rclka and tclka cannot be the same clock during this loopback because this will cause an unstable condition. framer loopback b when ccr1b.0 is set to a 1, the b framer/formatter will enter a framer loopback (flb) mode. this loopback is useful in testing and debugging appli cations. in flb, the ds2196 will loop data from the transmit side back to the receive side. when flb is enabled, the following will occur: 1. an unframed all 1?s code will be transmitted at tposob and tnegob outputs 2. data at rposib and rnegib will be ignored 3. all receive side signals will take on timing sy nchronous with tclkob instead of rclkib. note: the signals rclkb and tclkb cannot be the same clock during this loopback because this will cause an unstable condition.
ds2196 40 of 157 ccr2a: common control register 2 framer a (address = 38 hex) (msb) (lsb) tfm tb8zs tslc96 tzse rfm rb8zs rslc96 rfdl symbol position name and description tfm ccr2a.7 transmit frame mode select. 0 = d4 framing mode 1 = esf framing mode tb8zs ccr2a.6 transmit b8zs enable. 0 = b8zs disabled 1 = b8zs enabled tslc96 ccr2a.5 transmit slc?96 / fs?bit insertion enable. only set this bit to a 1 in d4 framing applicati ons. must be set to 1 to source the fs pattern. see section 18 for details. 0 = slc?96/fs?bit insertion disabled 1 = slc?96/fs?bit insertion enabled tzse ccr2a.4 transmit fdl zero stuffer enable. set this bit to 0 if using the internal hdlc/boc controller instead of the legacy support for the fdl. see section 18 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled rfm ccr2a.3 receive frame mode select. 0 = d4 framing mode 1 = esf framing mode rb8zs ccr2a.2 receive b8zs enable. 0 = b8zs disabled 1 = b8zs enabled rslc96 ccr2a.1 receive slc?96 enable. only set this bit to a 1 in d4/slc? 96 framing applications. s ee section 18 for details. 0 = slc?96 disabled 1 = slc?96 enabled rfdl ccr2a.0 receive fdl zero destuffer enable. set this bit to 0 if using the internal hdlc/boc controller instead of the legacy support for the fdl. see section 18 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled
ds2196 41 of 157 ccr2b: common control register 2 framer b (address = d8 hex) (msb) (lsb) tfm tb8zs tslc96 tzse rfm rb8zs rslc96 rfdl symbol position name and description tfm ccr2b.7 transmit frame mode select. 0 = d4 framing mode 1 = esf framing mode tb8zs ccr2b.6 transmit b8zs enable. 0 = b8zs disabled 1 = b8zs enabled tslc96 ccr2b.5 transmit slc?96 / fs?bit insertion enable. only set this bit to a 1 in d4 framing applicati ons. must be set to 1 to source the fs pattern. see section 18 for details. 0 = slc?96/fs?bit insertion disabled 1 = slc?96/fs?bit insertion enabled tzse ccr2b.4 transmit fdl zero stuffer enable. set this bit to 0 if using the internal hdlc/boc controller instead of the legacy support for the fdl. see section 18 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled rfm ccr2b.3 receive frame mode select. 0 = d4 framing mode 1 = esf framing mode rb8zs ccr2b.2 receive b8zs enable. 0 = b8zs disabled 1 = b8zs enabled rslc96 ccr2b.1 receive slc?96 enable. only set this bit to a 1 in d4/slc? 96 framing applications. s ee section 18 for details. 0 = slc?96 disabled 1 = slc?96 enabled rfdl ccr2b.0 receive fdl zero destuffer enable. set this bit to 0 if using the internal hdlc/boc controller instead of the legacy support for the fdl. see section 18 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled
ds2196 42 of 157 ccr3a: common control register 3 framer a (address = 30 hex) (msb) (lsb) lidst tclksrc rlos rsms fbct2 ecus tloop fbct1 symbol position name and description lidst ccr3a.7 line interface tx digita l signal tri-state. tri-state control for the liu pins lfsync, lclk and lnrz. 0 = pins not tri-stated 1 = pins tri-stated tclksrc ccr3a.6 transmit clock source select. this function allows the user to internally select mclk as the clock source for the transmit side formatter. 0 = tclk supplied by lotc mux (see tcr1a.7) 1 = use mclk for tclk rlosf ccr3a.5 function of the rlosa/lotca output. 0 = receive loss of sync (rlos) 1 = loss of transmit clock (lotc) rsms ccr3a.4 rmsynca multiframe skip control. useful in framing format conversions from d4 to esf. 0 = rmsynca will output a pulse at every multiframe 1 = rmsynca will output a pulse at every other multiframe fbct2 ccr3a.3 f bit corruption type 2. setting this bit high enables the corruption of one ft (d4 framin g mode) or fps (esf framing mode) bit in every 128 ft or fps bits as long as the bit remains set. ecus ccr3a.2 error counter update select. selects the update rate of the error counters and the period of the one second timer (sr2a.5). see sections 7 & 8 for details. 0 = update error counters once a second 1 = update error counters every 42 ms (333 frames) tloop ccr3a.1 transmit loop code enable. see section 12 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in tcd register fbct1 ccr3a.0 f bit corruption type 1. a low to high transition of this bit causes the next three consecutive ft (d4 framing mode) or fps (esf framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization.
ds2196 43 of 157 ccr3b: common control register 3 framer b (address = d0 hex) (msb) (lsb) ? tclksrc rlos rsms fbct2 ecus tloop fbct1 symbol position name and description ? ccr3b.7 not assigned. should be set to 0 when written to. tclksrc ccr3b.6 transmit clock source select. this function allows the user to internally select mclk as the clock source for the transmit side formatter. 0 = tclk supplied by lotc mux (see tcr1b.7) 1 = use mclk for tclk rlosf ccr3b.5 function of the rlosb/lotcb output. 0 = receive loss of sync (rlos) 1 = loss of transmit clock (lotc) rsms ccr3b.4 rmsync multiframe skip control. useful in framing format conversions from d4 to esf. 0 = rmsyncb will output a pulse at every multiframe 1 = rmsyncb will output a pulse at every other multiframe fbct2 ccr3b.3 f bit corruption type 2. setting this bit high enables the corruption of one ft (d4 framin g mode) or fps (esf framing mode) bit in every 128 ft or fps bits as long as the bit remains set. ecus ccr3b.2 error counter update select. selects the update rate of the error counters and the period of the one second timer (sr2b.5). see sections 7 & 8 for details. 0 = update error counters once a second 1 = update error counters every 42 ms (333 frames) tloop ccr3b.1 transmit loop code enable. see section 12 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in tcd register fbct1 ccr3b.0 f bit corruption type 1. a low to high transition of this bit causes the next three consecutive ft (d4 framing mode) or fps (esf framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization.
ds2196 44 of 157 ccr4a: common control register 4 framer a (address = 11 hex) (msb) (lsb) lclkpol pwclkpol bertmen lnrzais ? lfamc rtdlpm tirfs symbol position name and description lclkpol ccr4a.7 lclk polarity select. 0 = data updated on rising edge. 1 = data updated on falling edge. pwclkpol ccr4a.6 pclk/wclk polarity select. 0 = data sampled on falling edge. 1 = data sampled on rising edge. bertmen ccr4a.5 transmit bert mux enable. 0 = bert mux disabled. 1 = bert mux enabled. lnrzais ccr4a.4 lnrz ais enable. 0 = lnrz and lfsync operate normally. 1 = lnrz =1, lfsync = 0. ? ccr4a.3 not assigned. must be set to 0 when written. lfamc ccr4a.2 liu to framer a mux control. 0 = liu connected on-chip to framer/formatter a. 1 = liu disconnected from framer/formatter a. rtdlpm ccr4a.1 rx/tx data link pin mode. determines the function of the rchclka/rlclka, rchblka/rlinka, tchclka/tlclka and tchblka/tlinka pins. 0 = rchclka, rchblka, tchclka, tchblka. 1 = rlclka, rlinka, tlclka, tlinka. tirfs ccr4a.0 transmit idle registers (tir) function select. see section 11 for timing details. 0 = tirs define in which ch annels to insert idle code 1 = tirs define in which channe ls to insert data from rsera (i.e., per channel loopback function)
ds2196 45 of 157 ccr4b: common control register 4 framer b (address = b1 hex) (msb) (lsb) rclkipol tclkopol bertmen ? ? fafbmc rtdlpm tirfs symbol position name and description rclkipol ccr4b.7 rclkib polarity select. 0 = no inversion. 1 = invert. tclkopol ccr4b.6 tclkob polarity select. 0 = no inversion. 1 = invert. bertmen ccr4b.5 transmit bert mux enable. 0 = bert mux disabled. 1 = bert mux enabled. ? ccr4b.4 not assigned. must be set to 0 when written. ? ccr4b.3 not assigned. must be set to 0 when written. fafbmc ccr4b.2 framer/formatter a to framer/formatter b mux control. 0 = framer/formatter a connected on-chip to framer/formatter b 1 = framer/formatter a disconnected from framer/formatter b rtdlpm ccr4b.1 rx/tx data link pin mode. determines the function of the rchclkb/rlclkb, rchblkb/rlinkb, tchclkb/tlclkb and tchblkb/tlinkb pins. 0 = rchclkb, rchblkb, tchclkb, tchblkb 1 = rlclkb, rlinkb, tlclkb, tlinkb tirfs ccr4b.0 transmit idle registers (tir) function select. see section 11 for timing details. 0 = tirs define in which ch annels to insert idle code 1 = tirs define in which channe ls to insert data from rserb (i.e., per = channel loopback function)
ds2196 46 of 157 ccr5a: common control register 5 framer a (address = 19 hex) (msb) (lsb) tjc llb liais tcm4 tcm3 tcm2 tcm1 tcm0 symbol position name and description tjc ccr5a.7 transmit japanese crc6 enable. 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jt?g704 crc6 calculation llb ccr5a.6 local loopback. 0 = loopback disabled 1 = loopback enabled liais ccr5a.5 line interface ais generation enable. see figure 1?1 for details. ais generati on is based on mclk. 0 = allow normal data from tposia/tnegia to be transmitted at ttip and tring 1 = force unframed all 1?s to be transmitted at ttip and tring tcm4 ccr5a.4 transmit channel monitor bit 4. msb of a channel decode that determines which transmit channel data will appear in the tds0m register. see section 10 for details. tcm3 ccr5a.3 transmit channel monitor bit 3. tcm2 ccr5a.2 transmit channel monitor bit 2. tcm1 ccr5a.1 transmit channel monitor bit 1. tcm0 ccr5a.0 transmit channel monitor bit 0. lsb of the channel decode.
ds2196 47 of 157 ccr5b: common control register 5 framer b (address = b9 hex) (msb) (lsb) tjc ? ? tcm4 tcm3 tcm2 tcm1 tcm0 symbol position name and description tjc ccr5b.7 transmit japanese crc6 enable. 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jt?g704 crc6 calculation ? ccr5b.6 not assigned. must be set to 0 when written. ? ccr5b.5 not assigned. must be set to 0 when written. tcm4 ccr5b.4 transmit channel monitor bit 4. msb of a channel decode that determines which transmit channel data will appear in the tds0m register. see section 10 for details. tcm3 ccr5b.3 transmit channel monitor bit 3. tcm2 ccr5b.2 transmit channel monitor bit 2. tcm1 ccr5b.1 transmit channel monitor bit 1. tcm0 ccr5b.0 transmit channel monitor bit 0. lsb of the channel decode. ccr6a: common control register 6 framer a (address = 1e hex) (msb) (lsb) rjc eams mecu rcm4 rcm3 rcm2 rcm1 rcm0 symbol position name and description rjc ccr6a.7 receive japanese crc6 enable. 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jt?g704 crc6 calculation eams ccr6a.6 error accumulation mode select. 0 = ccr3a.2 determines accumulation time 1 = ccr6a.5 determines accumulation time mecu ccr6a.5 manual error counter update. when enabled by ccr6a.6, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. the user must wait a minimum of 972 ns (1.5 clock periods) before reading the error count registers to allow for proper update. rcm4 ccr6a.4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data will appear in the rds0m register. see section 10 for details. rcm3 ccr6a.3 receive channel monitor bit 3. rcm2 ccr6a.2 receive channel monitor bit 2. rcm1 ccr6a.1 receive channel monitor bit 1. rcm0 ccr6a.0 receive channel monitor bit 0 . lsb of the channel decode. ccr6b: common control register 6 framer b (address = be hex)
ds2196 48 of 157 (msb) (lsb) rjc eams mecu rcm4 rcm3 rcm2 rcm1 rcm0 symbol position name and description rjc ccr6b.7 receive japanese crc6 enable. 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jt?g704 crc6 calculation eams ccr6b.6 error accumulation mode select. 0 = ccr3b.2 determines accumulation time 1 = ccr6b.5 determines accumulation time mecu ccr6b.5 manual error counter update. when enabled by ccr6b.6, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. the user must wait a minimum of 972 ns (1.5 clock periods) before reading the error count registers to allow for proper update. rcm4 ccr6b.4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data will appear in the rds0m register. see section 10 for details. rcm3 ccr6b.3 receive channel monitor bit 3. rcm2 ccr6b.2 receive channel monitor bit 2. rcm1 ccr6b.1 receive channel monitor bit 1. rcm0 ccr6b.0 receive channel monitor bit 0 . lsb of the channel decode.
ds2196 49 of 157 ccr7a: common control register 7 framer a (address = 0a hex) (msb) (lsb) lirst rlb ais13-24 ais1-12 disrcl ? ? lbos3 symbol position name and description lirst ccr7a.7 line interface reset. setting this bit from a 0 to a 1 will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. normally this bit is only toggled on power?up. must be cleared and set again for a subsequent reset. rlb ccr7a.6 remote loopback. 0 = loopback disabled 1 = loopback enabled ais13-24 ccr7a.5 channels 13 ? 24 ais enable 0 = do not transmit ais in channels 13 ? 24 1 = transmit ais in channels 13 - 24 ais1-12 ccr7a.4 channels 1 ? 12 ais enable 0 = do not transmit ais in channels 1 ? 12 1 = transmit ais in channels 1 - 12 disrcl ccr7a.3 liu receive carrier loss (rcl) pin disable. 0 = normal operation. 1 = disable the liu rcl pin. pin will always output a ?0?. the lrcl status bit in rir3a.3 continues to report correct lrcl status. ? ccr7a.2 not assigned. should be set to 0 when written to. ? ccr7a.1 not assigned. should be set to 0 when written to. lbos3 ccr7a.0 line build out select bit 3. sets the transmitter build out; see the table 19?1
ds2196 50 of 157 ccr7b: common control register 7 framer b (address = aa hex) (msb) (lsb) ? belb ais13-24 ais1-12 uop3 uop2 uop1 uop0 symbol position name and description ? ccr7b.7 not assigned. should be set to 0 when written to. belb ccr7b.6 back end loopback. 0 = loopback disabled 1 = loopback enabled ais13-24 ccr7b.5 channels 13 ? 24 ais enable 0 = do not transmit ais in channels 13 ? 24 1 = transmit ais in channels 13 - 24 ais1-12 ccr7b.4 channels 1 ? 12 ais enable 0 = do not transmit ais in channels 1 ? 12 1 = transmit ais in channels 1 - 12 uop3 ccr7b.3 user defined output pin 3. 0 = logic 0 level at pin 1 = logic 1 level at pin uop2 ccr7b.2 user defined output pin 2. 0 = logic 0 level at pin 1 = logic 1 level at pin uop1 ccr7b.1 user defined output pin 1. 0 = logic 0 level at pin 1 = logic 1 level at pin uop0 ccr7b.0 user defined output pin 0. 0 = logic 0 level at pin 1 = logic 1 level at pin remote loopback when ccr7a.6 is set to a 1, the 2196 will be forced into remote loopback (rlb). in this loopback, data input via the rposi and rnegi pins will be transmitted back to the tposo and tnego pins. data will continue to pass through the receive side of framer a as it would normally and the data from the transmit side of formatter a will be ignor ed. please see figure 1?1 for more details. back end loopback when ccr7b.6 is set to a 1, the 2196 will be forced into back end loopback (belb). in this loopback, data input via the rposib and rnegib pins w ill be transmitted back to the tposob and tnegob pins. data will continue to pass through the receive side of framer b as it would normally and the data from the transmit side of forma tter b will be ignored. please see figure 1?1 for more details. power?up sequence on power?up, after the supplies are stable, the ds2196 should be configured for operation by writing to all of the internal registers (this includes setting the test registers to 00hex) since the contents of the internal registers cannot be predicted on power?up.
ds2196 51 of 157 7. status and information registers found in each framer/formatter is a set of nine registers that contai n information on the current real time status of the ds2196, status register 1 (sr1), status register 2 (sr2), receive information registers 1 to 3 (rir1/rir2/rir3) and a set of four regist ers for the onboard hdlc and boc controller for the fdl. bert generator and receiver status is contai ned in the bert information register (bir). the specific details on the registers pertaining to the be rt and fdl functions are covered in section 15 and 18 but they operate the same as the other status re gisters in the ds2196 and this operation is described below. when a particular event has occurred (or is occurring), the appropriate bit in 1 of these nine registers will be set to a 1. all of the bits in sr1, sr2, rir1, ri r2, and rir3 registers operate in a latched fashion. this means that if an event or an alarm occurs and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. the bit will be clea red when it is read and it will not be set again until the event has occurred again (or in the case of the rbl, ryel, lrcl or frcl, and rlos alarms, the bit will remain set if the alarm is still present). there are bits in the four fdl status registers that are not latched and these bits are listed in section 18. the user will always precede a read of any of the nine registers with a write. the byte written to the register will inform the ds2196 which bits the user wi shes to read and have cleared. the user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. when a 1 is written to a bit location, the read register will be updated with the latest in formation. when a 0 is written to a bit position, the read register will not be updated and the previous value w ill be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte that was just written a nd this value should be written back into the same register to insure that bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. this write?read? write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in th e register. this operation is key in controlling the ds2196 with higher?order software languages. the sr1, sr2, hsr and bir registers have the unique ability to initiate a hardware interrupt via the int output pin. each of the alarms and events in the sr1, sr2, hsr and bir can be either masked or unmasked from the interrupt pin via the interrupt mask register 1 (imr1), interrupt mask register 2 (imr2), hdlc interrupt mask register (himr) and bert control register (bc1) respectively. the bc1 register is covered in section 15. th e himr register is covered in section 18. the interrupts caused by alarms in sr1 (namely ryel, lrcl or rcl, rbl, and rlos) act differently than the interrupts caused by events in sr1 and sr2 (namely lup, ldn, lspare, lotc, rmf, tmf, sec, rfdl, tfdl, rmtch, raf, and lorc) and fimr. the alarm caused interrupts will force the int pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in table 7?2). the int pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that cause d the interrupt to occur even if the alarm is still present. the event caused interrupts will force the int pin low when the event occurs. the int pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. isr: interrupt status register (address = 0e hex)
ds2196 52 of 157 (msb) (lsb) ? birq fdlsb sr2b sr1b fdlsa sr2a sr1a symbol position name and description ?isr.7 not assigned. could be any value when read. birq isr.6 bert interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. fdlsb isr.5 framer b fdls interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. sr2b isr.4 framer b sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. sr1b isr.3 framer b sr1 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. fdlsa isr.2 framer a fdls interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. sr2a isr.1 framer a sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. sr1a isr.0 framer a sr1 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending.
ds2196 53 of 157 rir1a: receive information re gister 1 framer a (address = 22 hex) (msb) (lsb) cofa 8zd 16zd ? ? sefe b8zs fbe symbol position name and description cofa rir1a.7 change of frame alignment . set when the last resync resulted in a change of frame or multiframe alignment. 8zd rir1a.6 eight zero detect. set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at rposia and rnegia. 16zd rir1a.5 sixteen zero detect. set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at rposia and rnegia. ? rir1a.4 not assigned. could be any value when read. ? rir1a.3 not assigned. could be any value when read. sefe rir1a.2 severely errored framing event. set when 2 out of 6 framing bits (ft or fps) are received in error. b8zs rir1a.1 b8zs code word detect. set when a b8zs code word is detected at rposia and rnegia independent of whether the b8zs mode is selected or not via ccr2.6. useful for automatically setting the line coding. fbe rir1a.0 frame bit error. set when a ft (d4) or fps (esf) framing bit is received in error.
ds2196 54 of 157 rir1b: receive information register 1 framer b (address = c2 hex) (msb) (lsb) cofa 8zd 16zd ? ? sefe b8zs fbe symbol position name and description cofa rir1b.7 change of frame alignment . set when the last resync resulted in a change of frame or multiframe alignment. 8zd rir1b.6 eight zero detect. set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at rposib and rnegib. 16zd rir1b.5 sixteen zero detect. set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at rposib and rnegib. ? rir1b.4 not assigned. could be any value when read. ? rir1b.3 not assigned. could be any value when read. sefe rir1b.2 severely errored framing event. set when 2 out of 6 framing bits (ft or fps) are received in error. b8zs rir1b.1 b8zs code word detect. set when a b8zs code word is detected at rposib and rnegib independent of whether the b8zs mode is selected or not via ccr2.6. useful for automatically setting the line coding. fbe rir1b.0 frame bit error. set when a ft (d4) or fps (esf) framing bit is received in error.
ds2196 55 of 157 rir2a: receive information re gister 2 framer a (address = 31 hex) (msb) (lsb) rlosc lrclc frclc ? ? rblc ? ? symbol position name and description rlosc rir2a.7 receive loss of sync clear. set when the framer achieves synchronization; will remain set until read. lrclc rir2a.6 line interface receive carrier loss clear. set when the carrier signal is restored; will remain set until read. see table 7?2. frclc rir2a.5 framer receive carrier loss clear. set when the carrier signal is restored; will remain set until read. see table 7?2. ? rir2a.4 not assigned. could be any value when read. ? rir2a.3 not assigned. could be any value when read. rblc rir2a.2 receive blue alarm clear. set when the blue alarm (ais) is no longer detected; will remain set until read. see table 7?2. ? rir2a.1 not assigned. could be any value when read. ? rir2a.0 not assigned. could be any value when read. rir2b: receive information register 2 framer b (address = d1 hex) (msb) (lsb) rlosc frclc ? ? ? rblc ? ? symbol position name and description rlosc rir2b.7 receive loss of sync clear. set when the framer achieves synchronization; will remain set until read. ? rir2b.6 not assigned. could be any value when read. frclc rir2b.5 framer receive carrier loss clear. set when the carrier signal is restored; will remain set until read. see table 7?2. ? rir2b.4 not assigned. could be any value when read. ? rir2b.3 not assigned. could be any value when read. rblc rir2b.2 receive blue alarm clear. set when the blue alarm (ais) is no longer detected; will remain set until read. see table 7?2. ? rir2b.1 not assigned. could be any value when read. ? rir2b.0 not assigned. could be any value when read.
ds2196 56 of 157 rir3a: receive information re gister 3 framer a (address = 10 hex) (msb) (lsb) rl1 rl0 jalt lorc lrcl ? ? rais-ci symbol position name and description rl1 rir3a.7 receive level bit 1. see table 7?1. rl0 rir3a.6 receive level bit 0. see table 7?1. jalt rir3a.5 jitter attenuator limit trip. set when the jitter attenuator fifo reaches to within 4 bits of its limit; useful for debugging jitter attenuation operation. lorc rir3a.4 loss of receive clock. set when the rclkia pin has not transitioned for at least 2 s (3 s 1 s). lrcl rir3a.3 line interface receive carrier loss. set when 192 consecutive zeros have been received at the rring and rtip pins; allowed to be cleared wh en 14 or more 1?s out of 112 possible bit positions are received. ? rir3a.2 not assigned. could be any value when read. ? rir3a.1 not assigned. could be any value when read. rais-ci rir3a.0 receive ais-ci detect. set when the ais-ci pattern is detected. (see note below) rir3b: receive information register 3 framer b (address = b0 hex) (msb) (lsb) ???lorc???rais-ci symbol position name and description ? rir3b.7 not assigned. could be any value when read. ? rir3b.6 not assigned. could be any value when read. ? rir3b.5 not assigned. could be any value when read. lorc rir3b.4 loss of receive clock. set when the rclkib pin has not transitioned for at least 2 s(3 s 1 s). ? rir3b.3 not assigned. could be any value when read. ? rir3b.2 not assigned. could be any value when read. ? rir3b.1 not assigned. could be any value when read. rais-ci rir3a.0 receive ais-ci detect. set when the ais-ci pattern is detected. (see note below)
ds2196 57 of 157 table 7-1: receive t1 level indication rl1 rl0 typical level received 0 0 +2 db to ?7.5 db 0 1 ?7.5 db to ?15 db 1 0 ?15 db to ?22.5 db 1 1 less than ?22.5 db note: the rais-ci bit is qualified with the rbl status bit (sr1a.3 and sr1b.3). hence the rais-ci status bit will not be set unless the rbl status bit is set. if the rbl bit is set and the rais-ci bit has transitioned from a 1 to a 0 (i.e., it has cleared), it is recommended that the software wait at lest 1.5 seconds and then read the rais-ci bit again to make sure that the alarm has indeed cleared. sr1a: status register 1 framer a (address = 20 hex) (msb) (lsb) lup ldn lotc lspare rbl ryel frcl rlos symbol position name and description lup sr1a.7 loop up code detected. set when the loop up code as defined in the rupcd register is being received. see section 12 for details. ldn sr1a.6 loop down code detected. set when the loop down code as defined in the rdncd register is being received. see section 12 for details. lotc sr1a.5 loss of transmit clock. set when the tclka pin has not transitioned for one channel time (or 5.2 s). will force the rlosa/lotca pin high if enabled via ccr1a.6. also will force transmit side formatter to switch to mclk if so enabled via tcr1a.7. lspare sr1a.4 spare code detected. set when the spare code as defined in the rspare register is bein g received. see section 12 for details. rbl sr1a.3 receive blue alarm. set when an unframed all 1?s code is received at rposia and rnegia. ryel sr1a.2 receive yellow alarm. set when a yellow alarm is received at rposia and rnegia. frcl sr1a.1 framer receive carrier loss. set when a red alarm is received at rposia and rnegia. rlos sr1a.0 receive loss of sync. set when the device is not synchronized to the receive t1 stream.
ds2196 58 of 157 sr1b: status register 1 framer b (address = c0 hex) (msb) (lsb) lup ldn lotc lspare rbl ryel frcl rlos symbol position name and description lup sr1b.7 loop up code detected. set when the loop up code as defined in the rupcd register is being received. see section 12 for details. ldn sr1b.6 loop down code detected. set when the loop down code as defined in the rdncd register is being received. see section 12 for details. lotc sr1b.5 loss of transmit clock. set when the tclkb pin has not transitioned for one channel time (or 5.2 s). will force the rlosb/lotcb pin high if enabled via ccr1b.6. also will force transmit side formatter to switch to mclk if so enabled via tcr1b.7. lspare sr1b.4 spare code detected. set when the spare code as defined in the rspare register is being received. see section 12 for details. rbl sr1b.3 receive blue alarm. set when an unframed all 1?s code is received at rposib and rnegib. ryel sr1b.2 receive yellow alarm. set when a yellow alarm is received at rposib and rnegib. frcl sr1b.1 framer receive carrier loss. set when a red alarm is received at rposib and rnegib. rlos sr1b.0 receive loss of sync. set when the device is not synchronized to the receive t1 stream.
ds2196 59 of 157 table 7-2: alarm criteria alarm set criteria clear criteria blue alarm (ais) (see note 1 below) when over a 3 ms window, 5 or less zeros are received when over a 3 ms window, 6 or more zeros are received yellow alarm (rai) 1. d4 bit 2 mode(rcr2.2=0) 2. d4 12th f?bit mode (rcr2.2=1; this mode is also referred to as the ?japanese yellow alarm?) 3. esf mode when bit 2 of 256 consecutive channels is set to 0 for at least 254 occurrences when the 12th framing bit is set to ?1? for two consecutive occurrences when 16 consecutive patterns of 00ff appear in the fdl when bit 2 of 256 consecutive channels is set to 0 for less than 254 occurrences when the 12th framing bit is set to 0 for two consecutive occurrences when 14 or less patterns of 00ff hex out of 16 possible appear in the fdl red alarm (lrcl or rcl) (this alarm is also referred to as loss of signal) when 192 consecutive 0?s are received when 14 or more 1?s out of 112 possible bit positions are received starting with the first 1 received notes: 1. the definition of blue alarm (or alarm indication si gnal) is an unframed all 1?ss signal. blue alarm detectors should be able to operate properly in th e presence of a 10e?3 error rate and they should not falsely trigger on a framed all 1?ss signal. the blue alarm criteria in the ds2196 have been set to achieve this performance. it is recommended that the rbl bit be qualified with the rlos bit. 2. ansi specifications use a differ ent nomenclature than the ds2196 does; the following terms are equivalent: rbl = ais lrcl = los rlos = lof ryel = rai
ds2196 60 of 157 sr2a: status register 2 framer a (address = 21 hex) (msb) (lsb) rmf tmf sec rfdl tfdl rmtch raf ? symbol position name and description rmf sr2a.7 receive multiframe. set on receive multiframe boundaries. tmf sr2a.6 transmit multiframe. set on transmit multiframe boundaries. sec sr2a.5 one second timer. set on increments of one second based on rclk; will be set in increm ents of 999 ms, 999 ms, and 1002 ms every 3 seconds. set on incr ements of 42 ms (333 frames) if ccr3a.2 = 1. rfdl sr2a.4 receive fdl buffer full. set when the receive fdl buffer (rfdl) fills to capacity (8 bits). tfdl sr2a.3 transmit fdl buffer empty. set when the transmit fdl buffer (tfdl) empties. rmtch sr2a.2 receive fdl match occurrence. set when the rfdl matches either rmtch1a or rmtch2a. raf sr2a.1 receive fdl abort. set when eight consecutive 1?s?s are received in the fdl. ?sr2a.0 not assigned. could be any value when read. sr2b: status register 2 framer b (address = c1 hex) (msb) (lsb) rmf tmf sec rfdl tfdl rmtch raf ? symbol position name and description rmf sr2b.7 receive multiframe. set on receive multiframe boundaries. tmf sr2b.6 transmit multiframe. set on transmit multiframe boundaries. sec sr2b.5 one second timer. set on increments of one second based on rclk; will be set in increm ents of 999 ms, 999 ms, and 1002 ms every 3 seconds. set on incr ements of 42 ms (333 frames) if ccr3b.2 = 1. rfdl sr2b.4 receive fdl buffer full. set when the receive fdl buffer (rfdl) fills to capacity (8 bits). tfdl sr2b.3 transmit fdl buffer empty. set when the transmit fdl buffer (tfdl) empties. rmtch sr2b.2 receive fdl match occurrence. set when the rfdl matches either rmtch1b or rmtch2b. raf sr2b.1 receive fdl abort. set when eight consecutive 1?s?s are received in the fdl. ?sr2b.0 not assigned. could be any value when read.
ds2196 61 of 157 imr1a: interrupt mask register 1 framer a (address = 7f hex) (msb) (lsb) lup ldn lotc lspare rbl ryel frcl rlos symbol position name and description lup imr1a.7 loop up code detected. 0 = interrupt masked 1 = interrupt enabled ldn imr1a.6 loop down code detected. 0 = interrupt masked 1 = interrupt enabled lotc imr1a.5 loss of transmit clock. 0 = interrupt masked 1 = interrupt enabled lspare imr1a.4 spare code detected. 0 = interrupt masked 1 = interrupt enabled rbl imr1a.3 receive blue alarm. 0 = interrupt masked 1 = interrupt enabled rye imr1a.2 receive yellow alarm. 0 = interrupt masked 1 = interrupt enabled frcl imr1a.1 framer receive carrier loss. 0 = interrupt masked 1 = interrupt enabled rlos imr1a.0 receive loss of sync. 0 = interrupt masked 1 = interrupt enabled
ds2196 62 of 157 imr1b: interrupt mask register 1 framer b (address = ff hex) (msb) (lsb) lup ldn lotc lspare rbl ryel frcl rlos symbol position name and description lup imr1b.7 loop up code detected. 0 = interrupt masked 1 = interrupt enabled ldn imr1b.6 loop down code detected. 0 = interrupt masked 1 = interrupt enabled lotc imr1b.5 loss of transmit clock. 0 = interrupt masked 1 = interrupt enabled lspare imr1a.4 spare code detected. 0 = interrupt masked 1 = interrupt enabled rbl imr1b.3 receive blue alarm. 0 = interrupt masked 1 = interrupt enabled rye imr1b.2 receive yellow alarm. 0 = interrupt masked 1 = interrupt enabled frcl imr1b.1 framer receive carrier loss. 0 = interrupt masked 1 = interrupt enabled rlos imr1b.0 receive loss of sync. 0 = interrupt masked 1 = interrupt enabled
ds2196 63 of 157 imr2a: interrupt mask register 2 framer a (address = 6f hex) (msb) (lsb) rmf tmf sec rfdl tfdl rmtch raf ? symbol position name and description rmf imr2a.7 receive multiframe. 0 = interrupt masked 1 = interrupt enabled tmf imr2a.6 transmit multiframe. 0 = interrupt masked 1 = interrupt enabled sec imr2a.5 one second timer. 0 = interrupt masked 1 = interrupt enabled rfdl imr2a.4 receive fdl buffer full. 0 = interrupt masked 1 = interrupt enabled tfdl imr2a.3 transmit fdl buffer empty. 0 = interrupt masked 1 = interrupt enabled rmtch imr2a.2 receive fdl match occurrence. 0 = interrupt masked 1 = interrupt enabled raf imr2a.1 receive fdl abort. 0 = interrupt masked 1 = interrupt enabled ? imr2a.0 not assigned. should be set to 0 when written to.
ds2196 64 of 157 imr2b: interrupt mask register 2 framer b (address = ef hex) (msb) (lsb) rmf tmf sec rfdl tfdl rmtch raf ? symbol position name and description rmf imr2b.7 receive multiframe. 0 = interrupt masked 1 = interrupt enabled tmf imr2b.6 transmit multiframe. 0 = interrupt masked 1 = interrupt enabled sec imr2b.5 one second timer. 0 = interrupt masked 1 = interrupt enabled rfdl imr2b.4 receive fdl buffer full. 0 = interrupt masked 1 = interrupt enabled tfdl imr2b.3 transmit fdl buffer empty. 0 = interrupt masked 1 = interrupt enabled rmtch imr2b.2 receive fdl match occurrence. 0 = interrupt masked 1 = interrupt enabled raf imr2b.1 receive fdl abort. 0 = interrupt masked 1 = interrupt enabled ?imr2b.0 not assigned. should be set to 0 when written to. 8. error count registers there is a set of three counters per framer that record bipolar violations, excessive zeros, errors in the crc6 code words, framing bit errors, and number of multiframes that the device is out of receive synchronization. each of these three counters can be automatically update d on either one second boundaries (ccr3.2=0) or every 42 ms (ccr3.2=1) as determined by the timer in status register 2 (sr2.5) or manually (ccr6.6=1 and triggering w ith ccr6.5). when updated automatically, the user can use the interrupt from the one-second timer to determin e when to read these registers. the user has a full second (or 42 ms) to read the counters before the data is lost. all three count ers will saturate at their respective maximum counts and they will not rollover ( note: only the line code violation count register has the potential to over-flow but the bit error would have to exceed 10e-2 before this would occur).
ds2196 65 of 157 line code violation count register (lcvcr) line code violation count register 1 (lcvcr1) is the most significant word and lcvcr2 is the least significant word of a 16?bit counter that records c ode violations (cvs). cvs are defined as bipolar violations (bpvs) or excessive zeros. see table 8- 1 for details of exactly what the lcvcrs count. if the b8zs mode is set for the receive side via ccr2.2, then b8zs code words are not counted. this counter is always enabled; it is not disabled durin g receive loss of synchronization (rlos=1) conditions. lcvcr1a: line code violation count register 1 framer a (address = 23 hex) lcvcr2a: line code violation count register 2 framer a (address = 24 hex) lcvcr1b: line code violatio n count register 1 framer b (address = c3 hex) lcvcr2b: line code violatio n count register 2 framer b (address = c4 hex) (msb) (lsb) lcv15 lcv14 lcv13 lcv12 lcv11 lcv10 lcv9 lcv8 lcvcr1 lcv7 lcv6 lcv5 lcv4 lcv3 lcv2 lcv1 lcv0 lcvcr2 symbol position name and description lcv15 lcvcr1.7 msb of the 16?bit code violation count lcv0 lcvcr2.0 lsb of the 16?bit code violation count
ds2196 66 of 157 table 8-1: line code violation counting arrangements count excessive zeros (rcr1.7) b8zs enabled (ccr2.2) what is counted in the lcvcrs no no bpvs yes no bpvs + 16 consecutive zeros no yes bpvs (b8zs code words not counted) yes yes bpv?s + 8 consecutive zeros path code violation count register (pcvcr) when the receive side of a framer is set to operate in the esf framing mode (ccr2.3=1), pcvcr will automatically be set as a 12?bit counter that will record errors in the crc6 code words. when set to operate in the d4 framing mode (ccr2.3=0), pcvcr will automatically count errors in the ft framing bit position. via the rcr2.1 bit, a framer can be programmed to also report errors in the fs framin g bit position. the pcvcr will be disabled during receive loss of synchronization (rlos= 1) conditions. see table 8-2 for a detailed description of exactly what errors the pcvcr counts. pcvcr1a: path violation count register 1 framer a (address = 25 hex) pcvcr2a: path violation count register 2 framer a (address = 26 hex) pcvcr1b: path violation count register 1 framer b (address = c5 hex) pcvcr2b: path violation count register 2 framer b (address = c6 hex) (msb) (lsb) (note 1) (note 1) (note 1) (note 1) crc/ fb11 crc/ fb10 crc/ fb9 crc/ fb8 pcvcr1 crc/ fb7 crc/ fb6 crc/ fb5 crc/ fb4 crc/ fb3 crc/ fb2 crc/ fb1 crc/ fb0 pcvcr2 symbol position name and description crc/fb11 pcvcr1.3 msb of the 12?bit crc6 error or frame bit error count (note #2) crc/fb0 pcvcr2.0 lsb of the 12?bit crc6 error or frame bit error count (note #2) notes: 1. the upper nibble of the counter at address 25 is us ed by the multiframes out of sync count register 2. pcvcr counts either errors in crc code words (in the esf framing mode; ccr2.3=1) or errors in the framing bit position (in the d4 framing mode; ccr2.3=0).
ds2196 67 of 157 table 8-2: path code violation counting arrangements framing mode (ccr2.3) count fs errors? (rcr2.1) what is counted in the pcvcrs d4 no errors in the ft pattern d4 yes errors in both the ft & fs patterns esf don?t care errors in the crc6 code words multiframes out of sync count register (moscr) normally the moscr is used to count the number of multiframes that the receive synchronizer is out of sync (rcr2.0=1). this number is us eful in esf applications needing to measure the parameters loss of frame count (lofc) and esf error events as described in at&t publication tr54016. when the moscr is operated in this mode, it is not disabl ed during receive loss of synchronization (rlos=1) conditions. the moscr has alternate operating mode whereby it will count either errors in the ft framing pattern (in the d4 mode) or errors in the fps framing pattern (in the esf mode). when the moscr is operated in this mode, it is disabled during receive loss of synchronization (rlos = 1) conditions. see table 8-3 for a detailed descrip tion of what the moscr is capable of counting. moscr1a: multiframes out of sync count register 1 framer a (address = 25 hex) moscr2a: multiframes out of sync count register 2 framer a (address = 27 hex) moscr1b: multiframes out of sync count register 1 framer b (address = c5 hex) moscr2b: multiframes out of sync count register 2 framer b (address = c7 hex) (msb) (lsb) mos/ fb11 mos/ fb10 mos/ fb9 mos/ fb8 (note 1) (note 1) (note 1) (note 1) moscr1 mos/ fb7 mos/ fb6 mos/ fb5 mos/ fb4 mos/ fb3 mos/ fb2 mos/ fb1 mos/ fb0 moscr2 symbol position name and description mos/fb11 moscr1.7 msb of the 12?bit multiframes out of sync or f?bit error count (note #2) mos/fb0 moscr2.0 lsb of the 12?bit multiframes out of sync or f?bit error count (note #2) notes: 1. the lower nibble of the counter at address 25 is used by the path code violation count register 2. moscr counts either errors in framing bit position (rcr2.0=0) or the number of multiframes out of sync (rcr2.0=1) table 8-3: multiframes out of sync counting arrangements
ds2196 68 of 157 framing mode (ccr2.3) count mos or f?bit errors (rcr2.0) what is counted in the moscrs d4 mos number of multiframes out of sync d4 f?bit errors in the ft pattern esf mos number of multiframes out of sync esf f?bit errors in the fps pattern 9. signaling operation the robbed?bit signaling bits embedded in the t1 stre am can be extracted from the receive stream and inserted into the transmit stream by each framer. there is a set of 12 registers for the receive side (rs1 to rs12) and 12 registers on the transmit side (ts1 to ts12). the signaling registers are detailed below. the ccr1.5 bit is used to control the robbed signaling bits as they appear at rser. if ccr1.5 is set to 0, then the robbed signaling bits will appear at the rs er pin in their proper position as they are received. if ccr1.5 is set to a 1, then the robbed signalin g bit positions will be forced to a 1 at rser. rs1a to rs12a: receive signaling registers framer a (address = 60 to 6b hex) rs1b to rs12b: receive signaling registers framer b (address = e0 to eb hex) (msb) (lsb) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) rs1 a(16) a(15) a(14) a(13) a(12) a(11) a(10) a(9) rs2 a(24) a(23) a(22) a(21) a(20) a(19) a(18) a(17) rs3 b(8) b(7) b(6) b(5) b(4) b(3) b(2) b(1) rs4 b(16) b(15) b(14) b(13) b(12) b(11) b(10) b(9) rs5 b(24) b(23) b(22) b(21) b(20) b(19) b(18) b(17) rs6 a/c(8) a/c(7) a/c(6) a/c(5) a/c(4) a/c(3) a/c(2) a/c(1) rs7 a/c(16) a/c(15) a/c(14) a/c(13) a/ c(12) a/c(11) a/c(10) a/c(9) rs8 a/c(24) a/c(23) a/c(22) a/c(21) a/ c(20) a/c(19) a/c(18) a/c(17) rs9 b/d(8) b/d(7) b/d(6) b/d(5) b/d(4) b/d(3) b/d(2) b/d(1) rs10 b/d(16) b/d(15) b/d(14) b/d(13) b/d(12) b/d(11) b/d(10) b/d(9) rs11 b/d(24) b/d(23) b/d(22) b/d(21) b/d(20) b/d(19) b/d(18) b/d(17) rs12 symbol position name and description d(24) rs12.7 signaling bit d in channel 24 a(1) rs1.0 signaling bit a in channel 1
ds2196 69 of 157 each receive signaling register (rs1 to rs12) reports the incoming robbed bit signaling from eight ds0 channels. in the esf framing mode, there can be up to four signaling bits per channel (a, b, c, and d). in the d4 framing mode, there are only two framing bits per channel (a and b). in the d4 framing mode, the framer will replace the c and d signaling bit positions with the a and b signaling bits from the previous multiframe. hence, whether the framer is operated in either framing mode, the user needs only to retrieve the signaling bits every 3 ms. the b its in the receive signaling registers are updated on multiframe boundaries so the user can utilize the r eceive multiframe interrupt in the receive status register 2 (sr2.7) to know when to retrieve the signaling bits. the receive signaling registers are frozen and not updated during a loss of sync condition (sr1.0=1). th ey will contain the most recent signaling information before the ?oof? occurred. the signaling data reported in rs1 to rs12 is also available at the rser pin. ts1a to ts12a: transmit si gnaling registers framer a (address = 70 to 7b hex) ts1b to ts12b: transmit si gnaling registers framer b (address = f0 to fb hex) (msb) (lsb) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) ts1 a(16) a(15) a(14) a(13) a(12) a(11) a(10) a(9) ts2 a(24) a(23) a(22) a(21) a(20) a(19) a(18) a(17) ts3 b(8) b(7) b(6) b(5) b(4) b(3) b(2) b(1) ts4 b(16) b(15) b(14) b(13) b(12) b(11) b(10) b(9) ts5 b(24) b(23) b(22) b(21) b(20) b(19) b(18) b(17) ts6 a/c(8) a/c(7) a/c(6) a/c(5) a/ c(4) a/c(3) a/c(2) a/c(1) ts7 a/c(16) a/c(15) a/c(14) a/c(13) a/ c(12) a/c(11) a/c(10) a/c(9) ts8 a/c(24) a/c(23) a/c(22) a/c(21) a/ c(20) a/c(19) a/c(18) a/c(17) ts9 b/d(8) b/d(7) b/d(6) b/d(5) b/d(4) b/d(3) b/d(2) b/d(1) ts10 b/d(16) b/d(15) b/d(14) b/d(13) b/d(12) b/d(11) b/d(10) b/d(9) ts11 b/d(24) b/d(23) b/d(22) b/d(21) b/d(20) b/d(19) b/d(18) b/d(17) ts12 symbol position name and description d(24) ts12.7 signaling bit d in channel 24 a(1) ts1.0 signaling bit a in channel 1 each transmit signaling register (ts1 to ts12) contains the robbed bit signaling for eight ds0 channels that will be inserted into the outgoing st ream if enabled to do so via tcr1.4. in the esf framing mode, there can be up to four signaling b its per channel (a, b, c, and d). on multiframe boundaries, the framer will load the values present in the transmit signaling register into an outgoing signaling shift register that is internal to the device. the user can utilize the transmit multiframe interrupt in status register 2 (sr2.6) to know when to update the signaling bits. in the esf framing mode, the interrupt will come every 3 ms and the us er has a full 3ms to update the tsrs. in the d4 framing mode, there are only two framing bits per cha nnel (a and b). however in the d4 framing mode, the framer uses the c and d bit positions as the a and b bit positions for the next multiframe. the framer will load the values in the tsrs into the outgoing shift register every other d4 multiframe.
ds2196 70 of 157 10. ds0 monitoring function each framer in the ds2196 has the ability to monito r one ds0 64 kbps channel in the transmit direction and one ds0 channel in the receive direction at the same time. in the transmit direction the user will determine which channel is to be monitored by properly setting the tcm0 to tcm4 bits in the ccr5a & ccr5b registers. in the receive direction, the rcm0 to rcm4 bits in the ccr6a & ccr6b registers need to be properly set. the ds0 channel pointed to by the tcm0 to tcm4 bits will appear in the transmit ds0 monitor (tds0m) register and the ds0 channel pointed to by the rcm0 to rcm4 bits will appear in the receive ds0 (rds0m) register. the tcm4 to tcm0 and rcm4 to rcm0 bits should be programmed with the decimal dec ode of the appropriate t1 channe l. channels 1 through 24 map to register values 0 through 23. for example, if ds0 channel 6 in the transmit direction and ds0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into ccr5 and ccr6: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0 ccr5a: common control register 5 framer a (address = 19 hex) ccr5b: common control register 5 framer b (address = b9 hex) [repeated here from section 6 for convenien ce with only the tx monitor function present] (msb) (lsb) tcm4 tcm3 tcm2 tcm1 tcm0 symbol position name and description tcm4 ccr5.4 transmit channel monitor bit 4. msb of a channel decode that determines which transmit channel data will appear in the tds0m register. tcm3 ccr5.3 transmit channel monitor bit 3. tcm2 ccr5.2 transmit channel monitor bit 2. tcm1 ccr5.1 transmit channel monitor bit 1. tcm0 ccr5.0 transmit channel monitor bit 0. lsb of the channel decode.
ds2196 71 of 157 tds0ma: transmit ds0 monitor register framer a (address = 1a hex) tds0mb: transmit ds0 monitor register framer b (address = ba hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbol position name and description b1 tds0m.7 transmit ds0 channel bit 1. msb of the ds0 channel (first bit to be transmitted). b2 tds0m.6 transmit ds0 channel bit 2. b3 tds0m.5 transmit ds0 channel bit 3. b4 tds0m.4 transmit ds0 channel bit 4. b5 tds0m.3 transmit ds0 channel bit 5. b6 tds0m.2 transmit ds0 channel bit 6. b7 tds0m.1 transmit ds0 channel bit 7. b8 tds0m.0 transmit ds0 channel bit 8. lsb of the ds0 channel (last bit to be transmitted). ccr6a: common control register 6 framer a (address = 1e hex) ccr6b: common control register 6 framer b (address = be hex) [repeated here from section 6 for convenien ce with only the rx monitor function present] (msb) (lsb) rcm4 rcm3 rcm2 rcm1 rcm0 symbol position name and description rcm4 ccr5.4 receive channel monitor bit 4. msb of a channel decode that determines which receive ds0 channel data will appear in the rds0m register. rcm3 ccr5.3 receive channel monitor bit 3. rcm2 ccr5.2 receive channel monitor bit 2. rcm1 ccr5.1 receive channel monitor bit 1 . rcm0 ccr5.0 receive channel monitor bit 0. lsb of the channel decode that determines which receive ds0 channel data will appear in the rds0m register.
ds2196 72 of 157 rds0ma: receive ds0 monitor register framer a (address = 1f hex) rds0mb: receive ds0 monitor register framer b (address = bf hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbol position name and description b1 rds0m.7 receive ds0 channel bit 1. msb of the ds0 channel (first bit to be received). b2 rds0m.6 receive ds0 channel bit 2. b3 rds0m.5 receive ds0 channel bit 3. b4 rds0m.4 receive ds0 channel bit 4. b5 rds0m.3 receive ds0 channel bit 5. b6 rds0m.2 receive ds0 channel bit 6. b7 rds0m.1 receive ds0 channel bit 7. b8 rds0m.0 receive ds0 channel bit 8. lsb of the ds0 channel (last bit to be received). 11. per?channel code (idle) generation and loopback the ds2196 can replace data on a channel?by?channel basis in both the transmit and receive directions. the transmit direction is from the backplane to the t1 line and is covered in section 11.1. the receive direction is from the t1 line to the ba ckplane and is covered in section 11.2. 11.1 transmit side code generation the transmit idle registers (tir1/2/3) are used to determine which of the 24 t1 channels should be overwritten with the code placed in the transmit id le definition register (t idr). this method allows the same 8?bit code to be placed into any of the 24 t1 channels. if this method is used, then the ccr4.0 control bit must be set to 0. each of the bit position in the transmit idle registers (tir1/tir2/tir3) represent a ds0 channel in the outgoing frame. when these bits are set to a 1, the corresponding channel will transmit the idle code contained in the transmit idle definition register (tidr). bit 7 stuffing will occur over the programmed idle code unless the ds0 channel is made transparent by the transmit transparency registers. the transmit idle registers (tirs) have an alternate function that allows them to define a per?channel loopback (pclb). if the tirfs control bit (ccr4.0) is set to 1, then the tirs will determine which channels (if any) from the backplan e should be replaced with the data from the receive side or in other words, off of the t1 line. if this mode is enable d, then transmit and receive clocks and frame syncs must be synchronized. one method to accomplish this would be to tie rclk to tclk and rsync to tsync.
ds2196 73 of 157 tir1a/tir2a/tir3a: transmit idle registers framer a (address = 3c to 3e hex) tir1b/tir2b/tir3b: transmit idle registers framer b (address = dc to de hex) [also used for per?channel loopback] (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tir1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tir2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tir3 symbols positions name and description ch1-24 tir1.0-3.7 transmit idle code in sertion control bits. 0 = do not insert the idle code in the tidr into this channel 1 = insert the idle code in the tidr into this channel note: if ccr4.0=1, then a 0 in the tirs implies that channe l data is to be sourced from tser and a 1 implies that channel data is to be sourced from the output of the receive side framer (i.e., per?channel loopback; see figure 1?1). tidra: transmit idle definition register framer a (address = 3f hex) tidrb: transmit idle definition register framer b (address = df hex) (msb) (lsb) tidr7 tidr6 tidr5 tidr4 tidr3 tidr2 tidr1 tidr0 symbol position name and description tidr7 tidr.7 msb of the idle code (this bit is transmitted first) tidr0 tidr.0 lsb of the idle code (this bit is transmitted last) 11.2 receive side code generation the receive mark registers (rmr1/ 2/3) are used to determine which of the 24 t1 channels should be overwritten with either a 7fh idle code or with a digital milliwatt pattern. the rcr2.7 bit will determine which code is used. the digital milliwatt code is an eight-byte repeating pattern that represents a 1 khz sine wave (1e/0b/0b/1e/9e/8b/8b/9e). each bit in th e rmrs, represents a particular channel. if a bit is set to a 1, then the receive data in that channel will be replaced with one of the two codes. if a bit is set to 0, no replacement occurs.
ds2196 74 of 157 rmr1a/rmr2a/rmr3a: receive mark registers framer a (address = 2d to 2f hex) rmr1b/rmr2b/rmr3b: receive mark registers framer b (address = cd to cf hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rmr1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rmr2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rmr3 symbols positions name and description ch1-24 rmr1.0-3.7 receive channel mark control bits 0 =do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with either the idle code or the digital milliwatt code (depends on the rcr2.7 bit) 12. programmable in?band code generation and detection each framer in the ds2196 has the ability to generate a nd detect a repeating bit pattern that is from one to 8 bits and 16 bits in length. to transmit a pattern, the user will load the pattern to be sent into the transmit code definition (tcd1&tcd2) registers and select the proper length of the pattern by setting the tc0 and tc1 bits in the in?band code control (ibcc) register. when generating a 1, 2, 4, 8 or 16 bit pattern both transmit code definition registers (tcd1&tcd2) must be filled with the proper code. generation of a 3, 5, 6 and 7 bit pattern only requires tcd1 to be filled. once this is accomplished, the pattern will be transmitted as long as the tloop cont rol bit (ccr3.1) is enabled. normally (unless the transmit formatter is programmed to not insert the f?bit position) the framer will overwrite the repeating pattern once every 193 bits to allow the f?bit position to be sent. see figure 21-7 for more details. as an example, if the user wished to transmit the sta ndard ?loop up? code for cha nnel service units which is a repeating pattern of ...10000100001... then 80h would be lo aded into tcd1 and the length would set to 5 bits. each framer can detect three separate repeating patterns. typically, two of the detectors are used for ?loop up? and ?loop down? code detection. the user will program the codes to be detected in the receive up code defin ition (rupcd1 & rupcd2) registers and the receive down code definition (rdncd1 & rdncd2) registers and th e length of each pattern will be selected via the ibcc register. there is a third detector (spare) and it is de fined and controlled via the rscd1/rscd2 and rscc registers. when detecting an 8 or 16 bit pattern bot h receive code definition re gisters must be filled with the proper code. for 8 bit patterns both receive code definition registers will be filled with the same value. detection of a 1, 2, 3, 4, 5, 6 and 7 bit pattern only requires the first receive code definition register to be filled. a third or spare detector is available for user defin ition. the framer will detect repeating pattern codes in both fram ed and unframed circumstances with bit error rates as high as 10e?2. the detectors are capable of handling both f-bit inserted and f-bit overwrite patterns. writing the least significant byte of receive code definition register re sets the integration period for that detector. the code detector has a nominal integration period of 30 ms. hence, after about 30 ms of receiving a valid code, the proper status bit (lup at sr1a/b.7 , ldn at sr 1a/b.6 and lspare at sr1a/b.4 ) will be set to a 1. normally codes are sent for a period of 5 seconds . it is recommend that the software poll the framer every 50 ms to 1000 ms until 5 seconds has elapsed to insure that the code is continuously present. ibcca: in?band code control register framer a (address = 12 hex)
ds2196 75 of 157 ibccb: in?band code control register framer b (address = b2 hex) (msb) (lsb) tc1 tc0 rup2 rup1 rup0 rdn2 rdn1 rdn0 symbol position name and description tc1 ibcc.7 transmit code length definition bit 1. see table 12?1 tc0 ibcc.6 transmit code length definition bit 0. see table 12?1 rup2 ibcc.5 receive up code length definition bit 2. see table 12?2 rup1 ibcc.4 receive up code length definition bit 1. see table 12?2 rup0 ibcc.3 receive up code length definition bit 0. see table 12?2 rdn2 ibcc.2 receive down code length definition bit 2. see table 12-2 rdn1 ibcc.1 receive down code length definition bit 1. see table 12-2 rdn0 ibcc.0 receive down code length definition bit 0. see table 12-2 table 12-1: transmit code length tc1 tc0 length selected 0 0 5 bits 0 1 6 bits / 3 bits 1 0 7 bits 1 1 16 bits / 8 bits / 4 bits / 2 bits / 1 bit table 12-2: receive code length rup2/ rdn2/rsc2 rup1/ rdn1/rsc1 rup0/ rdn0/rsc0 length selected 0 0 0 1 bits 0 0 1 2 bits 0 1 0 3 bits 0 1 1 4 bits 1 0 0 5 bits 1 0 1 6 bits 1 1 0 7 bits 1 1 1 8 / 16 bits
ds2196 76 of 157 tcd1a: transmit code definition register 1 framer a (address = 13 hex) tcd1b: transmit code definition register 1 framer b (address = b3 hex) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 tcd1.7 transmit code definition bit 7. first bit of the repeating pattern. c6 tcd1.6 transmit code definition bit 6. c5 tcd1.5 transmit code definition bit 5. c4 tcd1.4 transmit code definition bit 4. c3 tcd1.3 transmit code definition bit 3. c2 tcd1.2 transmit code definition bit 2. a don?t care if a 5-bit length is selected. c1 tcd1.1 transmit code definition bit 1. a don?t care if a 5 or 6 bit length is selected. c0 tcd1.0 transmit code definition bit 0. a don?t care if a 5, 6 or 7 bit length is selected.
ds2196 77 of 157 tcd2a: transmit code definition register 2 framer a (address = 16 hex) tcd2b: transmit code definition register 2 framer b (address = b6 hex) least significant byte of 16 bit codes (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 tcd2.7 transmit code definition bit 7. a don?t care if a 5, 6 or 7 bit length is selected. c6 tcd2.6 transmit code definition bit 6. a don?t care if a 5, 6 or 7 bit length is selected. c5 tcd2.5 transmit code definition bit 5. a don?t care if a 5, 6 or 7 bit length is selected. c4 tcd2.4 transmit code definition bit 4. a don?t care if a 5, 6 or 7 bit length is selected. c3 tcd2.3 transmit code definition bit 3. a don?t care if a 5, 6 or 7 bit length is selected. c2 tcd2.2 transmit code definition bit 2. a don?t care if a 5, 6 or 7 bit length is selected. c1 tcd2.1 transmit code definition bit 1. a don?t care if a 5, 6 or 7 bit length is selected. c0 tcd2.0 transmit code definition bit 0. a don?t care if a 5, 6 or 7 bit length is selected.
ds2196 78 of 157 rupcd1a: receive up code definition register 1 framer a (address = 14 hex) rupcd1b: receive up code definition register 1 framer b (address = b4 hex) note: writing this register resets the detector?s integration period. (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 rupcd1.7 receive up code definition bit 7. first bit of the repeating pattern. c6 rupcd1.6 receive up code definition bit 6. a don?t care if a 1 bit length is selected. c5 rupcd1.5 receive up code definition bit 5. a don?t care if a 1 or 2 bit length is selected. c4 rupcd1.4 receive up code definition bit 4. a don?t care if a 1 to 3 bit length is selected. c3 rupcd1.3 receive up code definition bit 3. a don?t care if a 1 to 4 bit length is selected. c2 rupcd1.2 receive up code definition bit 2. a don?t care if a 1 to 5 bit length is selected. c1 rupcd1.1 receive up code definition bit 1. a don?t care if a 1 to 6 bit length is selected. c0 rupcd1.0 receive up code definition bit 0. a don?t care if a 1 to 7 bit length is selected.
ds2196 79 of 157 rupcd2a: receive up code definition register 2 framer a (address = 17 hex) rupcd2b: receive up code definition register 2 framer b (address = b7 hex) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 rupcd2.7 receive up code definition bit 7. a don?t care if a 1 to 7 bit length is selected. c6 rupcd2.6 receive up code definition bit 6. a don?t care if a 1 to 7 bit length is selected. c5 rupcd2.5 receive up code definition bit 5. a don?t care if a 1 to 7 bit length is selected. c4 rupcd2.4 receive up code definition bit 4. a don?t care if a 1 to 7 bit length is selected. c3 rupcd2.3 receive up code definition bit 3. a don?t care if a 1 to 7 bit length is selected. c2 rupcd2.2 receive up code definition bit 2. a don?t care if a 1 to 7 bit length is selected. c1 rupcd2.1 receive up code definition bit 1. a don?t care if a 1 to 7 bit length is selected. c0 rupcd2.0 receive up code definition bit 0. a don?t care if a 1 to 7 bit length is selected.
ds2196 80 of 157 rdncd1a: receive down code defi nition register 1 framer a (address = 15 hex) rdncd1b: receive down code defi nition register 1 framer b (address = b5 hex) note: writing this register resets the detector?s integration period. (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 rdncd1.7 receive down code definition bit 7. first bit of the repeating pattern. c6 rdncd1.6 receive down code definition bit 6. a don?t care if a 1 bit length is selected. c5 rdncd1.5 receive down code definition bit 5. a don?t care if a 1 or 2 bit length is selected. c4 rdncd1.4 receive down code definition bit 4. a don?t care if a 1 to 3 bit length is selected. c3 rdncd1.3 receive down code definition bit 3. a don?t care if a 1 to 4 bit length is selected. c2 rdncd1.2 receive down code definition bit 2. a don?t care if a 1 to 5 bit length is selected. c1 rdncd1.1 receive down code definition bit 1. a don?t care if a 1 to 6 bit length is selected. c0 rdncd1.0 receive down code definition bit 0. a don?t care if a 1 to 7 bit length is selected.
ds2196 81 of 157 rdncd2a: receive down code defi nition register 2 framer a (address = 18 hex) rdncd2b: receive down code defi nition register 2 framer b (address = b8 hex) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 rdncd2.7 receive down code definition bit 7. a don?t care if a 1 to 7 bit length is selected. c6 rdncd2.6 receive down code definition bit 6. a don?t care if a 1 to 7 bit length is selected. c5 rdncd2.5 receive down code definition bit 5. a don?t care if a 1 to 7 bit length is selected. c4 rdncd2.4 receive down code definition bit 4. a don?t care if a 1 to 7 bit length is selected. c3 rdncd2.3 receive down code definition bit 3. a don?t care if a 1 to 7 bit length is selected. c2 rdncd2.2 receive down code definition bit 2. a don?t care if a 1 to 7 bit length is selected. c1 rdncd2.1 receive down code definition bit 1. a don?t care if a 1 to 7 bit length is selected. c0 rdncd2.0 receive down code definition bit 0. a don?t care if a 1 to 7 bit length is selected. rscca: in?band receive spare control register framer a (address = 1d hex) rsccb: in?band receive spare control register framer b (address = bd hex) (msb) (lsb) ?????rsc2rsc1rsc0 symbol position name and description ? rscc.7 not assigned. should be set to 0 when written to. ? rscc.6 not assigned. should be set to 0 when written to. ? rscc.5 not assigned. should be set to 0 when written to. ? rscc.4 not assigned. should be set to 0 when written to. ? rscc.3 not assigned. should be set to 0 when written to. rsc2 rscc.2 receive spare code length definition bit 2. see table 12?2 rsc1 rscc.1 receive spare code length definition bit 1. see table 12?2 rsc0 rscc.0 receive spare code length definition bit 0. see table 12?2
ds2196 82 of 157 rscd1a: receive spare code definition register 1 framer a (address = 1b hex) rscd1b: receive spare code defi nition register 1 framer b (address = bb hex) note: writing this register resets the detector?s integration period. (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 rscd1.7 receive spare code definition bit 7. first bit of the repeating pattern. c6 rscd1.6 receive spare code definition bit 6. a don?t care if a 1-bit length is selected. c5 rscd1.5 receive spare code definition bit 5. a don?t care if a 1 or 2 bit length is selected. c4 rscd1.4 receive spare code definition bit 4. a don?t care if a 1 to 3 bit length is selected. c3 rscd1.3 receive spare code definition bit 3. a don?t care if a 1 to 4 bit length is selected. c2 rscd1.2 receive spare code definition bit 2. a don?t care if a 1 to 5 bit length is selected. c1 rscd1.1 receive spare code definition bit 1. a don?t care if a 1 to 6 bit length is selected. c0 rscd1.0 receive spare code definition bit 0. a don?t care if a 1 to 7 bit length is selected.
ds2196 83 of 157 rscd2a: receive spare code definition register 2 framer a (address = 1c hex) rscd2b: receive spare code defi nition register 2 framer b (address = bc hex) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position name and description c7 rscd2.7 receive spare code definition bit 7. a don?t care if a 1 to 7 bit length is selected. c6 rscd2.6 receive spare code definition bit 6. a don?t care if a 1 to 7 bit length is selected. c5 rscd2.5 receive spare code definition bit 5. a don?t care if a 1 to 7 bit length is selected. c4 rscd2.4 receive spare code definition bit 4. a don?t care if a 1 to 7 bit length is selected. c3 rscd2.3 receive spare code definition bit 3. a don?t care if a 1 to 7 bit length is selected. c2 rscd2.2 receive spare code definition bit 2. a don?t care if a 1 to 7 bit length is selected. c1 rscd2.1 receive spare code definition bit 1. a don?t care if a 1 to 7 bit length is selected. c0 rscd2.0 receive spare code definition bit 0. a don?t care if a 1 to 7 bit length is selected. 13. clock blocking registers the receive channel blocking registers (rcbr1 /rcbr2/rcbr3) and the transmit channel blocking registers (tcbr1/tcbr2/tcbr3) control the rchblk and tchblk pins respectively. the rchblk and tchblk pins are user programmable outputs that can be forced either high or low during individual channels. these outputs can be used to block clocks to a uart or lapd controller in fractional t1 or isdn?pri applications. when the appropriate bits are set to a 1, the rchblk and tchblk pins will be held high during the en tire corresponding channel time. see the timing in section 21 for an example.
ds2196 84 of 157 rcbr1a/rcbr2a/rcbr3a: receive channel blocking registers framer a (address = 6c to 6e hex) rcbr1b/rcbr2b/rcbr3b: receive ch annel blocking registers framer b (address = ec to ee hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rcbr1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rcbr2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rcbr3 symbols positions name and description ch1-24 rcbr1.0-3.7 receive channel blocking control bits. 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time tcbr1a/tcbr2a/tcbr3a: transmit channel blocking registers framer a (address = 32 to 34 hex) tcbr1b/tcbr2b/tcbr3b: transmit channel blocking registers framer b (address = d2 to d4 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tcbr1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tcbr2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tcbr3 symbols positions name and description ch1-24 tcbr1.0-3.7 transmit channel blocking control bits. 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time
ds2196 85 of 157 14. transmit transparency each of the 24 t1 channels in the transmit direction of the framer can be either forced to be transparent or in other words, can be forced to stop bit 7 stuffing from overwriting the data in the channels. transparency can be invoked on a channel by ch annel basis by properly setting the ttr1, ttr2, and ttr3 registers. each of the bit position in the transmit transparency registers (ttr1/ttr2/ttr3) represent a ds0 channel in the outgoing frame. when these bits ar e set to a 1, the corresponding channel is transparent (or clear). if a ds0 is programmed to be clear, no bit 7 stuffing will be performed. however, in the d4 framing mode, bit 2 will be overwritten by a zero when a yellow alarm is transmitted. also the user has the option to prevent the ttr registers from determining which channels are to have bit 7 stuffing performed. if the tcr2.0 and tcr1.3 bits are set to 1, then all 24 t1 channels will have bit 7 stuffing performed on them regardless of how the ttr regist ers are programmed. please see figure 21-7 for more details. ttr1a/ttr2a/ttr3a: transmit transparency register framer a (address = 39 to 3b hex) ttr1b/ttr2b/ttr3b: transmit transparency register framer b (address = d9 to db hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ttr1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ttr2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 ttr3 symbols positions name and description ch1-24 ttr1.0-3.7 transmit transparency registers. 0 = this ds0 channel is not transparent 1 = this ds0 channel is transparent
ds2196 86 of 157 15. bert function the bert block can generate and detect both pseudor andom and repeating bit pa tterns and it is used to test and stress data communication links. the bert block is capable of generatin g and detected the following patterns: the pseudorandom patterns 2e7, 2e11, 2e15, and qrss a repetitive pattern from 1 to 32 bits in length alternating (16-bit) words wh ich flip every 1 to 256 words daly pattern the bert receiver has a 32-bit bit counter and a 24- bit error counter. the bert receiver will report three events, a change in receive synchronizer status, a bit error being detected, and if either the bit counter or the error counter overflows. each of th ese events can be masked within the bert function via the bert control register 1 (bc1). if the software detects that the bert has reported an event has occurred, then the software must read the bert information register (bir) to determine which event(s) has occurred. to activate the bert block, the host must configure the bert mux via the bic register (see figure 15-1). the bert interrupt request (birq) status bit loca ted at isr.6 will be set to a 1 if there is a major change of state in the bert receiver. a major change of state is defined as either a change in the receive synchronization (i.e. the bert has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the bit counter or the error counter. the host must read the status bits of the bert in the bert in formation register (bir) to determine the change of state. the birq bit will be cleared when read and will not be set again until the bert has experienced another change of state.
ds2196 87 of 157 formatter a/b select mux mux clock data fsync tchblk clock normal transmit data transmit formatter a clock data fsync tchblk clock data clock clock tchblk fsync formatter / flb b select mux transmit load signal generation note 1 note 2 transmit side receive side frame sync align toggle (bic.3) flb b bert select (decoded from ccr1b.2 & ccr1b.3) framed / unframed select (bic.2) use tchblk select (bic.1) formatter a/b select (bic.0) formatter a formatter b framer a clock data rchblk fsync framer b clock data rchblk fsync framer a/b select mux framed / unframed select (bic.6) use rchblk select (bic.5) framer a/b select (bic.4) note 1 note 2 bert_mux bert clock data clock data transmit load clock rchblk fsync data note 1: always includes a clock pulse for the f-bit position note 2: f-bit clock is blocked in the framed mode flb b mux tpos/tnrz tclk tneg/ tfsync thru mode bert mode ais with sync ais w/o sync tpos/tnrz tclk tneg/ tfsync enable (ccr4a.5) mux normal transmit data transmit formatter b enable (ccr4b.5) ccr1b.2 / ccr1b.3 figure 15-1: bert mux diagram
ds2196 88 of 157 15.1 bert register description bc0: bert control register 0 (address = 40 hex) (msb) (lsb) ? tinv rinv ps2 ps1 ps0 lc resync symbol position name and description ? bc0.7 not assigned. should be set to 0 when written to. tinv bc0.6 transmit invert data enable (tinv). 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream rinv bc0.5 receive invert data enable (rinv). 0 = do not invert the incoming data stream 1 = invert the incoming data stream ps2 bc0.4 pattern select bit 2. refer to table 15-1 for details. ps1 bc0.3 pattern select bit 1. refer to table 15-1 for details. ps0 bc0.2 pattern select bit 0. refer to table 15-1 for details. lc bc0.1 load bit and error counters (lc). a low to high transition latches the current bit and erro r counts into the host accessible registers bbc0/bbc1/bbc2/bbc3 and bec0/bec1/bec2 and clears the internal count. this bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. must be cleared and set again for a subsequent loads. resync bc0.0 force resynchronization (resync). a low to high transition will force the receive bert synchronizer to resynchronize to the incoming data stream. this bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. must be cleared and set again for a subsequent resynchronization.
ds2196 89 of 157 table 15-1: bert pattern select options ps2 ps1 ps0 pattern definition 000 pseudorandom 2e7 ? 1 001 pseudorandom 2e11 ? 1 010 pseudorandom 2e15 ? 1 011 pseudorandom pattern qrss. a 2 20 - 1 pattern with 14 consecutive zero restriction. 100 repetitive pattern 101 alternating word pattern 110 modified 55 octet (daly) pattern the daly pattern is a repeating 55 octet pattern that is byte aligned into the active ds0 timeslots. the pattern is defined in a atis (alliance for telecommunications industry solutions) committee t1 technical report number 25 (november 1993). 111 reserved bc1: bert control register 1 (address = 41 hex) (msb) (lsb) iesync iebed ieof ? rpl3 rpl2 rpl1 rpl0 symbol position name and description iesync bc1.7 change of synchronization status interrupt enable. interrupt enable for synchronizer status (bir.0) 0 = interrupt masked 1 = interrupt enabled iebed bc1.6 bit error detected interrupt enable. interrupt enable for bit error detected (bir.3) 0 = interrupt masked 1 = interrupt enabled ieof bc1.5 bit & error counter overflow interrupt enable. interrupt enable for the bert bit counter (bir.2) and bert error counter (bir.1) overflow. 0 = interrupt masked 1 = interrupt enabled ? bc1.4 not assigned. should be set to 0 when written to. rpl3 bc1.3 repetitive pattern length bit 3 (rpl3). refer to table 15-2 for details. rpl2 bc1.2 repetitive pattern length bit 2 (rpl2). refer to table 15-2 for details. rpl1 bc1.1 repetitive pattern length bit 1 (rpl1). refer to table 15-2 for details. rpl0 bc1.0 repetitive pattern length bit 0 (rpl0). refer to table 15-2 for details.
ds2196 90 of 157 repetitive pattern length configuration rpl0 is the lsb and rpl3 is the msb of a nibble that describes the how long the repetitive pattern is. the valid range is 17 (0000) to 32 (1111). these bits are ignored if the receive bert is programmed for a pseudorandom pattern. to create re petitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. for example, to create a 6 bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101). table 15-2: repetitive pattern length options length rpl3 rpl2 rpl1 rpl0 17 bits0000 18 bits0001 19 bits0010 20 bits0011 21 bits0100 22 bits0101 23 bits0110 24 bits0111 25 bits1000 26 bits1001 27 bits1010 28 bits1011 29 bits1100 30 bits1101 31 bits1110 32 bits1111
ds2196 91 of 157 bc2: bert control register 2 (address = 42 hex) (msb) (lsb) eib2 eib1 eib0 sbe ? ? ? tc symbol position name and description eib2 bc2.7 error insert bit 2. will automatically insert bit errors at the prescribed rate into the genera ted data pattern. useful for verifying error detection opera tion. refer to table 15-3 for details. eib1 bc2.6 error insert bit 1. refer to table 15-3 for details. eib0 bc2.5 error insert bit 0. refer to table 15-3 for details. sbe bc2.4 single bit error insert. a low to high transition will create a single bit error. must be clea red and set again for a subsequent bit error to be inserted. ? bc2.3 not assigned. should be set to 0 when written. ? bc2.2 not assigned. should be set to 0 when written. ? bc2.1 not assigned. should be set to 0 when written. tc bc2.0 transmit pattern load. a low to high transition loads the pattern generator with the pattern that is to be generated. this bit should be toggled from low to high whenever the host wishes to load a new pattern. must be cleared and set again for a subsequent loads. table 15-3: bert rate insertion select eib2 eib1 eib0 error rate inserted 0 0 0 no errors automatically inserted 00110e-1 01010e-2 01110e-3 10010e-4 10110e-5 11010e-6 11110e-7
ds2196 92 of 157 bir: bert information re gister (address = 43 hex) (refer to section 7 for explanation of reading latched register bits) (msb) (lsb) ? ra1 ra0 rlos bed bbco bec0 sync symbol position name and description ?bir.7 not assigned. maybe any value when read. ra1 bir.6 receive all 1?s (ra1). a latched bit which is set when 32 consecutive 1?s are received. allo wed to be cleared once a 0 is received. ra0 bir.5 receive all zeros (ra0). a latched bit which is set when 32 consecutive zeros are received. allowed to be cleared once a 1 is received. rlos bir.4 receive loss of synchronization (rlos). a latched bit which is set whenever the receive bert begins searching for a pattern. once synchronization is achieved, this bit will remain set until read. bed bir.3 bit error detected (bed). a latched bit which is set when a bit error is detected. the receive bert must be in synchronization for it detect bit e rrors. cleared when read. can generate interrupts if enabled via iebed (bc1.6). bbco bir.2 bert bit counter overflow (bbco). a latched bit which is set when the 32-bit bert bit counter (bbc) overflows. cleared when read and will not be set again until another overflow occurs. can generate interrupts if enabled via ieof (bc1.5). beco bir.1 bert error counter overflow (beco). a latched bit which is set when the 24-bit bert error counter (bec) overflows. cleared when read and will not be set again until another overflow occurs. can gene rate interrupts if enabled via ieof (bc1.5). sync bir.0 real time synchronization status (sync). real time status of the synchronizer (this bit is not latched). will be set when the incoming pattern matches for 32 consecutive bit positions. will be cleared when 6 or more bits out of 64 are received in error. can generate interrupts on change of state if enabled via iesync (bc1.7).
ds2196 93 of 157 bawc: bert alternating word count rate. (address = 44 hex) (msb) (lsb) altcnt7 altcnt6 altcnt5 altcnt4 altcnt3 altcnt2 altcnt1 altcnt0 symbol position name and description altcnt7 bawc.7 alternating word count rate bit 7. (msb) altcnt6 bawc.6 alternating word count rate bit 6 . altcnt5 bawc.5 alternating word count rate bit 5. altcnt4 bawc.4 alternating word count rate bit 4. altcnt3 bawc.3 alternating word count rate bit 3. altcnt2 bawc.2 alternating word count rate bit 2. altcnt1 bawc.1 alternating word count rate bit 1. altcnt0 bawc.0 alternating word count rate bit 0. (lsb) when the bert is programmed in the alternating wo rd mode, the words will repeat for the count loaded into this register then flip to the other word a nd again repeat for the number of times loaded into this register. brp0: bert repetitive pattern set register 0 (address = 45 hex) brp1: bert repetitive pattern set register 1 (address = 46 hex) brp2: bert repetitive pattern set register 2 (address = 47 hex) brp3: bert repetitive pattern set register 3 (address = 48 hex) (msb) (lsb) rpat7 rpat6 rpat5 rpat4 rpat3 rpat2 rpat1 rpat0 brp0 rpat15 rpat14 rpat13 rpat12 rpat11 rpat10 rpat9 rpat8 brp1 rpat23 rpat22 rpat21 rpat20 rpat19 rpat18 rpat17 rpat16 brp2 rpat31 rpat30 rpat29 rpat28 rpat27 rpat26 rpat25 rpat24 brp3 symbol position name and description rpat31 bertrp3.7 msb of the 32?bit repe titive pattern set rpat0 bertrp0.0 lsb of the 32?bit repe titive pattern set bert repetitive pattern set. these registers must be properly loaded for the bert to properly generate and synchronize to a repetitive pattern, a ps eudorandom pattern, alterna ting word pattern, or a daly pattern. for a repetitive pattern that is less than 32 bits, then the pattern should be repeated so that all 32 bits are used to describe the pattern. for example if the pattern was the repeating 5-bit pattern ?01101? (where the right most bit is the one sent firs t and received first) then brp0 should be loaded with adh, brp1 with b5h, brp2 with d6h, a nd brp3 should be loaded with 5ah. for a pseudorandom pattern, all four registers should be loaded with a ll 1?s (i.e. xff). for an alternating word pattern, one word should be placed into brp0 and brp1 and the other word should be placed into brp2 and brp3. for example, if the dds stress pattern "7 e" is to be described, the user would place 00h in brp0, 00h in brp1, 7eh in brp2, and 7eh in brp3 a nd the alternating word c ounter would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7eh to be sent and received.
ds2196 94 of 157 bbc0: bert bit count register 0 (address = 49 hex) bbc1: bert bit count register 1 (address = 4a hex) bbc2: bert bit count register 2 (address = 4b hex) bbc3: bert bit count register 3 (address = 4c hex) (msb) (lsb) bbc7 bbc6 bbc5 bbc4 bbc3 bbc2 bbc1 bbc0 bbc0 bbc15 bbc14 bbc13 bbc12 bbc11 bbc10 bbc9 bbc8 bbc1 bbc23 bbc22 bbc21 bbc20 bbc19 bbc18 bbc17 bbc16 bbc2 bbc31 bbc30 bbc29 bbc28 bbc27 bbc26 bbc25 bbc24 bbc3 symbol position name and description bbc31 bbc3.7 msb of the 32?bit bit counter bbc0 bbc0.0 lsb of the 32?bit bit counter bert bit counter (bbc0/ bbc1/ bbc2/ bbc3). once bert has achieved synchronization, this 32-bit counter will increment for each data bit (i.e. clock) received. toggling the lc control bit in bc0 can clear this counter. this counter saturate s when full and will set the bbco status bit. bec0: bert error count register 0 (address = 4d hex) bec1: bert error count register 1 (address = 4e hex) bec2: bert error count register 2 (address = 4f hex) (msb) (lsb) ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 bertec0 ec15 ec14 ec13 ec12 ec11 ec10 ec9 ec8 bertec1 ec23 ec22 ec21 ec20 ec19 ec18 ec17 ec16 bertec2 symbol position name and description ec24 bec2.7 msb of the 24?bit error counter ec0 bec0.0 lsb of the 24?bit error counter bert error counter (bec0/ bec1/ bec2). once bert has achieved synchronization, this 24-bit counter will increment for each data bit received in error. toggling the lc control bit in bc0 can clear this counter. this counter saturates wh en full and will set the beco status bit.
ds2196 95 of 157 bic: bert interface contro l register (address = 50 hex) (msb) (lsb) ? rfus rrcb rabs tbat tfus ttcb tabs symbol position name and description ?bic.7 not assigned. should be set to 0 when written to. rfus bic.6 receive framed/unframed select. 0 = bert will not be sent da ta from the f-bit position (framed) 1 = bert will be sent data from the f-bit position (unframed) rrcb bic.5 receive rchblk select. 0 = do not use rchblk to select which ds0 channels are to be routed to bert 1 = use rchblk to select which ds0 channels are to be routed to bert rabs bic.4 receive framer a or b select. 0 = route data from framer a 1 = route data from framer b tbat bic.3 transmit byte align toggle. a 0 to 1 transition will force the bert to byte align it?s pattern with the transmit formatter. this bit must be transitioned in order to byte align the daly pattern. tfus bic.2 transmit framed/unframed select. 0 = bert will not source data into the f-bit position (framed) 1 = bert will source data into the f-bit position (unframed) ttcb bic.1 transmit tchblk select. 0 = do not use tchblk to sel ect which ds0 channels are to contain bert data 1 = use tchblk to select which ds0 channels are to contain bert data tabs bic.0 transmit formatter a or b select. 0 = route data to formatter a 1 = route data to formatter b
ds2196 96 of 157 16. error insertion function an error insertion function is available in each forma tter of the ds2196 and is used to create errors in the payload portion of the t1 frame in the transmit path. see figure 21-7 for location. errors can be inserted over the entire frame or the user may select which channels are to be corrupted. errors are created by inverting the last bit in the count sequence. for ex ample if the error rate 1 in 16 is selected, the 16 th bit is inverted. f-bits are excluded from the count and are never corrupted. error rate changes occur on frame boundaries. error insertion options include continuous and absolute number with both options supporting selectable insertion rates. transmit error insertion setup guideline. 1. enter desired error rate in the erc regi ster. refer to table 16-1 for available rates. note: if er3:0 = 0, no errors will be generated even if the constant error insertion feature is enabled. 2a. for constant error inse rtion set ce = 1 (erc.4). or 2b. for a defined number of errors: - set ce = 0 (erc.4) - load noe1 & noe 2 with the number of errors to be inserted - toggle wnoe (erc.7) from 0 to 1, to begin error insertion
ds2196 97 of 157 erca: error rate control register framer a (address = 80 hex) ercb: error rate control register framer a (address = 85 hex) (msb) (lsb) wnoe rnoe tcbe ce er3 er2 er1 er0 symbol position name and description wnoe erc.7 write noe registers. if the host wishes to update to the noe registers, this bit must be toggled from a 0 to a 1 after the host has already loaded the prescribed error count into the noe registers. the toggling of this bit causes the error count loaded into the noe registers to be loaded into the error insertion circuitry on the next clock cycle. subsequent updates require that the wnoe b it be set to 0 and then 1 once again. rnoe erc.6 read rnoel registers. if the host wishes to obtain the latest count of the number of erro rs left to be inserted by the error insertion function, then this bit must be toggled from a 0 to a 1. subsequent reads require that the rnoe bit be set to 0 and then 1 once again. the host must wait at least 972 ns (1.5 clock periods) after toggling this bit to read the noel registers. the host may read the noel registers at any time but they will contain either th e count of errors left to be inserted (after toggling the rnoe bit) or the count of the number of errors that the host has loaded (after writing to the noe registers). tcbe erc.5 tchblk enable. this bit determines whether the tchblk signal should be used to ?block? certain channels from being corrupted. when tcbe is set high, then the error insertion logic will not corrupt ds0 channels in which the tchblk signal has be programmed high. 0 = all the error insertion logic to corrupt all ds0 channels 1 = allow the error insertion logic to only corrupt the ds0 channels determined by the tchblk signal ce erc.4 constant errors. when this bit is set high (and the er0 to er3 bits are not set to 0000), the error insertion logic will ignore the number of error registers (noe1a, noe2a, noe1b, and noe2b) and generate errors constantly at the selected insertion rate. when ce is set to 0, the noe registers determine how many errors are to be inserted. er3 erc.3 error rate bit 3. refer to table 16-1 for details. er2 erc.2 error rate bit 2. refer to table 16-1 for details. er1 erc.1 error rate bit 1. refer to table 16-1 for details. er0 erc.0 error rate bit 0. refer to table 16-1 for details.
ds2196 98 of 157 table 16-1: error rate options er3 er2 er1 er0 error rate 0000no errors inserted 00011 in 16 00101 in 32 00111 in 64 01001 in 128 01011 in 256 01101 in 512 01111 in 1024 10001 in 2048 10011 in 4096 10101 in 8192 10111 in 16384 11001 in 32768 11011 in 65536 11101 in 131072 11111 in 262144 noe1a: number of errors 1 framer a (address = 81 hex) noe1b: number of errors 1 framer b (address = 86 hex) noe2a: number of errors 2 framer a (address = 82 hex) noe2b: number of errors 2 framer b (address = 87 hex) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 noe1 ??????c9c8noe2 symbol position name and description c9 noe2.1 msb of the 10?bit numb er of errors counter c0 noe1.0 lsb of the 10?bit number of errors counter number of errors registers. the number of error registers determines how many errors will be generated. up to 1023 errors can be generated. the ho st will load the number of errors to be generated into the noe registers. the host can also update the number of errors to be created by first loading the prescribed value into the noe registers and then toggling the wnoe bit in the error rate control registers. refer to table 16-2 for examples.
ds2196 99 of 157 table 16-2: error insertion examples value write read 000h do not create any errors no errors left to be inserted 001h create a single error 1 error left to be inserted 002h create 2 errors 2 errors left to be inserted 3ffh create 1023 errors 1023 errors left to be inserted noel1a: number of errors le ft 1 framer a (address = 83 hex) noel1b: number of errors le ft 1 framer b (address = 88 hex) noel2a: number of errors le ft 2 framer a (address = 84 hex) noel2b: number of errors le ft 2 framer b (address = 89 hex) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 noel1 ??????c9c8noel2 symbol position name and description c9 noel2.1 msb of the 10?bit number of errors left counter c0 noel1.0 lsb of the 10?bit number of errors left counter number of errors left registers. the host can read the noel registers at any time (to determine how many errors are left to be inserted) by toggling the rnoe bit in the error rate control registers (erca and ercb) from a 0 to a 1. after the rnoe bit is toggled, the host may read the noel registers after waiting at least 972 ns (1.5 clock periods). 17. hdlc controller the ds2196 has an enhanced hdlc controller config urable for use with the facilities data link or ds0s. there are 64 byte buffers in both the transmit and receive paths. the user can select any ds0 or multiple ds0s as well as any specific bits within the ds0(s) to pass through the hdlc controller. see figure 21-7 for details on formatting the transmit side. note that tboc.6 = 1 and tdc1.7 = 1 cannot exist without corrupting the data in the fdl. for use with the fdl, see section 18. see table 17-1 for configuring the transmit hdlc controller. table 17-1: transmit hdlc configuration function tboc.6 tdc1.7 tcr1.2 ds0(s) 0 1 1 or 0 fdl 101 disable 0 0 1 or 0
ds2196 100 of 157 four new registers were added for the enhanced functionality of the hdlc controller; rdc1, rdc2, tdc1, and tdc2. note that the boc controller is functional when the hdlc controller is used for ds0s. section 18 contains all of the hdlc and boc registers and information on fdl/fs extraction and insertion with and without the hdlc controller. 17.1 hdlc for ds0s when using the hdlc controllers for ds0s, the same registers shown in section 18 will be used except for the tboc and rboc registers and bits hcr.7, hsr.7, and himr.7. as a basic guideline for interpreting and sending hdlc messages and boc messages, the following sequences can be applied. receive a hdlc message 1. enable rps interrupts 2. wait for interrupt to occur 3. disable rps interrupt and enable e ither rpe, rne, or rhalf interrupt 4. read rhir to obtain rempty status a. if rempty=0, then record obyte, cbyte, and pok bits and then read the fifo a1. if cbyte=0 then skip to step 5 a2. if cbyte=1 then skip to step 7 b. if rempty=1, then skip to step 6 5. repeat step 4 6. wait for interrupt, skip to step 4 7. if pok=0, then discard whole pack et, if pok=1, accept the packet 8. disable rpe, rne, or rhalf interrupt, enab le rps interrupt and return to step 1. transmit a hdlc message 1. make sure hdlc controller is done sending any pr evious messages and is current sending flags by checking that the fifo is empty by reading the tempty status bit in the thir register 2. enable either the thalf or tnf interrupt 3. read thir to obtain tfull status a. if tfull=0, then write a byte into the fifo and skip to next step (special case occurs when the last byte is to be written, in this case set teom=1 before writing the byte and then skip to step 6) b. if tfull=1, then skip to step 5 4. repeat step 3 5. wait for interrupt, skip to step 3 6. disable thalf or tnf interrupt and enable tmend interrupt 7. wait for an interrupt, then read tudr status bit to make sure packet was transmitted correctly.
ds2196 101 of 157 18. fdl/fs extraction and insertion each framer/formatter has the ability to extract/insert data from/ into the facility data link (fdl) in the esf framing mode and from/into fs?bit position in the d4 framing mode. since slc?96 utilizes the fs-bit position, this capability can also be used in slc?96 applications. the ds2196 contains a complete hdlc and boc controller for the fdl and this ope ration is covered in section 18.1. to allow for backward compatibility between the ds2196 and ea rlier devices, the ds2196 maintains some legacy functionality for the fdl and this is covered in section 18.2. s ection 18.3 covers d4 and slc?96 operation. please contact the factory for a copy of c language source code for implementing the fdl on the ds2196. 18.1 hdlc and boc controller for the fdl 18.1.1 general overview the ds2196 contains a complete hdlc controller with 64?byte buffers in both the transmit and receive directions as well as separate de dicated hardware for bit oriented codes (boc). the hdlc controller performs all the necessary overhead for generating and receiving performance report messages (nprms and sprms) as described in ansi t1.403-1998 and the messages as described in at&t tr54016. the hdlc controller automatically generates and detects flags, generates and checks the crc check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the hdlc data stream. the 64?byte buffers in the hdlc controller are large enough to allow a full nprm or sprm to be received or trans mitted without host intervention. th e boc controller will automatically detect incoming boc sequences and alert the host. when the boc ceases, the ds2196 will also alert the host. the user can set the device up to send any of the possible 6?bit boc codes. there are thirteen registers that the host will use to operate and control the operation of the hdlc and boc controllers. a brief description of the registers is shown in table 18?1.
ds2196 102 of 157 table 18-1: hdlc/boc controller register list name function hdlc control register (hcr) general c ontrol over the hdlc and boc controllers hdlc status register (hsr) key status information for both transmit and receive directions hdlc interrupt mask register (himr) allows/st ops status bits to/from causing an interrupt receive hdlc information register (rhir) status information on rece ive hdlc controller status receive boc register (rboc) information on receive boc controller receive hdlc fifo register (rhfr) access to 64?byte hdlc fifo in receive direction receive hdlc ds0 control register 1 (rdc1) receive hdlc ds0 control register 2 (rdc2) controls the hdlc function when used on ds0 channels transmit hdlc information register (thir) status information on transmit hdlc controller transmit boc register (tboc) enables/disables transmission of boc codes transmit hdlc fifo register (thfr) access to 64?byte hdlc fifo in transmit direction transmit hdlc ds0 control register 1 (tdc1) transmit hdlc ds0 control register 2 (tdc2) controls the hdlc function when used on ds0 channels
ds2196 103 of 157 18.1.2 status register for the hdlc four of the hdlc/boc controller registers (hsr, rhir, rboc, and thir) provide status information. when a particular event has occurred (or is occurring) , the appropriate bit in one of these four registers will be set to a 1. some of the bits in these four hdlc status registers are latched and some are real time bits that are not latched. section 18.1.4 contains register descriptions th at list which bits are latched and which are not. with the latched bits, when an event occurs and a bit is set to a 1, it will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again. the real time bits report the cu rrent instantaneous conditions that are occurring and the history of these bits is not latched. like the other status registers in the ds2196, the us er will always proceed a read of any of the four registers with a write. the byte written to the regi ster will inform the ds2196 which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). the user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. when a 1 is written to a bit location, the read register will be updated with current value and it will be cleared. when a 0 is written to a bit position, the read regist er will not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. this write?read?write (for polled driven access) or write?read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in th e register. this operation is key in controlling the ds2196 with higher?order software languages. like the sr1 and sr2 status registers, the hsr register has the unique ability to initiate a hardware interrupt via the int output pin. each of the events in the hsr can be either masked or unmasked from the interrupt pin via the hdlc interrupt mask register (himr). interrupts will force the int pin low when the event occurs. the int pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. 18.1.3 basic oper ation details to allow the framer to properly source/receive da ta from/to the hdlc and boc controller the legacy fdl circuitry (which is described in section 18.2) should be disabled and the following bits should be programmed as shown: tcr1.2 = 1 (source fdl data from the hdlc and boc controller) tboc.6 = 1 (enable hdlc and boc controller) ccr2.5 = 0 (disable slc?96 and d4 fs?bit insertion) ccr2.4 = 0 (disable legacy fdl zero stuffer) ccr2.1 = 0 (disable slc?96 reception) ccr2.0 = 0 (disable legacy fdl zero stuffer) imr2.4 = 0 (disable legacy receive fdl buffer full interrupt) imr2.3 = 0 (disable legacy transmit fdl buffer empty interrupt) imr2.2 = 0 (disable legacy fdl match interrupt) imr2.1 = 0 (disable legacy fdl abort interrupt). as a basic guideline for interpreting and sending both hdlc messages and boc messages, the following sequences can be applied:
ds2196 104 of 157 receive a hdlc message or a boc 1. enable rboc and rps interrupts 2. wait for interrupt to occur 3. if rboc=1, then follow steps 5 and 6 4. if rps=1, then follow steps 7 through 12 5. if lbd=1, a boc is present, then read the code from the rboc register and take action as needed 6. if bd=0, a boc has ceased, take action as needed and then return to step 1 7. disable rps interrupt and enable e ither rpe, rne, or rhalf interrupt 8. read rhir to obtain rempty status a. if rempty=0, then record obyte, cbyte, and pok bits and then read the fifo a1. if cbyte=0 then sk ip to step 9 a2. if cbyte=1 then skip to step 11 b. if rempty=1, then skip to step 10 9. repeat step 8 10. wait for interrupt, skip to step 8 11. if pok=0, then discard whole packet, if pok=1, accept the packet 12. disable rpe, rne, or rhalf interrupt, enable rps inte rrupt and return to step 1. transmit a hdlc message 1. make sure hdlc controller is done sending any pr evious messages and is current sending flags by checking that the fifo is empty by reading the tempty status bit in the thir register 2. enable either the thalf or tnf interrupt 3. read thir to obtain tfull status a. if tfull=0, then write a byte into the fifo and skip to next step (special case occurs when the last byte is to be written, in this case set teom=1 before writing the byte and then skip to step 6) b. if tfull=1, then skip to step 5 4. repeat step 3 5. wait for interrupt, skip to step 3 6. disable thalf or tnf interrupt and enable tmend interrupt 7. wait for an interrupt, then read tudr status bit to make sure packet was transmitted correctly. transmit a boc 1. write 6?bit code into tboc 2. set sboc bit in tboc=1
ds2196 105 of 157 18.1.4 hdlc/boc regi ster description hcra: hdlc control register framer a (address = 00 hex) hcrb: hdlc control register framer b (address = a0 hex) (msb) (lsb) rbr rhr tfs thr tabt teom tzsd tcrcd symbol position name and description rbr hcr.7 receive boc reset. a 0 to 1 transition will reset the boc circuitry. must be cleared and set again for a subsequent reset. rhr hcr.6 receive hdlc reset. a 0 to 1 transition will reset the hdlc controller. must be cleared and set again for a subsequent reset. tfs hcr.5 transmit flag/idle select. 0 = 7eh 1 = ffh thr hcr.4 transmit hdlc reset. a 0 to 1 transition will reset both the hdlc controller and the transmit boc circuitry. must be cleared and set again for a subsequent reset. tabt hcr.3 transmit abort. a 0 to 1 transition will cause the fifo contents to be dumped and one feh abort to be sent followed by 7eh or ffh flags/idle until a new packet is initiated by writing new data into the fifo. must be cleared and set again for a subsequent abort to be sent. teom hcr.2 transmit end of message. should be set to a 1 just before the last data byte of a hdlc packet is written into the transmit fifo at thfr. the hdlc controller will clear this bit when the last byte has been transmitted. tzsd hcr.1 transmit zero stuffer defeat. overrides internal enable. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer tcrcd hcr.0 transmit crc defeat. 0 = enable crc generation (normal operation) 1 = disable crc generation
ds2196 106 of 157 hsra: hdlc status register framer a (address = 01 hex) hsrb: hdlc status register framer b (address = a1 hex) (msb) (lsb) rboc rpe rps rhalf rne thalf tnf tmend symbol position name and description rboc hsr.7 receive boc detector change of state. set whenever the boc detector sees a change of state from a boc detected to a no valid code seen or vice versa. the setting of this bit prompt the user to read the rboc register for details. rpe hsr.6 receive packet end. set when the hdlc controller detects either the finish of a valid message (i.e., crc check complete) or when the controller has experienced a message fault such as a crc checking error, or an overrun condition, or an abort has been seen. the setting of this bit prompts the user to read the rhir register for details. rps hsr.5 receive packet start . set when the hdlc controller detects an opening byte. the setting of this bit prompts the user to read the rhir register for details. rhalf hsr.4 receive fifo half full. set when the receive 64?byte fifo fills beyond the half waypoint. the setting of this bit prompts the user to read the rhir register for details. rne hsr.3 receive fifo not empty. set when the receive 64?byte fifo has at least one byte available for a read. the setting of this bit prompts the user to read the rhir register for details. thalf hsr.2 transmit fifo half empty. set when the transmit 64?byte fifo empties beyond the half waypoint. the setting of this bit prompts the user to read the thir register for details. tnf hsr.1 transmit fifo not full. set when the transmit 64?byte fifo has at least one byte available. the setting of this bit prompts the user to read the thir register for details. tmend hsr.0 transmit message end. set when the transmit hdlc controller has finished sending a message. the setting of this bit prompts the user to read the thir register for details. note: the rboc, rpe, rps, and tmend bits are latched and will be cleared when read.
ds2196 107 of 157 himra: hdlc interrupt mask register framer a (address = 02 hex) himrb: hdlc interrupt mask register framer b (address = a2 hex) (msb) (lsb) rboc rpe rps rhalf rne thalf tnf tmend symbol position name and description rboc himr.7 receive boc detector change of state. 0 = interrupt masked 1 = interrupt enabled rpe himr.6 receive packet end. 0 = interrupt masked 1 = interrupt enabled rps himr.5 receive packet start. 0 = interrupt masked 1 = interrupt enabled rhalf himr.4 receive fifo half full. 0 = interrupt masked 1 = interrupt enabled rne himr.3 receive fifo not empty. 0 = interrupt masked 1 = interrupt enabled thalf himr.2 transmit fifo half empty. 0 = interrupt masked 1 = interrupt enabled tnf himr.1 transmit fifo not full. 0 = interrupt masked 1 = interrupt enabled tmend himr.0 transmit message end. 0 = interrupt masked 1 = interrupt enabled
ds2196 108 of 157 rhira: receive hdlc information register framer a (address = 03 hex) rhirb: receive hdlc information register framer b (address = a3 hex) (msb) (lsb) rabt rcrce rovr rvm rempty pok cbyte obyte symbol position name and description rabt rhir.7 abort sequence detected. set whenever the hdlc controller sees 7 or more 1?s in a row. rcrce rhir.6 crc error. set when the crc checksum is in error. rovr rhir.5 overrun. set when the hdlc controller has attempted to write a byte into an already full receive fifo. rvm rhir.4 valid message. set when the hdlc controller has detected and checked a complete hdlc packet. rempty rhir.3 empty. a real?time bit that is set high when the receive fifo is empty. pok rhir.2 packet ok. set when the byte available for reading in the receive fifo at rhfr is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the crc was correct). cbyte rhir.1 closing byte. set when the byte available for reading in the receive fifo at rhfr is the last byte of a message (whether the message was valid or not). obyte rhir.0 opening byte. set when the byte available for reading in the receive fifo at rhfr is the first byte of a message. note: the rabt, rcrce, rovr, and rvm bits are latched and will be cleared when read.
ds2196 109 of 157 rboca: receive bit oriented code register framer a (address = 04 hex) rbocb: receive bit oriented code register framer b (address = a4 hex) (msb) (lsb) lbd bd boc5 boc4 boc3 boc2 boc1 boc0 symbol position name and description lbd rboc.7 latched boc detected. a latched version of the bd status bit (rboc.6). will be cleared when read. bd rboc.6 boc detected. a real?time bit that is set high when the boc detector is presently seeing a valid sequence and set low when no boc is currently being detected. boc5 rboc.5 boc bit 5. last bit received of the 6?bit code word. boc4 rboc.4 boc bit 4. boc3 rboc.3 boc bit 3. boc2 rboc.2 boc bit 2. boc1 rboc.1 boc bit 1. boc0 rboc.0 boc bit 0. first bit received of the 6?bit code word. note: 1. the lbd bit is latched and will be cleared when read. 2. the rboc0 to rboc5 bits display the last valid boc code verified; these bits will be set to all 1?s on reset. rhfra: receive hdlc fifo from framer a (address = 05 hex) rhfrb: receive hdlc fi fo from framer b (address = a5 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbol position name and description hdlc7 rhfr.7 hdlc data bit 7 . msb of a hdlc packet data byte. hdlc6 rhfr.6 hdlc data bit 6. hdlc5 rhfr.5 hdlc data bit 5. hdlc4 rhfr.4 hdlc data bit 4. hdlc3 rhfr.3 hdlc data bit 3. hdlc2 rhfr.2 hdlc data bit 2. hdlc1 rhfr.1 hdlc data bit 1. hdlc0 rhfr.0 hdlc data bit 0. lsb of a hdlc packet data byte.
ds2196 110 of 157 thira: transmit hdlc information for formatter a (address = 06 hex) thirb: transmit hdlc information for formatter b (address = a6 hex) (msb) (lsb) ?????temptytfulltudr symbol position name and description ?thir.7 not assigned. could be any value when read. ?thir.6 not assigned. could be any value when read. ?thir.5 not assigned. could be any value when read. ?thir.4 not assigned. could be any value when read. ?thir.3 not assigned. could be any value when read. tempty thir.2 transmit fifo empty. a real?time bit that is set high when the fifo is empty. tfull thir.1 transmit fifo full. a real?time bit that is set high when the fifo is full. tudr thir.0 transmit fifo underrun. set when the transmit fifo unwantedly empties out and an abort is automatically sent. note: the tudr bit is latched and will be cleared when read.
ds2196 111 of 157 tboca: transmit bit oriented code for formatter a (address = 07 hex) tbocb: transmit bit oriented code for formatter b (address = a7 hex) (msb) (lsb) sboc hben boc5 boc4 boc3 boc2 boc1 boc0 symbol position name and description sboc tboc.7 send boc. rising edge triggered. must be transitioned from a 0 to a 1 transmit the boc code placed in the boc0 to boc5 bits instead of data from the hdlc controller. hben tboc.6 transmit hdlc & boc controller enable. 0 = source fdl data from the tlink pin 1 = source fdl data from the onboard hdlc and boc controller boc5 tboc.5 boc bit 5. last bit transmitted of the 6?bit code word. boc4 tboc.4 boc bit 4. boc3 tboc.3 boc bit 3. boc2 tboc.2 boc bit 2. boc1 tboc.1 boc bit 1. boc0 tboc.0 boc bit 0. first bit transmitted of the 6?bit code word. thfra: transmit hdlc fifo for formatter a (address = 08 hex) thfrb: transmit hdlc fifo for formatter b (address = a8 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbol position name and description hdlc7 thfr.7 hdlc data bit 7. msb of a hdlc packet data byte. hdlc6 thfr.6 hdlc data bit 6. hdlc5 thfr.5 hdlc data bit 5. hdlc4 thfr.4 hdlc data bit 4. hdlc3 thfr.3 hdlc data bit 3. hdlc2 thfr.2 hdlc data bit 2. hdlc1 thfr.1 hdlc data bit 1. hdlc0 thfr.0 hdlc data bit 0. lsb of a hdlc packet data byte.
ds2196 112 of 157 rdc1a: receive hdlc ds0 control register 1 framer a (address = 90 hex) rdc1b: receive hdlc ds0 cont rol register 1 framer b (address = 94 hex) (msb) (lsb) rds0e - rds0m rd4 rd3 rd2 rd1 rd0 symbol position name and description rds0e rdc1.7 hdlc ds0 enable. 0 = use receive hdlc controller for the fdl. 1 = use receive hdlc controller for one or more ds0 channels. - rdc1.6 not assigned. should be set to 0. rds0m rdc1.5 ds0 selection mode. 0 = utilize the rd0 to rd4 bits to select which single ds0 channel to use. 1 = utilize the rchblk control registers to select which ds0 channels to use. rd4 rdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. rd3 rdc1.3 ds0 channel select bit 3. rd2 rdc1.2 ds0 channel select bit 2. rd1 rdc1.1 ds0 channel select bit 1. rd0 rdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select.
ds2196 113 of 157 rdc2a: receive hdlc ds0 control register 2 framer a (address = 91 hex) rdc2b: receive hdlc ds0 cont rol register 2 framer b (address = 95 hex) (msb) (lsb) rdb8 rdb7 rdb6 rdb5 rdb4 rdb3 rdb2 rdb1 symbol position name and description rdb8 rdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to 1 to stop this bit from being used. rdb7 rdc2.6 ds0 bit 7 suppress enable. set to 1 to stop this bit from being used. rdb6 rdc2.5 ds0 bit 6 suppress enable. set to 1 to stop this bit from being used. rdb5 rdc2.4 ds0 bit 5 suppress enable. set to 1 to stop this bit from being used. rdb4 rdc2.3 ds0 bit 4 suppress enable. set to 1 to stop this bit from being used. rdb3 rdc2.2 ds0 bit 3 suppress enable. set to 1 to stop this bit from being used. rdb2 rdc2.1 ds0 bit 2 suppress enable. set to 1 to stop this bit from being used. rdb1 rdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to 1 to stop this bit from being used.
ds2196 114 of 157 tdc1a: transmit hdlc ds0 control register 1 framer a (address = 92 hex) tdc1b: transmit hdlc ds0 control register 1 framer b (address = 96 hex) (msb) (lsb) tds0e - tds0m td4 td3 td2 td1 td0 symbol position name and description tds0e tdc1.7 hdlc ds0 enable. 0 = use transmit hdlc controller for the fdl. 1 = use transmit hdlc controller for 1 or more ds0 channels. - tdc1.6 not assigned. should be set to 0. tds0m tdc1.5 ds0 selection mode. 0 = utilize the td0 to td4 bits to select which single ds0 channel to use. 1 = utilize the tchblk control registers to select which ds0 channels to use. td4 tdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. td3 tdc1.3 ds0 channel select bit 3. td2 tdc1.2 ds0 channel select bit 2. td1 tdc1.1 ds0 channel select bit 1. td0 tdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select.
ds2196 115 of 157 tdc2a: transmit hdlc ds0 control register 2 framer a (address = 93 hex) tdc2b: transmit hdlc ds0 control register 2 framer b (address = 97 hex) (msb) (lsb) tdb8 tdb7 tdb6 tdb5 tdb4 tdb3 tdb2 tdb1 symbol position name and description tdb8 tdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to 1 to stop this bit from being used. tdb7 tdc2.6 ds0 bit 7 suppress enable. set to 1 to stop this bit from being used. tdb6 tdc2.5 ds0 bit 6 suppress enable. set to 1 to stop this bit from being used. tdb5 tdc2.4 ds0 bit 5 suppress enable. set to 1 to stop this bit from being used. tdb4 tdc2.3 ds0 bit 4 suppress enable. set to 1 to stop this bit from being used. tdb3 tdc2.2 ds0 bit 3 suppress enable. set to 1 to stop this bit from being used. tdb2 tdc2.1 ds0 bit 2 suppress enable. set to 1 to stop this bit from being used. tdb1 tdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to 1 to stop this bit from being used. 18.2 legacy fdl support 18.2.1 overview the ds2196 maintains the circuitry that existed in the previous generati on of dallas semiconductor?s single chip transceivers and quad framers. section 18.2 covers the circuitry and operation of this legacy functionality. in new applications, it is recommended that the hdlc controller and boc controller described in section 18.1 be used. on the receive side, it is possible to have both the new hdlc/boc controller and the legacy hardware working at the same time. however this is not possible on the transmit side since there can be only one source the of the fdl data internal to the device. 18.2.2 receive section in the receive section, the recovered fdl bits or fs bits are shifted bit?by?bit into the receive fdl register (rfdl). since the rfdl is 8 bits in length, it will fill up every 2 ms (8 times 250 us). the framer will signal an external micro controller that the buffer has filled via the sr2.4 bit. if enabled via imr2.4, the int pin will toggle low indicating that th e buffer has filled and needs to be read. the user has 2 ms to read this data before it is lost. if the byte in the rfdl matches either of the bytes programmed into the rmtch1 or rmtch2 registers, then the sr2.2 bit will be set to a 1 and the int pin will toggled low if enabled via imr2.2. this feat ure allows an external microcontroller to ignore the fdl or fs pattern until an important event occurs. the framer also contains a zero destuffer, which is controlled via the ccr2.0 bit. in both ansi t1.403 and tr54016, communications on the fdl follows a subs et of a lapd protocol. the lapd protocol states that no more than five 1?s should be trans mitted in a row so that the data does not resemble an
ds2196 116 of 157 opening or closing flag (01111110) or an abort signal (11111111). if enabled via ccr2.0, the ds2196 will automatically look for five 1?s in a row, fo llowed by a 0. if it finds such a pattern, it will automatically remove the zero. if the zero destuffer sees six or more 1?s in a row followed by a 0, the 0 is not removed. the ccr2.0 bit should always be set to a 1 when the ds2196 is extracting the fdl. more on how to use the ds2196 in fdl applications in th is legacy support mode is covered in a separate application note. rfdla: receive fdl register fr om framer a (address = 28 hex) rfdlb: receive fdl register fr om framer b (address = c8 hex) (msb) (lsb) rfdl7 rfdl6 rfdl5 rfdl4 rfdl3 rfdl2 rfdl1 rfdl0 symbol position name and description rfdl7 rfdl.7 msb of the received fdl code rfdl0 rfdl.0 lsb of the received fdl code the receive fdl register (rfdl) reports the incoming facility data link (fdl) or the incoming fs bits. the lsb is received first. rmtch1a: receive fdl match register 1 framer a (address = 29 hex) rmtch2a: receive fdl match register 2 framer a (address = 2a hex) rmtch1b: receive fdl match register 1 framer b (address = c9 hex) rmtch2b: receive fdl match register 2 framer b (address = ca hex) (msb) (lsb) rmfdl7 rmfdl6 rmfdl5 rmfdl4 rmfdl3 rmfdl2 rmfdl1 rmfdl0 symbol position name and description rmfdl7 rmtch1a.7 rmtch2a.7 rmtch1b.7 rmtch2b.7 msb of the fdl match code rmfdl0 rmtch1a.0 rmtch2a.0 rmtch1b.0 rmtch2b.0 lsb of the fdl match code when the byte in the receive fdl register matches either of the two receive match registers (rmtch1/rmtch2), sr2.2 will be set to a 1 and the int will go active if enabled via imr2.2. 18.2.3 transmit section the transmit section will shift out into the t1 data stream, either the fdl (in the esf framing mode) or the fs bits (in the d4 framing mode) contained in the transmit fdl register (tfdl). when a new value
ds2196 117 of 157 is written to the tfdl, it will be multiplexed serially (lsb first) into the proper position in the outgoing t1 data stream. after the full 8 bits has been shifted out, the framer will signal the host microcontroller that the buffer is empty and that more data is n eeded by setting the sr2.3 bit to a 1. the int will also toggle low if enabled via imr2.3. the user has 2 ms to update the tfdl with a new value. if the tfdl is not updated, the old value in the tfdl will be tr ansmitted once again. the framer also contains a zero stuffer, which is controlled via the ccr2.4 bit. in both ansi t1.403 and tr54016, communications on the fdl follows a subset of a lapd protocol. the lapd protocol states that no more than five 1?s should be transmitted in a row so that the data do es not resemble an opening or closing flag (01111110) or an abort signal (11111111). if enabled via ccr2.4, the framer will automatically look for five 1?s in a row. if it finds such a pattern, it will automatically insert a 0 after the five 1?s. the ccr2.0 bit should always be set to a 1 when the framer is inserting the fdl. more on how to use the ds2196 in fdl applications is covered in a separate application note. tfdla: transmit fdl register for formatter a (address = 7e hex) tfdlb: transmit fdl register for formatter b (address = fe hex) [also used to insert fs framing patte rn in d4 framing mode; see section 18.3] (msb) (lsb) tfdl7 tfdl6 tfdl5 tfdl4 tfdl3 tfdl2 tfdl1 tfdl0 symbol position name and description tfdl7 tfdl.7 msb of the fdl code to be transmitted tfdl0 tfdl.0 lsb of the fdl code to be transmitted the transmit fdl register (tfdl) contains the facility data link (fdl) information that is to be inserted on a byte basis into the outgoing t1 data stream. the lsb is transmitted first. 18.3 d4/slc?96 operation in the d4 framing mode, the framer uses the tfdl register to insert the fs framing pattern. to allow the device to properly insert the fs framing pattern, the tf dl register at address 7eh must be programmed to 1ch and the following bits must be programmed as shown: tcr1.2=0 (source fs data from the tfdl register) ccr2.5=1 (allow the tfdl register to load on multiframe boundaries) since the slc?96 message fields share the fs?bit positi on, the user can access the message fields via the tfdl and rfdl registers. please see the separate application note for a deta iled description of how to implement a slc?96 function.
ds2196 118 of 157 19. line interface function the line interface function in the ds2196 contains thr ee sections; (1) the recei ver which handles clock and data recovery, (2) the transmitter which wave shapes and drives the t1 line, and (3) the jitter attenuator. each of these three sections is controlled by the line inter-face control register (licr) which is described below. licr: line interface control register framer a (address = 7c hex) (msb) (lsb) lbos2 lbos1 lbos0 egl jas jabds dja tpd symbol position name and description lbos2 licr.7 line build out select bit 2. sets the transmitter build out; see the table 19?1 lbos1 licr.6 line build out select bit 1. sets the transmitter build out; see the table 19?1 lbos0 licr.5 line build out select bit 0. sets the transmitter build out; see the table 19?1 egl licr.4 receive equalizer gain limit. 0 = ?36 db 1 = ?15 db jas licr.3 jitter attenuator select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side jabds licr.2 jitter attenuator buffer depth select. 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) dja licr.1 disable jitter attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled tpd licr.0 transmit power down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the ttip and tring pins 19.1 receive clock and data recovery the ds2196 contains a digital clock recovery system . see the ds2196 block diagram in section 1 and figure 19?1 for more details. the ds2196 couples to th e receive t1 twisted pair via a 1:1 transformer. see table 19?2 for transformer details. the 1.544 mhz clock attached at the mclk pin is internally multiplied by 16 via an internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16 times over sampler, which is used to recover the clock and data. this over sampling technique offers outstanding jitter tolerance (see figure 19?2).
ds2196 119 of 157 normally, the clock that is output at the rclklo pin is the recovered clock from the t1 ami/b8zs waveform presented at the rtip and rring inputs. when no ami signal is present at rtip and rring, a receive carrier loss (lrcl) condition will occur and the rclklo will be sourced from the clock applied at the mclk pin. if the jitter attenuator is either placed in the transmit path or is disabled, the rclklo output can exhibit slightly shorter high cycles of the clock. this is due to the highly over sampled digital clock recovery circuitr y. if the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the rclk to being close to 50% duty cycle. please see the receive ac timing characteristic s in section 22 for more details. 19.2 transmit waveshap ing and line driving the ds2196 uses a set of laser?trimmed delay lines along with a precision di gital?to?analog converter (dac) to create the waveforms that are transmitted onto the t1 line. the waveforms created by the ds2196 meet the latest ansi, at&t, and itu specif ications. see figure 19?3. the user will select which waveform is to be generated by properl y programming the lbos3/lbos2/lbos1/lbos0 bits in the line interface control register (licr) . the ds2196 can set up in a number of various configurations depending on the app lication. see table 19?1 and figure 19?1. table 19-1: line build out select in licr lbo s3 lbo s2 lbo s1 lbo s0 line build out application 0 0 0 0 0 to 133 feet/ dsx?1/0db csu 0 0 0 1 133 feet to 266 dsx?1 0 0 1 0 266 feet to 399 dsx?1 0 0 1 1 399 feet to 533 dsx?1 0 1 0 0 533 feet to 655 dsx?1 0 1 0 1 ?7.5 db csu 0 1 1 0 ?15 db csu 0 1 1 1 ?22.5 db csu 1 0 0 0 square wave output custom wave shape 1 0 0 1 open drain output driver enable custom wave shape note: lbos3 is located at ccr7a.0. due to the nature of the design of the trans mitter in the ds2196, very little jitter (less then 0.005 uipp broadband from 10 hz to 100 khz) is added to the jitter present on tclkli. also, the waveforms that they create are independent of the duty cycle of tclkli. the transmitter in the ds2196 couples to the t1 transmit twisted pair via a 1:2 step up transforme r for the as shown in figure 19?1. in order for the devices to create the proper waveforms, this transformer used must meet the specifications listed in table 19?2.
ds2196 120 of 157 table 19-2: transformer specifications specification recommended value turns ratio 1:1(receive) and 1:2(transmit) 5% primary inductance 600 h minimum leakage inductance 1.0 h maximum intertwining capacitance 40 pf maximum transmit transformer dc resistance primary (device side) secondary 1.0 maximum 2.0 maximum receive transformer dc resistance primary (device side) secondary 1.2 maximum 1.2 maximum 19.3 jitter attenuator the ds2196 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the jabds bit in the line interface control register (licr). the 128-bit mode is used in applications where large excursions of wander are expected. the 32-bit mode is used in delay sensitive applications. the characteristics of the attenuation are shown in figure 19?4. the jitter attenuator can be placed in either the receive path or the transmit path by a ppropriately setting or clearing the jas bit in the licr. also, the jitter attenuator can be disabled (in effect, removed) by setting the dja bit in the licr. in order for the jitter attenuator to operate properly, a 1.544 mhz clock (50 ppm) must be applied at the mclk pin. onboard circuitry adjusts either the r ecovered clock from the clock/data recovery block or the clock applied at the tclkli pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/ bursty clock at the tclkli pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120 uipp (buffer depth is 128 bits) or 28 uipp (buffer depth is 32 b its), then the ds2196 will divide the internal nominal 24.704 mhz clock by either 15 or 17 instead of th e normal 16 to keep the buffer from overflowing. when the device divides by either 15 or 17, it also se ts the jitter attenuator limit trip (jalt) bit in the receive information register (rir3.5)
ds2196 121 of 157 figure 19-1: external analog connections notes: 1. resistor values are 1%. 2. circuit requires use of schottky diodes for d1-d4. 3. s is a 6v transient suppresser. 4. c1 is 0.1 uf. 5. the rp resistors are used to prevent the fuses from opening during a surge. 6. see the separate application note for details on how to construct a protected interface. 7. mclk requires a ttl level 1.544 mhz clock (+50 ppm) for proper device operation. rtip rring ttip tring 1:1 t1 receive line t1 transmit line 2:1 (larger winding toward the network) ds2196 1uf (non- polarized) dvdd dvss 0.1uf rvdd rvss 0.1uf tvdd tvss 0.1uf +3.3v 0.1uf rp 0.01uf 1.544mhz mclk +3.3v 470 470 100 rp fuse fuse rp fuse rp fuse s c1 d1 d2 d3 d4 rtip rring 1:1 t1 receive line 0.1uf 470 470 rp fuse rp fuse a lternate receive interface 50 50 10 uf tant
ds2196 122 of 157 frequency ( hz ) unit intervals (uipp) 1k 100 10 1 0.1 10 100 1k 10k 100k ds2196 tolerance 1 mimimum tolerance level as per tr 62411 (dec. 90) figure 19-2: jitter tolerance figure 19-3: transmit waveform template 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 time (ns) n o r m al iz e d a m pl it u d e t1.102/87, t1.403, cb 119 (oct. 79), & i.431 template -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui time a mp. maximum curve ui time a mp. minimum curve
ds2196 123 of 157 frequency ( hz ) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k ds2196 jitter attenuation curve tr 62411 (dec. 90) prohibited area c u r v e b curve a figure 19-4: jitter attenuation
ds2196 124 of 157 20. jtag-boundary scan arch itecture and test access port 20.1 description the ds2196 ieee 1149.1 design supports the standard instruction codes sample/preload, bypass, and extest. optional public instructions included with this design are highz, clamp, and idcode. see figure 20-1 for a block diagram. the ds2196 contains the following items, which meet the requirements, set by the ieee 1149.1 st andard test access port and boundary scan architecture. test access port (tap) tap controller instruction register bypass register boundary scan register device identification register details on boundary scan architecture and the test access port can be found in ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. the test access port has the necessary interface pins; jtrst, jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details. figure 20-1: boundary scan architecture +v boundary scan register identification register bypass register instruction register jtdi jtms jtclk jtrst jtdo +v +v test access port controller mux 10k 10k 10k select output enable
ds2196 125 of 157 20.2 tap controller state machine this section covers the details on the operation of the test access port (tap) controller state machine. please see figure 20.2 for details on e ach of the states described below. tap controller the tap controller is a finite state machine that responds to the logic le vel at jtms on the rising edge of jtclk. test-logic-reset upon power up of the ds2196, the tap c ontroller will be in the test-logic -reset state. the instruction register will contain the idcode instruction. a ll system logic of the ds2196 will operate normally. run-test-idle the run-test-idle is used between scan operations or during specific te sts. the instruction register and test registers will remain idle. select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and will initiate a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir capture-dr data may be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of jtclk, the controller will go to the shift- dr state if jtms is low or it will go to the exit1-dr state if jtms is high. shift-dr the test data register selected by the current in struction will be connected between jtdi and jtdo and will shift data one stage towards its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. exit1-dr while in this state, a rising edge on jtclk with jtms high will put the controller in the update-dr state, and terminate the scanning process. a rising edge on jtclk with jtms low will put the controller in the pause-dr state. pause-dr shifting of the test registers is halted while in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while jtms is low. a rising edge on jtclk with jtms high will put the controller in the exit2-dr state.
ds2196 126 of 157 exit2-dr while in this state, a rising edge on jtclk with jtms high will put the controller in the update-dr state and terminate the scanning process. a rising edge on jtclk with jtms low will enter the shift- dr state. update-dr a falling edge on jtclk while in the update-dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register. a rising edge on jtclk with jtms low, will put the controller in the run-test-idle state. with jtms high, the controller will enter the select-dr-scan state. select-ir-scan all test registers retain their previous state. the instruction register will remain unchanged during this state. with jtms low, a rising edge of jtclk m oves the controller into the capture-ir state and will initiate a scan sequence for the instruction register. jtms high during a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller will enter the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller will enter the shift-ir state. shift-ir in this state, the shift register in the instruction register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk towards the serial output. the parallel registers, as well as all test registers remain at their previous states. a rising edge on jtclk with jtms high will move the controller to the exit1-ir state. a rising edge on jtclk with jtms low will keep the controller in the shift-ir state while moving data one stage thorough the instruction shift register. exit1-ir a rising edge on jtclk with jtms low will put the controller in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller will enter the update-ir state and terminate the scanning process. pause-ir shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk will put the controller in the exit2-ir state. the cont roller will remain in the pause-ir state if jtms is low during a rising edge on jtclk. exit2-ir a rising edge on jtclk with jtms low will put the controller in the update-ir state. the controller will loop back to shift-ir if jtms is high during a rising edge of jtclk in this state.
ds2196 127 of 157 update-ir the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jt ms low, will put the controller in the run-test-idle state. with jtms high, the controller will enter the select-dr-scan state. figure 20-2: tap controller state machine 20.3 instruction register and instructions the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, th e instruction shift register will be connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low will shift the data one stage towards the serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the exit2- ir state with jtms high will move the controller to the update-ir state the falling edge of that same jtclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the ds2196 with their respective opera tional binary codes are shown in table 20-1. 1 0 0 1 11 1 1 1 1 1 11 1 1 00 00 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
ds2196 128 of 157 table 20-1: instruction codes for the ds 21352/552 ieee 1149.1 architecture instruction selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp boundary scan 011 highz boundary scan 100 idcode device identification 001 sample/preload a mandatory instruction for the ieee 1149.1 specificati on. this instruction supports two functions. the digital i/os of the ds2196 can be sampled at the bounda ry scan register without interfering with the normal operation of the device by using the capture- dr state. sample/preload also allows the ds2196 to shift data into the boundary scan re gister via jtdi using the shift-dr state. extest extest allows testing of all inte rconnections to the ds2196. when th e extest instruction is latched in the instruction register, the following actions occur. once enabled via the update-ir state, the parallel outputs of all digital output pins will be driven. the boundary scan register will be connected between jtdi and jtdo. the capture-dr will sample a ll digital inputs into the boundary scan register. bypass when the bypass instruction is latched into the parallel instruction register, jtdi connects to jtdo through the 1-bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation. idcode when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code will be loaded into the identification register on the rising edge of jtclk following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially via jtdo. during test-logic-reset, the identification code is forced into the instruction register?s parallel output. the id c ode will always have a ?1? in the lsb position. the next 11 bits identify the manufacturer?s jedec numbe r and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. see figure 20-3. tabl e 20-2 lists the device id codes for the ds2196. table 20-2: id code structure msb lsb contents version (contact factory) device id (see table 20-3) jedec ?00010100001? ?1? length 4 bits 16 bits 11 bits 1 bit
ds2196 129 of 157 table 20-3: device id codes device 16-bit number ds2196 0009 h highz all digital outputs of the ds2196 will be placed in a high impedance state. the bypass register will be connected between jtdi and jtdo. clamp all digital outputs of the ds2196 will output da ta from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs will not change during the clamp instruction. test registers ieee 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. an optional test register has been included with the ds 2196 design. this test register is the identification register and is used in conjunction with the idcode instruction and the test-logic-reset state of the tap controller. boundary scan register this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells and is 126 bits in length. table 20- 3 shows all of the cell bit locations and definitions. bypass register this is a single 1-bit shift register used in conjunction with the bypass, clamp, and highz instructions, which provides a s hort path between jtdi and jtdo. identification register the identification register contains a 32-bit shift register and a 32-bit latc hed parallel output. this register is selected during the idcode instruction and when the tap controller is in the test-logic- reset state.
ds2196 130 of 157 table 20-4: boundary scan register description pin scan register bit symbol type control bit description 13 pclki 22 pnrzi 31 wclki 40 wnrzi 5- jtmsi 6- jtclki 7- jtrst*i 8- jtdii 9- jtdoo 10 83 rcl o 11 82 lnrz o 12 81 lclk o 13 80 lfsync o 14 79 rposlo o 15 78 rneglo o 16 77 rclklo o 17 76 bts i 18 - rtip i 19 - rring i 20 - rvdd - 21 - rvss - 22 75 int* o 23 - rvss - 24 - mclk i 25 74 uop3 o 26 73 uop2 o 27 72 uop1 o 28 71 uop0 o 29 - ttip o 30 - tvss - 31 - tvdd - 32 - tring o 33 70 tposli i 34 69 tnegli i 35 68 tclkli i 67 tchblkb/ tlinkb control - 0 = tlinkb an input 1 = tchblkb an output 36 66 tchblkb/ tlinkb i/o 37 65 tchclkb/ tlclkb o
ds2196 131 of 157 pin scan register bit symbol type control bit description 64 tsyncb control - 0 = tsyncb an input 1 = tsyncb an output 38 63 tsyncb i/o 39 62 tclkb i 40 61 tserb i 41 60 tposob/ tnrzb o 42 59 tnegob / tfsyncb o 43 58 tclkob o 44 - dvss - 45 - dvdd - 46 57 tclkoa o 47 56 tnegoa / tfsynca o 48 55 tposoa / tnrza o 49 54 tsera i 50 53 tclka i 52 tsynca control - 0 = tsynca an input 1 = tsynca an output 51 51 tsynca i/o 52 50 tchclka / tlclka o 49 tchblka / tlinka control - 0 = tlinka an input 1 = tchblka an output 53 48 tchblka / tlinka i/o 54 47 mux i 46 bus control - 0 = d0?d7/a0-a7 are inputs 1 = d0?d7/a0-a7 are outputs 55 45 d0 / ad0 i/o 56 44 d1 / ad1 i/o 57 43 d2 / ad2 i/o 58 42 d3 / ad3 i/o 59 41 d4 / ad4 i/o 60 40 d5 / ad5 i/o 61 39 d6 / ad6 i/o 62 38 d7 / ad7 i/o 63 - dvss - 64 - dvdd - 65 37 a0 i 66 36 a1 i 67 35 a2 i 68 34 a3 i
ds2196 132 of 157 pin scan register bit symbol type control bit description 69 33 a4 i 70 32 a5 i 71 31 a6 i 72 30 a7 / ale i 73 29 rd*(ds*) i 74 28 cs* i 75 27 wr*(r/w*) i 76 26 rchblka / rlinka o 77 25 rchclka / rlclka o 78 24 rclkia i 79 23 rposia i 80 22 rnegia i 81 21 rclka o 82 20 rsera o 83 19 rmsynca o 84 18 rfsynca o 85 17 rlosa/ lotca o 86 16 rbpva o 87 - dvss - 88 - dvdd - 89 15 rbpvb o 90 14 rlosb/ lotcb o 91 13 rfsyncb o 92 12 rmsyncb o 93 11 rserb o 94 10 rclkb o 95 9 rnegib i 96 8 rposib i 97 7 rclkib i 98 6 rchclkb / rlclkb o 99 5 rchblkb / rlinkb o 100 4 wps i
ds2196 133 of 157 frame# 12345678910111212345 rfsync 1 rmsync rfsync 2 rlclk rlink 3 notes: 1. rfsync double-wide frame sync is not enabled (rcr2.5 = 0) 2. rfsync double-wide frame sync is enabled (rcr2.5 = 1) 3. rlink data ( fs - bits ) is u p dated one bit p rior to even frames and held for two frames 21. timing diagrams figure 21-1: receive side d4 timing
ds2196 134 of 157 12 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 frame# rfsync rmsync 1 2 rfsync rlclk rlink 3 4 rlclk rlink 5 6 notes: 1. rfsync double-wide frame sync is not enabled (rcr2.5 = 0) 2. rfsync double-wide frame sync is enabled (rcr2.5 = 1) 3. zbtsi mode disabled (rcr2.6 = 0) 4. rlink data (fdl bits) is updated one bit time before odd frames and held for two frames 5. zbtsi mode is enabled (rcr2.6 = 1) 6. rlink data ( z bits ) is u p dated one bit time before odd frames and held for four frames figure 21-2: receive side esf timing
ds2196 135 of 157 figure 21-3: receive side boundary timing rclk rchclk rmsync rchblk 3 notes: 1. rlos transitions high during the f-bit time that caused an oof event or when loss of carrier is detected. 2. rbpv transitions high when the bit in error emerges from rser. if b8zs is enabled, rbpv will not report the zero replacement code. 3. rchblk is programmed to block channel 24. 4. shown is rlink/rlclk in the esf framin g mod e rlclk rlink rser lsb msb f msb channel 23 channel 24 lsb channel 1 rfsync 4 rbpv rlos 2 1
ds2196 136 of 157 figure 21-4: transmit side d4 timing frame# 12345678910111212345 1 2 3 4 tsync / tfsync tsync tsync tlclk tlink notes: 1. tsync in the frame mode (tcr2.3 = 0) and double-wide frame sync is not enabled (tcr2.4 = 0) 2. tsync in the frame mode (tcr2.3 = 0) and double-wide frame sync is enabled (tcr2.4 = 1) 3. tsync in the multiframe mode (tcr2.3 = 1) 4. tlink data (fs - bits) is sampled during the f-bit position of even frames for insertion into the out g oin g t1 stream when enabled via tcr1. 2
ds2196 137 of 157 figure 21-5: transmit side esf timing 12 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 frame# 1 2 3 4 6 7 tsync tsync tsync tlclk tlink tlclk tlink notes: 1. tsync in the frame mode (tcr2.3 = 0) and double-wide frame sync is not enabled (tcr2.4 = 0) 2. tsync in the frame mode (tcr2.3 = 0) and double-wide frame sync is enabled (tcr2.4 = 1) 3. tsync in the multiframe mode (tcr2.3 = 1) 4. zbtsi mode disabled (tcr2.5 = 0) 5. tlink data (fdl bits) is sampled during the f-bit time of odd frame and inserted into the outgoing t1 stream if enabled via tcr1.2 6. zbtsi mode is enabled (tcr2.5 = 1) 7. tlink data (z bits) is sampled during the f-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled via tcr1.2 8. tlink and tlclk are not s y nchronous with tfsyn c
ds2196 138 of 157 figure 21-6: transmit side boundary timing tclk tser lsb msb f msb channel 1 lsb tchclk tsync tchblk n otes: 1. tsync is in the output mode (tcr2.2 = 1) 2. tsync is in the input mode (tcr2.2 = 0) 3. tchblk is programmed to block channel 4. shown is tlink/tlclk in the esf framing d tlclk tlink lsb msb channel 2 tsync don't care 2 1 4 3
ds2196 139 of 157 figure 21-7: transmit data flow idle code / per channel lb = register = device pin = selector tir1 to tir3 software signaling insertion ts1 to ts12 bit 7 stuffing f-bit mux crc mux ami or b8zs converter / blue alarm gen. software signaling enable (tcr1.4) to waveshaping, filters, and line drivers transmit blue (tcr1.1) b8zs enable (ccr2.6) crc insertion frame mode select (ccr2.7) d4 yellow alarm select (tcr2.1) transmit yellow (tcr1.0) ttr1 to ttr3 bit 7 zero suppression enable (tcr2.0) global bit 7 stuffing (tcr1.3) frame mode select (ccr2.7) crc pass through (tcr1.5) frame mode select (ccr2.7) key: d4 bit 2 yellow alarm insertion d4 12th fs bit yellow alarm gen. frame mode select (ccr2.7) d4 yellow alarm select (tcr2.1) transmit yellow (tcr1.0) esf yellow alarm gen. (00ff hex in the fdl) frame mode select (ccr2.7) transmit yellow (tcr1.0) 1 0 1 0 10 01 ds2152 transmit data flow figure 15.11 fps or ft bit insertion tfdl select (tcr1.2) tfdl tlink 1 0 1 0 hdlc/boc enable (tboc.6) tir function select (ccr4.0) tidr 1 0 rser in-band loop code generator ibcc tdr ccr3.1 (note#1) notes: 1. tclk should be tied to rclk and tsync should be tied to rfsync for data to be p ro p erl y sourced from rser. tser / tdata 10 hdlc controller tdc2 ds0 insertion enable (tdc1.7) 1 0 tdc1.5 tchblk fdl mux 1 f-bit pass through (tcr1.6) tcd1 (4:0) boc controller tboc.7 1 0 bert generator & detector error insertion function error rate control (erc) number of errors (noe1, noe2) bert function (section 15) ch 1-12 & 13-24 ais enable ch 1-12 ais enable (ccr7.4) ch 13-24 ais enable (ccr7.5) crc calculation
ds2196 140 of 157 figure 21-8: receive data flow rcr2.7 rmr1 to rmr3 signaling extraction receive mark code insertion rnegi rposi b8zs decoder 01 rser ccr1.5 signaling all ones rs1 to rs12 receive code select channel enables receive signaling
ds2196 141 of 157 22. operating parameters absolute maximum ratings* voltage on any lead with respec t to vss (except vdd) ?0.3v to +5.5v supply voltage (vdd) with respect to vss ?0.3v to +3.63v operating temperature for ds2196l 0oc to +70oc operating temperature for DS2196LN ?40oc to +85oc storage temperature ?55oc to +125oc soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at th ese or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0oc to +70oc for ds2196l) (-40oc to +85oc for DS2196LN) parameter symbol min typ max units notes logic 1 v ih 2.0 5.5 v logic 0 v il ?0.3 +0.8 v supply v dd 3.135 3.465 v 1 capacitance (t a =25oc) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf dc characteristics (0oc to +70oc; v dd = 3.135 to 3.465v for ds2196l) (-40oc to +85oc; v dd = 3.135 to 3.465v for DS2196LN) parameter symbol min typ max units notes supply current @ 3.3v i dd 85 ma 2 input leakage i il ?1.0 +1.0 a 3 output leakage i lo 10 a 4 output current (2.4v) i oh ?1.0 ma output current (0.4v) i ol +4.0 ma notes: 1. applies to rvdd, tvdd, and dvdd. 2. tclk=rclk=mclk=1.544 mhz; ttip & tring loaded, other outputs open circuited. 3. 0.0v < v in < v dd . 4. applied to int when 3?stated.
ds2196 142 of 157 ac characteristics ? multiplexed parallel port (mux=1) (0oc to +70oc; v dd = 3.135 to 3.465v for ds2196l) (-40oc to +85oc; v dd = 3.135 to 3.465v for DS2196LN) parameter symbol min typ max units notes cycle time t cyc 200 ns pulse width, ds low or rd* high pw el 100 ns pulse width, ds high or rd* low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w* hold time t rwh 10 ns r/w* set up time before ds high t rws 50 ns cs* set up time before ds, wr* or rd* active t cs 20 ns cs* hold time t ch 0ns read data hold time t dhr 10 50 ns write data hold time t dhw 0ns mux?d address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr* or rd* to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr* or rd* t ased 10 ns output data delay time from ds or rd* t ddr 20 150 ns data set up time t dsw 50 ns (see figures 22-1 to 22-3 for details)
ds2196 143 of 157 ac characteristics ? non?multiplexed parallel port (mux=0 ) (0oc to +70oc; v dd = 3.135 to 3.465v for ds2196l) (-40oc to +85oc; v dd = 3.135 to 3.465v for DS2196LN) parameter symbol min typ max units notes set up time for a0 to a7 valid to cs* active t 1 0ns set up time for cs* active to either rd*, wr*, or ds* active t 2 0ns delay time from either rd* or ds* active to data valid t 3 150 ns hold time from either rd*, wr*, or ds* inactive to cs* inactive t 4 0ns hold time from cs* inactive to data bus 3? state t 5 520ns wait time from either wr* or ds* active to latch data t 6 75 ns data set up time to either wr* or ds* inactive t 7 10 ns data hold time from either wr* or ds* inactive t 8 10 ns address hold from either wr* or ds* inactive t 9 10 ns see figures 22?4 to 22?7 for details.
ds2196 144 of 157 ac characteristics ? receive side (0oc to +70oc; v dd = 3.135 to 3.465v for ds2196l) (-40oc to +85oc; v dd = 3.135 to 3.465v for DS2196LN) parameter symbol min typ max units notes rclklo period t lp 648 ns rclklo pulse width t lh t ll 250 250 324 324 ns ns 1 1 rclklo pulse width t lh t cl 200 200 324 324 ns ns 2 2 rclki period t cp 648 ns rclki pulse width t ch t cl 75 75 ns ns rposi/rnegi set up to rclki falling t su 20 ns rposi/rnegi hold from rclki falling t hd 20 ns rclki rise and fall times t r , t f 25 ns delay rclklo to rposlo, rneglo valid t dd 50 ns delay rclk to rser, rlink valid t d1 50 ns delay rclk to rchclk, rfsync, rmsync, rchblk, rlclk t d2 50 ns delay wclk/pclk to wnrz, pnrz t d3 50 ns see figures 22-8 to 22-9 for details. notes: 1. jitter attenuator enabled in the receive path. 2. jitter attenuator disabled in the receive path.
ds2196 145 of 157 ac characteristics ? transmit side (0oc to +70oc; v dd = 3.135 to 3.465v for ds2196l) (-40oc to +85oc; v dd = 3.135 to 3.465v for DS2196LN) parameter symbol min typ max units notes tclk period t cp 648 ns tclk pulse width t ch t cl 75 75 ns ns tclkli period t lp 648 ns tclkli pulse width t lh t ll 75 75 ns ns tsync set up to tclk falling t su 20 t ch ?5 or t sh ?5 ns tsync pulse width t pw 50 ns tser, tlink set up to tclk falling t su 20 ns tposli, tnegli set up to tclkli falling t su 20 ns tser, tlink hold from tclk falling t hd 20 ns tposli, tnegli hold from tclkli falling t hd 20 ns tclk, tclki rise and fall times t r , t f 25 ns delay tclko to tposo, tnego valid t dd 50 ns delay tclk to tchblk, tchblk, tsync, tlclk t d2 50 ns see figures 22?10 to 22?11 for details.
ds2196 146 of 157 figure 22-1: intel bus read ac timing (bts=0 / mux = 1) ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased cs* ad0-ad7 dhr t ddr ale rd* wr*
ds2196 147 of 157 figure 22-2: intel bus write timing (bts=0 / mux=1) ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl ds w dhw ch cs asl ased cs* ad0-ad7 rd* wr* ale
ds2196 148 of 157 figure 22-3: motorola bus ac timing (bts = 1 / mux = 1) t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws ahl pw el t cyc as ds ad0-ad7 (write) ad0-ad7 (read) r/w* cs*
ds2196 149 of 157 figure 22-4: intel bus read ac timing (bts=0 / mux=0) address valid data valid a0 to a7 d0 to d7 wr* cs* rd* t1 t2 t3 t4 t5
ds2196 150 of 157 figure 22-5: intel bus write ac timing (bts=0 / mux=0) address valid a0 to a7 d0 to d7 rd* cs* w r* t1 t2 t6 t4 t7 t8
ds2196 151 of 157 figure 22-6: motorola bus read ac timing (bts=1 / mux=0) address valid data valid a0 to a7 d0 to d7 r/w* cs* d s * t1 t2 t3 t4 t5
ds2196 152 of 157 figure 22-7: motorola bus write ac timing (bts=1 / mux=0) address valid a0 to a7 d0 to d7 r/w* cs* ds* t1 t2 t6 t4 t7 t8
ds2196 153 of 157 figure 22-8: receive side ac timing t d1 t d2 t d2 t d2 t d2 rser rchclk rchblk rsync rlclk rlink t d1 notes: 1. shown is rlink/rlclk in the esf framing mode. 2. no relationshi p between rchclk and rchblk and the other si g nals is im p lied. rclk 1
ds2196 154 of 157 figure 22-9: receive line interface ac timing t f t r rposi, rnegi rclki cl t t cp ch t t su t hd t dd rposlo, rneglo rclklo ll t t lp lh t t f t r wnrz, pnrz wclk, pclki cl t t cp ch t t su t hd
ds2196 155 of 157 figure 22-10: transmit side ac timing t f t r 1 tclk tser tchclk t t cl t ch cp tsync tsync tlink tlclk tchblk t d2 t d2 t d2 t t t t t hd su d2 su hd t hd 2 notes: 1. tsync is in the output mode (tcr2.2 = 1). 2. tsync is in the input mode (tcr2.2 = 0). 3. tser is sampled on the falling edge of tclk when the transmit side elastic store is disabled. 4. tchclk and tchblk are synchronous with tclk when the transmit side elastic store is disabled. 5. tlink is only sampled during f-bit locations. 6. no relationshi p between tchclk and tchblk and the other si g nals is im p lied. 5 t su
ds2196 156 of 157 figure 22-11: transmit line interface side ac timing tclko tposo, tnego t f t r tclkli tposli, tnegli t t ll t lh lp t hd t su tfsync t dd
ds2196 157 of 157 23. 100-pin lqfp package specifications

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