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4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 1 4 meg x 4 edo dram technology, inc. 4 meg x 4 edo dram part numbers part number vcc refresh package refresh MT4LC4M4E8DJ 3.3v 2k soj standard MT4LC4M4E8DJs 3.3v 2k soj self mt4lc4m4e8tg 3.3v 2k tsop standard mt4lc4m4e8tgs 3.3v 2k tsop self mt4lc4m4e9dj 3.3v 4k soj standard mt4lc4m4e9djs 3.3v 4k soj self mt4lc4m4e9tg 3.3v 4k tsop standard mt4lc4m4e9tgs 3.3v 4k tsop self mt4c4m4e8dj 5v 2k soj standard mt4c4m4e8djs 5v 2k soj self mt4c4m4e8tg 5v 2k tsop standard mt4c4m4e8tgs 5v 2k tsop self mt4c4m4e9dj 5v 4k soj standard mt4c4m4e9djs 5v 4k soj self mt4c4m4e9tg 5v 4k tsop standard mt4c4m4e9tgs 5v 4k tsop self mt4lc4m4e8, mt4c4m4e8 mt4lc4m4e9, mt4c4m4e9 dram features ? industry-standard x4 pinout, timing, functions and packages ? state-of-the-art, high-performance, low-power cmos silicon-gate process ? single power supply (+3.3v 0.3v or +5v 10%) ? all inputs, outputs and clocks are ttl-compatible ? refresh modes: ras#-only, hidden and cas#- before-ras# (cbr) ? optional self refresh (s) for low-power data retention ? 11 row, 11 column addresses (2k refresh) or 12 row, 10 column addresses (4k refresh) ? extended data-out (edo) page mode access cycle ? 5v-tolerant inputs and i/os on 3.3v devices options marking ? voltages 3.3v lc 5v c ? refresh addressing 2,048 (i.e. 2k) rows e8 4,096 (i.e. 4k) rows e9 ? packages plastic soj (300 mil) dj plastic tsop (300 mil) tg ? timing 50ns access -5 60ns access -6 ? refresh rates standard refresh none self refresh (128ms period) s ? part number example: MT4LC4M4E8DJ-6 note: the 4 meg x 4 edo dram base number differentiates the offerings in two places - mt4 lc4m4 e8. the third field distinguishes the low voltage offering: lc designates v cc = 3.3v and c designates v cc = 5v. the fifth field distinguishes various options: e8 designates a 2k refresh and e9 designates a 4k refresh for edo drams. pin assignment (top view) 24/26-pin soj (da-2) v cc dq1 dq2 we# ras# *nc/a11 a10 a0 a1 a2 a3 v cc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 v ss dq4 dq3 cas# oe# a9 a8 a7 a6 a5 a4 v ss v cc dq1 dq2 we# ras# *nc/a11 a10 a0 a1 a2 a3 v cc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 v ss dq4 dq3 cas# oe# a9 a8 a7 a6 a5 a4 v ss 24/26-pin tsop (db-2) * nc on 2k refresh and a11 on 4k refresh options. general description the 4 meg x 4 dram is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 con- figuration. ras# is used to latch the row address (first 11 bits for 2k and first 12 bits for 4k). once the page has been opened by ras#, cas# is used to latch the column address key timing parameters speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 10ns note: the # symbol indicates signal is active low.
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 2 4 meg x 4 edo dram technology, inc. general description (continued) (the latter 11 bits for 2k and the latter 10 bits for 4k, address pins a10 and a11 are dont care). read and write cycles are selected with the we# input. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. an early write occurs when we# is taken low prior to cas# falling. a late write or read-modify-write occurs when we# falls after cas# is taken low. during early write cycles, the data outputs (q) will remain high-z regardless of the state of oe#. during late write or read-modify- write cycles, oe# must be taken high to disable the data outputs prior to applying input data. if a late write or read-modify-write is attempted while keeping oe# low, no write will occur, and the data outputs will drive read data from the accessed location. the four data inputs and the four data outputs are routed through four pins using common i/o, and pin direction is controlled by we# and oe#. page access page operations allow faster data operations (read, write or read-modify-write) within a row address- defined page boundary. the page cycle is always initiated figure 1 oe# control of dqs with a row address strobed-in by ras#, followed by a column address strobed-in by cas#. cas# may be toggled-in by holding ras# low and strobing-in different column addresses, thus executing faster memory cycles. returning ras# high terminates the page mode of operation, i.e., closes the page. edo page mode the 4 meg x 4 edo dram provides edo page mode, which is an accelerated fast page mode cycle. the primary advantage of edo is the availability of data-out even after cas# returns high. edo allows cas# precharge time ( t cp) to occur without the output data going invalid. this elimination of cas# output control allows pipeline reads. fast page mode drams have traditionally turned the output buffers off (high-z) with the rising edge of cas#. edo page mode drams operate like fast page mode drams, except data will remain valid or become valid after cas# goes high during reads, pro- vided ras# and oe# are held low. if oe# is pulsed while ras# and cas# are low, data will toggle from valid data to high-z and back to the same valid data. if oe# is toggled or pulsed after cas# goes high while ras# remains low, data will transition to and remain high-z (refer to v v ih il cas# v v ih il ras# v v ih il addr row column (a) column (b) don?t care undefined v v ih il oe# v v ioh iol open dq t od valid data (b) valid data (a) column (c) valid data (a) t oe valid data (c) column (d) valid data (d) t od t oehc t od t oep t oes the dqs go back to low-z if t oes is met. the dqs remain high-z until the next cas# cycle if t oehc is met. the dqs remain high-z until the next cas# cycle if t oep is met.
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 3 4 meg x 4 edo dram technology, inc. figure 1). we# can also perform the function of disabling the output devices under certain conditions, as shown in figure 2. during an application, if the dq outputs are wire ord, oe# must be used to disable idle banks of drams. alter- natively, pulsing we# to the idle banks during cas# high time will also high-z the outputs. independent of oe# control, the outputs will disable after t off, which is refer- enced from the rising edge of ras# or cas#, whichever occurs last. refresh preserve correct memory cell data by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr or hidden) so that all combinations of ras# addresses (2,048 for 2k and 4,096 for 4k) are executed within t ref (max), regardless of se- quence. the cbr and self refresh cycles will invoke the internal refresh counter for automatic ras# addressing. an optional self refresh mode is also available on the s version. the s option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms. the optional self refresh feature is initiated by performing a cbr re- fresh cycle and holding ras# low for the specified t rass. additionally, the s option allows for an extended refresh period of 128ms, or 31.25 m s per row for a 4k refresh and 62.5 m s per row for a 2k refresh if using distributed cbr refresh. this refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. the self refresh mode is terminated by driving ras# high for a minimum time of t rps. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras# low-to-high transition. if the dram controller uses a distributed refresh se- quence, a burst refresh is not required upon exiting self refresh . however, if the dram controller utilizes a ras#- only or burst refresh sequence, all rows must be refreshed within the average internal refresh rate , prior to the resumption of normal operation. standby returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. the chip is preconditioned for the next cycle during the ras# high time. figure 2 we# control of dqs v v ih il cas# v v ih il ras# v v ih il addr row column (a) don?t care undefined v v ih il we# v v ioh iol open dq t wpz the dqs go to high-z if we# falls and, if t wpz is met, will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). v v ih il oe# valid data (b) t whz we# may be used to disable the dqs to prepare for input data in an early write cycle. the dqs will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). t whz column (d) valid data (a) column (b) column (c) input data (c)
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 4 4 meg x 4 edo dram technology, inc. functional block diagram - 2k refresh 2048 2048 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ras# 11 11 11 no. 2 clock generator refresh controller no. 1 clock generator v dd v ss 11 we# cas# 10 column address buffer(11) row address buffers (11) 2048 row decoder 2048 1024 column decoder oe# dq1 dq2 dq3 dq4 4 4 4 4 refresh counter 1 row transfer (1 of 2) row transfer (1 of 2) 1024 4096 x 1024 x 4 memory array sense amplifiers i/o gating data-out buffer data-in buffer complement select 2048 row select (2 of 4096) functional block diagram - 4k refresh 4096 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ras# 12 12 10 no. 2 clock generator refresh controller no. 1 clock generator v dd v ss 12 we# cas# 10 column address buffer(10) row address buffers (12) row decoder 4096 1024 column decoder oe# dq1 dq2 dq3 dq4 4 4 4 4 refresh counter 1024 4096 x 1024 x 4 memory array sense amplifiers i/o gating data-out buffer data-in buffer complement select 4096 row select (1 of 4096)
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 5 4 meg x 4 edo dram technology, inc. truth table addresses data-in/out function ras# cas# we# oe# t r t c dq1-dq4 standby h h ? xxxxx high-z read l l h l row col data-out early write l l l x row col data-in read write l l h ? ll ? h row col data-out, data-in edo-page-mode 1st cycle l h ? l h l row col data-out read 2nd cycle l h ? l h l n/a col data-out edo-page-mode 1st cycle l h ? l l x row col data-in early write 2nd cycle l h ? l l x n/a col data-in any cycle l l ? h h l n/a n/a data-out edo-page-mode 1st cycle l h ? lh ? ll ? h row col data-out, data-in read-write 2nd cycle l h ? lh ? ll ? h n/a col data-out, data-in hidden read l ? h ? l l h l row col data-out refresh write l ? h ? l l l x row col data-in ras#-only refresh l h x x row n/a high-z cbr refresh h ? l l h x x x high-z self refresh h ? l l h x x x high-z
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 6 4 meg x 4 edo dram technology, inc. absolute maximum ratings* voltage on v cc pin relative to v ss : 3.3v ................................................................ -1v to +4.6v 5v ...................................................................... -1v to +7v voltage on nc, inputs or i/o pins relative to v ss : 3.3v ................................................................ -1v to +5.5v 5v ...................................................................... -1v to +7v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +150 c power dissipation ............................................................. 1w short circuit output current ..................................... 50ma *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1) 3.3v 5v parameter/condition symbol min max min max units notes supply voltage v cc 3.0 3.6 4.5 5.5 v input high voltage: valid logic 1; all inputs, i/os and any nc v ih 2.0 5.5 2.4 v cc +1 v input low voltage: valid logic 0; all inputs, i/os and any n c v i l -1. 0 0. 8 - 0 . 5 0. 8 v input leakage current: any input at v in (0v v in v ih [max]) ; i i -2 2 -2 2 m a 4 all other pins not under test = 0v output high voltage: i out = -2ma (3.3v), -5ma (5v) v oh 2.4 - 2.4 - v output low voltage: i out = 2ma (3.3v), 4.2ma (5v) v ol - 0.4 - 0.4 v output leakage current: any output at v out (0v v out 5.5v); i oz -5 5 -5 5 m a dq is disabled and in high-z state
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 7 4 meg x 4 edo dram technology, inc. icc operating conditions and maximum limits (notes: 1, 2, 3) 3.3v 5v 2k 4k 2k 4k parameter/condition sym speed refresh refresh refresh refresh units notes standby current: ttl i cc 1 all1111ma (ras# = cas# = v ih ) standby current: cmos (non-s version only) i cc 2 all 500 500 500 500 m a (ras# = cas# = other inputs = v cc -0.2v) standby current: cmos (s version only) i cc 2 all 150 150 150 150 m a (ras# = cas# = other inputs = v cc -0.2v) operating current: random read/write -5 110 90 140 120 ma 5, 6 average power supply current i cc 3 -6 100 80 130 110 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: edo page mode -5 110 100 110 100 ma 5, 6 average power supply current (ras# = v il ,i cc 4 -6 100 90 100 90 cas#, address cycling: t pc = t pc [min]) refresh current: ras#-only -5 110 90 140 120 ma 5, 6 average power supply current i cc 5 -6 100 80 130 110 (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr -5 110 90 140 120 ma 5, 7 average power supply current i cc 6 -6 100 80 130 110 (ras#, cas#, address cycling: t rc = t rc [min]) refresh current: extended (s version only) average power supply current: cas# = 0.2v or all 300 300 300 300 m a 5, 7 cbr cycling; ras# = t ras (min); we# = i cc 7 v cc -0.2v; a0-a11,oe# and d in = v cc -0.2v or t rc 62.5 31.25 62.5 31.25 m s25 0.2v (d in may be left open) refresh current: self (s version only) average power supply current: cbr with ras# 3 t rass (min) and cas# held low; we# = i cc 8 all 300 300 300 300 m a 5, 7 v cc -0.2v; a0-a11, oe# and d in = v cc -0.2v or 0.2v (d in may be left open)
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 8 4 meg x 4 edo dram technology, inc. ac electrical characteristics (notes: 2, 3, 9, 10, 11, 12, 17) (v cc [min] v cc v cc [max]) ac characteristics -5 -6 parameter symbol min max min max units notes access time from column address t aa 25 30 ns column address setup to cas# precharge t ach 12 15 ns column address hold time (referenced to ras#) t ar 38 45 ns column address setup time t asc 0 0 ns row address setup time t asr 0 0 ns column address to we# delay time t awd 42 49 ns 13 access time from cas# t cac 13 15 ns 14 column address hold time t cah 8 10 ns cas# pulse width t cas 8 10,000 10 10,000 ns cas# low to dont care during self refresh t chd 15 15 ns cas# hold time (cbr refresh) t chr 8 10 ns 7 cas# to output in low-z t clz 0 0 ns data output hold after next cas# low t coh 3 3 ns cas# precharge time t cp 8 10 ns 15 access time from cas# precharge t cpa 28 35 ns cas# to ras# precharge time t crp 5 5 ns cas# hold time t csh 38 45 ns cas# setup time (cbr refresh) t csr 5 5 ns cas# to we# delay time t cwd 28 35 ns 13 write command to cas# lead time t cwl 8 10 ns data-in hold time t dh 8 10 ns 16 data-in setup time t ds 0 0 ns 16 output disable t od 0 12 0 15 ns output enable t oe 12 15 ns 17 oe# hold time from we# during t oeh 8 10 ns 18 read-modify-write cycle oe# high hold from cas# high t oehc 5 10 ns 18 oe# high pulse width t oep 5 5 ns oe# low to cas# high setup time t oes 4 5 ns output buffer turn-off delay t off 0 12 0 15 ns 20 capacitance parameter symbol max units notes input capacitance: address pins c i 1 5pf8 input capacitance: ras#, cas#, we#, oe# c i 2 7pf8 input/output capacitance: dq c io 7pf8
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 9 4 meg x 4 edo dram technology, inc. ac electrical characteristics (notes: 2, 3, 9, 10, 11, 12, 17) (v cc [min] v cc v cc [max]) ac characteristics -5 -6 parameter symbol min max min max units notes oe# setup prior to ras# during t ord 0 0 ns hidden refresh cycle edo-page-mode read or write cycle time t pc 20 25 ns edo-page-mode read-write cycle time t prwc 47 56 ns access time from ras# t rac 50 60 ns 19 ras# to column address delay time t rad 9 12 ns 21 row address hold time t rah 9 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (edo page mode) t rasp 50 125,000 60 125,000 ns ras# pulse width during self refresh t rass 100 100 m s random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 11 14 ns 22 read command hold time (referenced to cas#) t rch 0 0 ns 23 read command setup time t rcs 0 0 ns refresh period (2,048 cycles) t ref 32 32 ms refresh period (4,096 cycles) t ref 64 64 ms refresh period s version t ref 128 128 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns ras# precharge time exiting self refresh t rps 90 105 ns read command hold time (referenced to ras#) t rrh 0 0 ns 23 ras# hold time t rsh 13 15 ns read write cycle time t rwc 116 140 ns ras# to we# delay time t rwd 67 79 ns 13 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns write command hold time (referenced to ras#) t wcr 38 45 ns we# command setup time t wcs 0 0 ns 13 output disable delay from we# t whz 0 12 0 15 ns write command pulse width t wp 5 5 ns we# pulse to disable at cas# high t wpz 10 10 ns we# hold time (cbr refresh) t wrh 8 10 ns we# setup time (cbr refresh) t wrp 8 10 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 10 4 meg x 4 edo dram technology, inc. notes 1. all voltages referenced to v ss . 2. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0?c t a 70?c) is ensured. 3. an initial pause of 100 m s is required after power-up, followed by eight ras# refresh cycles (ras#-only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 4. nc pins are assumed to be left floating and are not tested for leakage. 5. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 6. column address changed once each cycle. 7. enables on-chip refresh and address counters. 8. this parameter is sampled. v cc = v cc min ; f = 1 mhz. 9. ac characteristics assume t t = 2.5ns. 10. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 11. in addition to meeting the transition rate specifica- tion, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 12. measured with a load equivalent to two ttl gates and 100pf; and v ol = 0.8v and v oh = 2v. 13. t wcs, t rwd, t awd and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. t rwd, t awd and t cwd apply to read-modify-write cycles. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. if t wcs < t wcs (min) and t rwd 3 t rwd (min), t awd 3 t awd (min) and t cwd 3 t cwd (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of data-out is indeterminate. oe# held high and we# taken low after cas# goes low results in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle. 14. requires that t aa and t rac are not violated. 15. if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas# must be pulsed high for t cp. 16. these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 17. if oe# is tied permanently low, late write or read-modify-write operations are not permis- sible and should not be attempted. additionally, we# must be pulsed during cas# high time in order to place i/o buffers in high-z. 18. late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously read data if cas# remains low and oe# is taken back low after t oeh is met. if cas# goes high prior to oe# going back low, the dqs will remain open. 19. requires that t aa and t cac are not violated. 20. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . it is referenced from the rising edge of ras# or cas#, whichever occurs last. 21. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac and t cac must always be met. 22. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd limit, t aa and t cac must always be met. 23. either t rch or t rrh must be satisfied for a read cycle. 24. a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high. 25. the refresh period is extended from 32ms (2k refresh) or 64ms (4k refresh) to 128ms (both 2k and 4k refreshes). for 4k refresh, t rc = 31.25 m s (128ms/ 4,096 rows = 31.25 m s) and for 2k refresh, t rc = 62.5 m s (128ms/2,048 rows = 62.5 m s).
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 11 4 meg x 4 edo dram technology, inc. read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column cas# we# note 1 t ach don?t care undefined note: 1. t off is referenced from rising edge of ras# or cas#, whichever occurs last. -5 -6 symbol min max min max units t off 0 12 0 15 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t rp 30 40 ns t rrh 0 0 ns t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t csh 38 45 ns t od 0 12 0 15 ns t oe 12 15 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 12 4 meg x 4 edo dram technology, inc. early write cycle don? care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh we# cas# t ach -5 -6 symbol min max min max units t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rcd 11 14 ns t rp 30 40 ns t rsh 13 15 ns t rwl 13 15 ns t wch 8 10 ns t wcr 38 45 ns t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t crp 5 5 ns t csh 38 45 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns t rad 9 12 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 13 4 meg x 4 edo dram technology, inc. read-write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh we# t ach cas# don?t care undefined -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 ns t oeh 8 10 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rcd 11 14 ns t rcs 0 0 ns t rp 30 40 ns t rsh 13 15 ns t rwc 116 140 ns t rwd 67 79 ns t rwl 13 15 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t awd 42 49 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t csh 38 45 ns t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 14 4 meg x 4 edo dram technology, inc. edo-page-mode read cycle valid data valid data valid data column column column row row don?t care undefined t od t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# t cas t cas cas# we# t coh t oep t oehc t oes t oes t ach t ach t ach -5 -6 symbol min max min max units t oehc 5 10 ns t oep 5 5 ns t oes 4 5 ns t off 0 12 0 15 ns t pc 20 25 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t rp 30 40 ns t rrh 0 0 ns t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 ns t crp 5 5 ns t csh 38 45 ns t od 0 12 0 15 ns t oe 12 15 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 15 4 meg x 4 edo dram technology, inc. edo-page-mode early write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ach t ach t ach t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# oe# v v ih il don?t care undefined -5 -6 symbol min max min max units t pc 20 25 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rp 30 40 ns t rsh 13 15 ns t rwl 13 15 ns t wch 8 10 ns t wcr 38 45 ns t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t cp 8 10 ns t crp 5 5 ns t csh 38 45 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 16 4 meg x 4 edo dram technology, inc. edo-page-mode read-write cycle (late write and read-modify-write cycles) don? care undefined t oe t oe t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t cas t rsh t cp t rp t rasp t cas t cp t cas t rcd t csh t pc t crp row column column column row v v ih il cas# v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# we# t prwc t oeh t od t od t od note 1 note: 1. t pc is for late write cycles only. -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 ns t oeh 8 10 ns t pc 20 25 ns t prwc 47 56 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rcs 0 0 ns t rp 30 40 ns t rsh 13 15 ns t rwd 67 79 ns t rwl 13 15 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t awd 42 49 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t cpa 28 35 ns t crp 5 5 ns t csh 38 45 ns t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 17 4 meg x 4 edo dram technology, inc. edo-page-mode read early write cycle (pseudo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ih il oe# v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid data in t rcs t rch t wcs t oe valid data (b) valid data (a) t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach cas# t cas t cas t cp t cp don?t care undefined -5 -6 symbol min max min max units t oe 12 15 ns t pc 20 25 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t rp 30 40 ns t rsh 13 15 ns t wch 8 10 ns t wcs 0 0 ns t whz 0 12 0 15 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ach 12 15 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 ns t crp 5 5 ns t csh 38 45 ns t dh 8 10 ns t ds 0 0 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 18 4 meg x 4 edo dram technology, inc. read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz don?t care undefined cas# -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t crp 5 5 ns t csh 38 45 ns t od 0 12 0 15 ns t oe 12 15 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t rcd 11 14 ns t rch 0 0 ns t rcs 0 0 ns t whz 0 12 0 15 ns t wpz 10 10 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 19 4 meg x 4 edo dram technology, inc. ras#-only refresh cycle (oe# and we# = dont care) row v v ih il cas# v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc cbr refresh cycle (addresses and oe# = dont care) t rp v v ih il ras# t ras open t chr t csr v v ih il v v oh ol cas# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh we# t wrp t wrh don?t care undefined -5 -6 symbol min max min max units t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rp 30 40 ns t rpc 5 5 ns t wrh 8 10 ns t wrp 8 10 ns timing parameters -5 -6 symbol min max min max units t asr 0 0 ns t chr 8 10 ns t cp 8 10 ns t crp 5 5 ns t csr 5 5 ns t rah 9 10 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 20 4 meg x 4 edo dram technology, inc. hidden refresh cycle 24 (we# = high; oe# = low) don? care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rp t chr t ras dq v v oh ol v v ih il addr v v ih il v v ih il ras# v v ih il t oe t od oe# t ord cas# -5 -6 symbol min max min max units t oe 12 15 ns t off 0 12 0 15 ns t ord 0 0 ns t rac 50 60 ns t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rcd 11 14 ns t rp 30 40 ns t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t aa 25 30 ns t ar 38 45 ns t asc 0 0 ns t asr 0 0 ns t cac 13 15 ns t cah 8 10 ns t chr 8 10 ns t clz 0 0 ns t crp 5 5 ns t od 0 12 0 15 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 21 4 meg x 4 edo dram technology, inc. self refresh cycle (addresses and oe# = dont care) v v ih il ras# t rass open v v ih il v v oh ol dq t rpc t chd t rps t rpc t rp t cp cas# we# v v ih il t wrh t wrp t wrh t wrp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note 1 t csr don't care undefined t cp note 2 ( ) ( ) ( ) ( ) note: 1. once t rass (min) is met and ras# remains low, the dram will enter self refresh mode. 2. once t rps is satisfied, a complete burst of all rows should be executed. -5 -6 symbol min max min max units t rpc 5 5 ns t rps 90 105 ns t wrh 8 10 ns t wrp 8 10 ns timing parameters -5 -6 symbol min max min max units t chd 15 15 ns t cp 8 10 ns t csr 5 5 ns t rass 100 100 m s t rp 30 40 ns
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 22 4 meg x 4 edo dram technology, inc. 24/26-pin plastic soj (300 mil) da-2 r .299 (7.59) .305 (7.75) .679 (17.25) .673 (17.09) .340 (8.64) .330 (8.38) .050 (1.27) typ .600 (15.24) typ pin #1 index .020 (0.51) .015 (0.38) .132 (3.35) .142 (3.61) .109 (2.77) .094 (2.39) .260 (6.60) .275 (6.99) .030 (0.76) .040 (1.02) seating plane .025 (0.64) min .037 (0.94) max dambar protrusion .026 (0.66) .032 (0.81) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
4 meg x 4 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d47.pm5 C rev. 3/97 ? 1997, micron technology, inc. 23 4 meg x 4 edo dram technology, inc. 24/26-pin plastic tsop (300 mil) db-2 .047 (1.20) max .367 (9.32) .359 (9.12) .302 (7.67) .298 (7.57) .050 (1.27) typ .678 (17.23) .672 (17.07) .020 (0.50) .012 (0.30) pin #1 index .037 (0.95) see detail a .007 (0.18) .005 (0.13) .004 (0.10) .024 (0.60) .016 (0.40) .006 (0.15) .002 (0.05) detail a .010 (0.25) .032 (0.80) typ gage plane seating plane note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900, micron datafax: 208-368-5800 e-mail: prodmktg@micron.com , internet: http://www.micron.com , customer comment line: 800-932-4992

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