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RT9046 1 ds9046-01 april 2011 www.richtek.com low-dropout linear regulator controller with pgood indication ordering information typical application circuit marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. function block diagram pin configurations (top view) sot-23-6 en gnd fb vcc dri pgood 4 23 5 6 general description the RT9046 is a low-dropout voltage regulator controller designed specifically for use with an external n-mosfet for various applications. the controller features a 2% reference, a high current driver capability of driving a high current/low r ds(on) n-mosfet, programmable output voltage, a power monitor with a 0.6ms delay, internal soft- start function, under voltage protection, and chip enable for power conservation. the device is also useful in other high current applications. the RT9046 is available in a small footprint package of sot-23-6. features z z z z z programmable output voltage z z z z z high current driver for high current fet z z z z z high accuracy 2% voltage reference z z z z z quick line and load transient response z z z z z power good monitor with output delay z z z z z internal soft-start function to reduce inrush current z z z z z enable control and under voltage protection z z z z z small footprint package sot-23-6 z z z z z rohs compliant and halogen free applications z large-scale, telecom blade systems z large-scale, mass storage blade systems z high current systems requiring sequencing z high current systems requiring power management + - - + reference voltage 0.5v 0.45v 0.6ms delay en dri fb vcc pgood gnd driver v cc v in pgood v out c out c in c cc r pgood r1 r2 q1 vcc dri pgood RT9046 4 5 6 v out = 0.5x[(r1+r2)/r2] en gnd fb 1 2 3 chip enable RT9046 package type e : sot-23-6 lead plating system g : green (halogen free and pb free)
RT9046 2 ds9046-01 april 2011 www.richtek.com test circuit figure 1. typical test circuit functional pin description pin no. pin name pin function 1 en chip enable (active high). 2 gnd ground. 3 fb output voltage feedback. 4 pgood power good open drain output. 5 dri driver output. 6 vcc power supply input. figure 2. dri source/sink current test circuit v in pgood v out r1 r2 q1 en gnd fb vcc dri pgood RT9046 1k 2k phd3055 chip enable v out = 0.5x[(r1+r2)/r2] r pgood 100k c cc 1f v cc 12v c in 100f c out 100f v cc c cc v dri c fb a en gnd fb vcc dri pgood RT9046 chip enable 1f 12v 5v v fb v fb = 0.7v for current sink at dri v fb = 0.3v for current source at dri
RT9046 3 ds9046-01 april 2011 www.richtek.com electrical characteristics (v cc = 5v/12v, t a = 25c, unless otherwise specified) parameter symbol test conditions min typ max unit por threshold v cc rising 2.6 2.85 3.2 v por hysteresis -- 0.2 -- v v cc supply current v cc = 12v -- 0.3 0.8 ma driver source current v cc = 12v, v dri = 6v 5 -- -- ma driver si nk current v cc = 12v, v dri = 6v 5 -- -- ma reference voltage (v fb ) v cc = 12v, v dri = 5v 0.49 0.5 0.51 v reference line regulation (v fb ) v cc = 4.5v to 15v -- 3 6 mv amplifier voltage gain v cc = 12v, no load -- 70 -- db psrr at 100hz v cc = 12v, no load 50 -- -- db power good rising threshold v cc = 12v -- 90 -- % hysteresis v cc = 12v -- 15 -- % sink capability v cc = 12v @ 1ma -- 0.2 0.4 v delay time v cc = 12v 0.2 0.6 2 ms falling delay v cc = 12v -- 15 -- s chip enable logic-high voltage v ih v cc = 12v 1.4 -- 5.5 en threshold logic-low voltage v il v cc = 12v -- -- 0.4 v standby current v cc = 12v, v en = 0v -- -- 5 a absolute maximum ratings (note 1) z supply input voltage, v cc ------------------------------------------------------------------------------------------- 15v z enable v oltage --------------------------------------------------------------------------------------------------------- 6.5v z power good output v oltage ---------------------------------------------------------------------------------------- 6.5v z power dissipation, p d @ t a = 25 c sot-23-6 ---------------------------------------------------------------------------------------------------------------- 0.4w z package thermal resistance (note 2) sot-23-6, ja ----------------------------------------------------------------------------------------------------------- 250 c /w z lead temperature (soldering, 10 se c.) --------------------------------------------------------------------------- 260 c z junction temperature ------------------------------------------------------------------------------------------------- 150 c z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c recommended operating conditions (note 3) z supply input voltage, v cc ------------------------------------------------------------------------------------------- 3.3v to 13.5v z enable v oltage --------------------------------------------------------------------------------------------------------- 0v to 5. 5v z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c to be continued
RT9046 4 ds9046-01 april 2011 www.richtek.com parameter symbol test c onditions min typ max u nit soft-start function output turn-on rise time v cc = 12v, v out = 1.5v, c out = 800 f 0.2 0.35 -- ms uv protection under voltage protection v cc = 12v 40 50 60 % note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective single layer thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. the device is not guaranteed to function outside its operating conditions.
RT9046 5 ds9046-01 april 2011 www.richtek.com typical operating characteristics v in = 1.8v, v out = 1.5v, v cc = 12v, c in = c out = 100 f, r 1 = 4k, r2 = 2k, t a = 25 c, unless otherwise specified. quiescent current vs. v cc supply voltage 0.30 0.35 0.40 0.45 0.50 0.55 0.60 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 v cc supply voltage (v) quiescent current (ma) v en = 5v quiescent current vs. temperature 0.30 0.35 0.40 0.45 0.50 0.55 0.60 -50 -25 0 25 50 75 100 125 temperature quiescent current (ma) v en = 5v ( c) en threshold voltage vs. temperature 0.65 0.70 0.75 0.80 0.85 0.90 0.95 -50 -25 0 25 50 75 100 125 temperature en threshold voltage (v) rising ( c) falling shutdown current vs. temperature -0.04 -0.02 0 0.02 0.04 -50 -25 0 25 50 75 100 125 temperature shutdown current ( a) v en = 0v ( c) reference voltage vs. v cc supply voltage 0.490 0.493 0.495 0.498 0.500 0.503 0.505 0.508 0.510 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 v cc supply voltage (v) reference voltage (v) v en = 5v reference voltage vs. temperature 0.490 0.493 0.495 0.498 0.500 0.503 0.505 0.508 0.510 -50 -25 0 25 50 75 100 125 temperature reference voltage (v) v en = 5v ( c)
RT9046 6 ds9046-01 april 2011 www.richtek.com dri sink current vs. dri voltage 0 3 6 9 12 15 00.511.522.53 dri voltage (v) dri sink current (ma) dri sink current vs. temperature 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 -50 -25 0 25 50 75 100 125 temperature dri sink current (ma) ( c) v en = 5v, v dri = 6v, v fb = 0.7v dri source current vs. temperature 35 40 45 50 55 60 -50 -25 0 25 50 75 100 125 temperature dri source current (ma) ( c) v en = 5v, v dri = 6v, v fb = 0.3v pgood delay time vs. temperature 200 250 300 350 400 450 500 550 600 -50 -25 0 25 50 75 100 125 temperature pgood delay time ( s) ( c) v en = 5v start up from en and inrush current time (100 s/div) i in (1a/div) v en (5v/div) v out (1v/div) pgood (1v/div) v en = 5v, i load = 0a start up from en and pgood delay time (100 s/div) i out (2a/div) v en (5v/div) v out (1v/div) pgood (1v/div) v en = 5v, i load = 3a
RT9046 7 ds9046-01 april 2011 www.richtek.com line transient response time (100 s/div) v in = 1.5v to 2.5v, v en = 5v, i load = 3a v in (v/div) v fb (mv/div) 0 10 -10 1.5 2.5 load transient response time (250 s/div) v en = 5v, i load = 0a to 5a i load (5a/div) v fb (20mv/div) start up from v in time (2.5ms/div) i in (2a/div) v out (1v/div) v in (1v/div) pgood (2v/div) v en = 5v, i load = 3a pgood off time (50 s/div) i out (2a/div) v en (5v/div) v out (2v/div) pgood (2v/div) v en = 5v, i load = 3a start up from v cc time (1ms/div) i in (2a/div) v out (1v/div) v cc (10v/div) pgood (2v/div) v en = 5v, i load = 3a
RT9046 8 ds9046-01 april 2011 www.richtek.com application information capacitor selection external capacitors are necessary for the proper operation of the RT9046. the power supply, requires a 1 f ceramic capacitor between vcc and ground. this capacitor shunts power supply current transients to ground and stabilizes the input voltage to the RT9046. the capacitor should be placed as close to vcc as possible. the power source for the pass transistor, v in , requires an input capacitor. a larger 100 f ceramic capacitor should be placed as close to the pass transistor's (q1's) drain as possible to ensure the best psrr and line transient response for v out . again, it is necessary to place a 100 f capacitor between v out and ground to reduce noise, and improve load transient response and psrr. output voltage setting the output voltage, is determined using a simple resistor divider and the internal 0.5v, 2% reference. the output can be programmed by the following equation : + = out r1 r2 v0.5 r2 in order to achieve desired output voltage regulation, resistors must be selected for the accuracy of their nominal value. for a 5% accurate output voltage, 1% resistors should be employed in the design. power good function the RT9046 has the power good function with 0.6ms delay. the power good output, is an open drain output. connect a 100k pull up resistor between vout and pgood, to sample the output voltage. when the output voltage, reaches 90% of the desired value, the power good will output a logic high 0.6ms later. when the output voltage drops below 75% of the desired value, pgood will output a logic low 15 s later. there are two exceptions : if the chip enable is pulled low or if vcc drops below the power-on reset (por) value (2.65v @ 25 c), pgood will output a logic low. chip enable operation the en pin is the chip enable input. pull the en pin low (<0.4v) to shutdown the device. during shutdown mode, the RT9046 quiescent current drops below 5 a. the external capacitor and load current determine the output voltage decay rate (see accelerating v out shutdown to improve shutdown speed). drive the en pin high (>1.4v) to turn the device on again. under voltage protection the RT9046 provides v out with under voltage protection, uvp. the uvp circuit begins monitoring v out after it achieves 90% of the desired output voltage and the pgood pin has output a logic high. if v out drops below 50% of its desired value, the pgood and dri pins will be pulled low and the RT9046 will enter latch mode. the RT9046 can only be unlatched by cycling the vcc or en pin low and then high again. this action will cause the RT9046 to exit the latch mode and restart. mosfet selection the RT9046 is designed to drive an external n-mosfet. the mosfet selection criteria include : ` maximum continuous drain current, i dmax ` on-resistance, r ds(on) ` threshold voltage, v gs_th ` drain-to-source voltage, v ds ` package thermal resistance, ja the mosfet must be able to carry the maximum current required by the load at v out . mosfet i d(max) should be greater than or equal to i load(max) for v out . once we know i load(max) , we can calculate the maximum allowable mosfet r ds(on) as follows : ( ) ? = in out ds(on) load(max) vv r i for example, if the maximum load current, i load(max) , is 2a, v in is 1.5v, and v out is 1.2v, then ( ) ? == ds(on) 1.5v 1.2v r150m 2a
RT9046 9 ds9046-01 april 2011 www.richtek.com thus, the mosfet must have an r ds(on) equal to or lower than 150m when operating with v ds of 0.3v at 2a. the mosfet must also have a v gs_th low enough to be turned on by the driver circuit at the driver output, v dri . finally, the mosfet's junction to ambient temperature thermal resistance, ja , must be considered. the mosfet's junction temperature should be kept below its recommended maximum junction temperature; t j(max) = 125 c is a conservative maximum junction temperature. in the worst case example, the mosfet will have to dissipate, 0.6w : p d = v ds x i ds(max) . in order to keep the junction temperature below the RT9046's guaranteed maximum operating ambient temperature specification (t a(max) ) of 85 c, we must select a mosfet with a ja of less than 67 c/w : ja = (t j(max) ? t a(max) )/ p d . a philips phd3055e n-mosfet with a ja of 50 c/w in the d-pak package, maximum r ds(on) of 150m at v gs = 10v, i d(max) = 10.3a, and v dss = 55v is a good choice. higher current and power applications may require the use of additional layout consideration, package selections, and pcb application in order to improve thermal performance of the mosfet. accelerating v out shutdown in order to accelerate the shutdown of v out , a pnp transistor can be used. given the sink capabilities of the RT9046's dri output the ksb772 pnp transistor is a good choice. figure 3 shows the implementation of this circuit with q2 as the ksb772 pnp transistor. shutdown delay will be determined by the load current. figure 3 v cc v in pgood v out c out c in c cc r pgood r1 r2 q1 vcc gnd en dri pgood fb RT9046 chip enable q2 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT9046, the junction temperature is 125 cand t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for sot-23-6 packages, the thermal resistance ja is 250 c/w on the standard jedec 51-3 single layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (250 c/w) = 0.4w for sot-23-6 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT9046 package, the figure 4 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. sot-23-6 single layer pcb figure 4. derating curves for RT9046 packages
RT9046 10 ds9046-01 april 2011 www.richtek.com layout considerations there are three critical layout considerations. the divider resistors, r1 and r2, should be mounted as close to the RT9046 fb pin as possible to minimize noise. capacitor, c in , should be as close to the mosfet's drain as possible, and output capacitor, c out , as close to the mosfet's source as possible. finally, in cases where high load currents are required, designers will have to get creative. mosfets with mountable drains, increased copper in the layout, and fan generated air flow may be necessary to achieve workable designs. a layout example demonstrating passive placement and using increased copper area for the drain of a mosfet pass transistor in the d-pak package is illustrated by figure 5. figure 5 v in v cc en pgood fb v out gnd gnd + + +
RT9046 11 ds9046-01 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 e b b d c h l sot-23-6 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 0.889 1.295 0.031 0.051 a1 0.000 0.152 0.000 0.006 b 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 c 2.591 2.997 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024

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