quadrature clock converter features: ? x1, x2 and x4 mode selection ? up to 16mhz output clock frequency ? index input and output ? up/down indicator output ? programmable output clock pulse width ? on-chip filtering of inputs for optical or magnetic encoder applications. ? ttl and cmos compatible i/os ? +3v to +12v operation (v dd - v ss ) ? ls7082n1 (dip); ls7082n1-s (soic ) - see figure 1 input/output description: v dd (pin 1) supply voltage positive terminal. indx (pin 2) encoder index pulses are applied to this input. rbias (pin 3) input for external component connection. a resistor con- nected between this input and v ss adjusts the output clock pulse width (tow). for proper operation, the output clock pulse width must be less than or equal to the a, b pulse separation (t ow t ps) . v ss (pin 4 ) supply voltage negative terminal. a (pin 5) quadrature clock input a. this input has a filter circuit to validate input logic level and eliminate encoder dither. x2 (pin 8) a low level applied to this input selects x2 mode of opera- tion. see table 1 for mode selection truth table and figure 2 for input/output timing relationship. b (pin 9) quadrature clock input b. this input has a filter circuit identical to input a. x4/x1 (pin 10) this input selects between x1 and x4 modes of operation. see table 1 for mode selection truth table and figure 2 for input/output timing relationship. up/dn (pin 11) the count direction at any instant is indicated at this output. an up count direction is indicated by a high, and a down count direction is indicated by a low (see figure 2). dnck (pin 12) this down clock output consists of low-going pulses gen- erated when a input lags the b input (see figure 2). upck (pin 13) this up clock output consists of low-going pulses gener- ated when a input leads the b input (see figure 2). indx (pin 14) this output consists of low-going pulses generated by a positive clock transition at the a input when indx input is high and b input is low and a negative clock transition at the b input when indx input is high and a input is high. (see figure 2). note : all unused input pins must be tied to v dd or v ss . description: the ls7082n1 is a cmos quadrature clock converter. quad- rature clocks derived from optical or magnetic encoders, when applied to the a and b inputs of the ls7082n1 , are converted to strings of up clocks and down clocks. pulses derived from the index track of an encoder, when applied to the indx input, produce absolute position reference pulses which are syn- chronized to the up clocks and down clocks. these outputs can be interfaced directly with standard up/down counters for direction and position sensing of the encoder. june 2015 7082n1-062315-1 table 1. mode selection truth table x2 input x4/x1 input mode 0 0 or 1 x2 10x1 11x4 lsi/csi lsi computer systems, inc. 1235 walt whitman road, me lville, ny 11747 (631) 2 71-0400 fax (631) 271-0405 ls7082n1 u l ? a3800 1 2 3 4 5 6 7 ls7082n1 upck dnck up/dn x4/x1 b x2 v dd ( +v ) indx rbias v ss ( -v ) a nc nc 14 13 12 11 8 9 10 figure 1 pin assignment - top view lsi indx
absolute maximum ratings: parameter symbol value units dc supply voltage v dd - v ss 16 v voltage at any input v in v ss -0.3 to v dd +0.3 v operating temperature t a -20 to +85 oc storage temperature t stg -55 to 150 oc dc electrical characteristics: (unless otherwise specified v dd = 3v to 12v and t a = -20oc to +85oc) parameter symbol min typ max units condition supply voltage v dd 3-12v - supply current i dd - 1.5 1.65 ma v dd = 12v, all input frequencies=0 hz and r bias = 2m x4 / x1n: logic 0 v x4l - - 0.5 v - logic 1 v x4h v dd - 0.5 --v logic 0 input current i x4l - 2.2 4.2 a v dd = 3v i x4l - 3.5 6.9 a v dd = 5v i x4l - 8.3 16.2 a v dd = 12v logic 1 input current i x4h - -2 -9.8 a v dd = 3v i x4h - -3.4 -6.6 a v dd = 5v i x4h - -8.2 -16 a v dd = 12v x2n / indx: logic 0 v indxl -- 0.3*v dd v- logic 1 v indxh 0.7*v dd --v input current i indxlk - 0 10 na - a,b inputs: logic 0 v abl -- 0.25*v dd v- logic 1 v abh 0.7*v dd --v - input current i ablk - 0 10 na - rbias input: external resistor r b 2k - 10m - all outputs: sink current i ol - -3.2 - ma i ol - -4.8 - ma i ol - -7.2 - ma source current i oh - 1.7 - ma i oh - 2.2 - ma i oh - 3.1 - ma transient characteristics (t a = -20 oc to +85 oc) parameter symbol min typ max units condition output clock pulse width t ow 540 ns v dd = 3v t ow 180 ns v dd = 5v t ow 60 ns v dd = 12v a,b inputs: validation delay t vd - 450 - v dd = 3v t vd - 200 - v dd = 5v t vd -90- v dd = 12v phase delay t ps t vd +t ow s- pulse width t pw 2t ps - s- frequency f a,b - 1/(2t pw ) hz - input to output delay t ds - 490 565 ns v dd = 3v t ds - 220 345 ns v dd = 5v t ds - 125 135 ns v dd = 12v 7082n1 \062315 \ 2
7082n1-043009-3 upck ( x2 ) a b indx upck ( x1 ) dnck ( x1 ) dnck ( x2 ) upck ( x4 ) indx up/dn t pw t ds t ps tow t ds figure 2. ls7082n1 input/output timing diagram dnck ( x4 ) mux clock and direction decode dual one-shot dual one-shot current mirror v dd figure 3. ls7082n1 block diagram x2 clock 14 11 13 12 3 5 9 10 8 1 4 2 indx a b x2 indx v ss filter rbias +v -v x4/x1 filter up/dn
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