View PE99151-14_8530709.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

page 1 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. product description the pe99151 is a radiation hardened point-of-load buck regulator delivering high efficiency at v in = 5v and output currents up to 2a continuous. this single-chip solution is perfect for hi-rel applications and delivers peak efficiency exceeding 93%. a minimal external component count and high switching frequency enables >10 w/in 2 standard pcb designs while high efficiency minimizes thermal concerns. all power switching devices are integrated on-chip. fabricated in peregrine?s patented ultracmos ? technology, the pe99151 offers excellent power efficiency and intrinsic radiation tolerance. product specification hi-rel 2a dc-dc converter radiation hardened ultracmos ? monolithic point-of-load synchronous buck regulator with integrated switches pe99151 die features ?? up to 2a continuous ?? output voltage range from 1.0v to 3.6v by external select resistors ?? input voltage range 4.6v ? 6.0v ?? current mode control, pulse-by-pulse current limit, current sharing enabled and (n+k) redundancy compatible shutdown mode ?? sync function, 100 khz ? 5 mhz lock range with selectable 500 khz /1 mhz free running frequency ?? shutdown pin, power good output pin for supply sequencing ?? better than 1% typical initial accuracy (25c) ?? control inputs compatible with ttl, lvttl, lvcmos (2.5v and 3.3v) and 5v cmos figure 1. typical application diagram tid 100 krad(si) sel > 90 mev?cm 2 /mg seb > 90 mev?cm 2 /mg set > 90 mev?cm 2 /mg sefi > 90 mev?cm 2 /mg segr > 90 mev?cm 2 /mg sel, seb, segr, seu, sefi: none observed, au/60 degrees set: no events exceeding 30 mv transient observed @ au, let=90, 60 degrees and normal incidence table 1. radiation performance
product specification pe99151 die page 2 of 15 ?2012-2014 peregrine semiconductor corp. all rights reserved. document no. doc-50370-3 ultracmos ? power management solutions table 2. electrical specifications 1 temp (t a ) = ?55 to +125c, v in = 4.6v ? 6.0v, v out = 1.0v ? 3.6v (except as noted) parameter condition min typ max unit synchronous frequency range, fsw_range 0.1 5 mhz maximum cycle-averaged rms output current, imax 2 a supply current (shutdown), iddsd sdb = gnd, v in = 5.5v 1.8 3.2 ma sdb = gnd, v in = 6.0v 3.1 5.5 supply current (no-load, 1 mhz async), idd0 17.5 ma high side on resistance, ron,hss test current = 100 ma 97 160 m ? low side on resistance, ron,lss test current = 100 ma 113 190 m ? output voltage reference voltage accuracy, vref 2 v in = 5.0v, i out = imax/2, -40 t a +85c, fsw = 100 khz - 1 mhz -1.0 0 1.0 % v in = 5.0v, i out = imax/2, -55 t a +125c, fsw = 100 khz - 1 mhz -1.5 0 1.5 reference voltage line regulation, kvi (steady state) 2 4.6v v in 6.0v, i out = 1a, v out = 2.5v, fsw = 1 mhz -0.2 0 0.2 % reference voltage load regulation, kvo (steady state) 2 v in = 5.0v, 500 ma i out 1a, v out = 2.5v, fsw = 1 mhz -0.25 0 0.25 % internal oscillator and sync capture oscillator frequency, fosc_freq sync = gnd 320 530 700 khz sync = open or v in 0.71 1 1.42 mhz internal oscillator duty cycle, fosc_dc 46 54 % sync lock capture frequency, sync_lock 40 khz external sync duty cycle, sync_dc 40 60 % internal current limit max, ilimxint 2 v out = 1.0v, iset = 3.0v, icomp = 0v, rsel pin shorted to ground, not min-on-time limited 2 3 4 a externally set max current limit accuracy, ilimxext 2 v out = 1.0v, rset = 130 ? , iset = 3.0v, icomp = 0v, rsel = v in , not min-on-time limited 2 3 4 % max voltage across rset, vmaxrset 1.3 1.5 1.75 v i out /i rset, g iref 2 i out set for 50% rated current 300 378 450 a/a icomp cap, cicomp 2 110 pf current compensation gain, icomp gain, g icomp 2 2.3 3 4 a/v current limiting and current mode control loop notes: 1. wafer level screening is performed at 25c and 85c only. however, performance is guaranteed over the full operating temperature range based on a population of parts th at were packaged and characterized at ?55c and 125c 2. parameter not tested at wafer level due to high current limitat ions of test setup
product specification pe99151 die page 3 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. pgood pgood threshold eainm_up_thresh entering pgood window 103 110 118 % eainm_lo_thresh exiting pgood window 83 89 98 % eainm_up (% of vref) 2 % eainm_lo 1.67 pgood low sink current, pgood i_ol v_pgood = 0.4v 3.5 8 ma pgood high leakage current, pgood i_oh v_pgood = v in 9 22.5 ua pgood deglitch time 64 syncob cycles error amp eainm leakage measured at 1v input 0.2 ua eainp leakage measured at 1v input 0.2 ua eaout source current measured at 1v input -490 -345 -220 ua eaout sink current measured at 1v input 100 200 295 ua error amplifier transconductance eaout = 1.5v, dc 0.4 1.25 2.2 ms error amplifier output resistance 3.5 6.5 9.5 m ? ea input offset 1 mhz internal -6 4 6 mv undervoltage lockout under-voltage lockout v in rising 3.5 4.2 4.59 v v in falling 3.4 3.8 4.1 v under-voltage lockout hysteresis 400 mv soft start ss pin pull-up resistance v sscap = 0v 1.2 m ? internal sscap 16 pf vref track, v_sscap - vref_ext v sscap = 0.5v -170 0 170 mv dc characteristics sdb turn-on threshold v ih 2 v v il 1.45 v syncob low sink current, syncob i_ol v_syncob = 0.4 3.5 8 ma syncob high leakage current, syncob i_oh v_syncob = v in 9 22.5 a sync v ih 2 v v il 1.25 v hss leakage v out = sdb = 0v -0.09 -0.001 ma lss leakage v out = v in , sdb = 0v 0.09 0.7 ma pgood hysteresis table 2. electrical specifications 1 (continued) temp (t a ) = ?55 to +125c, v in = 4.6v ? 6.0v, v out = 1.0v ? 3.6v (except as noted) note 1: wafer level screening is performed at 25c and 85c only. however, performance is guaranteed over the full operating temperature range based on a population of parts th at were packaged and characterized at ?55c and 125c
product specification pe99151 die page 4 of 15 ?2012-2014 peregrine semiconductor corp. all rights reserved. document no. doc-50370-3 ultracmos ? power management solutions figure 2. pin layout (top view) pin no. pin name x y description 1 gnd 1385.9 1433.4 ground 2 sw 1366.9 1179.65 switch 3 sw 1366.9 810.35 switch 4 gnd 1365.9 500 ground 5 sw 1366.9 189.65 switch 6 sw 1366.9 -189.65 switch 7 gnd 1366.9 -500 ground 8 sw 1366.9 -810.35 switch 9 sw 1366.9 -1179.65 switch 10 gnd 1385.9 -1433.4 ground 11 gnd -1343.9 -1437.25 switch 12 icomp -1343.9 -1266.9 variable current compensa- tion/resistor to vout 13 iset -1343.9 -1068.3 current set-point input/loop to eaout 14 eaout -1343.9 -869.7 error amplifier output/loop iset pin no. pin name x y description 17 vrefsel1 -1343.9 -297.3 bandgap reference voltage fine adjust (1) 18 vrefsel2 -1343.9 -148.7 bandgap reference voltage fine adjust (2) 19 vrefsel3 -1343.9 -0.1 bandgap reference voltage fine adjust (3) 20 tcsel0 -1343.9 148.5 bandgap reference voltage fine adjust (0) 21 tcsel1 -1343.9 297.2 bandgap reference voltage fine adjust (0) 22 gnd -1343.9 500 ground 23 ccsel -1343.9 696.1 course trim code 24 eainm -1343.9 869.7 error amplifier (-) input, loop to vref 16 gnd -1343.9 -500 ground 15 vrefsel0 -1343.9 -696.1 bandgap reference voltage fine adjust (0) table 3. pin coordinates and descriptions note: all pin locations originate from the di e center and refer to the center of the pin
product specification pe99151 die page 5 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. table 3. pin coordinates and descriptions (continued) pin no. pin name x y description 25 eainp -1343.9 1068.3 error amplifier (+) input, load feedback 26 vref -1343.9 1266.9 1.000v reference output, loop to aainp. additional low pass filtering may be necessary 27 gnd -1343.9 1437.25 ground 28 agnd -1142.8 1283.2 bandgap ground 29 rset -1142.8 -1283.2 resistor to set reference current 30 sscap -944.2 1283.2 resistor to set reference current 31 syncob -944.2 -1283.2 loop-through comple- ment output 32 sync -745.6 1283.2 loop-through comple- ment output 33 pgood -745.6 -1283.2 power good flag output 34 sdb -547 1283.2 shutdown (l)/enable input 35 rsel_sdat -547 -1283.2 reference resistor selection 36 test -348.4 1283.2 ground 37 sclk -348.4 -1283.2 ground 38 vin 602.5 1000 input power supply 39 vin 1102.5 0 input power supply 40 vin 602.5 -1000 input power supply table 4. operating ranges table 5. absolute maximum ratings symbol parameter/condition min max unit v in power supply voltage -0.5 6.5 v t j operating temperature range (junction) -55 145 o c t st storage temperature range -65 150 o c i i dc into any signal input -10 10 ma i o dc into any signal output -50 50 ma i p dc into any single power pin -2 2 a symbol parameter/condition min max unit v in power supply voltage 4.6 6.0 v t a operating temperature range (ambient) -55 125 c electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up immunity unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. table 6. electrostatic discharge (esd) ratings model parameter/condition min max unit hbm v esd all pins 1000 v note: human body model esd volta ge (hbm, mil_std 883 method 3015.7) exceeding absolute maximum ratings may cause permanent damage. operation between maximum operating range and absolute maximum for extended periods may reduce reliability. eldrs the ultracmos ? process does not exhibit enhanced low-dose-rate sensitivity (eldrs) since bipolar minority carrier elements are not used.
product specification pe99151 die page 6 of 15 ?2012-2014 peregrine semiconductor corp. all rights reserved. document no. doc-50370-3 ultracmos ? power management solutions typical performance characteristics figure 3. efficiency curves over output load current and temperature figure 4. efficiency curves over typical output voltages note: the efficiency curves in figures 3 and 4 were measured on the packaged parts. 50 55 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 efficiency ? (%) output ? current ? (a) pe99151 ? efficiency ? versus ? output ? current vin=5v, ? vout=2.5v, ? fsw=1mhz tc ? = ?\ 55c tc ? = ? +25c tc=+125c 50 55 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 efficiency ? (%) output ? current ? (a) pe99151 ? efficiency ? versus ? output ? current vin=5v, ? fsw=1mhz, ? t=+25c vout ? = ? 3.3v vout ? = ? 2.5v vout ? = ? 1.5v vout ? = ? 1.0v
product specification pe99151 die page 7 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. figure 5. block diagram eainm eainp vin agnd vref current threshold comparator osc control logic current sense sync power good syncob pgood out reference current rsel iset rset icomp g iref g icomp sscap error amplifier eaout sdb soft start gnd 1.000v agnd
product specification pe99151 die page 8 of 15 ?2012-2014 peregrine semiconductor corp. all rights reserved. document no. doc-50370-3 ultracmos ? power management solutions theory of operation general the pe99151 is a radiat ion-hardened point-of-load buck regulator. this highly int egrated switching regulator contains two synchronous power switches capable of delivering up to 2a of continuous current. the pe99151 is designed to operate from a wide 5v bus and provide 1.0v to 3.6v supply rails for analog, digital and rf payloads. the internal oscillator can o perate at 500 khz or 1 mhz. optionally, the switching frequency can be synchronized to an external reference from 100 khz to 5 mhz. current limiting is adjustable with an external resistor and is achieved through peak current mode control. an external resistor also provides adj ustable slope compensation to optimize stability and closed loop bandwidth across output voltage and switching frequency range. loop compensation is externally adjustable to meet application transient response while still maintaining stability requirements. the output is tri-stated when the sdb pin is low to enable hot-spare capability. peak current mode control loop the pe99151 uses a peak current mode control architecture. at the falling edge of either the internal oscillator or, if present, the ex ternal reference, the high side switch turns on. the input voltage is then connected to the load voltage through the high side switch and the inductor for a time greater than the minimum-on-time. current in the inductor begins to ramp approximately as (v in ? v out )/l. energy is stored in the inductor during this period. as the inductor current rises, current through the high side switch is sensed and compared to a current threshold. the inductor current continues to ramp until the current threshold is reached. at this point the high side switch turns off and the low side switch turns on for at least the minimum-off-time. energy stored in the inductor during the previous phase is discharged into the load supply rail through the low side switch and the inductor. inductor current decreases at a rate of approximately v out /l. the low side switch stays on until the next falling edge of the reference clock. in order to prevent unintended harmonics or spurs, the part does not exit continuous conduction mode. whether the current threshold was met in the previous clock cycle or not, a minimum-off-time, followed by a minimum-on-time immediately follows the falling edge of the reference clock. while providing improved bandwidth and inherent current limiting, all current mode c ontrol switching regulators require slope compensation to ensure stability across all application conditions. the pe99151 provides adjustable slope compensation to allow the designer to optimize transient response and st ability requirements. the compensation ramp is provided through the icomp pin. inboard of the icomp pin is the cicomp capacitor which can be used to generate an rc compensation ramp by tying the icomp pin to either v out or v in through an external resistor to produce the desired ramp. see the design guide for selection of t he appropriate resistor value. the rc ramp is reset anytime the low side switch is on by a fet switch. current threshold and over current protection the current mode control thres hold current is set by the iset pin which is driven by the voltage control loop from the eaout pin. the pe99151 takes the voltage applied to the iset pin, subtracts 0.7v (typ) and applies that voltage to the r set resistor. an internal r set resistor will be used if the rsel pin is grounded or an external r set resistor connected to the rset pin is used if the rsel pin is tied high. the current flowing through the r set resistor is then used as a scaled current reference for the inductor current threshold comparison. the scaling ratio is defined as g iref in table 2 . over current protection is achieved by limiting the maximum voltage applied to the internal or external r set resistor to the vmaxrset value listed in table 2 . thus, the current limit can be adjus ted by selection of the external r set resistor. this flexibility allows characterization and testing to a high current in the lab while still limiting the current to lower level in the application. voltage control loop the output voltage is achieved by controlling the iset pin. the pe99151 contains an amplifier with both of the positive and negative input terminals, eainp and eainm respectively, and the output terminal eaout all pinned out to package pins. this allows fo r flexible configurations of the voltage reference, error amplifier, feedback networks and the current mode control loop. in normal configuration the error amp senses the output voltage, v out , through a resistor divider that produc es a 1.000v division at the target v out . it compares that feedback voltage to the 1.000v reference and increases the voltage applied to the iset pin when the output voltage is low and decreases the voltage applied to the iset pi n when the output voltage is high. loop compensation is required to attenuate the frequency content at and abov e the switching frequency and to achieve the desired phase margin in the voltage control loop. see the design guide for instructions on designing the compensation network.
product specification pe99151 die page 9 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. accurate voltage reference the pe99151 contains an accurate 1.000v reference which is used to drive an accurate output voltage. the 1.000v reference is trimmed at the factory to within 1% of 1.000v at 25c. soft start the soft start circuit uses the voltage on the sscap pin to limit (pull down) the exte rnal vref pin. this allows the designer to limit the output voltage ramp rate. voltage tracking is specified on the vref pin for applications that require an ex ternal tracking capability. the sscap pin is internally connected to a 16 pf (typ) cap to ground and to a 3v internal rail through a 1.2 m ? (typ) resistor. when the sdb pin is low, the sscap pin is pulled to ground by a 12 k ? (typ) resistor. when the shutdown signal is released the pull down switch is released and the voltage on the sscap pin begins to ramp up toward 3v. the ramp rate can be increased by tying the sscap pin to the 5v input rail through an external resistor. the pin is 5v capable. the ramp rate can also be slowed by connecting the sscap pin to ground through a supplemental capacitor. under voltage lockout an internal under voltage lo ckout feature prevents the pe99151 from powering up before input voltage rises above the uvlo threshold of 4.2v (typ). 400 mv (typ) of hysteresis is built-in to pr event false-triggering of the uvlo circuit. the under vo ltage lockout must be cleared and the sdb pin must be released before the part will be enabled. power good flag the pgood pin is an open drain output that can be used to sense when the output voltage of the converter has converged to within 10% (typ) of it?s final value. this pin can also be used to provide limited power sequencing when cascaded with the sdb pin of another pe99151 part. internal circuitry senses when the voltage at the eainm pin has reached to within 10% (typ) of an internal 1.000v reference voltage. when this happens, an internal counter begins counting reference clock cycles and continues counting as long as this condition remains true. when the counter has reached 64, the circuit will assert pgood. when eainm exits the pgood window, there is a 30 mv (typ) hysteresis to prevent chatter when entering or exiting the window. if during the count, the eainm pin exits the pgood threshold, the counter is reset, pgood is not asserted and the count will begin again when eainm re-enters the pgood window. when exiting the pgood state, once eainm is outside of the pgood threshold window, an internal counter begins counting and will de-assert pgood when it counts 64 reference clock cycles. if during the count, the eainm pin re-ent ers the pgood threshold, the counter is reset, pgood is not de-asserted and the count will begin again when eainm exits the pgood window. synchronous (external reference) or asynchronous (internal reference) switching frequency the pe99151 contains an inte rnal oscillator capable of operating at 1 mhz when the sync pin is tied to v in or left open or at 500 khz when the sync pin is tied to ground. this reference clock is used in the current mode control loop to time the rising edge of the out pin and as a global internal clock reference. when the sync pin is actively clocked at a rate of 100 khz to 5 mhz, the internal oscillator uses the clocked sync pulse train as the global internal clock reference. whether operating synchronously or asynchronously, the open drain syncob pin contains the inverted internal clock reference. th is inverted clock signal can be used to aid in the design of polyphase (n=2) power supplies.
product specification pe99151 die page 10 of 15 ?2012-2014 peregrine semiconductor corp. all rights reserved. document no. doc-50370-3 ultracmos ? power management solutions design guide setting the output voltage the pe99151 can be configured to output a dc voltage from +1.0v to +3.6v. the user can set the output voltage by selecting the external feedback resistors r fb1 and r fb2 . the feedback resistors divide down the output voltage to be compared to a +1.000v reference voltage. the error amplifier uses this comparison to determine the amount of current to send to the load. to set the output voltage, a re sistor divider must selected that will produce at +1.000v dc voltage at the eainm pin when v out has reached the tar get output voltage. v out = (r fb1 +r fb2 )/r fb2 = 1 + r fb1 /r fb2 , and r fb1 = r fb2 * ( v out - 1), +1v < v out +3.6v the pe99151 reference design uses a value of 10 k ? for r fb2 . example: desired v out = +2.5v r fb2 = 10 k ? r fb1 = 10 k ? * (+2.5v - 1) = 15 k ? * for a desired output voltage of 1v, rfb1 can be replaced with a 0 ? resistor and rfb2 not installed. this is equivalent to directly connecting v out to eainm. output inductor selection the output inductor serves as the main energy storage element in a switching regulat or. it is perhaps the most critical component influenci ng the performance of the buck regulator. it impacts many aspects of the power supply system performance, including power supply bandwidth, output voltage ripple and rippl e spectrum, and switching, conduction, and core losses. additionally, specific aspects of the buck regulator itself place requirements on the range of allowable inductor values. these aspects include the internal current detecto r sensitivity, the slope compensation ramp dynamic range, and the current limitations of the part. the se lection of the inductor is also a function of the s pecifics of the application including input voltage, out put voltage, load current range, switching frequency, pcb area, efficiency targets, power supply bandwidth, and ripple requirements, to name a few. many performance requirements and other component selections place restrictions on the inductor selection. however, since the inductor selection plays a central role in the performance of the power supply, its selection needs to be made early in the design process. therefore, as a starting point, the inductor needs to be initially selected based on a few rough calculations and selection can be refined iteratively as more system requirements are introduced. the voltage across the inductor is v l = l x ? il/ ? t, where ? il is defined to be the inductor peak-to-peak current ripple. the ripple current is the change in the inductor current during each switching cycle. for the pe99151, the lower limit of ? il is set by the current threshold comparator sensitivity, while the upper limit of ? il is set by the current mode compensation dynamic range. given the output voltage, switching frequency, input voltage and the minimum ? il required by the part, the inductance can be calculated as: l = v l x ? t/ ? il l = v out /(f sw x ? il) x [1 ? d] , where duty cycle = d = v out /v in switching frequency = f sw duration of inductor voltage = ? t = d/f sw as the output switches pull the out pin alternately to v in and to gnd, the inductor peak to peak current ripple (triangular current waveform m agnitude) is expressed as: ? il = v out /(l x f sw ) * (1 ? d) example: v in = +5.0v v out = +2.5v f sw = 1 mhz ? il = 0.5a l = v out /(f sw x ? il) x [1 ? d] l = (+2.5/(1 mhz x 0.5) * [(1 ? (+2.5/+5.0))] = 2.5 h the inductor self resonant frequency (srf) should be selected to be at least 10x higher than the switching frequency f sw . meeting this requirement will ensure stability, reduce output rippl e and improve efficiency. vout rfb1 error amp rfb2 + _ 1.000v eainm eainp vref figure 6. output voltage selection
product specification pe99151 die page 11 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. the dc resistance of the inductor will primarily impact efficiency. for optimal ef ficiency, the inductor dc resistance should be select ed to be on the order of magnitude of the r on of the high side switch and low side switch. calculation of the efficiency impact will be discussed in the efficiency se ction of the design guide. a smaller dc resistance will improve efficiency but will likely impact pcb area, a subject not addressed in this design guide. output capacitor selection the output capacitor works in tandem with the output inductor to filter the inducto r ripple current and to source and sink current to meet the load demand during a load step. the output capacitor is implemented as a network of parallel capacitors covering low, mid, and high frequency operation. the capac itor equivalent series resistance (esr) and equivalent series inductance (esl) have a direct impact on the output voltage ripple, output voltage droop under tr ansient loading, and loop stability. ceramic x7r di electric capacitors are recommended for their thermal and electrical properties, along with their size and cost. the output voltage droop should be empirically determined to satisfy the app lication load step response requirements. during a transient step in the load current, the output voltage will initiall y experience an ir drop of ? i load x esr. if the output capac itor bank is too large, the ir drop is minimized but the v out recovery time is longer. if the output capacitor bank is too small, the ir drop is increased but the v out recovery time is shorter. the output voltage ripple shoul d be chosen to meet the application requirements and tradeoff with the physical size of the capacitor bank . the output voltage ripple waveform can be estimated by taking the inverse fourier transform of the product of t he fourier transform of the input signal and the frequency domain transfer function of the network in figure 9 . (the input to the transfer function can be approximated as an ideal square wave with period of f sw , amplitude of v in and a duty ratio of v out /v in .) if a spice simulation tool is available, the above estimation can be done by placing the above mentioned square wave at the input of the filter network and solving for the output waveform. additionally, the total output capacitance and load resistance set the dominant pole of the voltage mode control loop. voltage mode loop stability is described in the "voltage control loop compensation network design" section. in addition to playing a role in stability and output voltage ripple, the output capacitor bank must be able to absorb the inductor ripple current. the inductor peak-to-peak ripple current, calculated as ? il in the inductor selection section, will be absorbed by the capacitor bank. note that the rms current th rough the output cap can be calculated as ? il/ 3 since inductor ripple current waveform is triangular. the frequency range of capacitors absorbing the rippl e current must be rated to handle this ripple current. the pe99151 reference design features three output capacitors (cout1, cout2, and cout3) that have been chosen to blend total capacitance, esr, and esl to meet the ripple, droop, and stability requirements over frequency. input capacitor selection the input capacitor network sources the trapezoidal current wave through the source terminal of the high side switch. therefore, t he rms current handling and maximum voltage rating are the main considerations in selecting the input capacitors. neglecting the small (as compared with the load) inductor ripple current and assuming that the input capacitor sources all of the ripple current, the rms current through the input capac itor can be calculated as i rms-cin = i load (max) x [d x (1-d)] in addition to sourcing the trapezoidal current wave through the high side switch, the input bypass capacitors absorb the high frequency comp onents of the switching power supply preventing conducted emi from reaching the up stream supply. as such, the input bypass capacitor srf should be on t he order of 10x higher than the switching frequency of t he buck regulator. additional high frequency capacitors may be added to further attenuate the high frequency conducted emi. like the output capacitors, ceramic x7r dielectric capacitors are recommended with the added benefit that the x7r capacitors have very low dc voltage de-rating. vout esr 1 esl 1 cout 1 low freq esr 2 esl 2 cout 2 mid freq esr 3 esl 3 cout 3 high freq dcr indu c tor srf cap load figure 7. output capacitor selection
product specification pe99151 die page 12 of 15 ?2012-2014 peregrine semiconductor corp. all rights reserved. document no. doc-50370-3 ultracmos ? power management solutions efficiency estimation and improvement the efficiency of a switch mode power supply can be estimated by identifying and es timating all sources of loss in the power supply system. these loss terms include switching losses, resistive losses, losses incurred on chip and losses associated with external passive components. external passive losses occur primarily in the output inductor, the output capacitor and the input capacitor. internal losses at high curr ent are dominated by the high and low side switch resistance. at low current, internal losses are dominated by quiescent bias current and switching related losses. the pe99151 design guide provides a simple tool for estimating loss. losses are parameterized across input voltage, output voltage and switching frequency to provide accurate estimates of the performance of the part under a variety of conditions. the following sections give t he mathematical expressions of six main loss terms calculated in the design guide spreadsheet. input capacitor the loss in the input capacitor can be calculated by using the estimate of the rms capac itor current calculated in the input capacitor select ion section. given that: i rms-cin = i load (max) x [d x (1-d)] power lost in the input capacitor can be calculated as: p loss-cin = i 2 rms-cin x r cin-esr output capacitor the rms current through the output capacitor in steady state was calculated in the output capacitor selection section as ? il/ 3. power loss in the output capacitor is then calculated as: p loss-cout = ( ? il 2 / 3) x r cout-esr note that r cout-esr is the esr of the frequency range of capacitors absorbing the ripple current. inductor the inductor rms current is given by: il rms = i load - ? il/2 + ? il/ 3 power lost in the dc resistance of the inductor is then given as: p loss-lout-dcr = i lrms 2 x r lout-dcr high side switch loss during the time the hss is on, it is supporting the load current plus the inductor ripple current. rms current through the hss, when it is on, is given by: i rms-hss = i load - ? il/2 + ? il/ 3 p loss-hss = i rms-hss 2 x r on-hss x d where the extra factor of d = v out /v in is the duty ratio and is included because power is only dissipated in the hss when it is on. low side switch loss during the time the lss is on, it is supporting the load current plus the inductor ripple current. rms current through the lss, when it is on, is given by: i rms-lss = i load - ? il/2 + ? il/ 3 p loss-lss = i rms-lss 2 x r on-lss x (1 -d) where the extra factor of 1 ? (d = v out /v in ) is the duty ratio of the lss and is included because power is only dissipated in the lss when it is on. other internal loss a complete list of internal losses in the pe99151 regulator is estimated and available in the pe99151 design guide spreadsheet available online. the internal losses are parameterized across input voltage, output voltage and switching frequency to provi de accurate estimates of the performance under a variety of conditions. setting the current limit when the rsel pin is grounded, the pe99151 uses an internal current limiting resist or that will limit the output current to a value of ilimxint listed in table 2 of the datasheet. see figure 8 for a visual description of the various current limits. the part can be programmed to use an alternate current limit by tying the rsel pin to v in . in this mode, the pe99151 can be programmed to various output current limits through the selection of a resistor connecting the rset pin to ground. c u r r e n t t h r e s h o l d i l i load ( a v e r a g e c u r r e n t ) m a x c u r r e n t l i m i t : i l i m x e x t o r i l i m x i n t o p e r a t i n g m a x : i m a x a b s o l u t e m a x : i o i n d u c t o r c u rre n t t i m e figure 8. pe99151 current limits
product specification pe99151 die page 13 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. in external rset mode, the pe99151 senses the voltage applied to the iset pin (from the eaout pin, through the compensation network) and subtracts the resulting reference current offs et. this subtraction is then applied to the rset pin. this voltage at the rset pin draws current through the rset resistor. this current is used as a current threshold to set the peak inductor current in the current mode control loop. the maximum voltage at the rset pin is limited to vmaxrset in table 2 independent of the voltage applied to the iset pin. since this voltage is lim ited, the maximum reference current through the r set resistor is limited to vmaxrset/r set . after a reference current is generated through the r set pin, the current is multiplied by the g iref parameter listed in table 2 . thus the peak current allowed by the current mode control loop will be limited to: i limit = g iref x (vmaxrset/r set ) - ? icomp solving for r set r set = (g iref x vmaxrset) / (i limit + ? icomp) slope compensation ramp selection while providing improved bandwidth and inherent current limiting, all current mode c ontrol switching regulators require slope compensation to ensure stability across all applications conditions. the pe99151 provides adjustable slope compensation to allow the designer to optimize transient response and stability requirements. during steady state, a compens ation ramp is created at the icomp pin. the rc ramp is created by the external r comp resistor and an internal capacitor. the ramp is reset any time the low side switch is on by means of a reset switch. the voltage at the icomp pin is multiplied by the g iref parameter in table 2 and is subtracted from the reference current of the current threshold comparator. before calculating the r equired slope compensation to ensure stability, a related slope is defined. in steady state, when the low side switch is on, the inductor current ramps down at a rate of m 2 . m 2 is given as v out /l, where l is the inductance of the output inductor. the minimum slope compensation ramp current, m a required for mathematical st eady state stability under all conditions is one half of m 2 . that is: m a m 2 /2 to provide margin to the minimum, a compensation slope equal to m 2 is recommended: m a = m 2 given the required compensation current (m a ), the voltage ramp rate at the icomp pin can be calculated by dividing by the g icomp parameter in table 2 . ? vicomp = ? icomp / g icomp , where ? icomp = ( ? il x ? t on x m a /m 2 ) / ? t off and ? vicomp = (0.95 x v out 2 ) / cicomp x r comp x f sw x v in ) next, substituting for ? il from the output inductor equation and given the required voltage ramp rate and the internal capacitance connected to the icomp pin, cicomp in table 2 , the resistor connected from v out to the icomp pin can be calculated: r comp = (0.95 x g icomp x l) / (cicomp x m a /m 2 ), where 95% of v out is used to achieve a linear approximation of the aver age current through cicomp, assuming the voltage drop over 1 cycle varies from 100 to 90%. figure 9. pe99151 slope compensation voltage control loop compensation network design the pe99151 contains a current mode control loop and a voltage mode control loop as shown in figure 10 . the current mode control loop, to first order, controls average inductor current and so behaves as a current source. conceptually, the current mode control loop can be replaced with a voltage controlled current source. external to the compensation network, the resulting network contains one pole in the voltage control loop. this pole is created by the parallel combination of cout and the load resistance and is located at: 1/(2 r load c out ) ma m1 m2 inductor current g iref = time i l vmaxrset r set i load avg slope compensation i com p t on t off
product specification pe99151 die page 14 of 15 ?2012-2014 peregrine semiconductor corp. all rights reserved. document no. doc-50370-3 ultracmos ? power management solutions one requirement of the vo ltage control loop stability analysis and design is to main tain significant attenuation at the switching frequency of the converter. if this requirement is not met, the switching noise can enter the control loop and loop stabilit y will be lost. to ensure sufficient attenuation at t he switching frequency, a unity gain cross over frequency one decade below the switching frequency is recommended. additional margin may be desired depending on the application requirements. the pole created by the load and the output capacitor is dependent on load current. the load current can vary, likely all the way down to zero load current. when this happens the output pole frequency fa lls arbitrarily low. it is clear that this highly vari able pole will not be sufficient to set a dominant pole in the loop to ensure stability. the recommended compensation technique is a combined pole-zero compensation network. the zero is set to cancel the variable load pole at minimum load so that the load pole does not af fect phase margin of the system when the pole location is at it's minimum value, possibly even in the bandwidth of the control loop. with the load pole canceled by t he additional zero, the added pole in the compensation network acts as a stable dominant pole. this dominant pole location can be selected for both attenuation of the f sw switching noise and for the required phase margin and loop bandwidth. with this compensation technique, the zero location is calculated as 1/(2 r c c c ). r c and c c should be selected to cancel the load pole at minimum load. if the compensation network resistor is selected to be much less than the output impedance r out of the error operational transconductance amplifier (ota), the dominant pole location can then be approximated as 1/ (2 r out c c ). at first glance this may seem to make the dominant pole location dependent on the loosely controlled error amp output impedance. however, as the error amp output impedance drops, the dc gain of the system and the dominant pole location reduce together. the result is that the unity gain cross over frequency (set by the dominant pole) is independent of ota output impedance variation over pr ocess and temperature. a compensation network design spreadsheet is available in the pe9915x design tool. figure 10. pe99151 control loops
product specification pe99151 die page 15 of 15 document no. doc-50370-3 www.psemi.com ?2012-2014 peregrine semiconductor corp. all rights reserved. order code description package shipping method 99151-01 1 engineering packaged parts 32-lead cqfp 24 units / jedec tray 99151-11 flight packaged parts 32-lead cqfp 24 units / jedec tray 99151x-98 1 engineering sample die with bonding x (x = a - h) die 49 units / waffle pack 99151x-99 flight die with bonding x (x = a - h) die 49 units / waffle pack 99151-00 evaluation kit 1 / box table 8. ordering information figure 11. waffle pack information note: dice will be orient ed in the same direction in and within all waffle packs. unless otherwise stated, dice will be orient ed such that the top left corner of the dice will be in-line with the ?notched? corner of the die plate base and cover. if a different orientation is requir ed, it will be shown on t he traveler or purchase order and process instructions. in all cases, t he die base cover label will be affixed on the die base cover such that the top of the label indicates the top of the dice within the waffle pack. table 7. mechanical specification parameter minimum typical maximum unit die size, singulated (x,y) 3.07 x 3.33 3.09 x 3.35 3.14 x 3.40 mm wafer thickness 180 200 220 m wafer size 150 mm advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregr ine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com . note 1: engineering sample (es) devices are prototype units in tended as initial evaluation units for customers of the flight u nits. the es device provides the same functionality and footprint as the space qualified device, and in tended for engineering evaluation only. they are tested at 25 c only and processed to a non- compliant flow (e.g. no burn-in, etc.). these units are not suit able for qualification, production, radiation testing or flight use

▲Up To Search▲

Price & Availability of PE99151-14

	To Download PE99151-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .