View IDT5V41068A_8596823.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

datasheet 2:1 pcie gen1/2/3 clock multiplexer IDT5V41068A idt? 2:1 pcie gen1/2/3 clock multiplexer 1 IDT5V41068A rev e 112211 description the IDT5V41068A is a 2:1 differential clock mux for pci express applications. it has very low additive jitter making it suitable for use in pcie gen2 and gen3 systems. the IDT5V41068A selects between 1 of 2 differential hcsl inputs to drive a single differential hcsl output pair. the output can also be terminated to lvds. recommended applications ? clock muxing in pcie gen2 and gen3 applications output features ? 1 ? 0.7v current mode differential hcsl output pair features/benefits ? low additive jitter; suitable for use in pcie gen2 and gen3 systems ? 16-pin tssop package; small board footprint ? outputs can be terminated to lvds; can drive a wider variety of devices ? oe control pin; greater system power management ? industrial temperature range available; supports demanding embedded applications key specifications ? additive cycle-to-cycle jitter <5 ps ? additive phase jitter (pcie gen3) <0.2ps ? operating frequency up to 200mhz block diagram vdd rr (iref) clk clk sel gnd in1 in1 in2 in2 mux 2 to 1 oe 3 3 pd
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 2 IDT5V41068A rev e 112211 pin assignment select table pin descriptions vd din 1 16 ^sel dif_in1 2 15 dif_0 dif_in1# 3 14 dif_0# ^pd# 4 13 gnd dif_in2 5 12 gnd dif_in2# 6 11 vdd ^oe 7 10 vdd gnd 89 iref 16-pin tssop 5v41068 note : pins preceeded by '*^ have internal 120k ohm pull up resistors sel outputs 0dif_in2 1dif_in1 pin # pin name pin type description 1 vddin pwr power p in for the in p uts, n om inal 3.3 v 2 dif_in1 in 0.7 v differential true in p ut 3 dif_in1# in 0.7 v differential com p lementar y in p ut 4^pd# in asynchronous active low input pin used to power down the device. the internal clocks are disabled and the vco and the crystal osc. (if any) are stopped. 5 dif_in2 in 0.7 v differential true input 6 dif_in2# in 0.7 v differential com p lementar y in p ut 7^oe in active high input for enabling outputs. this pin has an internal pull up resistor. 0 = disable outputs, 1= enable outputs 8 gnd pwr ground pin. 9iref out this pin establishes the reference for the differential current-mode output pairs. it requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. other impedances require different values. see data sheet. 10 vdd pwr power su pp l y , nominal 3.3v 11 vdd pwr power su pp l y , nominal 3.3v 12 gnd pwr ground pin. 13 gnd pwr ground pin. 14 dif_0# out 0.7v differential complementary clock output 15 dif_0 out 0.7v differential true clock out p ut 16 ^sel in selects between one of two inputs. this pin has internal pull up resistor.
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 3 IDT5V41068A rev e 112211 application information decoupling capacitors as with any high-performance mixed-signal ic, the IDT5V41068A must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guide lines should be observed. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the IDT5V41068A. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. external components a minimum number of external components are required for proper operation. decoupling capacitors of 0.01 f should be connected between vdd and gnd pairs (2,9 and 15,16) as close to the device as possible. current reference source r r (iref) if board target trace impedance (z) is 50 , then rr = 475 (1%), providing iref of 2.32 ma, output current (i oh ) is equal to 6*iref. load resistors r l since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. output termination the pci-express differential clock outputs of the IDT5V41068A are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the layout guidelines section. the IDT5V41068A can also be terminated to lvds compatible voltage levels. see the layout guidelines section.
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 4 IDT5V41068A rev e 112211 output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guide lines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the IDT5V41068A.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see layout guidelines sections - pages 5, 6
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 5 IDT5V41068A rev e 112211 layout guidelines common r ecommendations for differential routing d imension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 pcie (src) reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 6 IDT5V41068A rev e 112211 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 7 IDT5V41068A rev e 112211 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the IDT5V41068A. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. electrical characteristics?in put/supply/common parameters parameter symbol conditions min typ max units notes 3.3v logic supply voltage vdd 4.6 v 1,2 i nput low voltage v il gnd-0.5 v 1 input high voltage v ih v dd +0.5v v 1 storage temperature ts -65 150 c1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. ta = t com or t i nd; supply voltage vdd/vd da = 3.3 v +/-5%, see test loads for loading c onditions parameter symbol conditions min typ max units notes t com c ommmercial range 0 70 c 1 t ind industrial range -40 85 c 1 input high voltage v ih single-ended inputs, excep t smbus, low threshold and tri-level in p uts, if p re se nt 2.2 v dd + 0.3 v1 i nput low voltage v il single-ended inputs, excep t smbus, low threshold and tri-level in p uts, if p re se nt gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i in p sin gle -e nded inp uts v in = 0 v; inputs with internal pull-up resistors v in = vdd; input s w ith internal pull-down resistors -200 200 ua 1 inpu t fre quen cy f ibyp v dd = 3.3 v, bypass mode 200 mhz 2 pin i nductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c in dif _in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 oe latency t latoe# d if st art after oe# assertion d if stop af ter oe# deassertion 13clocks1,3,5 pd# latency t stabpd# dif driven to 200mv after pd e# assertion 300 usec 1,3,5 tfall t f fall time of control inputs 5 ns 1,2 trise t r r ise time of control inputs 5 ns 1,2 1 guaranteed by design and characterization, not 100% tested in product ion. 2 c ontrol input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for the oe pin to work ambient operating temperature input current 3 time from deassertion until outputs are >200 mv 4 ina/b inputs capacitance
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 8 IDT5V41068A rev e 112211 electrical characteristi cs?clock input parameters electrical characteristics?dif 0.7v current mode differential outputs electrical characterist ics?current consumption ta = t com or t ind; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading c onditions parameter symbol conditions m in typ max units n otes input h igh voltage - dif_in v ihd if dif ferential inputs ( sin g le-ended measurement ) 600 800 1150 mv 1 input low voltage - d if_in v il dif dif ferential inputs ( sin g le-ended measurement ) v ss - 300 0300mv1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 1 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j dif in differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero. ta = t com or t ind; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1.5 2.9 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 14 20 % 1, 2, 4 voltage high vhigh 660 761 850 1 voltage low vlow -150 0.6 150 1 max voltage vmax 860 1150 1 min voltage vmin -300 -78 1 vswing vswing scope averaging off 300 1531 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 354 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off -29 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of v_cross_min/max (v_cros s absolute) allowed. the intent is to limit vcross induced modulation by setting v_cross_delta to be smaller than v_cross absolut e. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? (100 ? differential impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate of clock / falling edge rate of clock#. it is measured in a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the osc illoscope uses for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). ta = t com or t ind; supply voltage vdd/vd da = 3.3 v +/-5%, see test loads for loading c onditions parameter symbol conditions min typ max units notes operating supply current i dd3.3op all outputs active @100mhz, c l = 2 pf; 40 ma 1 power down current i dd3 .3pd pd# pin low, input clock stopped 5 ma 1 1 guaranteed by design and characterization, not 100% tested in production.
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 9 IDT5V41068A rev e 112211 electrical characteristics? output duty cycle, jitter , and skew characteristics electrical characteristics?pc ie phase jitter parameter parameter symbol conditions min typ max units notes duty cycle t dc when driven by 932sq420 or equivalent 45 49 55 % 1 duty cycle distortion t dcd measured differentially, @100mhz -2 1 2 % 1,4 skew, input to output t pdby p v t = 50% 2500 3299 4500 ps 1 additive jitter t jcyc-cyc cycle to cycle additive jitter 1 5 ps 1,3 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 3 measured from differential waveform 4 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. ta = t com or t ind; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes t jphpcieg1 pcie gen 1 1 2 ps (p-p) 1,2,3,6 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.2 ps (rms) 1,2,5,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.1 0.2 ps (rms) 1,2,5,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.1 0.2 ps (rms) 1,2,4,5, 6 1 applies to all outputs. 5 for rms fi g ures, additive jitter is calculated by solvin g the followin g equation: additive jitter = sqrt[(total jittter)^2 - (input jitter)^2] 6 applies to 100mhz spread off and 0.5% down spread sources only. 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final radification by pci sig. 2 see http://www.pcisig.com for complete specs t jphpcieg2 additive phase jitter 33 hcsl output 33 50 50 hcsl differential output test load 2pf 2pf zo=100ohm differential
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 10 IDT5V41068A rev e 112211 thermal characteristics marking diagram marking diagram (industrial) notes: 1. $ is the mark code. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?g? after the two-letter package code denotes rohs compliant package. 4. ?i? denotes industrial grade. 5. bottom marking: country of origin if not usa. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 93 c/w ja 1 m/s air flow 78 c/w ja 3 m/s air flow 65 c/w thermal resistance junction to case jc 20 c/w 1 8 9 16 idt5v410 68apgg yyww$ 1 8 9 16 idt5v410 68apggi yyww$
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 11 IDT5V41068A rev e 112211 package outline and package dimensions (16-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information ?g" after the two-letter packag e code are the pb-free config uration, rohs 6 compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a -- 1.20 -- 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 a0 8 0 8 aaa -- 0.10 -- 0.004 part / order number marking shipping packaging package temperature 5v41068apgg see pg 10 tubes 16-pin tssop 0 to +70c 5v41068apgg8 see pg 10 tape and reel 16-pin tssop 0 to +70c 5v41068apggi see pg 10 tubes 16-pin tssop -40 to +85c 5v41068apggi8 see pg 10 tape and reel 16-pin tssop -40 to +85c
IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer idt? 2:1 pcie gen1/2/3 clock multiplexer 12 IDT5V41068A rev e 112211 revision history rev. originator issue date description page # a rdw 1/26/2011 initial release b rdw 6/9/2011 1. updated ordering info 2. updated electrical tables 3. added mark spec various c rdw 7/14/2011 1. updated vih min to 2.2v 7 d rdw 10/6/2011 released to final e rdw 11/22/2011 1. changed title to "2:4 pcie gen1/2/3 clock multiplexer" 2. updated pcie phase jitter table various
? 2011 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com IDT5V41068A 2:1 pcie gen1/2/3 clock multiplexer

▲Up To Search▲

Price & Availability of IDT5V41068A

	To Download IDT5V41068A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .