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general description the max155/max156 are high-speed, 8-bit, multichan - nel analog-to-digital converters (adcs) with simultaneous track/holds (t/hs) to eliminate timing differences between input channel samples. the max155 has 8 analog input channels and the max156 has 4 analog input channels. each channel has its own t/h, and all t/hs sample at the same instant. the adc converts a channel in 3.6s and stores the result in an internal 8x8 ram. the max155/ max156 also feature a 2.5v internal reference and power-down capability, providing a complete, sampling data-acquisition system. when operating from a single +5v supply, the max155/ max156 perform either unipolar or bipolar, single-ended or differential conversions. for applications requiring wider dynamic range or bipolar conversions around ground, the v ss supply pin may be connected to -5v. conversions are initiated with a pulse to the wr pin, and data is accessed from the adcs ram with a pulse to the rd pin. a bidirectional interface updates the channel configuration and provides output data. the adc may also be wired for output-only operation.the max155 comes in 28-pin pdip and wide so packages, and the max156 comes in 24-pin narrow pdip and 28-pin wide so packages. features 8 simultaneously sampling track/hold inputs 3.6s conversion time per channel unipolar or bipolar input range single-ended or differential inputs mixed input configurations possible 2.5v internal reference single +5v or dual 5v supply operation applications phase-sensitive data acquisition vibration and waveform analysis dsp analog input ac power meters portable data loggers ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max155.related . ain0 ain1 t/h 8-bit a/d 3.6s 2.5v v ref 8 8 8 8 x 8 ram control logic three- state buffer t/h ain2 t/h ain3 t/h ain4 t/h ain5 t/h ain6 t/h ain7 t/h 8 8 mode wr rd cs clk refin refout 8-bit data bus max155 max155/max156 8-/4-channel adcs with simultaneous t/hs and reference 19-2949; rev 2; 1/12 functional diagram evaluation kit available downloaded from: http:///
v dd to agnd ............................................................. -0.3v, +6v v dd to dgnd ............................................................. -0.3v, +6v agnd to dgnd ........................................... -0.3v, (v dd + 0.3v) v ss to agnd .............................................................. +0.3v, -6v v ss to dgnd ............................................................. +0.3v, -6v cs , wr , rd , clk, mode to dgnd ........... -0.3v, (v dd + 0 3v) busy, d0Cd7 to dgnd ............................... -0.3v, (v dd + 0 3v) refout to agnd ....................................... -0.3v, (v dd + 0 3v) refin to agnd ........................................... -0.3v, (v dd + 0 3v) ain to agnd .................................... (v ss - 0.3v), (v dd + 0 3v) output current (refout) ................................................. 30ma continuous power dissipation (t a = +70 c) 24-pin pdip (derate 8.7mw/ c above +70 c) ............ 696mw 28-pin pdip (derate 9.09mw/ c above +70 c) .......... 727mw 28-pin wide so (derate 12.5mw/ c above +70 c) .. 1000mw operating temperature ranges: max155/max156_c_ _ ...................................... 0 c to +70 c max155/max156_e_ _ .................................. -40 c to +85 c storage temperature range ............................ -65 c to +150 c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260 c (v dd = +5v, v refin = +2.5v. external reference, v agnd = v dgnd = 0v, v ss = 0v or -5v, f clk = 5mhz external, unipolar range single-ended mode, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units accuracy (note 1) resolution 8 bits integral linearity error max15_a ? lsb max15_b 1 no missing codes resolution guaranteed monotonic 8 bits offset error (unipolar) max15_a ? lsb max15_b 1 offset error (bipolar) max15_a 1 lsb max15_b 2 gain error unipolar max15_a 1 lsb max15_b 1 bipolar max15_a 1 max15_b 2 channel-to-channel matching max15_a ? lsb max15_b 1 dynamic performance (v in = 50khz, 2.5v p-p sine wave sampled at 220ksps) signal-to-noise and distortion ratio sinad max15_a 48 db max15_b 47 total harmonic distortion thd -60 db spurious-free dynamic range sfdr -62 db small-signal bandwidth 4 mhz aperture delay 20 ns aperture delay matching (note 2) 4 ns max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics downloaded from: http:///
(v dd = +5v, v refin = +2.5v. external reference, v agnd = v dgnd = 0v, v ss = 0v or -5v, f clk = 5mhz external, unipolar range single-ended mode, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units analog input voltage range, unipolar, single- ended ain_(+) to agnd 0 v ref v unipolar differential ain_(+) to ain_(-) 0 v ref bipolar, single-ended ain_(+) to agnd -v ref v ref bipolar, differential ain_(+) to ain_(-) -v ref v ref common-mode range differential mode v ss v dd dc input impedance ain = v dd 10 m? reference inputrefin range (for speciied performance) (note 2) 2.375 2.500 2.625 v i ref v refin = 2.5v 1 ma reference output (c l = 4.7f) output voltage i l = 0ma t a = +25c 2.44 2.50 2.56 v t a = t min to t max 2.38 2.50 2.62 load regulation t a = +25c, i out = 0 to 10ma -10 mv power-supply sensitivity t a = +25c, v dd = 5v 5% 1 3 mv temperature drift 100 ppm/c logic inputs (mode = open circuit) cs , rd , wr , clk, d0Cd7 (when inputs) input low voltage v il 0.8 v input high voltage v ih 2.4 v input current i in 10 a input capacitance (note 2) c in 15 pf mode input low voltage v il 0.5 v input high voltage v ih v dd - 0.5 v input midlevel voltage v mid v dd /2 - 0.5 v dd /2 + 0.5 v input floating voltage v flt v dd /2 v input current i in 50 100 a max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) downloaded from: http:///
(v dd = +5v, v refin = +2.5v. external reference, v agnd = v dgnd = 0v, v ss = 0v or -5v, f clk = 5mhz external, unipolar range single-ended mode, t a = t min to t max , unless otherwise noted.) (v dd = +5v, v refin = +2.5v. external reference, v agnd = v dgnd = 0v, v ss = 0v or -5v, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units logic outputs busy, d0Cd7 output low voltage v ol i out = 1.6ma 0.4 v output high voltage v oh i out = -360a 4 v d0Cd7 floating state leakage 10 a floating state output capacitance (note 2) c out 15 pf conversion time f clk = 5mhz, single channel 3.6 3.8 s power requirements positive power-supply voltage v dd 4.75 5.25 v positive power-supply current i dd pd = 0 max155 18 24 ma max156 9 12 pd = 1 clk, cs , wr , rd = 0v or v dd ; d out = 0v or v dd 25 100 a negative power-supply voltage v ss 0 -5 v negative power-supply current i ss pd = 0 2 50 a pd = 1 2 50 power-supply rejection (change in full-scale error) v dd = 5v 5%, v ss = 0v 0.1 0.25 lsb v dd = 5v, v ss = -5v 5% 0.1 parameter symbol conditions min typ max units cs to wr setup time t cws 0 ns cs to wr hold time t cwh 0 ns cs to rd setup time t crs 0 ns cs to rd hold time (note 2) t crh 0 ns wr low pulse width t wr max15_c/e 100 2000 ns rd low pulse width t rdl max15_c/e 100 ns rd high pulse width (note 2) t rdh max15_c/e 180 ns wr to rd delay (note 2) t wrd max15_c/e 280 ns wr to busy low delay t wbd max15_c/e 220 ns max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 4 timing characteristics (note 3, figures 1C7) electrical characteristics (continued) downloaded from: http:///
note 1: v dd = +5v, v refin = +2.5v, v ss = 0v. performance at 5% power-supply tolerance is guaranteed by power-supply rejection test. note 2: guaranteed by design, not production tested. note 3: all input control signals are specified with t r = t f = 20ns (10% to 90% of +5v) and timed from a +1.6v voltage level. output signals are timed from v oh and v ol . note 4: t dv is the time required for an output to cross +0.8v or +2.4v measured with load circuit of figure 1. note 5: t tr is the time required for the data lines to change 0.5v, measured with load circuits of figure 2. figure 1. load circuits for data-access timing figure 2. load circuits for three-state output timing parameter symbol conditions min typ max units busy high to wr delay (to update coniguration register) (notes 2, 3) t bwd 50 ns clk to wr delay (acquisition time) (note 2) t acq 800 ns busy high to rd delay (notes 2, 3) t brd 50 ns address-setup time t as 120 ns address-hold time t ah 0 ns rd to data valid (note 4) t dv max15_c/e 100 ns rd to data three-state output (note 5) t tr max15_c/e 80 ns clk to busy delay (note 2) t cb 100 300 ns clk frequency 0.5 5.0 mhz dn 3k ? 3k ? dgnd high-z to v oh 100pf dn +5v high-z to v ol 100pfdgnd dn 3k ? 3k ? v oh to high-z 10pf dn +5v v ol to high-z 10pf max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 5 timing characteristics (note 3, figures 1-7) (continued) (v dd = +5v, v refin = +2.5v. external reference, v agnd = v dgnd = 0v, v ss = 0v or -5v, t a = t min to t max , unless otherwise noted.) downloaded from: http:///
figure 3. write and read timing t cws t wr t wbd t conv t brd t bwd t acq t rdl t rdh t rdl t wrd t cwh t crs t crh t crs t crh t crs data in data out data out t ah t as t dv t dv t tr t tr cs wr rd busy d0Cd7 modev ss agnd 12 2423 ain1 ain0 ain3 v dd ain2 pdip top view 34 2221 wr busy d1/a1 56 2019 cs rd refout d0/a0 refin 78 1817 clk d2 9 16 d7/all d3/pd 10 15 d6/diff d4/inh 11 14 dgnd d5/bip 12 13 max156 + ain3n.c. ain0 12 2827 ain2n.c. ain1 n.c. n.c wide so 34 2625 agndrefin cs 5 24 v dd mode v ss 67 2322 refout rd 8 21 d0/a0 wr 9 20 d1/a1 busy 10 19 d2 clk 11 18 d3/pd d7/all 12 17 d4/inh d6/diff 13 16 d5/bip dgnd 14 15 + max156 ain1 ain0 ain7 12 2827 ain3 ain2 ain5 ain6 ain4 pdip/so 34 2625 cs rd refout 56 2423 modev ss agnd refin v dd 78 2221 wr d0/a0 9 20 busy d1/a1 10 19 clk d2/a2 11 18 d7/alld6/diff dgnd d3/pd d4/inh d5/bip 12 17 13 16 14 15 + max155 max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 6 pin coniguration downloaded from: http:///
pin name function max155 max156 pdip/so pdip so 1 23 26 ain3 sampling analog input, channel 3 2 24 28 ain2 sampling analog input, channel 2 3 1 2 ain1 sampling analog input, channel 1 4 2 4 ain0 sampling analog input, channel 0 5 3 5 mode mode conigures multiplexer and converter. see table 4. 6 4 6 v ss negative supply. power v ss with -5v for extended input range. 7 5 7 cs chip select input must be low for the adc to recognize rd , or wr 8 6 8 rd read input reads data sequentially from ram 9 7 9 wr write inputs rising edge initiates conversion and updates channel coniguration register. falling edge samples inputs. 10 8 10 busy busy output low when conversion is in progress 11 9 11 clk external clock input 12 10 12 d7/all three-state data output bit 7 (msb)/sequential or speciic conversion 13 11 13 d6/diff three-state data output bit 6/single-ended/differential select 14 12 14 dgnd digital ground 15 13 15 d5/bip three-state data output bit 5/unipolar/bipolar conversion 16 14 16 d4/inh three-state data output bit 4/inhibit conversion input 17 15 17 d3/pd three-state data output bit 3/power-down input 18 16 18 d2/a2 three-state data output bit 2/ram address bit a2 (max155 only) 19 17 19 d1/a1 three-state data output bit 1/ram address bit a1 20 18 20 d0/a0 three-state data output bit 0/ram address bit a0 21 19 21 refout reference output, +2.5v 22 20 22 refin reference input, +2.5 normally 23 21 23 agnd analog ground 24 22 24 v dd power-supply voltage, +5v normally 25C28 ain7C4 sampling analog input, channels 7C4 1, 3, 25, 27 n.c. no connection. no internal connectionpin unconnected. max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 7 pin description downloaded from: http:///
detailed description adc operation the max155/max156 contain a 3.6s successive approx - imation adc and 8/4 track-and-hold (t/h) inputs. when a conversion is started, all ain inputs are simultaneously sampled. all channels sample whether or not they are selected for the conversion. either a single-channel or multichannel conversion may be requested and channel configurations may be mixed, adc results are then stored in an internal ram. in hard-wired mode (see the multiplexer and aid configurations section) multichannel conversions are initiated with one write operation. in input/output (i/o) mode, multichannel configurations are set up prior to the conversion by loading channel selections into the con - figuration register. this register also selects single-ended/ differential, unipolar/bipolar (figure 9), power-down, and other functions. each channel selection requires a sepa - rate write operation (i.e. 8 writes for 8 channels), but only after power-up. once the desired channel arrangement is loaded, each subsequent write converts all selected channels without reconfiguring the multiplexer (mux). i/o mode requires more write operations, but provides more flexibility than hard-wired mode. to access conversion results, successive rd pulses auto - matically sence through ram, beginning with channel 0. each rd pulse increments the ram address counter, which resets to 0 when wr goes low in multi channel conversions. an arbitrary ram location may also be read by writing a 1 to inh while loading the ram address (a0C a2), and then performing a read operation. table 1. multiplexer configurations ?configuration inputs are shared with data outputs d0-d7. the functions of d0-d7 are not described in this table. ??diff and bip are not implemented on the current conversion, but go into effect on the.following conversion. pin name function d0/a0 d1/a1d2/a2 1 or 0 a0Ca2 select a multiple channel for the conigurations described below, or select a ram address for reading with a subsequent rd . d3/pd 0 normal adc operation 1 power-down reduces the power-supply current. coniguration data may be loaded and is maintained during power-down. d4/ i nh 0 a conversion starts when wr goes high 1 inhibits the conversion when wr goes high. allows mux coniguration to be loaded and ram locations to be accessed without starting a conversion. d5/bip** 0 unipolar conversion (figure 9a) for the channel speciied by a0Ca2. input range = 0v to v ref . 1 bipolar conversion (figure 9b) for the channel speciied by a0Ca2. input range = v ref . d6/diff** 0 single-ended coniguration for the channel speciied by a0Ca2 as described in table 2 1 differential contiguration for the channel speciied by a0Ca2 as described in table 2 d7/ all 0 all previously conigured channels are converted. data is read with consecutive rd pulses, beginning with the lowest conigured channel. 1 only the channel speciied by a2Ca0 is converted. a single rd pulse reads the result of that conversion. max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 8 downloaded from: http:///
multiplexer and a/d coniguration a conversion is started with a wr pulse. all channels sample on wr s falling edge. mux configuration data is loaded on wr s rising edge. in i/o mode (mode = open circuit), selections for channel number, single or multi - channel conversion, unipolar or bipolar input, and single- ended or differential input are made with a0-a2, all , bip, and diff (table 1). these input pins are also shared with the ram data outputs d0Cd7. an alternate, simpler inter - face is provided by the hard-wired mode, which selects some general mux configurations without requiring adc programming. hard-wired connections of mode and v ss se l ect from 4 mux configurations as l is ted in ta b l e 4 (see the hard-wired mode section) . on the rising edge of wr , the mux configuration register is updated; falling edge initiates sampling of all inputs. a channel selection can be implemented on the current conversion, but changes from unipolar to bipolar (with bip) or from single ended to differential operation (with diff) do not go into effect until the following wr . this can be overcome by writing to the configuration register while inhibiting the conversion (inh = 1), or by changing diff and bip one conversion early, i.e. on the previous write. table 2. single-ended channel selection (mode = open circuit) table 3. differential channel selection (mode = open circuit) note: shaded areas represent max156 operation. note: shaded areas represent max156 operation. mux address single-ended channel selection a0 a1 a2 diff 0 1 2 3 4 5 6 7 agnd 0 0 0 0 + - 1 0 0 0 + - 0 1 0 0 + - 1 1 0 0 + - 0 0 1 0 + - 1 0 1 0 + - 0 1 1 0 + - 1 1 1 0 + - mux address differential channel selection a0 a1 a2 diff 0 1 2 3 4 5 6 7 0 0 0 1 + - 0 1 0 1 + - 0 0 1 1 + - 0 1 1 1 + - 1 0 0 1 - + 1 1 0 1 - + 1 0 1 1 - + 1 1 1 1 - + max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 9 downloaded from: http:///
interface timing input/output mode, multichannel conversion timing i/o mode is selected when the mode input is open circuit. in i/o mode, the mux configuration register deter - mines the conversion type. the register is updated on the rising edge of wr . table 1 lists all conversion options. for example, at d6/diff, a logic 0 or 1 selects a single-ended or differen - tial conversion. data is loaded into addressed locations in the configuration register with a series of wr pulses. if inh is high while writing, no conversion takes place. a conversion is started by writing inh = 0 to the configura - tion register. when a change is made to the contents of the configuration register, a dummy conversion may be necessary. this is due to a built-in latency of one full con - version for unipolar/bipolar and single-ended/differential selections. it is not necessary to update the configuration register before every conversion. a particular mux configuration must be loaded only once after power-up (but the con - figuration may require several writes to be loaded). a mux configuration is retained for successive conversions and during power-down (pd = 1) so that reconfiguring is unnecessary when the adc returns to normal operation (pd = 0). configuration and ram data is lost only when power is removed from the adc at v dd . when updating the configuration register, inh should be high for all except the last wr so the conversion is not started until the mux is set. on wr s falling edge, all input channels sample simultaneously. busy goes low at the beginning of the conversion, and channels are converted sequentially starting with the lowest selected channel. when busy goes high, conversion results are stored in ram. at conversion end, a microprocessor (p) can access the ram contents with consecutive rd pulses. the first accessed data is the lowest channels result. subsequent rd pulses access conversion results for the remaining channels. the configuration data determines which ram locations are sequentially read by consecutive rd pulses, so new data should be placed in the configuration register only after a full rd operation. it is not necessary to update the configuration register for every conversion. a new conver - sion is initiated with a wr pulse (when inh = 0), regard - less of the number of channe ls that have been read. figure 4a shows the max155 timing for an 8-channel unipolar configuration. 8 channels are configured and 8 consecutive rd pulses access data. figure 4b illus - trates 4-channel differential conversion timing involving 4 sampled channels and 4 rd pulses. in cases where conflicting differential configurations are loaded, the last channel selected with diff = 1 will be the positive input of the differential channel. input/output mode, single-channel conver- sion timing figure 5a shows timing for a single-channel ( all = 1), single-ended conversion; figure 5b shows a differential conversion. with mode floating, the configuration reg - ister is updated on the rising edge of wr . busy goes low at the beginning of the conversion and returns high when the channel designated by the configuration reg - ister has been converted. all channels are sampled on the falling edge of wr even if only a single channel has been requested. at conversion end, the p can read the result for the selected channel with a single rd pulse. subsequent rd pulses will access old conversion results remaining in other ram locations. the next conversion is initiated with a wr pulse, regardless of the number of channels that have been read. inh and a0Ca2, in the configuration register, access loca - tions in ram. inh = 1 allows the ram address pointer to be updated without starting a conversion. a read pulse then reads the contents of the addressed location. max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 10 downloaded from: http:///
figure 4a. input/output mode timingCeight single-ended conversions t conv cs wr rd busy d0-d7 data in conversion endof all 8 channels accessed by consecutive rd pulses consecutive ram locations are update configurationregister and begin new conversion all 8 channels are sampled here note: after power-up, and prior to the above timing sequence, all single-ended channels mustbe set up by writing the following data into the configuration register. 8 wrs (see figure 3) are needed for 8 channels: a0 a1 a2 pd inh bip diff all 0 0 0 0 1 s 0 0 1 0 0 0 1 s 0 0 0 1 0 0 1 s 0 0 1 1 0 0 1 s 0 0 0 0 1 0 1 s 0 0 1 0 1 0 1 s 0 0 0 1 1 0 1 s 0 0 1 1 1 0 1 s 0 0 ch0 ch1 ch2 ch3 once the above data is loaded, all channels areconverted with a single wr to any address (this is where the above timing diagram begins). with inh = 0, and all = 0: the first ramlocation read is ch 0 s = may be selected a0 a1 a2 pd inh bip diff all 0 0 0 0 0 s 0 0 max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 11 downloaded from: http:///
figure 4b. input/output mode timingCfour differential conversions t conv data in conversion endof all 4 differential channels accessed by consecutive rd pulses consecutive ram locations are update configurationregister and begin new conversion 0,1 2,3 4,5 6,7 the first ramlocation read is ch 0,1 cs wr rd busy d0-d7 a0 a1 a2 pd inh bip diff all 0 0 0 0 1 s 0 0 1 1 0 0 1 s 0 0 0 0 1 0 1 s 0 0 1 1 1 0 1 s 0 0 once the above data is loaded, all channelsare converted with a single wr to any address (this is where the above timing diagram begins). with inh = 0, and all = 0: s = may be selected a0 a1 a2 pd inh bip diff all 0 0 0 0 0 s 0 0 note: after power-up, and prior to the above timing sequence, all differential channels mustbe set up by writing to the configuration register. (ain0, 2, 4, 6 are +, and ain1, 3, 5, 7 are - for this example). 4 wrs (see figure 3) are needed for 8 channels: all 4 differential channelsare sampled here max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 12 downloaded from: http:///
figure 5a. input/output mode timingCsingle-channel, single-ended conversion figure 5b. input/output mode timingCsingle-channel, differential conversion t conv cs wr rd busy d0-d7 data in data out update configurationregister and begin new conversion channel is sampled here note: a single-ended channel is converted by writing the following data into the configuration register(see figure 3) the bip and diff bits are not implemented until the next wr s = may be selected a0 a1 a2 pd inh bip diff all s s s 0 0 s 0 1 end of conversion read data indicatedby address t conv cs wr rd busy d0-d7 data in data out update configurationregister and begin new conversion channel is sampled here note: a differential channel is converted by writing the following data into the configuration register(see figure 3) the bip and diff bits are not implemented until the next wr s = may be selected a0 a1 a2 pd inh bip diff all s s s 0 0 s 1 1 end of conversion read data indicatedby address max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 13 downloaded from: http:///
hard-wired mode for simpler applications, the mode and v ss pins can be hard-wired to specify the type of conversion as outlined in table 4. in this mode, the configuration register is not used, so input data on do-d7 is ignored. for example, with mode tied low, an 8-channel, single-ended conver sion begins with wr with mode tied high, a 4-channel, differential conversion is init iated with wr . again, the configuration register is not affected by the data present on 00-07. these conversions are otherwise identical to those shown in figure 4. analog considerations lntemal reference the internal 2.5v reference (refout) must be bypassed to agnd (figure 8a) with a 4.7f electrolytic and a 0.1f ceramic capacitor to ensure stability. figure 6. input/output mode timingCreading arbitrary ram locations table 4. hard-wired modemultiplexer selections mode v ss conversion type open circuit x multiplexer coniguration register determines conversion type. not hard-wired. 0 agnd 8-channel, single-ended, unipolar conversion 1 agnd 4-channel, differential, unipolar conversion 0 -5v 8-channel, single-ended, bipolar conversion 1 -5v 4-channel, differential, bipolar conversion inh = 0 data in data out data out inh = 1 data out inh = 0 data in update configuration registerand begin new conversion end ofconversion read data indicatedby address update configurationregister with new address read dataat address update configuration register begin conversion all channels aresampled here note: a ram location is read by writing the following data into the configuration register and when performing a rd. if inh = 0, a conversion will begin. s = may be selected x = dont care for this wr if inh = 0, but may effect next conversion. a0 a1 a2 pd inh bip diff all s s s 0 1 x x 1 t conv cs wr rd busy d0-d7 max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 14 downloaded from: http:///
figure 7a. hard-wired mode timingeight single-ended conversions figure 7b. hard-wired mode timingeight single-ended conversions ch0 ch1 ch6 ch7 t conv end of conversionof 8 channels the first ramlocation read is ch 0 consecutive ram locations areaccessed by consecutive rd pulses mode = 0 all 8 channels aresampled here cs wr rd busy d0-d7 0, 1 2, 3 4, 5 6, 7 t conv end of conversionof 4 differential channels the first ramlocation read is ch 0, 1 consecutive ram locations areaccessed by consecutive rd pulses mode = 1 all 4 differential channelssampled here cs wr rd busy d0Cd7 max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 15 downloaded from: http:///
extemal reference if an external voltage reference is used at refin, refout must either be bypassed (figure 8b) or dis - abled to prevent its output from oscillating and generating unwanted conversion noise elsewhere in the adc. if com - ponent count is critical when using an external reference, refout may be disabled by connecting it to v dd . in this case, the unused internal reference does not need a bypass cap. a disadvantage of tying refout to v dd is that power-down current will be increased by about 250a above the specification limits. power-down mode the max155/max156 may be placed in a powered-down state by writing a 1 to the pd location in the configuration register (table 1). the register may be updated while in this state (to change mux configurations or exit power- down mode) and all register contents are retained; how - ever no data can be read from ram and no conversions can be started. the power-down command is implement - ed on wr s rising edge. to minimize current drain, the max155/max156 inter - nal reference is turned off during power-down. when returning to normal operation (pd = 0), up to 5ms may be needed to allow the reference to recharge its 4.7f bypass capacitor before a conversion is performed. if an external reference is used, and remains on during power- down, a conversion can be started within 50s after load - ing pd with a 0. bypassing a 47f electrolytic and a 0.1f ceramic capacitor should bypass v dd to agnd. if input signals below ground are expected, a negative supply is necessary. in that case, v ss should be bypassed to agnd with a 4.7f and 0.1f combination. the internal reference requires a 4.7f and 0.1f com - bination. if an external voltage reference is used, bypass refin to agnd with a 4.7f capacitor close to the chip. when an external reference is used, refout must still be either bypassed or connected to v dd . track/hold ampliiers the max155/max156 t/h amplifiers high input imped - ance usually requires no input buffering. all t/hs sample simultaneously. for best results, the analog inputs should not exceed the power-supply rails (v dd , v ss ) by more than 50mv. the time required for the t/h to acquire an input signal for one channel is a function of how quickly the channel input capacitance is charged. if the source impedance of the input signal is high, acquisition takes longer, and more time must be allowed between conversions. acquisition time is calculated by: t acq = 8(r s + r in ) x 4pf (but never less than 800ns) where r in = 15k?, and r s = source impedance of the adcs input signal. figure 8a. internal reference figure 8b. external reference, +2.5v full scale ainx refout refinagnd v ss v dd ainx (+) ainx (-) 0.1f 4.7f 0.1f 47f +5v max155max156 ainx refinagnd v ss refout v dd ainx (+) ainx (-) 0.1f +2.5v 4.7f 0.1f 47f +5v max155max156 max584 4.7f max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 16 downloaded from: http:///
conversion time conversion time is calculated by: t conv = (9 x n x 2)/f clk where n is the number of channels converted. this includes one clock cycle of uncertainty. for a single channel and 5mhz clock, the conversion time is (9 x 1 x 2)/5mhz = 3.6s. for the max155, the maxi mum conver- sion time for 8 channels is (9 x 8 x 2)/5mhz = 28.8s. in the application example (figure 10), six conversions are configured, and the conversion time is (9 x 6 x 2}/5mhz = 21.6s. applications information 9-bit a/d conversion in i/o mode, a 9th bit of resolution can be created by per - forming two unipolar differential conversions with opposite input polarities (i.e., first with ain0[+] and ain1[-], then with aino[-] and ain1[+]). only the a0 bit must be changed to reverse input channel polarity (table 3). the sign reversal also occurs on the current write without a one conversion delay. for a differential input signal, one of the two conver - sions will read 0 while the other will contain an 8-bit result. the input polarity that provides the 8-bit result indicates the 9th (sign) bit. 4 channels can be measured this way. a major drawback of this technique is that many of the sam - pling features of the max155/max156 are defeated since two separate samples are needed if only two 9-bit channels are needed, then two separate differential channels with reversed input polarities can be connected so that both input pairs sample at the same time. this way the simultaneoussampling advantages of the max155/max156 are retained. typical i/o mode application the max155/max156 address and configuration inputs for this example were determined by selecting the desired channel configurations in tables 2 and 3. figure 10 illus - trates the configuration outlined in table 5. an a/d conversion in i/o mode involves the following steps: 1) configure the mux by loading data into the con - figuration register based on selections from table 2 and/or 3 (with inh = 1 and mode = open circuit). figure 9a. transfer functionunipolar operation figure 9b. transfer functionbipolar operation table 5. typical multiplexer configuration a2 a1 a0 diff bip function 0 0 1 1 1 channel (1, 0) differential bipolar 0 1 0 0 0 channel 2 single-ended, unipolar 0 1 1 0 1 channel 3 single-ended, bipolar 1 0 0 0 1 channel 4 single-ended, bipolar 1 0 1 0 0 channel 5 single-ended, unipolar 1 1 0 1 0 channel (6. 7) differential, unipolar output code (fs - 3/2 lsb) fs = v ref fs 256 1 lsb = 1111 11111111 1110 1111 1101 0000 0011 0000 0010 0000 00010000 0000 0 1 lsb 2 lsbs ain, input voltage (lsb) fs - 1 lsb fs ain 3 lsbs output code fs = 2v ref fs 256 1 lsb = 0111 11110111 1110 0000 0010 0000 00011111 1111 1111 1110 1000 0001 1000 0000 0000 0000 +fs - 1 lsb ain -1/2 lsb +1/2 lsb max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 17 downloaded from: http:///
for this example, 6 write operations (with each address and data setting in table 5 above) load the mux after power-up. 2) sample all selected channels with a wr pulse (and inh = 0), and update or rewrite any one location of the configuration register. this write operation may be skipped by loading inh with a 0 on the last wr of the above step. the conversion then starts on the 6th wr . diff and sip cannot be changed on the 6th wr in the conversion is started at that time. when the conversion starts, busy goes low while all selected channels are sequentially converted. conversion results are stored in ram and are ready to read when busy returns high. 3) data is read from ram with inh = l and consecutive rd strobes. note that in the 6 channel configurations described in this example (figure 10), 6 rd pulses access all available data, start with the differential channel (1, 0). additional rd pulses loop around, accessing the lowest chan nel data again. 4) to start a new conversion cycle with the same mux configuration, repeat steps 2 and 3. figure 10. max155/max156 typical operating circuit max155 ain(1) differentialbipolar (0)(2) bipolar (-) 3 (+) 4 refin refout 22 21 2 (3) bipolar 1 differentialunipolar (4) bipolar 28 (5) bipolar(6) (7) 27 2.5v -1.75v agnd 23 14 6 dgnd v ss (+) 26 (-) 25 sensor 47f -5v 0.1f 47f 0.1f v dd +5v +24 47f 0.1f clk clock 11 mode 5 cs 7 rd 8 wr 9 busy 10 20...15, 13, 12 d0Cd7 data i/0 lines 8 max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 18 downloaded from: http:///
+denotes a lead(pb)-free/rohs-compliant package. *contact factory for dice specifications. part temp range pin- package error (lsbs) max155 acpi+ 0c to +70c 28 pdip ? max155bcpi+ 0c to +70c 28 pdip 1 max155acwi+ 0c to +70c 28 wide so ? max155bcwi+ 0c to +70c 28 wide so 1 max155bc/d 0c to +70c dice* 1 max155aepi+ -40c to +85c 28 pdip ? max155bepi+ -40c to +85c 28 pdip 1 max155aewi+ -40c to +85c 28 wide so ? max155bewi+ -40c to +85c 28 wide so 1 max156 acng+ 0c to +70c 24 pdip ? max156bcng+ 0c to +70c 24 pdip 1 max156acwi+ 0c to +70c 28 wide so ? max156bcwi+ 0c to +70c 28 wide so 1 max156bc/d 0c to +70c dice* 1 max156aeng+ -40c to +85c 24 pdip ? max156beng+ -40c to +85c 24 pdip 1 max156aewi+ -40c to +85c 28 wide so ? MAX156BEWI+ -40c to +85c 28 wide so 1 package type package code outline no. land pattern no. 24 pdip n24+8 21-0043 28 pdip p28+7 21-0044 28 wide so w28+3 21-0042 90-0109 max155/max156 8-/4-channel adcs with simultaneous t/hs and reference www.maximintegrated.com maxim integrated 19 ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos downloaded from: http:///
revision number revision date description pages changed 0 11/91 initial release 1 6/94 revised figure 9a 16 2 1/12 removed military grade packages and updated stylistic changes 1C5, 18C20 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max155/max156 8-/4-channel adcs with simultaneous t/hs and reference ? 2012 maxim integrated products, inc. 20 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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