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this is information on a product in full production. october 2013 docid13620 rev 5 1/39 VND5E008AY-E double channel high-side driver with analog current sense for automotive applications datasheet - production data features ? general: ? inrush current active management by power limitation ? very low standby current ? 3.0v cmos compatible input ? optimized electromagnetic emission ? very low electromagnetic susceptibility ? compliant with european directive 2002/95/ec ? proportional load current sense ? high current sense precision for wide range current ? very low current sense leakage ? diagnostic functions: ? off-state open-load detection ? current sense disable ? thermal shutdown indication ? output short to v cc detection ? overload and short to ground (power limitation) indication ? protection: ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? protection against loss of ground and loss of v cc ? thermal shut down ? reverse battery protection with self switch of the power mos applications ? all types of resistive, inductive and capacitive loads description the VND5E008AY-E is a device made using stmicroelectronics ? vipower ? mo-5 technology. it is intended for driving resistive or inductive loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes. this device integrates an analog current sense which delivers a current proportional to the load current when cs_dis high leads the current sense pin in high impedance. fault conditions such as overload, overtemperature or open-load are reported via the current sense pin output current limitation protects the device in overload condition. in case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears. max transient supply voltage v cc 41 v operating voltage range v cc 4.5 to 28v typ on-state resistance (per ch.) r on 8 m current limitation (typ) i limh 76 a off-state supply current i s 2 a (1) 1. typical value with all loads connected. powersso-36 www.st.com
contents VND5E008AY-E 2/39 docid13620 rev 5 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1 short to vcc and off-state open-load detection . . . . . . . . . . . . . . . . . . 27 3.4 maximum demagnetization energy (v cc = 13.5 v) . . . . . . . . . . . . . . . . . 29 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
docid13620 rev 5 3/39 VND5E008AY-E list of tables 3 list of tables table 1. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. switching (v cc = 13v; t j = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. current sense (8 v < v cc < 18 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. open-load detection (8 v < v cc < 18 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12. electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
list of figures VND5E008AY-E 4/39 docid13620 rev 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. i out /i sense vs i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. delay response time between rising edge of output current and rising edge of current sense (cs enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15. short to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. t j evolution in overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 20. input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 21. input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 22. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 23. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 24. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 25. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. i limh vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 27. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 28. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 29. cs_dis clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 30. low level cs_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 31. high level cs_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 32. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 33. current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 34. maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 35. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 36. rthj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . 31 figure 37. powersso-36 thermal impedance junction ambient single pulse (one channel on) . . . . 31 figure 38. thermal fitting model of a double channel hsd in powersso-36 . . . . . . . . . . . . . . . . . . . 32 figure 39. powersso-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 40. powersso-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 41. powersso-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
docid13620 rev 5 5/39 VND5E008AY-E block diagram and pin description 38 1 block diagram and pin description figure 1. block diagram table 1. pin function name function v cc battery connection out 1,2 power output gnd ground connection in 1,2 voltage controlled input pin with hysteresis, cmos compatible. controls output switch state cs 1,2 analog current sense pin, delivers a current proportional to the load current cs_dis active high cmos compatible pin, to disable the current sense pin &rqwuro 'ldjqrvwlf 9 && &+ &rqwuro 'ldjqrvwlf /2*,& '5,9(5 9 21 /lplwdwlrq &xuuhqw /lplwdwlrq 3rzhu &odps 2yhu whps 8qghuyrowdjh 9 6(16(+ &xuuhqw 6hqvh &+ 29(5/2$'3527(&7,21 $&7,9(32:(5/,0,7$7,21 ,1 ,1 &6 &6 &6b ',6 *1' 287 287 6ljqdo&odps 5hyhuvh %dwwhu\ 3urwhfwlrq )dxow *$3*&)7
block diagram and pin description VND5E008AY-E 6/39 docid13620 rev 5 figure 2. configuration diagram (top view) table 2. suggested connections for unused and not connected pins connection / pin current sense n.c. output input cs_dis floating not allowed x x x x to ground through 1 k resistor x not allowed through 10 k resistor through 10 k resistor 7$ % 9 && 287 287 287 287 287 287 287 287 287 287 287 287 287 287 287 287 287 287 287 287 1& ,1 1& 1& &6 1& 1& *1' 1& 1& &6 1& 1& &6b',6 ,1 1& ("1($'5
docid13620 rev 5 7/39 VND5E008AY-E electrical specifications 38 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings 9 )q , 6 , *1' 9 && 9 && 9 6(16( 287 , 287 , 6(16( ,1 , ,1 9 ,1 9 287 *1' &6b',6 , &6' 9 &6' ,1 , ,1 9 ,1 &6 287 , 287 , 6(16( 9 6(16( 9 287 &6 *$3*&)7 table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 28 v v ccpk transient supply voltage (t < 400 ms, r load > 1 )41v -v cc reverse dc supply voltage 16 v v cc_lsc maximum supply voltage for full protection to short-circuit (acc. aec-q100-012) 18 v -i gnd dc reverse ground pin current 200 ma i out dc output current internally limited a -i out reverse dc output current 50 a i in dc input current -1 to 10 ma i csd dc current sense disable input current -1 to 10 ma v csense current sense maximum voltage v cc - 41 +v cc v v e max maximum switching energy (single pulse) (l = 0.85 mh; r l = 0 ; v bat = 13.5 v; t jstart = 150 c; i out = i liml (typ.) ) 260 mj v esd electrostatic discharge (human body model: r = 1.5 k ; c = 100 pf) ?v cc , output ? input, cs_dis ? current sense 5000 4000 2000 v
electrical specifications VND5E008AY-E 8/39 docid13620 rev 5 2.2 thermal data v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c table 3. absolute maximum ratings (continued) symbol parameter value unit table 4. thermal data symbol parameter max. value unit r thj-case thermal resistance junction-case (max) (with one channel on) 0.85 c/w r thj-amb thermal resistance junction-ambient (max) see figure 36 in the thermal section c/w
docid13620 rev 5 9/39 VND5E008AY-E electrical specifications 38 2.3 electrical characteristics 8 v < v cc < 28 v; -40 c < t j < 150 c, unless otherwise specified table 5. power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 4.5 13 28 v v usd undervoltage shutdown 3.5 4.5 v v usdhyst undervoltage shutdown hysteresis 0.5 v r on on-state resistance i out = 6 a; t j = 25 c 8 m i out = 6 a; t j = 150 c 15 m i out = 6 a; v cc = 5 v; t j = 25 c 11 m r on rev reverse battery on-state resistance v cc = -13 v; i out = -6 a; t j = 25 c 8m v clamp clamp voltage i s = 20 ma 41 46 52 v i s supply current off-state; v cc = 13 v; t j = 25 c; v in = v out = v sense = v csd = 0 v 2 (1) 1. powermos leakage included. 5 (1) a on-state; v cc = 13 v; v in = 5 v; i out = 0 a 3.5 6.5 ma i l(off) off-state output current (2) 2. for each channel. v in = v out = 0 v; v cc = 13 v; t j = 25 c 00.013 a v in = v out = 0 v; v cc = 13 v; t j = 125 c 5a table 6. switching (v cc = 13v; t j = 25c) symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l = 2.2 (see figure 8 )?30?s t d(off) turn-off delay time r l = 2.2 (see figure 8 )?15?s (dv out /dt) on turn-on voltage slope r l = 2.2 ? see figure 23 ?v / s (dv out /dt) off turn-off voltage slope r l = 2.2 ? see figure 24 ?v / s w on switching energy losses during t won r l = 2.2 (see figure 8 )?1.2?mj w off switching energy losses during t woff r l = 2.2 (see figure 8 )?0.43?mj
electrical specifications VND5E008AY-E 10/39 docid13620 rev 5 table 7. current sense (8 v < v cc < 18 v) symbol parameter test conditions min. typ. max. unit k 0 i out /i sense i out = 0.25 a; v sense = 0.5 v t j = -40 c...150 c 3658 6000 8926 k 1 i out /i sense i out = 6 a; v sense = 0.5 v t j = -40 c...150 c t j = 25 c...150 c 3910 4336 6000 6000 8928 8044 dk 1 /k 1 (1) current sense ratio drift i out = 6 a; v sense = 0.5 v v csd = 0 v; t j = -40 c to 150 c -12 12 % k 2 i out /i sense i out = 10 a; v sense = 4 v t j = -40 c...150 c t j = 25 c...150 c 4948 5298 6000 6000 7372 6762 dk 2 /k 2 (1) current sense ratio drift i out = 10 a; v sense = 4 v; v csd = 0 v; t j = -40 c to 150 c -7 7 % k 3 i out /i sense i out = 25 a; v sense = 4 v t j = -40 c...150 c t j = 25 c...150 c 5455 5535 6000 6000 6762 6282 dk 3 /k 3 (1) current sense ratio drift i out = 25 a; v sense = 4 v; v csd = 0v; t j = -40 c to 150 c -5 5 % i sense0 analog sense leakage current i out = 0 a; v sense = 0 v; v csd = 5 v; v in = 0 v; t j = -40 c...150 c 01a v csd = 0 v; v in = 5 v; t j = -40 c...150 c 02a i out = 6 a; v sense = 0 v; v csd = v in = 5 v; 01a v sense max analog sense output voltage i out = 15 a; v csd = 0 v 5 v v senseh analog sense output voltage in overtemperature condition (2) v cc = 13 v; r sense = 10 k 8v i senseh analog sense output current in overtemperature condition (2) v cc = 13 v; v sense = 5 v 9 ma t dsense1h delay response time from falling edge of cs_dis pin v sense < 4 v, 1.5 a < i out < 25 a i sense = 90 % of i sense max (see figure 4 ) 50 100 s
docid13620 rev 5 11/39 VND5E008AY-E electrical specifications 38 t dsense1l delay response time from rising edge of cs_dis pin v sense < 4 v, 1.5 a < i out < 25 a i sense = 10 % of i sense max (see figure 4 ) 520s t dsense2h delay response time from rising edge of input pin v sense < 4 v, 1.5 a < i out < 25 a i sense = 90 % of i sense max (see figure 4 ) 70 300 s t dsen se 2h delay response time between rising edge of output current and rising edge of current sense v sense < 4 v, i sense = 90 % of i sensemax, i out = 90 % of i outmax i outmax = 5 a (see figure 11 ) 300 s t dsense2l delay response time from falling edge of input pin v sense < 4 v, 1.5 a < i out < 25 a i sense = 10 % of i sense max (see figure 4 ) 100 250 s 1. parameter guaranteed by design; it is not tested. 2. fault condition includes: power limitation, overtemperature and open load off-state detection. table 8. open-load detection (8 v < v cc < 18 v) symbol parameter test conditions min typ max unit v ol open-load off-state voltage detection threshold v in = 0 v 2 ? 4 v t dstkon output short circuit to v cc detection delay at turn-off see figure 5 180 ? 1200 s i l(off2)r off-state output current at v out = 4 v v in = 0v; v sense = 0 v; v out rising from 0 v to 4 v -120 ? 90 a i l(off2)f off-state output current at v out = 2 v v in = 0v; v sense = v senseh ; v out falling from v cc to 2 v -50 ? 90 a table 9. protections (1) symbol parameter test conditions min. typ. max. unit i limh dc short circuit current v cc = 13 v 53 76 106 a 5 v < v cc < 18 v 106 a i liml short circuit current during thermal cycling v cc = 13 v; t r < t j < t tsd 21 a t tsd shutdown temperature 150 175 200 c t r reset temperature t rs +1 t rs +5 c t rs thermal reset of status 135 c table 7. current sense (8 v < v cc < 18 v) (continued) symbol parameter test conditions min. typ. max. unit
electrical specifications VND5E008AY-E 12/39 docid13620 rev 5 figure 4. current sense delay characteristics t hyst thermal hysteresis (t tsd - t r ) 7c v demag turn-off output voltage clamp i out = 2 a; v in = 0; l = 6 mh v cc - 29 v cc - 32 v cc - 36 v v on output voltage drop limitation i out = 0.4 a; t j = -40 c...150 c (see figure 10 ) 25 mv 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper so ftware strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. table 10. logic input symbol parameter test conditions min. typ. max. unit v il input low level voltage 0.9 v i il low level input current v in = 0.9 v 1 a v ih input high level voltage 2.1 v i ih high level input current v in = 2.1 v 10 a v i(hyst) input hysteresis voltage 0.25 v v icl input clamp voltage i in = 1 ma 5.5 7 v i in = -1 ma -0.7 v v csdl cs_dis low level voltage 0.9 v i csdl low level cs_dis current v csd = 0.9 v 1 a v csdh cs_dis high level voltage 2.1 v i csdh high level cs_dis current v csd = 2.1 v 10 a v csd(hyst ) cs_dis hysteresis voltage 0.25 v v cscl cs_dis clamp voltage i csd = 1 ma 5.5 7 v i csd = -1 ma -0.7 v table 9. protections (1) (continued) symbol parameter test conditions min. typ. max. unit 6(16(&855(17 ,1387 /2$'&855(17 &6b',6 w '6(16(+ w '6(16(/ w '6(16(/ w '6(16(+ $*9
docid13620 rev 5 13/39 VND5E008AY-E electrical specifications 38 figure 5. open-load off-state delay timing figure 6. i out /i sense vs i out 9 ,1 9 &6 w '67.21 287387678&.$79 && 9 287 !9 2/ 9 6(16(+ $*9 i o u t /i / i s e n s e 2 5 0 0 3 2 5 0 4 0 0 0 4 7 5 0 5 5 0 0 6 2 5 0 7 0 0 0 7 7 5 0 8 5 0 0 9 2 5 0 10 1 0 0 0 0 10 1 0 7 5 0 0 . 0 5 . 0 1 0 . 0 1 5 . 0 20 2 0 . 0 25 2 5 . 0 iou i o u t [ a ] a b c d e a : : m a x , , t j = = - 40 4 0 c t t o 1 50 5 0 c d : m m i n , , t j = 25 2 5 c t t o 150 1 5 0 c b : : m a x , , t j = = 25 2 5 c t t o 1 50 5 0 c e : : m i n , , t j = - 4 0 c t t o 150 1 5 0 c c : : t y p i c a l , t j = - 40 4 0 c t t o 1 5 0 c gapgri00301
electrical specifications VND5E008AY-E 14/39 docid13620 rev 5 figure 7. maximum current sense ratio drift vs load current table 11. truth table conditions input output sense (v csd = 0 v) (1) 1. if the v csd is high, the sense output is at a high impedance, its potential depends on leakage currents and external circuit. normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overload h h x (no power limitation) cycling (power limitation) nominal v senseh short circuit to gnd (power limitation) l h l l 0 v senseh open-load off-state (with external pull up) lhv senseh short circuit to v cc (external pull up disconnected) l h h h v senseh < nominal negative output voltage clamp ll 0 -20 -15 -10 -5 0 5 10 15 20 0 5 10 15 20 25 30 iout [a] dk/k [%] a b a : max, tj = -40 c to 150 c b : min, tj = -40 c to 150 c
docid13620 rev 5 15/39 VND5E008AY-E electrical specifications 38 figure 8. switching characteristics figure 9. delay response time between rising edge of output current and rising edge of current sense (cs enabled) 9 287 g9 287 gw rq w u w i w grii ,1387 w w w grq g9 287 gw rii *$3*&)7 w :rq w :rii 9 ,1 , 287 , 2870$; , 2870$; w w w , 6(16(0$; ?w '6(16(+ , 6(16( , 6(16(0$; *$3*&)7
electrical specifications VND5E008AY-E 16/39 docid13620 rev 5 figure 10. output voltage drop limitation 9 21 , 287 7 m ?& 7 m ?& 7 m ?& 9 21 5 21 7 9 && 9 287 $*9
docid13620 rev 5 17/39 VND5E008AY-E electrical specifications 38 table 12. electrical transient requirements (part 1) iso 7637-2: 2004(e) test pulse test levels (1) 1. the above test levels must be considered referred to v cc = 13.5 v except for pulse 5b. number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75 v -100 v 5000 pulses 0.5 s 5 s 2 ms, 10 2a +37 v +50 v 5000 pulses 0.2 s 5 s 50 s, 2 3a -100 v -150 v 1h 90 ms 100 ms 0.1 s, 50 3b +75 v +100 v 1h 90 ms 100 ms 0.1 s, 50 4 -6 v -7 v 1 pulse 100 ms, 0.01 5b (2) 2. valid in case of external load dump clamp: 40v maximum referred to ground. the protection strategy allows powermos to be cyclically switched on duri ng load dump, so distributing the load dump energy along the time and to transfer a part of it to the load. +65 v +87 v 1 pulse 400 ms, 2 table 13. electrical transient requirements (part 2) iso 7637-2: 2004(e) test pulse test level results (1) 1. the above test levels must be considered referred to v cc = 13.5 v except for pulse 5b. iii iv 1c c 2a c c 3a c c 3b c c 4c c 5b (2)(3) 2. valid in case of external load dump clamp: 40v maximum referred to ground. the protection strategy allows powermos to be cyclically switched on dur ing load dump, so distributing the load dump energy along the time and to transfer a part of it to the load. 3. suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in table 3: absolute maximum ratings . cc table 14. electrical transient requirements (part 3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the
electrical specifications VND5E008AY-E 18/39 docid13620 rev 5 2.4 waveforms figure 11. normal operation figure 12. overload or short to gnd , 287 9 6(16( 9 &6b',6 ,1387 1rplqdoordg 1rplqdoordg 1rupdorshudwlrq $*9 3rzhu/lplwdwlrq , /lp+ ! , /lp/ ! 7khupdof\folqj 2yhuordgru6kruwwr*1' , 287 9 6(16( 9 &6b',6 ,1387 $*9
docid13620 rev 5 19/39 VND5E008AY-E electrical specifications 38 figure 13. intermittent overload ! 1rplqdoordg ,qwhuplwwhqw2yhuordg ! 2yhuordg ! , 287 9 6(16( 9 &6b',6 ,1387 9 6(16(+ , /lp+ , /lp/ $*9
electrical specifications VND5E008AY-E 20/39 docid13620 rev 5 figure 14. off-state open-load with external circuitry 2)) 6wdwh2shq/rdg zlwkh[whuqdoflufxwu\ ! , 287 9 6(16( 9 &6b',6 ,1387 9 287 $*9 9 2/ 9 287 !9 2/ 9 6(16(+ w '67.rq
docid13620 rev 5 21/39 VND5E008AY-E electrical specifications 38 figure 15. short to v cc figure 16. t j evolution in overload or short to gnd w '67.rq 5hvlvwlyh 6kruwwr9 && +dug 6kruwwr9 && 6kruwwr9 && , 287 9 287 9 &6b',6 9 2/ 9 287 !9 2/ w '67.rq $*9 7 - hyroxwlrqlq 2yhuordgru6kruwwr*1' , /lp+ ! 3rzhu/lplwdwlrq 6hoiolplwdwlrqriidvwwkhupdowudqvlhqwv ,1387 7 - , 287 7 -b67$57 7 5 7 76' 7 +<67 , /lp/ $*9
electrical specifications VND5E008AY-E 22/39 docid13620 rev 5 2.5 electrical characteristics curves figure 17. off-state output current figure 18. high level input current figure 19. input clamp voltage figure 20. input high level figure 21. input low level figure 22. input hysteresis voltage 7f> ?&@ ,orii>q$@ *$3*&)7 7f> ?&@ ,lk>x$@ *$3*&)7 9lq 9 7f> ?&@ 9lfo>9@ ,lq p$ *$3*&)7 7f> ?&@ 9lk>9@ *$3*&)7 7f> ?&@ 9lo>9@ *$3*&)7 7f> ?&@ 9lk\vw>9@ *$3*&)7
docid13620 rev 5 23/39 VND5E008AY-E electrical specifications 38 figure 23. on-state resistance vs t case figure 24. on-state resistance vs v cc figure 25. undervoltage shutdown figure 26. i limh vs t case figure 27. turn-on voltage slope figure 28. turn-off voltage slope 7f> ?&@ 5rq>p2kp@ ,rxw $ 9ff 9 *$3*&)7 9ff>9@ 5rq>p2kp@ 7f ?& 7f ?& 7f ?& 7f ?& *$3*&)7 7f> ?&@ 9xvg>9@ *$3*&)7 7f> ?&@ ,olpk>$@ 9ff 9 *$3*&)7 7f> ?&@ g9rxwgw2q>9pv@ 9ff 9 5o *$3*&)7 7f> ?&@ g9rxwgw2ii>9pv@ 9ff 9 5o *$3*&)7
electrical specifications VND5E008AY-E 24/39 docid13620 rev 5 figure 29. cs_dis clamp voltage figure 30. low level cs_dis voltage figure 31. high level cs_dis voltage 7f> ?&@ 9fvgfo>9@ ,lq p$ *$3*&)7 7f> ?&@ 9fvgo>9@ *$3*&)7 7f> ?&@ 9fvgk>9@ *$3*&)7
docid13620 rev 5 25/39 VND5E008AY-E application information 38 3 application information figure 32. application schematic 3.1 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the v ccpk max rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. 3.2 mcu i/os protection when negative transients are present on the v cc line, the control pin is pulled negative to approximately -1.5 v. st suggests to insert a resistor (r prot ) in line to prevent the microcontroller i/o pins from latching-up. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os. equation 1: -v ccpeak / i latchup r prot (v oh c - v ih ) / i ihmax calculation example: for v ccpeak = - 1.5 v; i latchup 20 ma; v oh c 4.5 v 75 r prot 240 k . recommended values: r prot =10 k , c ext =10 nf . 9 && *1' 287387 ' og p & 9 &6b',6 ,,1387 5 surw 5 surw &855(176(16( 5 surw 5 6(16( & h[w *$3*&)7 note: channel 2 has the same internal circuit as channel 1.
application information VND5E008AY-E 26/39 docid13620 rev 5 3.3 current sense and diagnostic the current sense pin performs a double function (see figure 33: current sense and diagnostic ): ? current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio k x . the current i sense can be easily converted to a voltage v sense by means of an external resistor r sense . linearity between i out and v sense is ensured up to 5 v minimum (see parameter v sense in table 7: current sense (8 v < vcc < 18 v) ). the current sense accuracy depends on the output current (refer to current sense electrical characteristics table 7: current sense (8 v < vcc < 18 v) ). ? diagnostic flag in fault conditions , delivering a fixed voltage v senseh up to a maximum current i senseh in case of the following fault conditions (refer to table 11: truth table ): ? power limitation activation ? overtemperature ? short to v cc in off-state ? open-load in off-state with additional external components. a logic level high on cs_dis pin sets at the same time all the current sense pins of the device in a high-impedance state, thus disabling the current monitoring and diagnostic detection. this feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and adc line among different devices.
docid13620 rev 5 27/39 VND5E008AY-E application information 38 figure 33. current sense and diagnostic 3.3.1 short to v cc and off-state open-load detection short to v cc a short-circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off-state. small or no current is delivered by the current sense during the on-state depending on the nature of the short-circuit. off-state open-load with external circuitry detection of an open-load in off mode requires an external pull-up resistor r pu connecting the output to a positive supply voltage v pu . it is preferable v pu to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. an external pull-down resistor r pd connected between output and gnd is mandatory to avoid misdetection in case of floating outputs in off-state (see figure 33: current sense and diagnostic ). r pd must be selected in order to ensure v out < v olmin unless pulled-up by the external circuitry: 0dlq026q 9 287q , /riiu 5 6(16( 5 3527 7rx&$'& 5 3' 5 38 9 38 3zub/lp 9 6 ( 1 6 ( 38b&0' 2yhuwhpshudwxuh 2/2)) 9 2/ &855(17 6(16(q , 287 . ; , 6(16(+ 9 %$7 , /riii 9 6(16(+ /rdg ,1387q 9 && *1' &6b',6 ("1($'5
application information VND5E008AY-E 28/39 docid13620 rev 5 equation 2: r pd 22 k is recommended. for proper open-load detection in off-state, the external pull-up resistor must be selected according to the following formula: equation 3: for the values of v olmin ,v olmax , i l(off2)r and i l(off2)f (see table 8: open-load detection (8 v < vcc < 18 v) ). v v i r v ol f off l pd off up pull out 2 min ) 2 ( _ = < ? = ? () () () v v r r i r r v r v ol pd pu r off l pd pu pu pd on up pull out 4 max ) 2 ( _ = > + ? ? ? ? = ?
docid13620 rev 5 29/39 VND5E008AY-E application information 38 3.4 maximum demagnetization energy (v cc = 13.5 v) figure 34. maximum turn-off current versus inductance note: values are generated with r l = 0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. demagnetization demagnetization demagnetization t v in , i l c : t jstart = 125 c (repetitive pulse) a : t jstart = 150 c (single pulse) b : t jstart = 100 c (repetitive pulse) ,$ /p+ 91'($ < 6lqjoh 3xovh 5hshwlwlyhsxovh7mvwduw ?& 5hshwlwlyhsxovh7mvwduw ?& ("1($'5
package and pcb thermal data VND5E008AY-E 30/39 docid13620 rev 5 4 package and pcb thermal data 4.1 powersso-36 thermal data figure 35. powersso-36 pc board $*9 note: layout condition of r th and z th measurements (board finish thic kness 1.6 mm +/-10 %; board double layer; board dimension 129 mm x 60 mm; board material fr4; cu thickness 0.070 mm; thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/-0.08 mm; cu thickness on vias 0.025 mm; footprint dimension 4.1 mm x 6.5 mm)
docid13620 rev 5 31/39 VND5E008AY-E package and pcb thermal data 38 figure 36. r thj-amb vs pcb copper area in open box free air condition (one channel on) figure 37. powersso-36 thermal impedance junction ambient single pulse (one channel on) 57+mdpe 57+mdpe 57+mbdpe?&: *$3*&)7 3&%&xkhdwvlqnfpa =7+?&: 7lphv &x fp &x fp &x irrwsulqw ("1($'5
package and pcb thermal data VND5E008AY-E 32/39 docid13620 rev 5 figure 38. thermal fitting model of a double channel hsd in powersso-36 equation 4: pulse calculation formula table 15. thermal parameter area/island (cm 2 ) footprint 2 8 r1 = r7 (c/w) 0.05 r2 = r8 (c/w) 0.3 r3 (c/w) 5 r4 (c/w) 8 r5 (c/w) 18 10 10 r6 (c/w) 27 23 14 c1 = c7 (w.s/c) 0.004 c2 = c8 (w.s/c) 0.008 c3 (w.s/c) 0.04 c4 (w.s/c) 0.5 c5 (w.s/c) 1 2 2 c6 (w.s/c) 3 6 9 *$3*&)7 note: the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycl ing during thermal shutdown) are not triggered. z th r th z thtp 1 ? () + ? = where t p t ? =
docid13620 rev 5 33/39 VND5E008AY-E package information 38 5 package information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information VND5E008AY-E 34/39 docid13620 rev 5 5.2 powersso-36 mechanical data figure 39. powersso-36 package dimensions ("1($' 5
docid13620 rev 5 35/39 VND5E008AY-E package information 38 table 16. powersso-36 mechanical data symbol millimeters min. typ. max. a 2.15 ? 2.47 a2 2.15 ? 2.40 a1 0 ? 0.075 b 0.18 ? 0.36 c 0.23 ? 0.32 d 10.10 ? 10.50 e 7.4 ? 7.6 e?0.5? e3 ? 8.5 ? g??0.1 g1 ? ? 0.06 h 10.1 ? 10.5 h??0.4 l 0.55 ? 0.85 n ? ? 10 deg x 4.1 ? 4.7 y 6.5 ? 7.1
package information VND5E008AY-E 36/39 docid13620 rev 5 5.3 packing information figure 40. powersso-36 tube shipment (no suffix) figure 41. powersso-36 tape and reel shipment (suffix ?tr?) $ & % all dimensions are in mm. base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1 9 86 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed gapgcft00003
docid13620 rev 5 37/39 VND5E008AY-E order codes 38 6 order codes table 17. device summary package order codes tube tape and reel powersso-36 VND5E008AY-E vnd5e008aytr-e
revision history VND5E008AY-E 38/39 docid13620 rev 5 7 revision history table 18. document revision history date revision changes 05-jun-2007 1 initial release 20-apr-2011 2 updated features list. updated following figures: ? figure 1: block diagram ? figure 2: configuration diagram (top view) ? figure 3: current and voltage conventions inserted following figures: ? figure 6: iout/isense vs iout ? figure 7: maximum current sense ratio drift vs load current ? figure 9: delay response time between rising edge of output current and rising edge of current sense (cs enabled) . updated following tables: ? table 1: pin function ? table 2: suggested connections for unused and not connected pins ? table 3: absolute maximum ratings v ccpk , v esd : updated parameter v cc_lsc , -i gnd : added parameter updated e max parameter ? table 4: thermal data r thj-case : added value ? table 5: power section ? table 6: switching (vcc = 13v; tj = 25c) ? table 7: current sense (8 v < vcc < 18 v) updated dk 1 /k 1, dk 2 /k 2 and dk 3 /k 3 minimum and maximum values v senseh , i senseh : added note ? table 8: open-load detection (8 v < vcc < 18 v) ? table 9: protections updated v demag and i limh values ? table 13: electrical transient requirements (part 2) added section 2.4: waveforms . updated section 2.5: electrical characteristics curves updated chapter 3: application information updated chapter 4: package and pcb thermal data 12-july-2012 3 updated figure 39: powersso-36 package dimensions 20-sep-2013 4 updated disclaimer. 25-oct-2013 5 updated footnote 2 into the table 12: electrical transient requirements (part 1) and table 13: electrical transient requirements (part 2) .
docid13620 rev 5 39/39 VND5E008AY-E 39 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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