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this product conforms to specifications per the terms of the ramtron standard warranty. the product has completed ramtrons internal qualification testing and has reached production status. cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 001 - 84492 rev. * b revised may 2 9 , 2013 fm 25v01 128 k b serial 3v f - ram memor y features 128 k bi t ferroelectric nonvolatile ram organized as 16 ,384 x 8 bits high endurance 100 trillion (10 14 ) read/writes 10 year data retention nodelay? writes advanced high - reliability ferroelectric process ver y fast serial peripheral interface - spi up to 40 mhz frequency direct hardware replacement for serial flash spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) write protection scheme hardware protection software protection device id device id reads out m anufactur er id & part id low voltage, low power low voltage oper ation 2.0 v C 3.6v active current 120 a (typ. @ 1mhz) standby current 90 a (typ.) sleep mode current 5 a (typ.) industry standard configurations industrial temperature - 40 c to + 85 c 8 - pin green/ rohs soic package description the fm 25v01 is a 128 - kilo bit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile and performs reads and writes like a ram. it provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by serial flash and other nonvolatile memories. unlike serial flash , the fm 25v01 performs write operations at bus speed. no write delays ar e incurred. data is written to the memory array immediately after it has been transferred to the devic e. the next bu s cycle may commence without the need for data polling . t he product offers v ery high write endurance , orders of magnitude more endurance tha n serial flash. also, f - ram exhibits low er power consumption than serial flash . these capabilities make the fm 25v01 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls whe re the long write time of serial flash can cause data loss. the fm 25v01 provides substantial benefits to users of serial flash as a hardware drop - in replacement. the de vice use s the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. the device incorporate s a read - only device id that allows the host to determine the manufacturer, product density, and product revision. the device is gua ranteed over an industrial temperature range of - 40c to +85c. pin configuration pin name function /s chip select /w write protect /hold hold c serial clock d serial data input q serial data output vdd supply volt age vss ground s q w vss vdd hold c d 1 2 3 4 8 7 6 5
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 2 of 1 8 figure 1. block diagram pin descriptions pin name i/o description / s input chip select: this active - low input activates the device. when high, the device enters low - power standby mode, ignores other inp uts, and all outputs are tri - stated. when low, the device internally activates the c signal. a falling edge on / s must occur prior to every op - code. c input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the ris ing edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 40 mhz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory op eration for another task. when /hold is low, the current operation is suspended. the device ignores any transition on c or / s . all transitions on /hold must occur while c is low. this pin has a weak internal pull - up (see r in spec, pg 11). however, if it is not used, the /hold pin should be tied to v dd . /w input write protect: this active - low pin prevents write operations to the status register only. a complete explanation of write protection is provided on pages 6 and 7. if not used, the /w pin should be tied to v dd . d input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of c and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. * d may be connected to q for a single pin data interface. q output serial output: this is the data output pin. it is driven during a read and remains tri - stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clo ck. * q may be connected to d for a single pin data interface. vdd supply power supply vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 2 k x 64 fram array 14 data i / o register 8 nonvolatile status register 3 w s c q d hold
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 3 of 1 8 overview the fm 25v01 is a serial f - ram memory. the memory array is logically organized as 16,384 x 8 and is accessed using an industry standard s erial peripheral interface or spi bus. functional operation of the f - ram is similar to serial flash . the major difference s between the fm 25v01 and a serial flash with the same pinout are the f - ram ?s superior write performance , very high endurance, and lowe r power consumption. memory architecture when accessing the fm 25v01 , the user addresses 16k locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit mul tiple devices on the bus), an op - code, and a two - byte address. the complete address of 14 - bits specifies each byte address uniquely. most functions of the fm 25v01 either are controlled by the spi interface or are handled automatically by on - board circuit ry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike serial flash , it is not necessary to poll the device for a ready condit ion since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained in more detail in the interface section. users expect several obvious system benefits from th e fm 25v01 due to its fast write cycle and high endurance as compared to serial flash . in addition there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less suscepti ble to corruption than serial flash since it is completed quickly. by contrast, serial flash requiring milliseconds to write is vulnerable to noise during much of the cycle. serial peripheral interface C spi bus the fm 25v01 employs a serial peripheral interface (spi) bus. it is speci fied to operate at speeds up to 40 mhz . this high - speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm 25v01 operates in spi mode 0 and 3. protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. e ach device is activated using a chip select. once chip select is activated by the bus master, the fm 25v01 will begin monitoring the clock and data lines. the relationship between the falling edge of / s , the clock and data is dictated by the spi mode. the d evice will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm 25v01 supports only modes 0 and 3. figure 2 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm 25v01 on the rising edge of c and data is expected on the first rising edge after / s goes active. if the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. the spi p rotocol is controlled by op - codes. these op - codes specify the commands to the device. after / s is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. certain op - code s are commands with no subsequent data transfer. the / s must go inactive after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select. spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 2. spi modes 0 & 3 s c d m s b l s b 7 6 5 4 3 2 1 0 s c d m s b l s b 7 6 5 4 3 2 1 0
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 4 of 1 8 system hookup the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm 25v01 devices wit h a microcontroller that has a dedicated spi port, as figure 3 illustrates. note that the clock, data - in, and data - out pins are common among all devices. the chip select and hold pins must be driven separately for each fm 25v01 device. for a microcontrol ler that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the hold pin. figure 4 shows a configuration that uses only three pins. figure 3 . 256 k bit ( 32 kb) system configuration with spi port figure 4 . system configuration without spi port s p i m i c r o c o n t r o l l e r f m 2 5 v 0 1 q d c s h o l d f m 2 5 v 0 1 q d c s h o l d s c k m o s i m i s o s s 1 s s 2 h o l d 1 h o l d 2 m o s i : m a s t e r o u t s l a v e i n m i s o : m a s t e r i n s l a v e o u t s s : s l a v e s e l e c t m i c r o c o n t r o l l e r f m 2 5 v 0 1 q d c s h o l d p 1 . 0 p 1 . 1 p 1 . 2 v d d
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 5 of 1 8 power up to first access the fm 25v01 is not accessible for a period of time (t pu ) after power up. users must comply with the timing parameter t pu , which is the minimum time from v dd (min) to the first /s low. data transfer all data transfers to and from the fm 25v01 occur in 8 - bit groups. they are synchronized to the clock signa l (c) , and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of c . outputs are driven from the falling edge of clock c . command structure there are ten commands called op - codes that can be issued by the bus m aster to the fm 25v01 . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function , such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register . the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op - code commands name description op - code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b fstrd fast read memory data 000 0 1011b write write memory data 0000 0010b sleep enter sleep mode 1011 1001b rdid read device id 1001 1111b wren C set write enable latch the fm 25v01 will power up with writes disabled. the wren command must be issued prior to any write operation. sen ding the wren op - code will allow the user to issue subsequent op - codes for write operations. these include wri ting the status register (wrsr) and w riting the memory (write) . sending the wren op - code causes the internal write enable latch to be set. a fla g bit in the status register , called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit. completing any write operation will automa tically clear the write - enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. figure 5. wren timing wrdi C write disable the wrdi command disab les all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 6. wrdi timing rdsr C read status register the rdsr command allows the bus master to verify the contents of the status r egister. reading status provides information about the current state of the write protection features. following the rds r op - code, the fm 25v01 will return one byte with the contents of the status r egister. the status r egister i s described in detail in the section below . 0 0 0 0 0 1 1 0 s c d q hi - z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 s c d q hi - z 0 1 2 3 4 5 6 7
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 6 of 1 8 wrsr C write status register the wrsr command allows the user to select certain write protection featur es by writing a byte to the status r egister. prior to issuing a wrsr command, the /w pin must be high or inactive. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operatio n and therefore clears the write enable latch. the bus configuration of rdsr and wrsr are shown below. figure 7. rdsr timing figure 8. wrsr timing (wren not shown) status register & write p rotection the write protection features of the fm 25v01 are multi - tiered. taking the /w pin to a logic low state is the hardw are write - protect function. status register write operations are blocked when /w is low. to write the memory with /w high, a wren op - code must first be issued. assuming that writes are enabled using wren and by /w , writes to memory are controlled by the status r egister. as described above, writes to the s tatus r egister are performed using the wrsr command and subject to the /w pin. the status r egister is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 6 are fi xed at 0 , and cannot can be modified. n ote that bit 0 ( ready in serial flash ) is unnecessary as the f - ram writes in real - time and is never bu sy, so it reads out as a ?0?. there is an exception to this when the device is waking up from sleep mode, which is described on the following page. the bp1 and bp0 control software write protection features. they are nonvolat ile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the s tatus r egister has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectivel y. bp1 and bp0 are memory block write protection bits. they specify po rtions of memory that are write - protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 3 000h to 3fff h (upper ?) 1 0 2 000h to 3fff h (upper ?) 1 1 0000h to 3fff h (all) the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block prote ct bits. the wpen bit controls the effect of the hardware /w pin. when wpen is low, the /w pin is ignored. when wpen is high, the /w pin controls write access to the s tatus r egister. thus the status r egister is write protected if wpen=1 and /w =0. this s cheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. this occurs if the bp1 and s c d q s c d q
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 7 of 1 8 bp0 bits are set to 1, the wpen bit is set to 1, and the /w pin is low . this occurs because the block prote ct bits prevent writing memory and the /w signal in hardware prevents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protecti on conditions. table 4. write protection wel wpen /w protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unp rotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f - ram te chnology. unlike serial flash , the fm 25v01 can perform sequential write s at bus speed. no page buffe r is needed and any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op - code. the next op - code is the write instruction. this op - code is followed by a two - byte address value , which specifies t he 14 - bit address of the first data byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 3fff h is reached, the counter will roll over to 0000 h. data is written msb first. a write operation is shown in figure 9. unlike serial flash , any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of / s terminates a write op - code operation. asserting /w active in the middle of a write operation will have no e ffect until the next falling edge of / s . read operation after the falling edge of / s , the bus master can issue a read op - code. followin g this instruction is a two - byte address value ( a13 - a0), specifying the address of the first data byte of the read operation. after the op - code and address are complete, the d pin is ignored. the bus master issues 8 clocks, with one b it read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 3fff h is reached, the counter will roll over to 0000 h. data is read msb first. the rising edge of / s terminates a read op - code operation and tri - states the q pin . a read operation is shown in figure 10 . fast read operation the fm 25v01 supports the fast read op - code (0bh) that is found on s erial flash devices. it is implemented for code compatibility with serial flash devic es . following this instruction is a two - byte address ( a13 - a0), specifying the address of the first data byte of the read operation. a dummy byte follows the address. it inserts one byte of read latency. the d pin is ignored after the op - code, 2 - byte addres s, and dummy byte are complete. the bus master issues 8 clocks, with one bit read out for each. the fast read operation is otherwise the same as an ordinary read. if the last address of 3fff h is reached, the counter will roll over to 0000 h. data is read ms b first. the rising edge of /s terminates a fast read op - code operation and tri - states the q pin. a f ast r ead operation is shown in figure 11. hold the fm 25v01 device has a /hold pin that can be used to interrupt a serial operation without aborting it. if the bus master pulls the /hold pin low while c is low, the current operation will pause. taking the /hold pin high while c is low will resume an operation. the transitions of /hold must occur while c is low, but the c and / s pins can toggle during a hold state.
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 8 of 1 8 figure 9. memory write with 2 - byte address (wren not shown) figure 10. memory read with 2 - byte address figure 11. fast read with 2 - byte address and dummy byte 7 6 0 1 2 3 4 5 6 7 0 1 2 3 5 4 5 6 7 0 1 2 3 4 5 6 7 op - code 0 0 0 0 1 0 1 m s b 14 - bit address 1 x x x x 7 6 5 4 3 2 1 0 l sb m s b l s b d a t a 1 2 s c d q 0 dummy byte x x 13 12 7 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 4 5 6 7 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 0 0 1 m s b 1 4 - b i t a d d r e s s 7 6 5 4 3 2 1 0 l s b m s b l s b d a t a 1 s c d q 8 3 1 2 0 10 x x 13 12 11 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 o p - c o d e 0 0 0 0 0 0 1 0 m s b 1 4 - b i t a d d r e s s 10 9 6 x x 13 12 11 s c d q 7 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 0 l s b m s b l s b d a t a
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 9 of 1 8 sleep mode a low power mode called sleep mode is implemented on the fm 25v01 device . th e device will enter thi s low power state when the sle ep op - code b9h is clocked - in and a rising edge of / s is applied . once in sleep mode, the c and d pins are ignored and q will be hi gh - z, but the device continues to monitor the /s pin. on the next falling edge of /s, the device will return to normal operation within t rec (400 s max.). the q pin remains in a hi - z state du ring the wakeup period. the device will not necessarily respond to an opcode within the wakeup period. to start the wakeup procedure, the controller may send a dummy read, for example, and wait the remainin g t rec time. it is not recommended to start the wakeup by asserting /s low, leaving /s low, and issuing clocks since the device wakeup is an asynchronous event and could misinterpret the opcode s . it is recommended that the controller deassert /s after each polled read opcode. polling is the process of looking for expected data and allows the system to determine if the device has returned to a normal operating condition. figure 12. sleep mode entry device id the fm 25v01 devi ce can be inter rogated for its manufacturer, product identification , and die revision . the r did op - code 9fh allows the user to read the manufacturer id and product id, both of which are read - only bytes . the jedec - assigned manufacturer id places the ramtr on identifier in bank 7, therefore there are six bytes of the continuation code 7fh followed by the single byte c2h. there are two bytes of product id, which includes a family code, a density code, a sub code, and product revision code. table 6 . manufactu rer and product id bit 7 6 5 4 3 2 1 0 hex manufacturer id 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation co de 0 1 1 1 1 1 1 1 7f continuation code 1 1 0 0 0 0 1 0 c2 jedec assigned ramtron c2h in bank 7 family density hex device id (1 st byte) 0 0 1 0 0 0 0 1 2 1 h density: 01h=128 k , 02h=256k, 03h=512k, 04=1m sub rev. rsvd device id (2 nd byte) 0 0 0 0 0 0 0 0 00h 00h=fm 25v01 figure 1 3 . read device id s c d q 7fh 7f h c2 h 00 h six bytes of continuation code 7fh 9f h 21 h 1 6 . . . . . . . s c d q e n ter sleep mode
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 10 of 1 8 endurance the fm 25v01 device is capable of being accessed at least 10 14 times, reads or writes. an f - ram memory operates with a read and restore mechanism. therefore, a n endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f - ram architecture is based on an array of rows and columns. rows are defined by a13 - a3 and column addresses by a2 - a0. see block diagram ( pg 2) which show s the array as 2 k rows of 64 - bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the table below shows endurance calcula tions for 64 - byte repeating loop, which includes an op - code, a starting address, and a sequential 64 - byte data stream. this causes each byte to experience one endurance cycle through the loop. f - ram read and write endurance is virtually unlimited even at 40mhz clock rate. table 7. time to reach 100 trillion cycles for repeating 64 - byte loop sck freq (mhz) endurance cycles/sec. endurance cycles/year years to reach 10 14 cycles 4 0 7 4 , 6 2 0 2.3 5 x 10 12 42 . 6 20 3 7 , 31 0 1.1 8 x 10 12 85.1 10 1 8, 66 0 5. 88 x 10 1 1 17 0 . 2 5 9 , 33 0 2. 9 4 x 10 1 1 340 . 3
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 11 of 1 8 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to + 4 . 5 v v in voltage on any pin with respect to v ss - 1.0v to + 4.5 v and v in < v dd +1.0v t stg storage temperature - 55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 26 0 c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 0 03 rev. e ) tbd 1.25kv 200v package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating conditions ( t a = - 40 c to + 85 c , v dd = 2.0 v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 2.0 3.3 3.6 v i dd power supply operating current @ c = 1 mhz @ c = 40 mhz 0.12 1. 3 0.22 2.5 ma ma 1 i sb standby current 9 0 15 0 a 2 i zz sleep mode current 5 8 a 3 i li input leakage current - 1 a 4 i lo output leakage current - 1 a 4 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage - 0.3 0.3 v dd v v oh1 output high voltage ( i oh = - 1 ma, v dd =2.7v) 2.4 - v v oh2 output high voltage ( i oh = - 100 a) v dd - 0.2 - v v ol1 output low voltage ( i ol = 2 ma, v dd =2.7v) - 0.4 v v ol2 output low voltage ( i ol = 150 a) - 0.2 v r in input resistance (/hold pin) for v in = v ih (min) for v in = v il (max) 4 0 1 k m 5 notes 1. c toggling between v dd - 0. 2 v and v ss , other inputs v ss or v dd - 0. 2 v. 2. / s =v dd . all inputs v ss or v dd . 3. in sleep mode and /s=v dd . all inputs v ss or v dd . 4. v ss v in v dd and v ss v out v dd . 5. the input pull - up circuit is strong er ( > 4 0k ) when the inp u t voltage is above v i h and weak ( > 1m ) when the input voltage is below v i l . data retention ( t a = - 40 c to + 85 c) parameter min max units notes data retention 10 - years
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 12 of 1 8 a c parameters ( t a = - 40 c to + 85 c, c l = 30pf , unless otherwise specified ) v dd 2.0 to 2.7 v v dd 2.7 to 3.6 v symbol parameter min max min max units notes f c c clock frequency 0 25 0 40 mhz t ch clock high time 20 11 ns 1 t cl clock low time 20 11 ns 1 t csu chip select setup 12 10 ns t csh chip select hold 12 10 ns t od output disable time 20 12 ns 2 t odv output data valid time 18 9 ns t oh output hold time 0 0 ns t d deselect time 60 40 ns t r data in rise time 50 50 ns 2,3 t f data in fall time 50 50 ns 2,3 t su data setup time 8 5 ns t h data h old time 8 5 ns t hs /hold setup time 12 10 ns t hh /hold hold time 12 10 ns t hz /hold low to hi - z 25 20 ns 2 t lz /hold high to data active 25 20 ns 2 notes 1. t ch + t cl = 1/f c . 2. this parameter is characterized but not 100% tested. 3. rise and f all times measured between 10% and 90% of waveform. capacitance ( t a = 25 c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output c apacitance ( q ) - 8 pf 1 c i input c apacitance - 6 pf 1 notes 1. this parameter is characterized and not 10 0% tested. ac test conditions input pulse levels 10% and 90% of v dd input rise and fall times 3 ns input and output timing levels 0.5 v dd output load capacitance 30 pf serial data bus timing s c d q 1 / t c k t c l t c h t c s h t o d v t o h t o d t c s u t s u t h t d t r t f
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 13 of 1 8 /hold timing power cycle timing power cycle & sleep timing ( t a = - 4 0 c to + 85 c, v dd = 2.0 v to 3.6v , unless otherwise specified ) symbol parameter min max units notes t vr v dd rise time 50 - s/v 1,2 t vf v dd fall time 100 - s/v 1,2 t pu power up (v dd min) to first access (/ s low) 2 5 0 - s 3 t pd last access (/ s high) to power down (v dd min) 0 - s t rec recovery time from sleep mode - 4 00 s notes 1. this parameter is characterized and not 100% tested. 2. slope measured at an y point on v dd waveform. 3. applies to v dd > 2.7v. when powering up to v dd < 2.7v, the t pu limit is 500 s. s c q hold t hs t hh t hz t lz t hs t hh v d d m i n . v d d s t v r t p d t p u t v f
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 14 of 1 8 mechanical drawing 8 - pin soic (jedec ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxxxxx = part number, p = package type r = rev code, lllll = lot code, z = package code ric = ramtron int?l corp, yy = year, ww = work week = pb - free example: fm25v01, green/rohs soic rev. a, lot 67989, soic year 2013, work week 07 pb - free fm25v01 - g a 67989s ric1307 xxxxxxx - p r lllll z ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 0 . 40 1 . 27 0 . 19 0 . 25 0 - 8 recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 15 of 1 8 revision history revision date summary 1.0 10 / 2 0 /2010 initial release. 1.1 9/22 /2011 removed s/n ordering option. added note to t pu timing parameter when v dd powers up to < 2.7v. 3.0 1/30/2012 changed to pr oduction status. ordering information part number features operating voltage package fm 25v01 - g device id 2.0 - 3.6v 8 - pin green/rohs soic fm 25v01 - gtr device id 2.0 - 3.6v 8 - pin green/rohs soic , tape & reel
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 16 of 1 8 appendix a - errata for fm2 5 v01 errata number 001 date january 1 2 , 2011 (updated j uly . 201 1 ) product fm25v01 the fm25v01 devices have a problem with the sleep mode function . some devices will not exit sleep at vdd voltages within the specified operating range. worst case is at high v dd (3.6v). the failing voltage will be lower at cold temperatures. this does not affect operation if the sleep function is not used. there is an effective scree n that is implemented at final test. a temporary part number has been assigned for customers who use sleep mode. customers who require sleep mode should order the fm25v01 - g . the part will be marked with a triangle to the right of the par t mark. an example of the mark is as follows: no sleep mode screen sleep mode screen fm25 v 01 - g fm25 v 01 - g a9646447 a9646447 ric1011 ric1011 this errata will remain in effect until the sleep function is fixed. update: ramtron has made circuit modifications to correct this problem. the starting date code for the fixed devices is 1127. (yy=11, ww=27) devices with a date code 1127 and later have a fully operational slee p mode function. an example of the new part marking is as follows: xxxxxxx - pt rllllllll ric yyww fm25 v01 - g a 1448278 1 ric 1127
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 17 of 1 8 document history document title: fm2 5v01 1 28k b serial 3 v f - ram memory document number: 001 - 8 4492 revision ecn orig. of change submission date description of change ** 3912930 gvch 02/25/2013 new spec *a 3985098 gvch 05 / 0 9 /2013 updated soic package marking scheme *b 4014247 gvch 05/29/2013 added appendix a - errata for fm2 5 v01
fm25v01 - 128kb spi fram document number: 001 - 84492 rev. * b page 18 of 1 8 sales , solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go /a utomotive clocks & buffers cypress.com/go/clocks interface cypress.com/go /i nterface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypres s.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb psoc ? solutions psoc.cypress. com/solutions psoc 1 | psoc 3 | psoc 5 cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support ramtron is a registered trademark and nodelay? is a trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semi conductor corporation, 2011 - 2013 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress p roduct. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life - support systems application impl ies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and s ubject to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress here by grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create derivative works of, and co mpile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in support of licen see product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. an y reproduction, modification, translation, compilation, or representation of this source code except as specified above is prohibited without the express w ritten permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress does n ot assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize it s products for use as critical components in life - support systems where a malfunction or failure may reasonably be expect ed to result in significant injury to the user. the inclusion of cypress product in a life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement .

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