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high isolation, silicon spdt, nonreflective switch, 0.1 ghz to 6.0 ghz data sheet hmc8038 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. al l rights reserved. technical support www.analog.com f eatures nonr eflective , 50 ? design high isolation : 6 0 db typical low insertion loss : 0.8 db typical high power handling 34 dbm through path 2 9 dbm terminated path high linearity 0.1 db compression ( p0.1db ) : 35 dbm typical input third - order intercept ( ip3 ) : 60 dbm typical esd ratings 4 k v human body model ( hbm ) , class 3a 1.2 5 k v charged device model (cdm) single positive supply 3.3 v to 5 v 1.8 v - compatible control all o ff state control 16- l ead , 4 mm 4 mm lfcsp ( 16 mm 2 ) pin c ompatible with the hmc849 a lp4ce application s cellular/4g infrastructure wireless infrastructure automotive telematics mobile radio s test equipment functional block dia gram 13554-001 12 11 10 1 3 4 9 2 6 5 7 8 16 15 14 13 v dd v ctl rfc nc rf2 nc nc nc nc gnd gnd rf1 en nc nc nc hmc8038 50 50 package base figure 1 . general description the hmc8038 is a high isolation , non reflective , 0.1 ghz to 6 .0 ghz , silicon , single - pole , double - throw ( spdt ) switch in a leadless , surface - mount package. the switch is ideal for cellular infrastructure applications , yielding up to 62 db of isolation up to 4.0 ghz , a low 0.8 db of insertion loss up t o 4 .0 ghz , and 60 dbm of input third - order intercept . power handling is excellent up to 6 .0 ghz , and it offers a n input power f or an 0. 1 db compression point ( p 0. 1db ) of 35 dbm ( v dd = 5 v ) . on - chip circuitry operates a single , positive supply voltage from 3.3 v to 5 v, as well as a single, positive voltage control from 0 v to 1.8 v /3.3 v /5.0 v at very low dc currents. an enable input (en) set to logic high places t he switch in an all off state, in which rfc is reflective. the hmc8038 has esd protection on all device pins, including the rf interface, and can stand 4 k v hmb and 1 .25 k v cdm. the hmc8038 offers very fast switching and rf settling times of 150 ns and 170 ns, respectively. the device comes in a rohs - complian t, compact 4 mm 4 mm lfcsp.
hmc8038 data sheet rev. a | page 2 of 11 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 interface schematics .....................................................................6 typical performance characteristics ..............................................7 insertion loss, isolation, and return loss ................................7 input compression and input third - order intercept .............8 theory of operation .........................................................................9 applicat ions information .............................................................. 10 outline dimensions ....................................................................... 11 ordering g uide .......................................................................... 11 revision history 11/15 rev. 0 to rev. a changes to tabl e 1 ............................................................................ 3 9/ 15 rev ision 0 : initial version
data sheet hmc8038 rev. a | page 3 of 11 specifications v dd = 3.3 v to 5 v, v ctl = 0 v /v dd , t a = 25 c, 50 ? system, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit insertion loss 0.1 ghz to 2 .0 ghz 0.7 1.0 db 2.0 ghz to 4 .0 ghz 0. 8 1. 1 db 4.0 ghz to 6.0 ghz 0.9 1.3 db isolation 0.1 ghz to 2 .0 ghz 55 70 db rfc to rf1/rf2 (worst case ) 2.0 ghz to 4.0 ghz 50 60 db 4.0 ghz to 6.0 ghz 40 51 db return loss on state 0.1 ghz to 2.0 ghz 24 db 2.0 ghz to 4.0 ghz 18 db 4.0 ghz to 6.0 ghz 18 db off state 0.1 ghz to 2.0 ghz 23 db 2.0 ghz to 4.0 ghz 22 db 4.0 ghz to 6.0 ghz 16 db switching speed t rise , t fall 10%/90% rf out 60 ns t on , t off 50% v ctl to 10%/90% rf out 150 ns rf settling time 50% v ctl to 0.1 db margin of final rf out 170 ns input power 1 db compression (p1db) v dd = 3.3 v 34 db v dd = 5 v 36 db 0.1 db compression (p0.1db) v dd = 3.3 v 33 db v dd = 5 v 35 db input third - order intercept (ip3) two - tone input power = 14 dbm/tone 60 dbm recommended operating conditions bias voltage range (v dd ) 3.0 5.4 v control voltage range (v ctl , en) 0 v dd v maximum rf input power 1 t case = 105c through path (5 v/3.3 v) 31/30 dbm terminated path 24 dbm hot switching 24 dbm t case = 85c through path (5 v/3.3 v) 34/33 dbm terminated path 27 dbm hot switching 27 dbm t case = 25c through path (5 v/3.3 v) 34/33 dbm terminated path 29 dbm hot switching 27 dbm t case = ?40c through path (5 v/3.3 v) 34/33 dbm terminated path 29 dbm hot switching 27 dbm case temperature range (t case ) ?40 +105 c 1 exposure to levels between the recommended operating conditions and the absolute maximum rating conditions for extended perio ds may affect device reliability.
hmc8038 data sheet rev. a | page 4 of 11 table 2 . digital control voltages state v dd = 3.3 v (5% v dd , t case = ?40c to +105c) v dd = 5 v (5% v dd , t case = ?40c to +105c) input control voltage low (v il ) 0 v to 0.85 v at <1 a, typical 0 v to 1.20 v at <1 a, typical high (v ih ) 1.15 v to 3.3 v at <1 a, typical 1.55 v to 5.0 v at <1 a, typical table 3. bias voltage vs. supply current parameter symbol min typ max unit typical i dd (ma) supply current i dd v dd = 3.3 v 0.14 ma 0.14 v dd = 5 v 0.16 ma 0.16
data sheet hmc8038 rev. a | page 5 of 11 absolute maximum rat ings table 4. parameter rating bias voltage range (v dd ) ? 0.3 v to +5.5 v control voltage range (v ctl , en ) ? 0.5 v to v dd + (+0.5 v) rf input power 1 ( see figure 2) through path 35 dbm terminated path 30 dbm hot switching 30 dbm channel temperature 135 c storage temperature range ? 65 c to + 150 c thermal resistance ( channel to package bottom ) through path 110c/w terminated path 100c/w esd sensitivity hbm 4 kv (class 3a) cdm 1.25 kv 1 for recommended operating conditions , see table 1 . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any o ther conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. during the through mode of operation, the supply voltage scales the maximum allowed input power. the power handling vs. frequency for the 3.3 v and 5 v supplie s is shown in figure 2 . 40 35 30 25 20 0 1 2 3 4 5 6 input power (dbm) frequency (ghz) amr operating 5v operating 3.3v 13554-002 figure 2 . through path, power handling vs. frequency esd caution
hmc8038 data sheet rev. a | page 6 of 11 pin configuration an d function descripti ons 12 11 10 1 3 4 9 2 6 5 7 8 16 15 14 13 v dd v ctl rfc nc rf2 nc nc nc nc gnd gnd rf1 en nc nc nc hmc8038 t op view (not to scale) notes 1. nc = no connect. the pins are not connected internally; however, all data shown herein was measured with these pins connected to rf/dc ground externally. 2. exposed pad. exposed pad must be connected to rf/dc ground. 13554-003 figure 3 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 v dd supply voltage pin . 2 v ctl control input pin. s ee figure 5 for the v ctl interface schematic . refer to table 6 and the recommended input control v oltage range in table 2. 3 rfc rf common port. this pin is dc - coupled and matched to 50 ?. a dc blocking capacitor is required on this pin . 4 , 6 to 8, 13 to 16 nc not internally connected. these pins are not internally connected; however, all data shown in this data sheet i s measured with the nc pins externally connected to rf/ dc ground on the evaluation board. 5 en enable input pin. s ee figure 5 for the en interface schematic . refer to table 6 and the recommended input control voltage range in table 2. 9 rf1 rf port 1. this pin is dc - coupled and matched to 50 ?. a dc blocking capacitor is required on this pin. 10 , 11 gnd ground. the p acka ge bottom has an exposed metal pad that must connect to the printed circuit board (pcb) rf ground. see figure 4 for the gnd interface schematic. 12 rf2 rf port 2. this pin is dc - coupled and matched to 50 ?. a dc blocking capacitor is required on this pin. epad exposed pad. exposed pad must be connected to rf/dc ground. interface schematics gnd 13554-004 figure 4 . gnd interface schematic v dd v ctl , en 13554-005 figure 5 . logic control interface schematic table 6. truth table control input signal path state v ctl state en state rfc to rf1 rfc to rf2 low low off on high low on off low high off off high high off off
data sheet hmc8038 rev. a | page 7 of 11 typical performance characteristics insertion loss, isol ation, and return lo ss 0 ?0.5 ?1.5 ?1.0 ?2.0 ?2.5 0 1 2 3 4 5 6 7 insertion loss (db) frequency (ghz) +105c +85c +25c ?40c 13554-006 figure 6 . insertion loss vs. frequency o ver temperatures, v dd = 5 v 0 ?20 ?60 ?40 ?80 ?100 0 1 2 3 4 5 6 7 isolation (db) frequency (ghz) rf1 rf2 all off 13554-007 figure 7 . isolation between rfc and rf 1/rf2 vs. frequency at v dd = 3.3 v to 5 v 0 ?40 ?30 ?35 ?25 ?15 ?5 ?20 ?10 return loss (db) 0 1 2 3 4 5 6 7 frequency (ghz) rfc rf1, rf2 off rf1, rf2 on 13554-008 figure 8 . return loss vs. frequency at v dd = 3.3 v to 5 v 0 ?0.5 ?1.5 ?1.0 ?2.0 ?2.5 0 1 2 3 4 5 6 7 insertion loss (db) frequency (ghz) +105c +85c +25c ?40c 13554-009 figure 9 . insertion loss vs. frequency o ver temperatures, v dd = 3.3 v 0 ?80 ?60 ?70 ?50 ?30 ?10 ?40 ?20 isolation (db) 0 1 2 3 4 5 6 7 frequency (ghz) rfc to rf1 on rfc to rf2 on 13554-010 figure 10 . isolation between rf1 and rf2 vs. frequency at v dd = 3.3 v to 5 v
hmc8038 data sheet rev. a | page 8 of 11 input compression an d input third - order intercept 40 38 36 34 32 30 28 26 0 2 1 3 4 5 6 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13554-0 1 1 figure 11 . input compression 1 db point vs. frequency o ver temperature, v dd = 5 v 40 38 36 34 32 30 28 26 0 2 1 3 4 5 6 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13554-012 figure 12 . input compression 1 db point vs. frequency over temperature, v dd = 3.3 v 65 60 55 50 45 0 1 2 3 4 5 6 ip3 (dbm) frequency (ghz) +105c +85c +25c ?40c 13554-013 figure 13 . input third - order intercept (ip3) point vs. frequency, v dd = 5 v 40 38 36 34 32 30 28 26 0 2 1 3 4 5 6 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13554-014 figure 14 . input compression 0.1 db point vs. frequency o ver temperature, v dd = 5 v 40 38 36 34 32 30 28 26 0 2 1 3 4 5 6 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13554-015 figure 15 . input compression 0.1 db point vs. frequency o ver temperature, v dd = 3.3 v 65 60 55 50 45 0 1 2 3 4 5 6 ip3 (dbm) frequency (ghz) +105c +85c +25c ?40c 13554-016 figure 16 . input third - order intercept (ip3) point vs. frequency, v dd = 3.3 v
data sheet hmc8038 rev. a | page 9 of 11 t heory of operation the hmc8038 requires a single - supply voltage applied to the v dd pin. bypassing capacitors are recommended on the supply line to minimize rf coupling. the hmc8038 is controlled via two digital control voltages applied to the v ctl pin and the en pin . a small bypassing capacitor is recommended on these digital signal lines to improve the rf signal iso lation. the hmc8038 is internally matched to 50 at the rf input port (rfc) and the rf output ports (rf1 and rf2); therefore, no external matching components are required. the rf x pins are dc - c oupled , and dc blocking capacitors are required on the rf lines. the design is bi directional ; the input and outputs are i nterchangeable. the ideal power - up sequence is as follows: 1. power up gnd . 2. power up v dd . 3. power up the d igital control inputs . the relati ve order of the logic control inputs are not important. powering the digital control inputs before the v dd supply can inadvertently forward bias and damage esd protection structures . 4. power up the rf input. with the en pin is logic low, the hmc8038 has two operation modes: o n and o ff . depending on the logic level applied to the v ctl pin, one rf output port (for example, rf1) is set to on mode , by which an insertion loss path is provi ded from the input to the output , as the other rf output port (for example, rf2) is set to off mode , by which the output is isolated from the input. when the rf output port (rf1 or rf2) is in isolation mode , internally terminate it to 50 , and the port absorb s the applied rf signal. when the en pin is logic high, t he en pin set s the hmc8038 switch to off mode. in off mode , both output ports are isolated from the input , and the rfc port is open reflective. table 7 . switch operation mode digital control inputs switch mode v en v ctl rfc to rf1 rfc to rf2 0 0 off mode. the rf1 port is isolated from the rfc port and is internally terminated to a 50 ? load to absorb the applied rf signals. on mode. a low insertion loss path from the rfc port to the rf2 port. 0 1 on mode. a low insertion loss path from the rfc port to the rf1 port. off mode. the rf2 port is isolated from the rfc port and i s i nternally t erminated to a 50 ? load to absorb the applied rf signals . 1 x 1 all in o ff mode. both the rf1 and rf2 ports are isolated from the rfc port, and the rfc port is reflective. 1 x stands for dont care.
hmc8038 data sheet rev. a | page 10 of 11 applications information generate the evaluation pcb used in the application shown in figure 17 with proper rf circuit design techniques. signal lines at the rf port must have a 50 impedance, and the package ground leads and backside ground slug must connect directly to the ground plane, as shown in figure 18. the evaluation board shown in figure 18 is available from analog devices, inc. upon request. table 8. bill of materials for evaluation board EV1HMC8038LP4C 1 reference designator description j1 to j3 pcb mount sma connector c1 to c6 100 pf capacitor, 0402 package c7 0.1 f capacitor, 0402 package r1, r2 0 resistor, 0402 package u1 hmc8038 spdt switch pcb 2 600-01267-00 evaluation pcb 1 reference to this evaluation board number when ordering the complete evaluation board. 2 circuit board material: roger 4350 or arlon 25fr. 12 11 10 1 3 49 2 6 5 7 8 1 6 1 5 1 4 1 3 50 ? 50 ? rf2 rf1 gnd gnd package base c3 100pf rfc en v ctl v dd c1 100pf c2 100pf c6 100pf c4 100pf c7 0.1f c5 100pf 13554-017 figure 17. hmc8038 application circuit 13554-018 figure 18. EV1HMC8038LP4C evaluation board
data sheet hmc8038 rev. a | page 11 of 11 outline dimensions 4.10 4.00 sq 3.90 0.39 0.33 0.27 2.55 2.40 sq 2.25 1 0.65 bsc bot t om view t o p view 16 5 8 9 12 13 4 exposed pad pin 1 indic a t or (0.30) 0.70 0.60 0.50 se a ting plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indic a t or 1.00 0.90 0.80 compliant to jedec standards mo-220-vggc for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-14-2015- a pkg-000000 1.95 ref figure 19 . 16- lead lead frame chip scale package [lfcsp] 4 mm 4 mm body and 0.90 mm package height (cp - 16 - 40 ) dimensions shown in millimeters ordering guide model 1 temperature range msl rating 2 package description package option branding 3 hmc8038lp4ce ? 40c to +105c msl3 16- lead lead frame chip scale package [lfcsp] cp -16-40 xxxx 8038 hmc8038lp4cetr ? 40c to 105c msl3 16- lead lead frame chip scale package lfcsp cp -16-40 xxxx 8038 EV1HMC8038LP4C ? 40c to 105c evaluation board 1 rohs - compliant part. 2 the maximum peak reflow temperature is 260c. 3 4 - digit lot number: xxxx. ? 2015 analog devices, inc. all rights r eserved. trademarks and registered trademarks are the property of their respective owners. d13554 - 0- 11/15(a)

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