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[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 1 - 1. general description AK8456 is an afe for three channels contact image sensor (cis). AK8456 has offset adjusting dac, digital programmable gain amplifier (pga) and led drivers. AK8456 is suitable for multi - function printer and image scanner. 2 . feature ? input block c hannel number 3 channel (1 channel mode is available ) range 1.3 vpp (min. ) gain 0db/6db ? adc maximum conversion ratio 30msps 10msps/ch @ 3 - channel mode 3 0msps/ch @ 1 - channel mode resolution 16bit ( straight binary code /gray code ) ? black correction dac range ? 3 69 mv ( equivalent input voltage) 250mv(min.) resolution 6 bit ? digital pga range 0db~ 18 db resolution 8 bit ? output format 8bit 2 ? led current 67.2 ma/ch (typ.) @ maximum setting adjustable by 12.5 % resolution channel independently ? cpu i/f 3 - wire serial interface ? supply voltage afe : 3.3v ? 0.3v , led driver: 4. 5v ~5.7v ? power consumption 190 mw ( typ. ) except led drive current. ? operating temperature 0 ? c~70 ? c ? package 3 6 pin qfn ( exposed die pad) , 0.4 mm pitch , 5 mm ? 5 mm AK8456 3 channel input 16bit 30msps video adc with led drive r
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 2 - 3. table of contents 1. general description ................................ ................................ ................................ ........................ 1 2. feature ................................ ................................ ................................ ................................ ............ 1 3. table of con tents ................................ ................................ ................................ ............................ 2 4. block diagram and functions ................................ ................................ ................................ .......... 3 5. pin allocation and functions ................................ ................................ ................................ ............ 5 6. absolute maximum ratings ................................ ................................ ................................ ............ 7 7. recommended operating conditions ................................ ................................ .............................. 7 8. electrical characteristics ................................ ................................ ................................ ................. 7 9. functional description ................................ ................................ ................................ .................. 17 10. register map ................................ ................................ ................................ ............................... 23 11. external circuit exa mple ................................ ................................ ................................ ............ 29 12. package ................................ ................................ ................................ ................................ ....... 31 13. important notice ................................ ................................ ................................ ......................... 32
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 3 - 4 . block diagram and functions fig.1 block diagram ? input block AK8456 is available for cis whose polarity is positive. the voltage difference between cisin0~2 input signal and sensor reference voltage vdc is sampled . vdc is input externally and also is able to generate internally. ther e are three channel mode and one channel mode. in one channel mode, sensor signal input pin is cisin 0. ? dac 6bit dac offset adjust is excused by adding dac output voltage to input signal. dac resolution is six bit and output range is 3 69 mv ( typ. ). 100 mv ( max.) out of 3 69 mv is used to cancel lsi internal offset. therefore effective range for correcting signal offset is 2 69 mv (typ . ) . ? sample and hold block s/h the voltage difference between cisin0~2 input signal and sensor reference voltage vdc is sampled at sample and hold block. gain at sample and hold block is selected from 0db and 6db. ? m ultiplexor mux due to process three channels in a time - division, mux selects one channel out of three channel s in order . sdata sdclk sdenb serial i/f reference voltage iset vrp dvo afe ch0 analog pga 16bit 30msps adc digital pga 16 6 16 cisin0 cisin1 cisin2 shd resetb por d0 d1 d2 d3 d4 d5 d6 d7 cmos output ldo_d dac vdc 3 to 1 mux analog pga 6 shd dac analog pga 6 shd dac output control led cont. led_r led_g led_b lvss lvdd leden_b leden_g leden_r lvdd lvss led driver 8 ovdd clock gen. shd adck avdd ovss afe ch1 afe ch2 avo ldo_a
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 4 - ? adc after offset adjust, the adc convert analog signal level to digital data. the adc has 16 - bit resolution and 30msps maximum conversion ratio. the output code is straight binary , 0000h corresponds to black signal and ffffh corresponds to white signal. ? digital pga the digital pga amplifies a/d data. its gain range is 0db~18db and gain resolution is 8bit. ? output control block the output control block converts 16 - bit width dat a to two 8 - bit width data. higher 8 - bit is output at adck rising edge and lower 8 - bit is ou tput at adck falling edge. gray code output is possible too by register setting. ? reference voltage generation block reference voltage this block generates internal reference voltage vrp, sensor reference voltage vdc and ldo reference voltage . ? internal clock generation block c lock gen thi s block generates internal pulses using a/d clock adck and sampling pulse shd. ? led driver control block led control this block controls led switching and led current. led current is adjustable from 100% to12.5% by 12.5% step channel independently. 100% c urrent is 6 7.2 ma per channel. ? serial interface block serial i/f control registers are written and read through 3 - wire serial interface. ? low dropout voltage regulator ldo the ldo generate 1.8v supply from 3.3v of avdd. the 1.8v is used for internal circu it. there are two ldo for analog circuit and digital circuit.
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 5 - 5 . pin allocation and functions d0 vrp iset vd c avo shd adc k led_ r lvss lvdd d2 d3 o vss o vdd d4 d5 d6 resetb c is in0 avdd c is in1 avdd c is in2 sdata AK8456 top view led_ b led_g dvo 9 8 7 6 5 4 3 2 1 1 8 1 7 1 6 1 5 14 13 12 11 10 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 d7 d1 leden_ r leden_ b leden_g lvss avdd s clk sdenb note) connect under side thermal exposed pad with avss. fig.2 pin layout ? p in functions no. name io stand by ( note 2) description 1 c is in0 i --- sensor signal input 2 avdd p --- analog supply 3 c is in1 i --- sensor signal input 4 avdd p --- analog supply 5 c is in2 i --- sensor signal input 6 resetb i --- reset input, active low include pull - up resistance 100k w (typ.) 7 sdenb i --- serial interface data enable 8 s clk i --- serial interface clock input 9 sdata i o high - z serial interface data input and output 10 leden_r i --- led_r control signal input include pull - down resistance 50k w (typ.)
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 6 - 11 leden_g i --- led_ g control signal input include pull - down resistance 50k ? (typ.) 12 leden_b i --- led_ b control signal input include pull - down resistance 50k ? (typ.) 13 lvdd p --- led driver supply (5v) 14 led_r o high - z led driver output r 15 lvss p --- led driver ground 16 led_g o h igh - z led driver output g 17 lvss p --- led driver ground 18 led_b o high - z led driver output b 19 d7 o low a/d data output ( note 1) (upper bit) 20 d6 o low a/d data output ( note 1) 21 d5 o low a/d data output ( note 1) 22 d4 o low a/d data output ( no te 1) 23 ovdd p --- a/d data output buffer supply (3.3v) 24 ovss p --- a/d data output buffer ground 25 d3 o low a/d data output ( note 1) 26 d2 o low a/d data output ( note 1) 27 d1 o low a/d data output ( note 1) 28 d0 o low a/d data output ( note 1) ( lower bit) 29 dvo o 1.8v digital ldo output pin (1.8v) keep dvo open. 30 adck i --- adc clock 31 shd i --- sampling clock 32 avdd p --- analog supply (ldo supply ) 33 avo o low analog block ldo output voltage monitor (1.8v) connect 1 f capacitor between avo and avss. 34 vrp o low adc reference voltage connect stabilize capacitor 1 ? f via avss 35 iset i --- resistance for reference current setting 36 v dc io high - z cis reference voltage connect stabilize capacitor 1 ? f via avss tab a vss p --- analog ground ( note 1) open drain output in cascade output mode ( note 2) standby is defined as the condition that power down bit npd=0 after reset. (note 3) i:input / o:output / p:power supply
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 7 - 6 . absolute maximum ratings a vss= o vss= lvss= 0 v . al l voltages are based on ground. item symbol min. max. unit remarks analog supply digital output buffer supply led driver supply avdd o vdd lvdd - 0.3 - 0.3 - 0.3 4.6 4.6 6. 2 v v v input voltage vina - 0.3 a vdd+0.3 v storage temperature tstg ? 65 150 ? c o peration at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 7 . recommended operating conditions a vss= ovss=lvss= 0 v . all voltages are based on ground. item symbol min. typ. max. uni t remarks analog supply digital output buffer supply led driver supply avdd o vdd lvdd 3.0 3.0 4.5 3.3 3.3 5.0 3.6 3.6 5.7 v v v operational temperature ta 0 70 ? c normal operation is guaranteed at avdd voltage = ovdd voltage . all supplies must be pow er - up. don t power off partial supplies for saving consumption. if ledd function is unnecessary . lvdd pins can connect vss level. 8 . electrical characteristics r eset timing fig.3 in case of i nternal power on reset (note) when using a power on reset circuit, the resetb pin must connect the capacity of 0.33 f to avss. (vdd avdd=ovdd =3.0~3.6v, ta=0~70 ? c) item symbol min. typ. max. unit c ondition vdd rise time prise 0.01 10 ms vdd 0v period poff 300 ms 0v peripd the wait ing time of the reset cancellation rtime 100 ms * start all powers at the same time. * when vdd_0v_period can not meet this condition , because a register isn't reset, this i nternal reset signal poff power prise 0.9avdd 0.1avdd prise rtime
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 8 - doesn't work normally. and the over - current may flow through vdd. it is same wh en using an external reset pin , too. fig.4 in case of external power on reset pin (vdd avdd=ovdd =3.0~3.6v, ta=0~70 ? c) item symbol min. typ. max. unit c ondition vdd rise time prise 0.01 ms r eset period 1 trst1 100 s r eset period 2 trst2 100 s *when re setb:low, ldo for afe power and ldo for digital power are power downed. the ti me of digital ldo power - off is 6 s . ( the time which becomes lower than 20% of 1.8 v ) ? ( a vdd = o vdd = 3.0 v~ 3.6v, ta= 0 ~ 70 ? c) item symbol pin min. max. unit remarks high input voltage vih n ote 1 ,2 ,3 0. 7 avdd v lo w input voltage vil n ote 1 ,2 ,3 0. 3 a vdd v high level output resister roh1 note 4 100 low level output resister rol1 note 4 100 high output voltage voh n ote 5 0.8 avdd v ioh= - 1 ma low output voltage vol n ote 5 0.2 avdd v iol=1ma input leakage il kg 1 n ote 1 ? 10 10 ? a input leakage ilkg2 n ote 2 ? 45 10 ? a input leakage ilkg3 n ote 3 ? 10 90 ? a input leakage ilkg 4 n ote 4 ? 10 10 ? a high - z input leakage ilkg 5 n ote 6 ? 10 10 ? a output leakage olkg n ote 7 ? 10 10 ? a (note1) adck, shd, sclk, sdata ( input ), sdenb, (note2) resetb (note3) leden_ r, leden_g, leden_b (note4) d0~d7 (note5) sdata ( output ) resetb trst2 trst1 0.1avdd power prise 0.9avdd 0.1avdd
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 9 - (note6) cisin0~2 (note7) led_r/g/b ( led driver off ) ? afe block analog characteristics 1 ( unless other specified, a vdd =ovdd = 3.3 v , lvdd=5.0v, ta= 25 ? c , adck=30mhz ) item symbol conditions min typ max unit reference voltage sensor ref erence vdc e external input range 0.8 1.2 v level vdci1 internal voltage 0.9 1.0 1.1 v vdci2 internal voltage 1.0 1.1 1.2 v adc reference voltage vrp 1.4 1.5 1.6 v sample and hold input range vi s/h gain =0db digital pga gain =0db 1.3 1.5 vpp gain gsh s /h gain =6db setting 5.5 6.0 6.5 db offset adjust dac resolution dres 6 bit range drng equivalent input level positive direction negative direction 300 - 440 369 - 369 440 - 300 mv mv differential nonlinearity ddnl dac code c onversion - 1 +1 l sb digital pga maximum gain gmax relative to 0db setting 18 db step width gsta monotonicity guaranteed 0.001 0.07 db adc resolution res 16 bit differential non - linearity dnl cisin~adc no missing code guaranteed at 12bit accuracy (pga=0db) - 1 +1 lsb integral non - linearity inl cisin~adc 12bit accuracy - 16 16 lsb noise, internal offset, cross talk no signal noise ( note 1) ni gain =0db gain =18db (s / h=6db, pga=12db) 14 67 lsb rms internal offset ( note 2) vofst gain =0db ? 50 50 mv cross tal k xtalk ( note 3) pga=0db - 256 ? 32 256 lsb
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 10 - ? a fe block analog characteristics 2 these specifications are defined under the condition external parts and their constants are in external circuit example. (avdd=ovdd=3.0 3.6v, lvdd=4.5 5.7v, ta=25 ? c, adck=30 mhz) c urrent consumption normal operation avdd ovdd lvdd (note 4) (note 5) (note 6 ) 37.4 8.6 6.2 51.2 25.5 8.4 ma ma ma stand by i stb 2.2 3 ma these specifications are defined under the condition external parts and their constants are in external cir cuit example. (note1) no signal noise is defined as sigma ( ) of adc code deviation under no input signal. (note2) when no input signal is applied , adc code changes from 0000h to 0001h between offset dac ? 50mv and offset dac 5 0mv. the offset dac cancels this internal offset as well as signal offset. thus adjust range for input signal offset is reduced by the internal offset. (note3) adck=30mhz , 3ch , pga gain of all channel is min imum . cross talk is defined, as change of output code when measured channel input is fixed and all other channel inputs is full - scale ? 2 db step signal . (note4) adck=30mhz, input - 2db of 1.5 vpp sine wave , 1mhz signal to three channels. (note5) load capacitance10pf (note6) @ led_r=100%, led_g=25%, led_b=25% setting (except led drive current) ? led driver analog characteristics ( unless otherwise specified, a vdd = o vdd = 3.3 v , lvdd=5.0v, ta= 0 ? c ~70 ? c , adc k=30mhz ) item min. typ. max. unit remarks maximum led current per channel 60.5 67.2 73.9 ma /ch i set resistance = 8.2 k led _r/g/b pin voltage = 2.0 v total maximum led current 100 .8 ma led current setting accuracy ? 5 5 % led _r/g/b pin voltage = 2.0 v dependence of led current on led _r/g/b pin voltage ? 2.5 2.5 % led _r/g/b pin s refer ence voltage = 2.0 v led _r/g/b pin voltage 0. 3 lvdd ? 1.1 v driving current
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 11 - ? switching characteristics ( unless otherwise specified, a vdd = o v d d= 3.0 v ~ 3.6v , ta=0 ~ 70 ? c) no. item pin min. typ. max. unit remarks 1 adck cycle (t) adck 33.3 2 000 ns 2 adck lo w width adck 15 ns 3 adck high width adck 15 ns 4 shd cycle shd 3 6 1 clocks 3ch normal output 3ch cascade output 1 ch mode 5 shd pulse width shd 8 ns 6 shd setup time to adck ? shd 2 ns 7 shd delay time to adck ? shd 10 ns 8 shd a perture delay shd 2.5 ns 9 d0 ~ 7 delay to adck ? ? d7 ~ d0 2 10 ns hold , set up c l =10 pf ( note 1) 10 pipeline delay ( adck unit ) d7 ~ d0 11 clocks 3ch mode 1 ch mode 11 shd= h prohibited region (to first adck ? after shd ? ) shd 1t+10 4t+10 10 ns 3ch no rmal output 3ch cascade output 1 ch mode 12 d0~7 enable time d7~d0 0 8.2 ns cascade output 13 d0~7 disable time d7~d0 2.4 7.2 ns cascade output these specifications refer to point crossing levels that defined in dc characteristics. (note1) refer to points adck , d7~d0 cross 50% of supply voltage. this delay is under a dck rise time t r and fall time tf are 1.65ns .
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 12 - 3ch input, normal output fig. 5 whole timing fig.6 details fig.7 d0~d7 delay m l m l m l m l m l m l m l m l m l m l m l m l m l l cisin0 c isin1 cisin2 cisin0 cisin1 cisin2 0 ? ? ? cisin0~2 adck shd d7~d0 in d7~d0, l means lower 8 bits, m means upper 8bits. 1 2 3 4 0 m l 1 2 3 4 5 6 7 8 9 1 1 10 clock 1 msb lsb msb lsb msb lsb msb lsb msb lsb m sb lsb msb lsb 3 2 4 5 6 7 8 9 9 11 cisin2(n ? 4) cisin1(n ? 4) cisin0(n ? 4) cisin2(n ? 5) cisin0(n ? 3) cisin1(n ? 3) cisin2(n ? 3) cisin0(n) cisin1(n) cisin0(n+1) cisin1(n+1) cis in0~2 shd adck d7~d0 sampling point adc k tr 0.7avdd 0.3avdd d7~d0 9 0.5ovdd 9 tf
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 13 - 3ch input, cascade output in d7~d0, l means lower 8 bits, m means upper 8bits. fig.8 whole timing fig.9 details fig.10 d0~d7 delay 2 1 3 4 5 6 7 8 9 11 cisin0 (n ? 4) cisin0(n) cisin1(n) cisin2(n) cisin0(n+1) cisin1(n+1) cisin2(n+1) cis in0~2 shd d7~d0 adck sampling point m l m l m l m l m l m l m cisin 1 (n ? 4) cisin 2 (n ? 4) l 9 cisin0~2 adck shd d7~d0 #0 1 0 m l m l m l 2 3 d7~d0 #1 m l m l m l m l m l m l m l m l m l m l m l m l m l m l m l m l cis in 0 cis in 1 cis in 2 cis in 0 cis in 1 cis in 2 ? 1 ? 2 0 adck tr 0.7avdd 0.3avdd d7~d0 9 0.5ovdd 9 12 13 tf
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 14 - 1ch inp ut fig.11 whole timing fig.12 details fig.13 d0~d7 delay 1 msb lsb 3 2 4 5 6 7 8 9 9 11 cis in 0 (n ? 11 ) cisin0(n) cisin0(n+1) cis in0 shd adck d7~d0 sampling point msb lsb cis in 0 (n ? 10 ) m l m l m l m l m l m l m l m l m l m l m l m l m l l ? 1 ? 10 cisin0 adck shd d7~d0 in d7~d0, l means lower 8 bits, m means upper 8bits. 1 0 2 3 4 5 6 7 8 9 10 11 12 ? 9 ? 8 ? 7 ? 6 ? 5 ? 4 ? 3 ? 2 0 1 adck tr 0.7avdd 0.3avdd d7~d0 9 0.5ovdd 9 t f
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 15 - ? serial interface switching characteristics s d e n b s c l k s d a t a s c y c s r s f 0 . 7 a v d d 0 . 3 a v d d s s u 0 . 3 a v d d 0 . 7 a v d d s s u s h s f s r s h i s l o 0 . 3 a v d d s s t s d l s s p s d e n h 0 . 7 a v d d i n p u t i n p u t o u t p u t o u t p u t 0 . 8 a v d d 0 . 2 a v d d s h 2 fig.14 serial interface timing ( unless otherwise sp ecified, avdd= o vdd = 3.0 v ~3.6v , ta=0~ 70 c , c l =10pf) item symbol condition min . typ . max . unit clock cycle scyc 10 mhz clock high width shi above 70% of avdd 40 ns clock low width slo under 30% of avdd 40 ns setup time ( to sclk ) ssu 4 0 ns hold time ( to sclk ) sh 4 0 ns sdenb hold time ( to sclk ) sh2 80 ns data enable delay ( to sclk ) sst high - z data out 0 30 ns data output delay ( to sclk ) sdl 0 30 ns data disable delay ( to sdenb ) ssp data out high - z 0 30 ns sdenb high width sden h above 70% of avdd 4 0 ns rise time sr 30% 70% of avdd 10 ns fall time sf 70% 30% of avdd 10 ns
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 16 - ? led driver switching characteristics ( unless otherwise specified, avdd=ovdd = 3.0 v ~3.6v , lvdd=4.5v~5.7v, ta=0~ 70 ? c ) item symbol conditions min . typ . max . unit leden_r/g/b setup time ( to shd ? ) tlens 15 ns leded_r/g/b hold time ( to shd ? ) tlenh 15 ns fig. 15 led driver switching characteristics ( unless otherwise specified, avdd=ovdd = 3.0 v ~3.6v , lvdd=4.5v~5.7v, ta=0~ 70 ? c ) item symbol conditions min . typ . max . unit led current rise time tlon 10 ? s led current fall time tloff 10 ? s fig. 16 led current timing led drivers are switched in leden_r/g/b those are synchronized with shd falling edge . therefore, if it can t meet setup time or hold time of leden_r/g/b , led lighting time will be 1~2 pixels change. leden_r/g/b shd 0.7avdd 0.3avdd 0.3avdd tlens tlenh tlenh tlens 0.7avdd leden_r/g/b led_r/g/b current tlon tloff 10% 90% 0.3avdd 0.3avdd shd
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 17 - ? 9 . functional descri ption ? start up there is no restriction on order of turning on avdd, ovdd and lvdd. please take a reset by hold resetb low level w hen the power avdd is turned on . leden_r/g/b must be low level during resetb rise s. user can ac cess to the registers after wa it time that are shown in followed figures from power - up. fig.17 not use power on reset not available (reset) avdd (3.3v) resetb dvo ( ldo output ) (1.8v) available access to r egister a few ms ldo start ~ 1ms internal reference circuits (related to ldo) are activated immediately . a few ma consumption leden_r/g/b leden_r/g/b are must be all low when resetb rise to high.
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 18 - fig.18 use power on reset a v d d r e s e t b a k 8 4 5 6 1 0 0 k ? 0 . 3 3 ? f power on reset circuit is composed by pull - up resist ance of resetb and external capacitor. when external capacitor is 0 .33 ? f , avdd rise time must be less than 10ms to reset exactly. staircase - like supply voltage rising is not allowed. fig.19 power on reset timing when down avd d to 0v, resetb level does not became 0v immediately because of charge remaining in resetb external capacitor. if up avdd again before resetb becoming 0v, power on reset does not carry out. the time avdd is 0v must be longer than 300ms for exact power on r eset at re - power up avdd . please control the resetb from outside without the use of a power - on reset if the above conditions are not met. during power up avdd, hold resetb low level. then raise resetb to high level. not available (reset) available ~ 100ms ldo start internal reference circuits (related to ldo) are activated immediately. a few ma consumption occurs. avdd (3.3v) resetb access to register leden_r/g/ leden_r/g/b are must be all low when resetb rise to high. dvo ( ldo output ) (1.8v)
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 19 - ? serial interface control registers are accessed through serial interface. the control registers are readable. if sdenb is l ow , it is possible to access registers. input address and data into sdata. sdata is captured by sclk rising edge. write the first bit of sdata is 0, data is written to register. from second bit to fourth bit must be 0. from fifth bit to eighth bit are address bits. the fifth bit is most significant bit of address. from n inth bit to sixteenth bit are data bit. data is written into register by rising edge of sdenb. if ris ing edge of sclk is less than sixteen, data isn't written into register. if rising edge of sclk is more than seventeen, front sixteen bits are effective. fig.20 write to register read the first bit of sdata is 1 , data is rea d from register. from second bit to fourth bit must be 0. from fifth bit to eighth bit are address bits. the fifth bit is most significant bit of address. data is output from the sclk falling after sclk rising incorporating an eighth bit. sdata pin is used as an input again if sdenb become high level . if there is a sclk 17 or more times, read data after the b0 is output is 0. fig.21 read from register 1 0 0 0 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 sclk sdata sdenb input input output 0 0 0 0 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 sclk sdata sdenb
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 20 - ? cis signal input channel number select there are 3 - channel mode and 1 - ch annel mode as input channel number. input channel number is selected by register. in 1 - channel mode, signal is input to cisin0. at this time, cisin1 and cisin2 can be connected to avss, or opened, or input dummy signal. sample and hold circuit and dac of n ot used channels are power down. frequency of adck in 3 - channel mode is three times the pixel frequency per channel. in 1 - channel mode, adck frequency is equal the pixel frequency. ? cis reference voltage it is able to select to use internal voltage or to use externally input voltage as sensor reference voltage by register. input range of external voltage is from 0.8v to 1.2v. internal voltage is 1.0v (typ.) or 1.1v (typ.). ? offset adjust ment offset adjustment is done by adding dac output voltage to senso r signal. resolution of dac is six bit, range is ? 3 69 mv (typ.) /300mv(min.) in equivalent input voltage. 50 mv (max.) out of ? 3 69 mv is used to cancel lsi internal offset. therefore effective range for correcting signal offset is ? 319mv (typ.) /250mv(min.) . th e equivalent input voltage does not change even if set 6db gain at sample and hold block. fig.22 offset adjustment ? sampling sensor signal are sampled at shd falling edge. ? gain adjustment it is possible to amplify signals at sample and hold block. and it is possible to amplify a/d output code by digital pga. gain of digital pga is from 0db to 18db. its resolution is 8bit. ? output format output formal is straight binary. gray code output is possible too. vdc offset dac s/h signal reference gnd internal reference level vref vref vsig vsig 369mv 369mv +max.(011111b) ? max.(100001b) cisinn
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 21 - fig.23 output format ? led driver led driver controls led current rgb independently. led must be connected as anode common. if leden_r/g/b are high level, led current are driven. if leden_r/g/b are l ow level, led current are stopped. leden_r/g/b are synchronized once by shd internally. therefore if shd is not input, leden_r/g/b are not effective. ? led current adjustment the led current can be adjusted in increments of 8.4ma to 67.2ma from 8.4ma chann el independently . ? led current limit AK8456 led driver current limitation is 100.8ma (total:150% setting). with the combination with leden_r/g/b pin logic and led drive current setting register value, in case of the combination that the total of the curr ent amount to flow through at the same time exceeds 150%(100.8 ma), the led drive current doesn't flow. for example, when making "leden_r/g/b" active at the same time and when the total of the led drive current set value exceeds 150%(100.8 ma), the led dri ve current doesn't flow. on the other hand, when making "leden_r/g/b" active individually, the current flows. a/d 16 gray code 16 16bit ? upper 8bit lower 8bit 8 digital pga 16 d7~d0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 g 0 g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 g 1 0 g 11 g 12 g 13 g 14 g 15 g 8 g 9 g 10 g 11 g 12 g 13 g 14 g 15 g 0 g 1 g 2 g 3 g 4 g 5 g 6 g 7 gray code conversion forward backward normal gray code forward backward
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 22 - ? cascade output mode it is possible that connect two AK8456 s output pins to same 8bit bus by cascade output mode. the cascade output mode is avail able only in 3 - channle input mode. it becomes the normal output regardless of the cascade mode register setting when the channel 1 input. if use cascade mode, please release the power - down after setting the devi ce id and cascade mode register . select the c ascade mode in the register and set 0 in id register of one and set 1 in id register of the other. device of id0 outputs the data before, id1 devices will output the data then refer to shd pulse . d7~d0 become high impedance when these pins don t output a/ d data. d7~d0 are open drain output in cascade mode. please connect pull - up resistance to each data output pin. maximum sampling rate in cascade mode is 5msps/ch. fig.24 c ascade mode explanation cisin0~2 adck shd d7~d0 #0 1 0 m l m l m l 2 3 d7~d0 #1 m l m l m l m l m l m l m l m l m l m l m l m l m l m l m l m l cis in 0 cis in 1 cis in 2 cis in 0 cis in 1 cis in 2 AK8456 #0 AK8456 #1 control ic sdenb2 sdenb1 8 8 sclk, sdata sclk, sdata d7~d0 d7~d0 2 2 ? 8
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 23 - 10 . register map adrs register name function 0h c ntrl 1 operation control 1 ( related to input stage ) 1h of st 0 cisin0 offset setting 2h of st 1 cisin1 offset setting 3h of st 2 cisin2 offset setting 4h gain0 cisin0 gain setting 5h gain1 cisin1 gain setting 6h gain2 cisin2 gain setting 7h cntrl2 operation control 2 ( related to output stage ) 8h iselr led _r current setting 9h iselg led _g current setting 0 ah iselb led _b current setting ** register - address 0bh - 0fh is an access - i nhibit. ** when writing an undefined bit, write 0.
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 24 - adrs name b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0h cntrl 1 npd shg0 shg1 shg2 --- vdco vdc sel chn default 0 0 0 0 0 0 0 0 ? address 0h b7 power - down setting npd operation 0 power - down 1 normal operation both of afe block and led driver power - down. ldo for analog block does not power C down. ? address 0h b 6 cisin0 sample and hold gain ? address 0h b5 cisin1 sample and hold gain ? address 0h b4 cisin2 sample and hold ga in shg 0/1/2 gain at sample and hold block 0 0db 1 6db ? address 0h b2 cis reference voltage source select vdco cis reference voltage source 0 external 1 internal (output to vdc pin) ? address 0h b 1 cis internal reference voltage select vdc sel cis reference voltage 0 1.0v 1 1.1v ? add ress 0h b0 input channel number select chn channel number 0 3 channels 1 1 channel ( input to cisin0 ) ** when writing an undefined bit, write 0.
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 25 - adrs name b7 b6 b5 b4 b3 b2 b1 b0 1h offset 0 ofst0 2h o ffset 1 ofst1 3h offset 2 ofst2 default 0 0 0 0 0 0 0 0 ? address 1h b5~b0 cisin0 offset setting ? address 2h b5~b0 cisin1 offset setting ? address 3h b5~b0 cisin2 offset setting ofst0/1/2 offset voltage 01 1111 01 1110 : 00 0001 00 0000 11 1111 : 10 0010 10 0001 10 0000 +369 mv +357.1mv +11.9mv ? 0mv ? 11. 9 mv ? 3 57.1 mv ? 369 mv inhibit when set minus value, signal magnitude becomes smaller. when set plus value, signal magnitude becomes larger. when ? 11.9m v setting, image signal decre ase 11.9mv . ** when writing an undefined bit, write 0.
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 26 - adrs name b7 b6 b5 b4 b3 b2 b1 b0 4h dpga 0 d gain0 5h dpga 1 d gain1 6h dpga 2 d gain2 default 0 0 0 0 0 0 0 0 ? address 4h b7~b0 cisin0 digital pga gain setting ? address 5h b7~b0 cisin1 digital pga gain setting ? address 6h b7~b0 cisin2 digital pga gain setting d gain0/1/2 digital pga gain 0000 0000 0000 0001 : 1111 1110 1111 1111 0db 18db inhibit 254 / 18 ) ( x x gain [db] x =0~254
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 27 - adrs name b7 b6 b5 b4 b3 b2 b1 b0 7h cntrl2 --- --- casc devid --- drv --- format default 0 0 0 0 0 0 0 0 ? address 7h b 5 cascade output mode select casc data output 0 normal output 1 cascade output if use cascade output mode, power down mode must be released after setting cascade output mode select register and device id s elect register. ? address 7h b4 device id for cascade output mode d evid device id 0 0 1 1 ? address 7h b2 output buffer ability select drv output buffer ability 0 normal 1 1/3 if set drv= 1 then output buffer ability of d7~d0 became 1/3 of normal. ? ad dress 7h b0 output format select format output format 0 straight binary code 1 gray code ** when writing an undefined bit, write 0.
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 28 - adrs name b7 b6 b5 b4 b3 b2 b1 b0 8h current r --- --- --- --- --- iselr 9h current g --- --- --- --- --- iselg ah current b --- --- --- --- --- iselb default 0 0 0 0 0 0 0 0 ? address 8h b 2 ~b0 led_r current setting ? address 9h b 2 ~b0 led_g current setting ? address ah b 2 ~b0 led_b current setting iselr/g/b led current 000 001 : 110 111 8.4 ma 16. 8 ma : 58.8 ma 67.2 ma ) 1 ( 4 . 8 ) ( ? ? [ ma ] x =0~ 7 ** when writing an undefined bit, write 0.
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 29 - 11 . external circuit example fig.25 r eference voltage: d0~ 7,sdout,avo,led_r/g/b note1 the resistance precision is 3 % (includ ing thermal - characteristic ) note2 the capacitance precision is 50 % (including thermal - characteristic ) note3 connect them near the pin. note4 keep off them from clock line(noise source) and so on. note5 when no t using a power on reset, it is unnecessary, connecting. note 6) be careful that the voltage of the led_r/g/b - pin doesn't exceed "lvdd+0.3v" , by the influence of the overshoot. in case of ,the overshoot is big and the led wiring is long, put a capacitor b etween " the led_r/g/b terminal " and the grand. fig.26 power pins *vss *vdd 10 ? f ( note 7) 0.1 ? f(note7) *vdd ovdd, avdd, lvdd *vss ovss, avss, lvss n ote7 each power pin need this cap. vdd 1 ? f(note3,4) 1 ? f(note2,3,4) vrp 8.2k ? (note1,4) iset min. 10k ? sdata vdc p ull - down or pull - up 0.33 ? f(note4,5) resetb min. 300 ? d0 7 p ull - up (only cascade mode) avss avss ovdd 1 ? f(note3,4) avo lvss (note6) led_r/g/b avss avss avss avss
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 30 - ? connection of cascade output mode fig.27 cascade mode connection example 28 29 1 8 17 19 20 21 22 23 24 25 26 27 d7 d6 d5 d4 ovdd ovss d3 d2 d1 28 29 18 17 19 20 21 22 23 24 25 26 27 d7 d6 d5 d4 ovdd ovss d3 d2 d1 d0 d0 3.3v r r r r r r r r r: min.300 ? 3.3v
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 31 - 1 2 . package ? dimensions (3 6pin qfn 5mm 5mm , pin pitch 0.4mm) fig.28 package dimensions ? marking 1. marketing code : ak 84 56 2. date code :xxx week number : y control code a k 8 4 5 6 x x x y note) marking is preliminary fig.29 AK8456 marking
[ak 8456 ] 014002433 - e - 00 201 4 / 06 - 32 - 1 3 . im portant notice important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( produ ct ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm p roducts . akm ne ither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automo biles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do n ot use product for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not u se or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and fol low the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or re gulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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