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32 - bit tx system risc tx 3 9 family t x3916f
tx3916f functional specification i capricorn 2 functional specification scope: this document describes the basic functions of tx3916f "capricorn2". this document is meant to provide al l information, which is needed to program and operate the device from a software developer's point of view. document history: rev. date changes pa1 20 - sep - 00 initial draft pa2 05 - dec - 00 second draft with major updates pa3 17 - jan - 01 removed halt and bo ot16 pin; corrections in ccr and dmac pa4 05 - feb - 01 minor changes in memc, dmac, txsei part. pa5 21 - feb - 01 some more improvements and enhancements pa6 21 - feb - 01 latest pinout pa7 01 - mar - 01 new layout, new document structure, minor changes in most chapters pa8 11 - apr - 01 corrections of the gdc?s digital output to the pios pa9 20 - apr - 01 added electrical characteristics pa10 24 - apr - 01 updated gdc part pa11 20 - jun - 01 changed power pin, pin 53 => no connect pa12 28 - jun - 01 review and corrections of memc, sramc, a ppendix chapters printed: 17 december 2001
table of contents iv table of contents handling precautions 1. the tx3916f ................................ ................................ ................................ ................................ ................................ ............. 1 - 1 1.1 applications and references ................................ ................................ ................................ ................................ ......... 1 - 1 1.2 features ................................ ................................ ................................ ................................ ................................ ............. 1 - 2 1.3 differences between tx3903af and tx3916f ................................ ................................ ................................ ........ 1 - 3 1.4 struct ure of tx3916f and a system example ................................ ................................ ................................ ........... 1 - 4 1.5 address map ................................ ................................ ................................ ................................ ................................ .... 1 - 6 1.6 clocks ................................ ................................ ................................ ................................ ................................ ................ 1 - 8 1.7 resets ................................ ................................ ................................ ................................ ................................ ................. 1 - 9 1.8 time - out - error control unit ................................ ................................ ................................ ................................ ...... 1 - 10 1.9 operating modes of tx3916f ................................ ................................ ................................ ................................ .... 1 - 10 1.10 chip configuration register (ccr) ................................ ................................ ................................ ........................... 1 - 11 2. memory controller (mc) ................................ ................................ ................................ ................................ ......................... 2 - 1 2.1 structure of me mory controller ................................ ................................ ................................ ................................ ... 2 - 2 2.2 example memory configuration ................................ ................................ ................................ ................................ .. 2 - 3 2.3 ports of memory controller ................................ ................................ ................................ ................................ ........... 2 - 6 2.4 registers ................................ ................................ ................................ ................................ ................................ ............ 2 - 6 2.5 sdramc functions ................................ ................................ ................................ ................................ ....................... 2 - 7 2.6 memc function ................................ ................................ ................................ ................................ ............................ 2 - 19 3. graphics display controller (gdc) ................................ ................................ ................................ ................................ ...... 3 - 1 3.1 gdc structure ................................ ................................ ................................ ................................ ................................ .. 3 - 2 3.2 internal blockdiagram ................................ ................................ ................................ ................................ .................... 3 - 9 3.3 r egisters ................................ ................................ ................................ ................................ ................................ .......... 3 - 10 3.4 setting example ................................ ................................ ................................ ................................ ............................. 3 - 18 4. interrupt controller (intc) ................................ ................................ ................................ ................................ ..................... 4 - 1 4.1 basic interrupt handling ................................ ................................ ................................ ................................ ................ 4 - 1 4.2 registers ................................ ................................ ................................ ................................ ................................ ............ 4 - 2 4.3 non maskable interrupt ................................ ................................ ................................ ................................ .................. 4 - 4 5. timer ................................ ................................ ................................ ................................ ................................ ......................... 5 - 1 5.1 pwm timer ................................ ................................ ................................ ................................ ................................ ...... 5 - 1 5.2 periodic timers ................................ ................................ ................................ ................................ ................................ 5 - 3 6. direct memory access controller (dmac) ................................ ................................ ................................ ......................... 6 - 1 6.1 programming the dma controller ................................ ................................ ................................ ............................... 6 - 2 6.2 registers ................................ ................................ ................................ ................................ ................................ ............ 6 - 5 7. can module (txcan) ................................ ................................ ................................ ................................ ........................... 7 - 1 7.1 block diagram ................................ ................................ ................................ ................................ ................................ . 7 - 2 7.2 txcan registers ................................ ................................ ................................ ................................ ........................... 7 - 3 7.3 txcan interrupt logic ................................ ................................ ................................ ................................ ............... 7 - 22 7.4 txcan operation modes ................................ ................................ ................................ ................................ ........... 7 - 25 7.5 handling of message - objects ................................ ................................ ................................ ................................ ..... 7 - 30 8. parallel interface (port ) ................................ ................................ ................................ ................................ ......................... 8 - 1 9. synchronous serial i/o (txsei) ................................ ................................ ................................ ................................ ............ 9 - 1 9.1 txsei structure ................................ ................................ ................................ ................................ .............................. 9 - 2 9.2 registers ................................ ................................ ................................ ................................ ................................ ............ 9 - 3
table of contents v 9.3 txsei operations ................................ ................................ ................................ ................................ ......................... 9 - 12 9.4 interrupts ................................ ................................ ................................ ................................ ................................ ......... 9 - 16 10. asynchronous serial interface (uart) ................................ ................................ ................................ .............................. 10 - 1 10.1 registers ................................ ................................ ................................ ................................ ................................ .......... 10 - 1 10.2 operations on serial interface ................................ ................................ ................................ ................................ ..... 10 - 9 10.3 timing ................................ ................................ ................................ ................................ ................................ ........... 10 - 1 6 11. appendix ................................ ................................ ................................ ................................ ................................ ................... 11 - 1 11.1 pin assignment ................................ ................................ ................................ ................................ .............................. 11 - 1 11.2 pin functions ................................ ................................ ................................ ................................ ................................ .. 11 - 5 11.3 register overview of tx3916f ................................ ................................ ................................ ................................ .. 11 - 8 11.4 electrical characteristics ................................ ................................ ................................ ................................ ............ 11 - 12
table of contents vi
chapter 1 the TMPR3916F 1 - 1 1. the TMPR3916F 1.1 applications and references the TMPR3916F is a family member of toshiba?s 32 - bit system risc family. as an application - specific standard product (assp) it is designed for a wide range of applications such as: car navigation systems driver i nformation displays personal digital assistants (pdas) musical instruments electronic book players the TMPR3916F uses a tx39/h core as its cpu. the tx39/h cpu core is a risc processor developed by toshiba based on the r3000a architecture of mips technolog ies inc. . in addition to the processor core, this assp includes peripheral circuits such as a graphics display controller, a memory controller, a dma controller, several serial communication interfaces, can - bus interfaces, interval timers and general pur pose i/os. please refer to the following document for information about the tx39 core architecture, including the instruction set: 32 - bit tx system risc tx39 family architecture (document number 44137d)
chapter 1 the TMPR3916F 1 - 2 1.2 features miscellaneous: 60 mhz maximum operating fr equency: 208 pin qfp package (qfp208 - p - 2828 - 0.50) 3.3 v power supply voltage ca. 1200mw maximum power dissipation - 40c to 85c operating ambient temperature built - in clock generator 5v tolerant i/os on uarts, txsei and can - bus interface unified memory ar chitecture with a high performance dual bus structure (video bus + cpu bus) graphics display controller: four - layer (a - d) overlay hardware processing with transparent color: layer a, b can display 256 out of 64 k colors each layer c, d can display 16 out of 64 k colors each alternatively layer a may be configured in picture mode with 64k colors sdram and sram frame - buffer memory (sram recommended only for low resolutions) burst access to frame - buffer memory 16 bytes built - in dot buffer built - in color look - up tables (for plane a - d, 544 colors in total) built - in three - channel 6 - bit video dac, alternatively connection to digital displays (digital rgb output) dotclock, horizontal and vertical synchronisation signals can be generated internally or input from ex ternal device built - in tx39 core: toshiba - developed tx39h core based on mips r3000a architecture 4 kb instruction cache, 1 kb data cache built - in debug support unit for in - system debugging incl. real time pc - tracing big - endian coding peripheral controlle rs: memory controller (memc), 4 channels for sram, rom, flash sdram controller (sdramc), 2 channels dma controller (dmac), 2 channels interrupt controller (intc), 13 internal interrupts, 3 external interrupts, 1 non - maskable interrupt (nmi) serial i/o : u art 4 channels, txsei 1 channel (spi compatible, with fifos) can - bus controller (txcan), 2 channels, 16 mailboxes each 30 pin general purpose i/os (port)
chapter 1 the TMPR3916F 1 - 3 1.3 differences between tx3903af and TMPR3916F in catchwords this section explains changed features of TMPR3916F in comparison to its predecessor tx3903af. for detailed information please have a deeper look into this document. 60 mhz operating frequency added dual can device added txsei functionality added two channel sdram controller separate video - and c pu - bus to sdram in order to increase system performance removed edo - dram channels from memc no more support of pipelined burst sram graphics display controller: increased number of colors from 16 to 256 in layer a and b raised number of 16 general purpose ios to 30 and added capability of triggering interrupt extended timer functionality to pwm - support increased number of internal interrupts modified uart incl. register structure external bus - master functionality is not supported any more
chapter 1 the TMPR3916F 1 - 4 1.4 structure of tmp r3916f and a system example the following picture shows the block diagram of the TMPR3916F: clock generator / pll tx39/h core core 4kb i$ 1kb d$ memory controller (mc) dsu sdramc memc gdc viewdac txcan channel 0 channel 1 intc timer pio sei sci channel 0 channel 1 channel 2 channel 3 xtal1 ,plloff, clken xtal2 sysclk reset pcst[2:0] dclk dsa0/tpc dbge sdi/dint dreset test[2:0] ext[2:0] nmi rxcan0, rxcan1 txcan0, txcan1 rout gout bout hsync vsync/csync hdisp dotclk pio[15:0] / digital rgb pio[29:16] / sci, sei ras cas we cke cs[1:0] dmac channel 0 channel 1 dreq0 dack0 halt cs[5:2] cpu bus video bus rd, wr, last bstart, burst a[26:2] d[31:0] be[3:0] ack, buserr figure 1.4 . 1 block diagram TMPR3916F
chapter 1 the TMPR3916F 1 - 5 the following picture shows a system example wi th TMPR3916F: TMPR3916F sdram rom cdrom i/f sram i/o ctrl mc sio sei can gps gyro gdc lc display rgb hsync vsync figure 1.4 . 2 system example using TMPR3916F
chapter 1 the TMPR3916F 1 - 6 1.5 address map the following table shows the memory map of TMPR3916F. memory area of tx39 - cpu physical address memory dev ice special use in TMPR3916F kernel uncached/ cached (kseg0, kseg1) 0x0000 0000 sdram, sram, rom * interrupt vector at 0x0000 0080 0x1c00 0000 internal register devices of TMPR3916F 0x1e00 0000 sdram, sram, rom * 0x1fc0 0000 boot rom start ad dress after reset or nmi inaccessible 0x2000 0000 user / kernel cached (kuseg) 0x4000 0000 sdram, sram, rom * user / kernel uncached (kuseg - reserved) 0xbf00 0000 kernel cached (kseg2) 0xc000 0000 kernel uncached (kseg2 - reserved) 0xff00 0000 figure 1.5 . 1 TMPR3916F?s memory map * for sdram, sram or rom shown in the above table, the software can define the address range of the connected memory devices. for further information se e chapter "memory controller".
chapter 1 the TMPR3916F 1 - 7 the following table shows the address ranges of the internal devices: address range (physical address) address range (virtuell address) device 0x1c00_0000 .. 0x1c00_07ff 0xbc00_0000 .. 0xbc00_07ff asynchronous serial int erface (uart) 0x1c00_8000 .. 0x1c00_ffff 0xbc00_8000 .. 0xbc00_ffff synchronous serial interface (txsei) 0x1c01_0000 .. 0x1c01_ffff 0xbc01_0000 .. 0xbc01_ffff timer 0x1c02_0000 .. 0x1c02_7fff 0xbc02_0000 .. 0xbc02_7fff memory controller (memc) 0x1c02_8 000 .. 0x1c02_ffff 0xbc02_8000 .. 0xbc02_ffff memory controller (sdramc) 0x1c03_0000 .. 0x1c03_ffff 0xbc03_0000 .. 0xbc03_ffff parallel interface (port) 0x1c04_0000 .. 0x1c04_ffff 0xbc04_0000 .. 0xbc04_ffff interrupt controller (intc) 0x1c05_0000 .. 0x1 c05_ffff 0xbc05_0000 .. 0xbc05_ffff graphic display controller (gdc) 0x1c06_0000 .. 0x1c06_ffff 0xbc06_0000 .. 0xbc06_ffff direct memory access controller (dmac) 0x1c07_0000 .. 0x1c07_7fff 0xbc07_0000 .. 0xbc07_7fff can module (txcan), channel 0 0x1c07_ 8000 .. 0x1c07_ffff 0xbc07_8000 .. 0xbc07_ffff can module (txcan), channel 1 0x1c08_0000 .. 0x1c08_ffff 0x1b08_0000 .. 0x1b08_ffff chip configuration register (ccr) figure 1.5 . 2 physical and virtual addre sses for internal devices note: please note that addresses seen on gbus are physical. therefore virtual addresses can only be used in program code and will be translated before being output to the bus.
chapter 1 the TMPR3916F 1 - 8 1.6 clocks the TMPR3916F incorporates an eight - times pll clock generator . connect a crystal oscillator with 1/8 the frequency of the processor clock (processor clock = tx39 core input clock frequency). to reduce power dissipation and simplify system design, the TMPR3916F can control the tx39 core operating freq uency and the bus operation reference frequency. clock types: master clock master clock regulates the TMPR3916F operations. the clock is eight times the frequency of the external crystal oscillator. processor clock this clock is used for TMPR3916F process or core operations. it has the same frequency as the master clock. (when using this clock, set reduced frequency indicator rf[1:0] of the core configuration register to 00. the processor clock will not operate if rf is set to any other value.) system clo ck the system clock regulates the TMPR3916F bus operations. it is generated from the processor clock and is of the same frequency and phase. this clock is output to pin sysclk. setting the clken pin to low stops all clocks of the device. the sysclk pin i s set to high in this state and power - consumption is reduced to a minimum. the processor can resume its function immediately after the clken pin has been asserted. for further information see chapter ?electrical characteristics?.
chapter 1 the TMPR3916F 1 - 9 1.7 resets setting reset* = l ow resets the TMPR3916F. reset* should be held low for at least 10 cycles of system clock (sysclk). because the reset* signal is synchronized with the TMPR3916F internal clock, the reset* signal can be set asynchronously to system clock. at a reset the t mpr3916f will do the following operations: pipeline will be stalled, internal states reset. the valid and lock bits of the tx39 cache will be cleared. during reset period the output signals have the following states: a[31:2] = undefined d[31:0] = undefine d be[3:0]* = ?high? rd*, wr* = ?high? burst* = ?high? last* = ?high? sysclk = continues outputting clock
chapter 1 the TMPR3916F 1 - 10 1.8 time - out - error control unit this unit is a kind of watchdog unit for the internal cpu - bus. when a master sends a gbstart signal, the time - out error control unit starts counting cycles. if no reaction has been detected on the bus, an internal acknowledging gack is generated after 1024 cycles so that the bus is free for interaction again. 1.9 operating modes of TMPR3916F in normal mode , the tx39 core and peripheral circuits operate at maximum frequency. halt mode halts the core operations and reduces power dissipation by stopping the clock in the tx39 core. to switch to halt mode, set the halt bit of the configuration register in tx39 core. in halt mode, the tx39 core holds the status of the pipeline processing and stops the core operations. the write buffer does not stop. if data remains in the write buffer when halt mode is selected, write operations continue until the write buffer becomes empty. also sysclk does not stop. the processor is released from halt mode by using the nmi* signal, reset* signal or by any kind of enabled interrupt. the corresponding exception handler is executed after the halt mode has been released. doze mode halts som e tx39 core operations and reduces power dissipation. unlike halt mode, only some clocks in the processor core stop, allowing external bus release requests to be received. also the peripheral blocks continue operating normally in doze mode. to switch to doze mode, set the doze bit of the configuration register in tx39 core. standby mode halts the clock generator pll circuit operation and reduces power dissipation. first, set clken pin to low to stop the clock supply. then, set plloff* pin to low to ha lt the pll circuit operations.
chapter 1 the TMPR3916F 1 - 11 1.10 chip configuration register (ccr) the configuration register is used to configure chip functions concerning more than one module. bit 31 30 29 28 27 26 25 24 name ? viewdac sfb bit 23 22 21 20 19 18 17 16 name ? canm c andiv bit 15 14 13 12 11 10 9 8 name ? seimux ? toe beow bit 7 6 5 4 3 2 1 0 name dma1cc dma0cc bit name function reset value r/w 31:26 ? wired to zero 0 r 25 viewdac by using this bit it is possible to power down the viewdac. 0 = disables the viewdac 1 = enables the viewdac (default) 1 r/w 24 sfb sram frame buffer: 0 = display frame is stored in sdram 1 = display frame is stored in sram 0 r/w 23:22 ? wired to zero 00 r 21:20 canm can operation mode 00 = normal mode x1 = internal test mode 1 0 = 2 internal can on one tx/rx pair, 1 transceiver 00 r/w 19 ? wired to zero 0 r 18:16 candiv the candiv bits set the clock divider for the can modules. the following table shows possible settings and the corresponding divider ratios. 000 = invalid sett ing 001 = system clock divided by 2 010 = system clock divided by 3 (default) 011 = system clock divided by 4 100 = system clock divided by 5 101 = system clock divided by 6 110 = system clock divided by 7 111 = system clock divided by 8 010 r/w 15:13 ? w ired to zero 0 r 12 seimux determines whether the txsei or the uart use pins pio16 to pio29. 0 = the uart uses pins 1 = the txsei uses pins 1 r/w 11:10 ? wired to zero 0 r 9 toe time - out error control the time - out error counter aborts bus transactions w ith exception after 1024 cycles, if they are not responded to. 0 = no time - out on internal bus 1 = abort not responded access on internal bus 1 r/w
chapter 1 the TMPR3916F 1 - 12 bit name function reset value r/w 8 beow bus error on write this bit determines, if a write transaction on internal bus will aborted, when no device responds after 1024 cycles. 0 = no bus - error on time - out at write 1 = generate bus - error on time - out at write 1 r/w 7:4 dma1cc these bits are used to select devices for dma transfers of dma channel 1. 0000 = uart0, transmission 0001 = uart0, reception 0010 = uart1, transmission 0011 = uart1, reception 0100 = uart2, transmission 0101 = uart2, reception 0110 = uart3, transmission 0111 = uart3, reception 1000 = txsei, transmission 1001 = txsei, reception 1010 = e xternal device 1111 = no device selected (reset value) other settings are invalid 1111 r/w 3:0 dma0cc these bits are used to select devices for dma transfers of dma channel 0. the settings are similar to dma1cc. 1111 r/w
chapter 2 memory controller (mc) 2 - 1 2. memory controller (mc) this system?s memory controller consists of two modules: the sdram controller (sdramc) and memc for other types of memory. six multi - purpose memory channels can be administrated: while the channels 0 and 1 are assigned to the sdram controller, the memory controller?s channels are numbered from 2 to 5. the sdram controller contains the following features: uses memory architecture single - data - rate sdram 2 memory channels with 32 bit width, 16 bit width connectivity is not supported fo r sdram devices base address, mask, dram size & organization configurable for each channel (same physical address space on both video and system - busses) true dual g - bus connectivity read bursts 4, 8, 16, 32 words, single read accesses, single write accesse s different, mixed burst sizes on both busses are possible fair memory arbitration, predictable latency memory arbitrated on a first come first serve basis for the case of a simultaneous transaction request, the prioritized g - bus can be configured one word write - back buffer to reduce bus utilization during write operations low - power / self - refresh mode supported background refresh during memc accesses built - in power - up logic programmable refresh cycle the memc contains the following features: 4 separate channels support for rom, mask rom, page mode rom, eprom, eeprom, sram, and flash devices support for page - mode base address and size programmable per channel external acknowledge mode for external asic slave device connectivity data bus width of 16 - bit/3 2 - bit is selectable by channel supports programmable setup and hold time for address, chip enable, write enable signals channel 5 supports boot options
chapter 2 memory controller (mc) 2 - 2 2.1 structure of memory controller capricorn2 owns two internal busses, the system bus and the video bus. the system bus can be accessed by the tx39 core and other devices capable of being master on the bus. additionally, the TMPR3916F provides a second, so called video bus. the video bus is used by the gdc in order to read picture data from the sdram frame bu ffer. the gdc is the only device on that bus and is not able to write data into sdram. it is only possible to write data into the frame buffer via the system bus. due to system performance considerations it is recommended to use sdram memory for frame buff er, though it is also possible to locate the frame buffer in memory devices accessible by the memc. for this purpose the TMPR3916F provides a bridge between system and video bus. in order to activate this bridge the sfb bit in chip configuration register ( ccr) needs to be asserted. it has to be assured that the gdc is not accessing sdram mapped memory in this case. in this mode, the system - performance is restricted by the higher utilization of the system bus and the reduced throughput to the frame buffer me mory devices. the following figure shows the structure of the memory controller: sdram controller internal system-bus interface to devices connected to the tx3903bf registered interface memc video to system bus bridge internal video-bus figure 2.1 . 1 data flow in memory controller
chapter 2 memory controller (mc) 2 - 3 2.2 example memory configuration the following figures show examples how to connect different devices to the TMPR3916F. it is possible to have a mixture of different kinds of memories because timing & device configurations are programmable for each channel in the mc. keep in mind that additionally a boot dev ice must always be connected to channel 5 of the memory controller! asynchronous sram connected to the TMPR3916F (16 bit data width): cs[x] * a[15:2] wr * rd * be[3] * be[2] * be[1] * be[0] * d[15:0] d[31:16] ce * a we * oe * lb * ub * d[15:0] TMPR3916F async . sram figure 2.2 . 1 16 - bit asynchronous sram con nected to TMPR3916F
chapter 2 memory controller (mc) 2 - 4 two asynchronous srams connected to one channel of the TMPR3916F : cs[x] a wr * rd * be[3] * be[2] * be[1] * be[0] * d[31:16] d[15:0] ce * a we * oe * lb * ub * d[15:0] ce * a we * oe * lb * ub * d[15:0] async . sram async . sram TMPR3916F figure 2.2 . 2 2 16 - bit asynchronous sram connected to one 32 - bit memory channel conn ection of an external slave device with a data width of 16 bit : sysclk cs[x] * a[15:2] bstart * last * burst * wr * ack buserr * be[1:0] * d[15:0] sysclk cs * a bstart * last * burst * rw * ack * buserr * be[1:0] d[15:0] TMPR3916F external slave figure 2.2 . 3 16 - bit external slave device connected to memory channel
chapter 2 memory controller (mc) 2 - 5 connection of an external slave device wi th a data width of 32 bit : sysclk cs[x * ] a[26:2] bstart * last * burst * rd * ack * buserr * be[3:0] * d[31:0] sysclk cs * a bstart * last * burst * rw * ackout * buserrout * be[3:0] * d[31:0] TMPR3916F external slave figure 2.2 . 4 32 - bit external slave device connected to memory channel the following figure shows the connection of a 32 bit width 16mbit sdram device to the TMPR3916F. as can be seen on the chip select signal connectivity (cs0) the device is accessed via channel 0 of the sdram controller. sysclk cke cs0 * a[12:2] a[16:15] ras * cas * we * be[3:0] * d[31:0] clk cke cs * a[10:0] ba[1:0] ras * cas * we * dqm dq[31:0] TMPR3916F sdram 16mbit * 32 figure 2.2 . 5 16 mbit 32 sdram devi ce connected to memory channel
chapter 2 memory controller (mc) 2 - 6 2.3 ports of memory controller the sdram controller externally connects up to two channels of sdram memory. each of the two sdram controller channels has its own organization register and can support different device sizes an d organization. the timing settings are shared for both channels and must be the same for both channels. refresh is conducted on both channels in parallel. the memory channels share the memory data, address and control busses with the exception of the chi p - select signal, which is wired individually for each channel. each channel must be connected with a width of 32 bits. devices with organizations of 4, 8, 16 and 32 bit width can be used as long as the connected devices jointly form a 32 bit channel. the f ollowing table summarizes the externally connected memory signals. signal type description sysclk out dram clock a[14:2] out row/column address bus, connect to a at the sdram device a[16:15] out bank address bus, connect to ba at the sdram device ras * out row access strobe signal cas * out column access strobe signal we * out write enable signal cke out clock enable signal for sdram cs * [1:0] out chip select signal, one for each sdram channel cs[0] => channel x cs[1] => channel y d[31:0] in/out data bus, connect to dq at the sdram device be[3:0] out output mask, connect to dqm at the sdram device 2.4 registers the following registers are used for configuration and operation of the TMPR3916F memory controllers. device register (short name) address (hex) function rccr2 1c02 0010h rom control register channel 2 rccr3 1c02 0014h rom control register channel 3 rccr4 1c02 0018h rom control register channel 4 memc rccr5 1c02 001ch rom control register channel 5 dccr 1c02 8000h sdram configuration register dcba 1c02 8004h sdram base address register dcam 1c02 8008h sdram address mask register sdram dctr 1c02 800ch sdram timing register
chapter 2 memory controller (mc) 2 - 7 2.5 sdramc functions 2.5.1 address translation the table below shows the different memory organizations that have been con sidered during the controller design and that can be used for each of the two memory channels. channel size (for one channel) mapped g - bus address bits toshiba device number organizations (devices banks rows columns bits) 8 mbyte [22:2] tc59s6432 1 4 2 k 256 32 (sdram, 64 mbit) 16 mbyte [23:2] tc59s6416 2 4 4 k 256 16 (sdram, 64 mbit) 32 mbyte [24:2] tc59s6408 tc59sm716 4 4 4 k 512 8 (sdram, 64 mbit) 2 4 4 k 512 16 (sdram, 128 mbit) 64 mbyte [25:2] tc59s6404 tc5 9sm708 tc59sm816 8 4 4 k 1 k 4 (sdram, 64 mbit) 4 4 4 k 1 k 8 (sdram, 128 mbit) 2 4 8 k 512 16 (sdram, 256 mbit) 128 mbyte [26:2] tc59sm704 tc59sm808 8 4 4 k 2 k 4 (sdram, 128 mbit) 4 4 8 k 1 k 8 (sdram, 256 mbit) 2 4 8 k 1 k 16 (sdram, 512 mbit) 256 mbyte [27:2] tc59sm804 8 4 8 k 2 k 4 (sdram, 256 mbit) 4 4 8 k 2 k 8 (sdram, 512 mbit) therefore, sdramc supports the following memory organizations: banks: 2 or 4 rows: 2 k, 4 k, 8 k columns: 256, 512, 1 k, 2 k the following table shows address translation of the g - bus address for supported memory configurations. organization column size organization row size organization bank size address mapping coladdr address mapping rowaddr address mappi ng bankaddr 2 k 2 4 gao[9:2] gao[20:10] gao[21] gao[22:21] 4 k 2 4 gao[9:2] gao[21:10] gao[22] gao[23:22] 256 8 k 2 4 gao[9:2] gao[22:10] gao[23] gao[24:23] 2 k 2 4 gao[10:2] gao[21:11] gao[22] gao[23:22] 4 k 2 4 gao[10:2] gao[22:11] gao[23] ga o[24:23] 512 8 k 2 4 gao[10:2] gao[23:11] gao[24] gao[25:24] 2 k 2 4 gao[11:2] gao[22:12] gao[23] gao[24:23] 4 k 2 4 gao[11:2] gao[23:12] gao[24] gao[25:24] 1024 8 k 2 4 gao[11:2] gao[24:12] gao[25] gao[26:25] 2 k 2 4 gao[12:2] gao[23:13] gao[24] gao[25:24] 4 k 2 4 gao[12:2] gao[24:13] gao[25] gao[26:25] 2048 8 k 2 4 gao[12:2] gao[25:13] gao[26] gao[27:26] note: gao (g - bus address output) refers to the physical address of the internal system bus.
chapter 2 memory controller (mc) 2 - 8 2.5.2 sdram controller function / bank interleaving the s dramc module functions as an advanced dram controller for synchronous dram. the TMPR3916F sdramc is ?advanced? compared to regular sdram controllers in the way that it is capable of handling two different mcu busses at the same time. sdram memory devices are usually organized in 4 different banks. all of these banks contain a high - speed static ram memory buffer, which allows fast sequential access once a dram memory row has been sensed into these buffers. the sensing of the dram memory row and the rewritin g of the sensed row are major contributors to the total duration of each memory access. the following picture shows the benefits of the dual - bus structure: single g-bus sdram controller command dq (output) gbusa start gbus a data actv a nop nop read a nop nop pchg a nop nop read b nop nop pchg b actv b nop qa1 qa2 qa3 qb1 qb2 qb3 qb4 qa4 nop nop nop nop command dq (output) gbusa start gbus a data gbus b start gbus b data dual g-bus sdram controller qa2 qa3 qb1 qb2 qb3 qb4 qa4 actv a nop nop read a nop nop pchg a read b pchg b actv b qb1 qb2 qb3 qa4 nop nop nop qa2 qa3 qb1 qb2 qb3 qb4 qa4 nop nop qa1 qb4 qa1 qa1 qa2 qa3 mcu access video/dma access mcu access video/dma access figure 2.5 . 1 benefits of dual - bus structure a regular sdram memory controller with only one mcu - bus interface will connect both the mcu and the video - controller on one bus. by transferring the bus - ownership both components access the external dram memory. typically, the sdram controller is able to work with only one address at the same time. it will not know the address for the next access before the previous transfer has been completed. a dual g - bus memory controller always knows the state and address of both busses. therefo re, it is possible to work with both addresses at the same time. the dual g - bus structure can only be effectively used, if the following condition is met: the two busses should utilize either different banks of the same channel or two different channels.
chapter 2 memory controller (mc) 2 - 9 this means for example that the frame - buffer for the video - controller and the program memory accessed by the mcu should be located in different memory banks. if the condition is not met for two consecutive addresses, the controller needs to precharge t he bank first and it has to wait for the precharge - to - active - latency before it can start with the access on the second mcu - bus. a memory throughput gain of up to 40 % can be achieved, if software allows the simultaneous utilization of several sdram banks. 2.5.3 self - refresh mode the sdram controller also offers support for the sdram self - refresh - mode. in self - refresh mode, the connected sdram devices maintain data retention without clock - supply and without the requirement of auto refresh cycles. the self - refresh mode significantly lowers the power consumption of the connected memory devices. self - refresh mode is entered with the assertion of the srm bit in the dccr register. the connected sdram channels and the sdram controller need to be enabled during this ope ration. upon assertion of this flag, sdramc will enter the self - refresh - mode by issuing a self - refresh - entry command. sdramc will remain in self - refresh mode until the deassertion of the srm flag. the sdramc logic guarantees a minimum time of apl latency cycles in self - refresh mode. the srm flag can be cleared in two different ways, by either writing the bit to ?0? or by conducting an access to mapped memory space. after clearing the srm flag, the cke signal is asserted to exit the self - refresh mode. the sdram controller issues nop commands for the number of cycles specified by the arl setting. after this, a regular auto refresh cycle will be conducted to finalize the sequence.
chapter 2 memory controller (mc) 2 - 10 2.5.4 configuration registers overview sdramc is configured using a total of four c onfiguration registers. these configuration registers reside in the sdramc configuration area. the configuration registers can be accessed using byte, half - word and word type accesses. following, the two memory channels are numbered x (cs0) and y (cs1). ea ch channel can be set up using its own memory configuration. the registers rsx, csx and bsx are used to set up the configuration for memory channel x. the registers rsy, csy and bsy are used to setup the configuration for memory channels y. control regist er (dccr) bit 31 30 29 28 27 26 25 24 name bit 23 22 21 20 19 18 17 16 name rsx csx bsx ? accd srm bit 15 14 13 12 11 10 9 8 name rsy csy bsy ? bit 7 6 5 4 3 2 1 0 name ? cen prio ? ena pwr bit name function reset value r/w 31:24 ? wired to zero 0 r 23:22 rsx row size for channel x the rsx, csx and bsx fields are used to specify the organization of memory channel x. 00 = 2 k 01 = 4 k 10 = 8 k 11 = invalid setting 00 r/w 21:20 csx column size for channel x number of columns 00 = 256 01 = 5 12 10 = 1 k 11 = 2 k 00 r/w 19 bsx bank size for channel x number of banks 0 = 2 banks 1 = 4 banks 0 r/w 18 ? wired to zero 0 r 17 accd acceleration disable disabling dual g - bus accelerations significantly lowers system performance. therefore, this mod e is meant to be used as fault mode only. 0 = all accelerations enabled 1 = prevents dual g - bus accelerations 0 r/w
chapter 2 memory controller (mc) 2 - 11 bit name function reset value r/w 16 srm self refresh mode this register is used to enter and exit the sdram self - refresh mode. self - re fresh mode will automatically be entered, by writing this register to 1. self - refresh mode is exited, by writing srm with a value of 0 or by conducting a read or write access to the sdram mapped memory region. cen or ena may not be deasserted during self - r efresh mode. if self - refresh mode is not utilized, initialize srm to 0. 0 r/w 15:14 rsy row size for channel y the rsy, csy and bsy fields are used to specify the organization of memory channel y. 00 = 2 k 01 = 4 k 10 = 8 k 11 = invalid setting 00 r/w 1 3:12 csy column size for channel y number of columns 00 = 256 01 = 512 10 = 1 k 11 = 2 k 00 r/w 11 bsy bank size for channel y number of banks 0 = 2 banks 1 = 4 banks 0 r/w 10:6 ? wired to zero 0 r 5 cen1 memory channel enable channel y 1 = enable addre ss decoding for this channel 0 = disable address decoding for this channel this setting enables and disables the address decoding for the memory channel. a memory channel cannot be accessed, if it is disabled using this bit and g - bus transactions within th e channel?s address range will not be answered. 0 r/w 4 cen0 memory channel enable channel x 1 = enable address decoding for this channel 0 = disable address decoding for this channel this setting enables and disables the address decoding for the memory c hannel. a memory channel cannot be accessed, if it is disabled using this bit and g - bus transactions within the channel?s address range will not be answered. r/w 3 prio g - bus priority setting this bit can be used to prioritize the access of one g - bus. ho wever, this bit has only a minor impact. in the scenario, the memory controller is in idle state when both g - busses simultaneously start a g - bus transaction: 1 = g - bus x will be serviced with priority 0 = g - bus y will be serviced with priority a real prior itization of one g - bus is not efficient in terms of performance, since it is not possible to utilize the dual g - bus structure under these circumstances. additionally, the latency of one g - bus would become unpredictable. 0 r/w 2 ? wired to zero 0 r
chapter 2 memory controller (mc) 2 - 12 bit name function reset value r/w 1 ena ena ? module enable 1 = enable module 0 = disable module if sdramc is disabled the state - machine of the sdram controller is suspended and the controller will remain in the idle state. this also means that connected sdr ams will not be refreshed and that their contents will be lost. the module should never be disabled during its normal operation. it has to be ensured, that no sdram accesses are performed on one of the g - busses when the module is disabled. for example, sd ramc should never be disabled in a situation, where read accesses are still performed on the video bus. it is mandatory to disable the gdc before sdramc is being disabled. software should also ensure, that the internal write - buffer has been written to sdra m memory. violations to these rules might result in bus hang - ups. 0 r/w 0 pwr pwr ? power - up sequence setting this bit will run the power - up sequence for all connected and enabled memory devices. the power - up sequence is described more closely in the nex t chapter. this flag can be read to determine the end of the power - up procedure. at the end of the power - up sequence, this bit is automatically cleared by the sdram controller state - machine. 0 r/w base address register (dcba) bit 31 22 21 16 n ame bax ? bit 15 6 5 0 name bay ? bit name function reset value r/w 31:22 bax base address memory channel x this register is used to define the base address for memory channel x. this address is compared to the upper 10 bits of the physical g - bus address. 0 r/w 21:16 ? wired to zero 0 r 15:6 bay base address memory channels y the same as for the memory channel x. 0 r/w 5:0 ? wired to zero 0 r
chapter 2 memory controller (mc) 2 - 13 address mask register (dcam) bit 31 22 21 16 name amx ? bit 15 6 5 0 n ame amy ? bit name function reset value r/w 31:22 amx address mask memory channel x this field is used to mask the base address for memory bank x. 1 = bit is taken into account during comparison 0 = bit is don?t care for the comparison the base addre ss mask is used to select the memory part of an appropriate size. it is also possible to mirror dram memory parts or to protect memory parts using this register. 0 r/w 21:16 ? wired to zero 0 r 15:6 amy address mask memory channels y the same as for memo ry channels x. 0 r/w 5:0 ? wired to zero 0 r timing register (dctr) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rfc wrl bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apl rasl casl pal arl bit name function reset value r/w 31:18 r fc refresh counter reload value this field provides the reload value for the internal refresh counter. the refresh counter is implemented as a 14 bit down counter, which reloads and issues a refresh request, every time a value of 0 is reached. this setting s depends on the specified refresh cycle time and number of rows of the connected memory devices: re gister value = rows of number frequency operation time fresh re (example settings at 60 mhz, counter values / settings in hex) time 2 k row 4 k row 8 k row 32 ms 0x03a9 0x01d4 0x00e a 64 ms 0x0752 0x03a9 0x01d4 128 ms 0x0ea4 0x0752 0x03a9 0x1000 r/w
chapter 2 memory controller (mc) 2 - 14 bit name function reset value r/w 17:16 wrl write recovery latency this setting defines the minimum number of cycles, from the point where the last word has been written until the ?pr echarge? command is issued. this setting has to match the write recovery time (t wr ) of the selected sdram. 00 = 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles 11 r/w 15:13 apl active to precharge latency this field and the associated timer is used to ensure the active to precharge latency (t ras ). the register value is used as reload value for an internal down counter. pchg latency 000 ..010 = invalid setting 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 111 r/w 12:10 rasl ras latency this timeframe has to safely match the t rcd time of the selected sdram device. the setting defines the number of cycles between providing the row address and the column address. this setting is used as reload value for a 3 bit down counter. 01 0 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles others = invalid setting 011 r/w 9:7 casl cas latency this setting defines the number of clock cycles from the time that the column address is provided (read, rda / write, wra) until the first data is taken/output from/on the sdram data bus. during the power - up sequence, this value is programmed into the mode register as it is. for the sdram controller this setting is used as a reload value for an internal down counter. cas latencies of less than 2 cycles are not supported! 010 = 2 cycles 011 = 3 cycles others = invalid settings 011 r/w 6:4 pal same bank precharge - > active/refresh latency this setting defines the minimum number of cycles from the point where the bank is precharged until it is reuse d (activate, refresh). this timeframe is defined by the t rp time of the selected memory device. this time will not be taken, if a different bank or a different memory device is accessed. 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 c ycles 111 = 7 cycles others = invalid settings 111 r/w
chapter 2 memory controller (mc) 2 - 15 bit name function reset value r/w 3:0 arl auto refresh to next command latency this setting defines the number of clocks, which are taken after an auto refresh command has been issued. this settin g is used as a reload value for a down counter. the counter will prevent any active sdram commands until it is expired. 0000 = invalid setting 0001 = 3 cycles 0010 = 4 cycles 0011 = 5 cycles ? ? 1111 = 17 cycles 111 r/w 2.5.5 software power - up sequence the pic ture below shows the software flow that is necessary to initialize the module. the sdram memory typically requires to be held in reset or disabled state until the internal circuits have stabilized. software has to ensure that this state is applied for the specified amount of time by not enabling the sdram controller during this timeframe. after the configuration registers have been sequentially configured, a power - up cycle needs to be scheduled by writing a ?1? value to the pwr bit in the dccr register. fi nally, the sdram controller and the utilized channels needs to be enabled to start the initialization. the pwr bit can be read to determine the end of the power - up sequence. during the power - up procedure, this flag will be read as ?1?. it is cleared, when the power - up procedure completes. software flow of initialization: wait for at least 200 m s reset configure control register (dccr) configure timing register (dctr) configure address mapping (dcam) set pwr in dccr enable the module by asserting the ena bit in dccr pwr cleared? dram ready for usage yes no configure address mapping (dcba) figure 2.5 . 2 sdram power - up software sequence flow chart
chapter 2 memory controller (mc) 2 - 16 2.5.6 address mask configuration the following example prov ides a step by step approach that shows how to configure base - address and address - masks for a memory channel. for the example it is assumed that two 128 mbit sdram devices with 16 bit connectivity are connected to one of the sdram controller channels. to configure the address mask proceed in the following order: (1) select a base - address for the memory area to be mapped. in this example, we choose 0x50000_0000 as the physical base address for the memory area to be mapped. (2) determine how much memory is connect ed to the memory channel: in this example 2 devices with 16 mbytes each => 32 mbyte (3) determine how many address bits are required to address 33.554.432 bytes log2 (33554432) = 25 this means that 25 address bits are required for the channel (4) therefore, the c orrect address mask is 0xfe00 (5) in this case, the memory area from 0x5000_0000 to 0x51ff_ffff will be mapped to the sdram channel. the sdram controller will respond only to bus accesses that refer to an address within this area. starting from this setup als o mirror areas and protected areas can be generated: example for mirroring: an address mask 0x7e00 will map the same physical memory twice to the addresses: 0x5000_0000 - 0x51ff_ffff and 0xd000_0000 - 0xd1ff_ffff example for protection: an address mask 0xff00 will leave the memory area 0x5000_0000 - 0x50ff_ffff accessible, while the second half 0x5100_0000 - 0x51ff_ffff is protected. please note that the sdram always refers to physical address space, which might differ from the virtual address space u sed within a computer program.
chapter 2 memory controller (mc) 2 - 17 timing diagrams basic read timing: clk cs* a ba / a[16:15] cke ras* cas* we* dq / d dqm / be cmd row bank a data0 act read column bank a data1 pchg act row bank a bank a rasl setting casl setting apl setting pal setting register settings for this example: rasl = 010 bin, casl = 010 bin, apl = 100 bin, pal = 011 bin figure 2.5 . 3 sdram read access timing diagram basic write timing: clk cs* a ba / a[16:15] cke ras* cas* we* dq / d dqm / be cmd row bank a data0 act write column bank a pchg act row bank a bank a rasl setting apl setting pal setting register settings for this example: rasl = 010 bin, casl = 010 bin, apl = 100 bin, pal = 011 bin, wrl = 01bin wrl setting figure 2.5 . 4 sdra m write access timing diagram
chapter 2 memory controller (mc) 2 - 18 bank interleaved read timing: clk cs* a ba / a[16:15] cke ras* cas* we* dq / d dqm / be cmd row bank a dataa0 act a read a column bank a dataa1 pchg a act b rasl setting casl setting dataa2 dataa3 datab0 datab1 datab2 datab3 read b rasl setting casl setting row bank b column bank b bank a bank b pchg b apl setting apl setting bank a bank b pal seeting ignored due to bank interleaving cycle figure 2.5 . 5 read access using bank interleaving auto - refresh timing: clk cs* a ba / a[16:15] cke ras* cas* we* dq / d dqm / be cmd pchg row bank a register settings for this example: pal = 011 bin, arl = 0010 bin aref act bank a pal setting arl setting figure 2.5 . 6 waveform for auto - refresh timing
chapter 2 memory controller (mc) 2 - 19 self refresh mode timing: clk cs* a ba/ a[16:15] cke ras* cas* we* dq/d dqm/be cmd pchg srm entry srm exit bank a pal setting aplreg arlreg aref act arlreg setting for this testcase: arl=0001 bin figure 2.5 . 7 timing diagram for self refresh mode
chapter 2 memory controller (mc) 2 - 20 2.6 memc function channel functionality is specifi ed by applying special values to channel control registers. they must be accessed using 32 - bit cycles. 2.6.1 channel assignment TMPR3916F contains the total of four multi - purpose memory controller channels. the following chip - select signals are assigned to th ese channels: chip enable signal assigned to channel cs2 memc channel 2 cs3 memc channel 3 cs4 memc channel 4 cs5 memc channel 5 (boot channel) channel 5 is a special function channel and is used to boot the microprocessor from external devices like sram, rom or flash memories. 2.6.2 channel 5 boot function for the system boot procedure, it can be chosen, whether the system shall be booted from a 16 or 32 bit device. this choice is made by connecting a pull - up or pull - down resistor to the a26/ boot16 p in. the value of this pin is latched once during system startup on the rising edge of the reset signal, when the ebif data bus is tri - stated. value of a26 / boot16 pin on rising edge of reset boot - function 0 channel 5 is 32 - bits wide at boot time 1 chan nel 5 is 16 - bits wide at boot time 2.6.3 operational modes there are two major modes of operation of the controller based on the state of the ack*/ready pin. in one mode, ack*/ready is always an input. in the other ack*/ready changes from input to output as ne eded on a channel - by - channel basis. in each of these two modes there are four sub - modes: normal, page, external ack*, and ready. these sub - modes can also be programmed on a channel - by - channel basis. between the two major modes there are some minor differen ces in the sub - modes that will be discussed later. 2.6.3.1 ack*/ready dynamic mode the controller enters this mode when no channel is programmed with rdy and wt[0] set. in this mode the ack*/ready pin is dynamic in that it changes from input to output on a chann el - by - channel basis. in normal or page sub - modes, ack*/ready is an output and displays the internal ack*. in external ack* or ready sub - modes, ack*/ready is an input. consult timing diagrams to avoid conflict when switching between input and output.
chapter 2 memory controller (mc) 2 - 21 2.6.3.2 ack*/ ready static mode the controller enters this mode when any channel is programmed with rdy and wt[0] set. in this mode the ack*/ready pin is static in that it remains an input at all times. since the pin is always an input, no internal ack* information can be obtained. this mode is primarily used by devices that use an open drain type node for the ack*/ready pin and conflict cannot be avoided without entering this mode. 2.6.3.3 normal sub - mode a channel enters this mode when the following conditions exist: pm=00, rdy=0, (pwt:wt[3:0])!=0x3fh. in this mode the ack*/ready pin is an ack* output and the cycle is terminated based on a 6 - bit wait counter. the 6 - bit wait counter is the concatenation of the pwt and wt fields (for rccr5 take wt[3:0]=wt[2:0]:bootai*). access time can be programmed to allow for 0 to 62 wait states. (note: pwt:wt=0x3fh indicates external ack* mode.) 2.6.3.4 external ack* sub - mode a channel enters this mode when the following conditions exist: pm=00, rdy=0, (pwt:wt[3:0])!=0x3fh. in this mode the ack*/ ready pin is an ack* input and the cycle is terminated by the external device. the ack* input is synchronized before it goes into the internal state machine. see section ack*input timing for more details. 2.6.3.5 page sub - mode a channel enters this mode when the following conditions exist: pm!=00, rdy=0. in this mode the ack*/ready pin is an ack* output and the cycle is terminated based on either the pwt or wt wait counter. the mode specifically targets page mode roms. during single cycle access, or the first wor d of a burst access, the 4 - bit wt field determines the access time. the access time can be programmed to allow for 0 to 15 wait states. during subsequent burst cycle accesses, the 2 - bit pwt field determines the access time and can be programmed to allow fo r 0 to 3 wait states. there are 3 different page mode burst size settings allowed in the pm field. when the page mode burst size is less than the cpu burst size, the channel will break the access up such that the 4 - bit wt field is always used on the progr ammed page mode boundary. in page mode the wt time must be greater than or equal to the pwt time or undetermined results may occur.
chapter 2 memory controller (mc) 2 - 22 2.6.3.6 ready sub - mode a channel enters this mode when the following conditions exist: pm=00, rdy=1. in this mode the ack*/ready pin is a ready input and the cycle is terminated by the external device. the ready input is synchronized before it goes into the internal state machine. ready is only checked for active once the 6 - bit wait counter has expired. the 6 - bit wait counter is th e concatenation of the pwt and wt fields. wt[0] is used to indicate the ack*/ready static/dynamic mode, and is therefore masked off for the count value. therefore, valid counts before ready is checked for active are 0, 2, 4, 6, ?, 62. burst accesses are n ot allowed in ready mode. 2.6.3.7 16 - bit bus operation in the case of 16 - bit mode if a single cycle is run from the g - bus that requires a single byte or half word that is contained within one 16 - bit word then only a single 16 - bit access is run on the external bus . otherwise two 16 - bit accesses are executed externally in the case of 16 - bit mode if a burst cycle is run from the g - bus, two 16 - bit cycles will be run for each of the burst accesses regardless or the fact that the internal byte enable signal is requestin g a byte, half word or any other combinations of internal byte enable signal that is not a full 32 - bit word. in 16 - bit mode the maximum channel size is 512 mbytes. 2.6.3.8 shwt option the shwt option is entered when the shwt field is non - zero. this option adds t he capability of adding setup and hold time between the following signals: setup: addr to ce, ce to oe, ce to bwe/be. hold: ce to addr, oe to ce, bwe/be to ce. it is typically used with slow i/o peripherals. all setup and hold times are the same for a gi ven value and are not individually programmable. shwt mode cannot be used in conjunction with page mode. all other modes can incorporate the shwt mode but are restricted in that burst accesses are not allowed.
chapter 2 memory controller (mc) 2 - 23 rom channel control register 2 - 4 (rccr2 - rcc r4) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rba rpm rpwt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rwt rcs rbs ? rbc ? rme rsht bit name function reset value r/w 31:20 rba base address designates the physical base address. 0 x000 r/w 19:18 rpm page mode , page size designates the page size of channel word burst page mode. 00 = not configured for page mode 01 = 4 - word burst page mode 10 = 8 - word burst page mode 11 = 16 - word burst page mode 00 r/w 17:16 rpwt page mode wait time designates a 2 - bit wait state counter in page mode for consecutive burst accesses. 00 = 0 wait cycles 01 = 1 wait cycle 10 = 2 wait cycles 11 = 3 wait cycles designates the upper 2 bits of a 6 - bit wait state counter for all other modes except external ack mode. external ack mode is entered when all bits of rpwt and rwt are set to 1. (refer to ? rwt ? ) 00 r/w 15:12 rwt normal mode wait time designates a 4 - bit wait state counter in page mode for single cycles or initial burst cycle. 0000 = 0 wait cycles 000 1 = 1 wait cycle 001 0 = 2 wait cycles : : 1111 = 15 wait cycles designates the lower 4 - bits of a 6 - bit wait state counter in all other modes except external ack mode. external ack mode is entered when all bits of rpwt and rwt are set to 1. rpwt [1: 0] : rwt [3:0] 000000 = 0 wait cycles 00000 1 = 1 wait cycle 0000 10 = 2 wait cycles : : 011110 = 30 wait cycles 011111 = 31 wait cycles : : 111110 = 62 wait cycles 111111: external ack * mode note: when pm=00, if setting rpwt: rwt = 0x3f, t he wait number doesn ? t become the longest in ack * output mode but the mode becomes ack * input 0000 r/w
chapter 2 memory controller (mc) 2 - 24 bit name function reset value r/w 11:8 rcs channel size designates the memory size to be assigned. 0000 = 1 m byte 0110: 64 m bytes 0001 = 2 m bytes 0111: 128 m bytes 0010 = 4 m bytes 1000: 256 m bytes 0011 = 8 m bytes 1001: 512 m bytes 0100 = 16 m bytes 1010: 1 g bytes 0101 = 32 m bytes 1011 - 1111: reserved in 16 - bit mode the maximum channel size allowed is 512m bytes. 0000 r/w 7 rbs bus size sets up the memory bus width of channel 2. 0 = 32 - bit bus size 1 = 16 - bit bus size 0 r/w 6 ? wired to zero 0 r 5 rbc byte control selects bwe * or be[3:0]. bwe * is the byte write enable signal to be active at only write cycle. be[3:0] is the byte enable signal to be active at both read cycle and write cycle. 0 = byte enables (be [3:0]) 1 = byte write enables (bwe * ) 0 r/w 4 ? wired to zero 0 r 3 rme master enable enables channel. 0 = channel is disabled 1 = channel is enabled 0 r/w 2:0 rsht setup/hold wait time selects the number of wait states between address and chip enable signal, chip select signal and write enable/output enable signal. 000 = disabled 001 = 1 wait 010 = 2 wait 011 = 3 wait : : 111 = 7 wait burst access and page mode are not allowed if this bit field is non - zero . 000 r/w
chapter 2 memory controller (mc) 2 - 25 rom channel control register 5 (rccr5) the channel 5 is used as boot channel. note that the pin a26 / boot16 has an impact on the bus width setting of the co nnected boot device. the rccr5 has the same bit function s like rccr2 to rccr4. only reset - values differ. for detailed description of function, please see rccr2 - rccr4. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rba rpm rpwt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rwt rcs rbs ? rbc ? rme rsht bit name function reset value r/w 31:20 rba base address (default: 0x1fc0 0000) 0x1fc r/w 19:18 rpm page mode , page size (default: no page mode) 00 r/w 17:16 rpwt page mode wait time (default: 3 wait cycles) 11 r/w 15:12 rwt normal mode wait t ime (default: 14 wait cycles) 1110 r/w 11:8 rcs channel size (default: 4 mbyte) 0010 r/w 7 rbs bus size (default: 16 bit) boot16 pin r/w 6 ? wired to zero 0 r 5 rbc byte control (default: byte enables only active on write access) 1 r/w 4 ? wired to ze ro 0 r 3 rme master enable (default: enabled) 1 r/w 2:0 rsht setup/hold wait time (default: disabled) 000 r/w
chapter 2 memory controller (mc) 2 - 26 2.6.4 timing diagrams single read access: sysclk csx a be rd wr bstart last burst d ack buserr address 0 be 0 data 0 single read with rwt = 01 (1 wait state) rwt wait states data latched figure 2.6 . 1 sdram single re ad access timing single write access: sysclk csx a be rd wr bstart last burst d ack buserr address 0 be 0 data 0 single write with rwt = 01 (1 wait state) rwt wait states figure 2.6 . 2 sdram single write access timing
chapter 2 memory controller (mc) 2 - 27 page mode read access: sysclk csx a be rd wr bstart last burst d ack buserr address 0 0000 data 0 data 1 data 2 data 3 address 1 address 2 address 3 4-word page-mode with rwt = 01 (1 wait state) and rpwt = 0001 (1 wait state) rwt wait states rpwt wait states rpwt wait states rpwt wait states data latched data latched data latched data latched figure 2.6 . 3 timin g diagram for read access using page mode external acknowledge mode read access: sysclk csx a be rd wr bstart last burst d ack buserr address 0 be 0 data 0 data latched figure 2.6 . 4 waveform for external acknowledge mode read access timing
chapter 2 memory controller (mc) 2 - 28 external acknowledge mode write access: sysclk csx a be rd wr bstart last burst d ack buserr address 0 be 0 data 0 figure 2.6 . 5 waveform for external acknowledge mode write access timing external acknowledge mode bus error: sysclk csx a be rd wr bstart last burst d ack buserr address 0 be 0 data 0 data latched figure 2.6 . 6 bus error during external acknowledge m ode timing
chapter 2 memory controller (mc) 2 - 29 16 bit read access: sysclk csx a be rd wr bstart last burst d ack buserr address 0 1100 data 0 data 2 address 1 data latched data latched 1111 1100 figure 2.6 . 7 sdram timing diagram for 16 - bit read access 16 bit write access: sysclk csx a be rd wr bstart last burst d ack buserr address 0 1100 data 0 data 2 address 1 1111 1100 figure 2.6 . 8 s dram timing diagram for 16 - bit write access
chapter 2 memory controller (mc) 2 - 30
chapter 3 graphics display controller (gdc) 3 - 1 3. graphics display controller (gdc) the graphics display controller contains the following characteristics: supports sdram and sram frame buffer ? burst mode for reading on sdram supports four - layer overlay display function using hardware processing layer a /e: map mode (256 colors) ? referred to as layer a, picture mode (65,536 colors) ? referred to as layer e layer b: map mode (one of the 256 colors is transparent) layer c: map mode (one of the 16 colors is transparent) layer d: map mode (one of the 16 colors is transparent) ? displaying layers a and e together is not possible. ? layer d screen size can be set independently of the other layer sizes. ? incorporates a 544 entries color palette (256 colors two layers and 16 colors two layers). display control: ? non - interlaced scanning ? smooth scrolling (vertical and horizontal) ? generates and outputs synchronization signals (hsync, vsync / csync), also supports control by external synchronization signal input. ? both digital and analog rgb signal o utput dot clock: ? supports internal and external dot clock
chapter 3 graphics display controller (gdc) 3 - 2 3.1 gdc structure 3.1.1 display screen the TMPR3916F can display four layers, overlaid in the following order: a/e, b, c and d. top layer is d (see figure 3.1 . 1 ). displaying layers a and e together is not possible because these layers use the same resources except for color palette and dot buffer. the blank signal blk enables the display data output. the layer active signals la, lb, lc and ld activate each layer. layer d screen size can be set independently of the other layer sizes. layer a can be switched between map mode and picture mode (then called layer e). use the lpa bit of the display control register (dcr) to switch the modes. layer a/e layer b layer c layer d la, lpa data a/e: layer a/e displayed lb data b: (0), 1 layer b displayed lc data c: (0), 1 layer c displayed ld data d: (0), 1 layer d displayed next layer displayed next layer displayed next layer displayed lx data x = 1 : display lx data x = 0 : no display (transparent) lx : bit in display control register data x : layer x display data x : a/e, b, c, d figure 3.1 . 1 layer arrangement
chapter 3 graphics display controller (gdc) 3 - 3 3.1.2 frame buffer the TMPR3916F supports sdram and sram as frame buffer. the gdc uses separated address generators for each of its four layers a/e, b, c, and d. it can specify the a/e, b, c, or d la yer display data address area by writing the data to the start address register (sarx, where x stands for: a/e, b, c, d), the memory width register (mwrx), the horizontal display start register (hdsr) and the horizontal display end register (hder). the hds r and hder are stored as one value in the horizontal display start end register (hdser). hder - hdsr sarx sarx + mwrx mwrx frame buffer 1 st line sarx 32 bit frame buffer sarx + mwrx sarx + n ? mwrx (n+1) th line 2 nd line figure 3.1 . 2 frame buffer data the sarx stores the address of the upper - left corner?s do t belonging to layer x. the mwrx stores the offset value to be added to the contents of sarx to get the address of the left - most pixel of the following line. it is not allowed to store the last dot of one line and the first dot of the next line within one memory word as shown below. the TMPR3916F dot data structure in the frame buffer is as follows: in map mode these values are addresses for color palette. in picture mode these values represent the displayed colors. data length per dot active level # col ors map mode c/d 4 bits layers c, d 16 map mode a/b 8 bits layers a, b 256 picture mode 16 bits layer e 64k accordingly, the data structure for each word is as follows. bits 31:28 27:24 23:20 19:16 15:12 11: 8 7:4 3:0 map mode c/d dot 1 dot 2 dot 3 dot 4 dot 5 dot 6 dot 7 dot 8 map mode a/b dot 1 dot 2 dot 3 dot 4 picture mode dot 1 dot 2
chapter 3 graphics display controller (gdc) 3 - 4 the minimum value to be stored in mwrx is equal to the number of dots per line in the frame buffer divided by 4 (in case of layers a and b, 8 for c and d and 2 for layer e) and rounded to the next greater integer value (mwrx stores numbers of 32 bit words). in practice, it is advisable to have a certain space between two adjacent lines. therefore the practical memory size is larger than the one requested to cove r just one layer. the frame buffer contents represent the address of the color palette which contains the displayed colors for the respective layer: 32 bit frame buffer line 1 dot 1 line 1 dot 2 line 1 dot 3 line 1 dot 4 line 1 dot n-1 line 1 dot n-2 line n dot 1 line n dot 2 line n dot 3 line n dot 4 line n dot n-2 line n dot n-1 16 bit-wide colour palette to digitalout or viewdac line 1 dot n line n dot n figure 3.1 . 3 frame buffer and color palette in case of layers a or b in case of layers c and d, the contents of register mwrx must be adjusted taking into consideration that there are 8 dots in a 32 bit word. therefore the minimum value is given by the number of dots in a line divide d by 8. 32 bit frame buffer line 1 dot 1 line 1 dot 2 line 1 dot 3 line 1 dot 4 line 1 dot n-1 line 1 dot n-2 line n dot 1 line n dot 2 line n dot 3 line n dot 4 line n dot n-2 line n dot n-1 16 bit colour palette to digitalout or viewdac line 1 dot 5 line 1 dot 6 line 1 dot 7 line 1 dot 8 line 1 dot n line n dot 5 line n dot 6 line n dot 7 line n dot 8 line n dot n figure 3.1 . 4 frame buffer and color palette in case of layers c or d in case of layer e, each 32 bit word is storing the data of 2 dots. so the minimum number to store i n mwra (e layer uses a layer registers) is equal to the number of pixels in a line divided by 2. no color palette is needed for layer e.
chapter 3 graphics display controller (gdc) 3 - 5 32 bit frame buffer line 1 dot 1 line 1 dot 2 line n dot 1 line n dot 2 to digitalout or viewdac line 1 dot n line n dot n figure 3.1 . 5 frame buffer in case of lay er e the number in mwrx is always rounded to the higher integer. some display devices do colour calibrations during synchronization periods. that is why the graphics display controller outputs black level as analog output from viewdac while hdisp=0. for digital output this value is stored in register pa (see port module) with respect to the output mode (dot or pixel). as a result the pa register has to be initialized with the correct value (reset value: 0x00h).
chapter 3 graphics display controller (gdc) 3 - 6 3.1.3 display control signal the gdc block gener ates and outputs the synchronization signal (hsync, vsync, and csync). the display uses non - interlaced scanning. hswr hdsr + 8 hdsr + 9 hder + 8 hcr hsync * hder + 8 vdsr + 1 vder vswr vsync * vdsrr vder vcr blanking area dot data display area figure 3.1 . 6 display timing the gdc block can select and output a separated synchronization (hsync*, vsync*) or a composite synchronization (csync*) signal. the composite csync* is the ex - nor (exclusive nor) signal of hsync* and vsync*. vsync * hsync * csync * figure 3.1 . 7 csync * timing in positive mode the composite csync is the ex - or (exclusive or) signal of hsync and vsync. hsync vsync csync figure 3.1 . 8 csync timing when hsync and vsync are in positive m ode the dcr bit csel enables composite synchronization signal output. the bit nsync enables using synchronization signals in positive mode. externally separated synchronization signals can also be used for input. set using the esync bit of the dcr.
chapter 3 graphics display controller (gdc) 3 - 7 not e that the use of external synchronization signals needs processing time. therefore the input signals hsync and vsync are delayed internally. to compensate this delay, set the horizontal display - related registers - 3, the vertical display - related registers needs not to be changed. for positive mode set the horizontal display - related register ? 6 and the vertical display - related register - 2. when using external hsync and vsync signals, the horizontal synchronization pulse width (hswr), vertical synchronizatio n pulse width (vswr), horizontal cycle register (hcr) and vertical cycle register (vcr) settings are invalid. external composite synchronization signals cannot be processed by the TMPR3916F. please note also that due to internal data structures hds and h de are automatically incremented by 8 so that the effective values are hds+8 and hde+8. 3.1.4 dots and pixels the gdc is able to support both, dot and pixel on digital output. the 16 - bit data for one dot is divided into r (red), g (green), and b (blue). a pixel represents one of these colors in a 6 - bit value. in consequence one dot represents three pixels as shown in the following figure: 15 11 ~ 10 6 ~ 5 0 ~ 0/1 r[5:0] g[5:0] b[5:0] 16-bit dot data 6-bit pixel data 0/1 figure 3.1 . 9 partitioning rgb data into dot and pixel data each six bits of rgb data are input to the 6 - bit dac (three channels) in the gdc. the lsb of r and g transmitted to the dac data are always fixed to zero. in dot mode (dcr[3] = 0) the gdc supports dots on the digital rgb port and dot clock on the dotclk port. in pixel mode (dcr[3] = 1) the gdc supports pixels on the lower 6 ports of the digital rgb port (pio[5:0]) and pixel clock on the dotclk port. in case of dot mode the lsb of r and g depend on the lsb bit on dcr (dcr[4]), the parallel data is output to pio[15:0].
chapter 3 graphics display controller (gdc) 3 - 8 3.1.4.1 dot clock the dot clock is the reference clock for graphics data output. it is also used to determine the screen size, for example, of each layer. use the following formula to select the dot clock: s) ( period display horizontal dots) visible non (including line per dots display of number = (mhz) speed clock dot m note tha t the internal circuit imposes the following restriction: dot clock speed (mhz) < ? sysclk. the dot clock can be provided internally as a derivative of the system clock. the divisor is defined by dckps (see display control register (dcr)) and can be set to 4, 6, 8, ?, 24. therefore frequencies of 2.5 mhz up to 15 mhz can be reached when using the internal dot clock. default setting for dckps is 0x4h for a dot clock of 6 mhz. alternatively the dot clock may be input via the dotclk pin. 3.1.5 color palette in map mode, each dot can be set for 16 colors using layer c or d and 256 colors using layer a or b. by using the color palette, any 16 or 256 colors respectively can be selected from among the 65,536 colors. the color palette can be set independently for eac h layer (a, b, c or d). one of the defined colors is transparent for layers b, c and d. it must not be used if no background layer is activated. in picture mode (layer e), the TMPR3916F can display up to 65,536 colors. the dot data are directly defined at the frame buffer and therefore no color palette is necessary. the following table shows the color palette structure: layer palette name number of colors color palette no. address color specification a cplta 256 colors 0 1 : 255 1c05 0800 1c05 0804 : 1c 05 0bfc free defined color 0 free defined color 1 : free defined color 255 b cpltb 255 colors 0 1 : 255 1c05 0c00 1c05 0c04 : 1c05 0ffc transparent free defined color 0 : free defined color 254 c cpltc 15 colors 0 1 : 15 1c05 0180 1c05 0184 : 1c05 01bc t ransparent free defined color 0 : free defined color 14 d cpltd 15 colors 0 1 : 15 1c05 01c0 1c05 01c4 : 1c05 01fc transparent free defined color 0 : free defined color 14
chapter 3 graphics display controller (gdc) 3 - 9 3.2 internal blockdiagram display control register horizontal transfer number register * 2 a & b & c & d memory width register * 4 a & b & c & d start address register * 4 a & b & c & d horizontal display start register * 2 horizontal display end register * 2 vertical display start r egister * 2 vertical display end register * 2 horizontal synchronous pulse width register horizontal cycle register vertical synchronous pulse width register vertical cycle register timing control dot shifter dot buffer a, b c, d color palette dot buffer e overlay hsync vsync/ csync hdisp d[31:0] a[31:2] be[3:0] * gdcint * dac analog out rout analog out gout analog out bout digital rgb via pio: [15:0] in dot mode [5:0] in pixel mode 32 16 16 dotclk figure 3.2 . 1 gdc block diagram
chapter 3 graphics display controller (gdc) 3 - 10 3.3 registers overview short name address name function dcr 1c050000 display control register sets the gdc operations. sara/e 1c050010 layer a/e?s start address register specifies the start address of laye r a/e on the frame buffer. sarb 1c050014 layer b?s start address register specifies the start address of layer b on the frame buffer. sarc 1c050018 layer c?s start address register specifies the start address of layer c on the frame buffer. sard 1c05001 c layer d?s start address register specifies the start address of layer d on the frame buffer. mwra/e 1c050020 layer a/e?s memory width register specifies the line width of layer a/e on the frame buffer. mwrb 1c050024 layer b?s memory width register spec ifies the line width of layer b on the frame buffer. mwrc 1c050028 layer c?s memory width register specifies the line width of layer c on the frame buffer. mwrd 1c05002c layer d?s memory width register specifies the line width of layer d on the frame buf fer. htn 1c050030 layer a/e, b, c?s horizontal transfer number register sets the number of display dots for one line divided by 32. for layers a/e, b, and c. htnd 1c050034 layer d?s horizontal transfer number register sets the number of display dots for one line divided by 32. for layer d. hdser 1c050038 layer a/e, b, c?s horizontal display start / end register sets the layer?s display position and the number of display dots for layers a/e, b, and c. hdserd 1c05003c layer d?s horizontal display start / end register sets the horizontal display position and the number of display dots for layer d. hcr 1c050040 horizontal cycle register specifies the total number of dots within a horizontal cycle. hswr 1c050044 horizontal synchronization pulse width regist er specifies the horizontal sync signal pulse width using the number of dot clocks. vcr 1c050048 vertical cycle register specifies the total number of lines within a vertical cycle. vswr 1c05004c vertical synchronization pulse width register specifies th e vertical sync signal pulse width using the number of lines. vdsr 1c050050 layer a/e, b, c?s vertical display start register sets the vertical display start position for layers a/e, b, and c. vdsrd 1c050054 layer d?s vertical display start register sets the vertical display start position for layer d. vder 1c050058 layer a/e, b, c?s vertical display end register sets the vertical display end position for layers a/e, b, and c. the difference vder ? vdsr defines the number of display dots for layers a/e, b, and c. vderd 1c05005c layer d?s vertical display end register sets the vertical display end position for layer d. the different vderd ? vdesrd defines the number of display dots for layer d.
chapter 3 graphics display controller (gdc) 3 - 11 display control register (dcr) bit 31 30 29 28 27 26 25 2 4 name blk dck ads lpa ld lc lb la bit 23 22 21 20 19 18 17 16 name dckps hv buserr vsync hsync bit 15 14 13 12 11 10 9 8 name ? bit 7 6 5 4 3 2 1 0 name ? lsb mode nsync csel esync bit name function reset value r/w 31 blk 0 blank screen 1 di splay frame buffer 0 r/w 30 dck 0 selects external dot clock 1 selects internal dot clock (divides sysclk) 0 r/w 29 ads 0 digital rgb output off 1 digital rgb output on when outputting a digital rgb signal, you must set bits [15:0] of pmux register in m odule port to 1. 0 r/w 28 lpa 0 map mode (layer a, 8 bits per dot) 1 picture mode (layer e, 16 bits per dot) 0 r/w 27 ld 0 do not display layer d 1 displays layer d 0 r/w 26 lc 0 do not display layer c 1 displays layer c 0 r/w 25 lb 0 do not display la yer b 1 displays layer b 0 r/w 24 la 0 do not display layer a/e 1 displays layer a/e 0 r/w 23:20 dckps dot clock: 0 hex not allowed 1 hex 1/4 system frequency 2 hex 1/6 system frequency 3 hex 1/8 system frequency 4 hex 1/10 system frequency 5 hex 1/12 system f requency 6 hex 1/14 system frequency 7 hex 1/16 system frequency 8 hex 1/18 system frequency 9 hex 1/20 system frequency a hex 1/22 system frequency b hex 1/24 system frequency others 1/10 system frequency these bits are relevant only when dck = 1. 0x4 r/w 19 h v 0 interrupt at vsync * 1 interrupt at hsync * 0 r/w 18 buserr 0 no bus error during gdc transfer 1 bus error during gdc transfer 0 r/w
chapter 3 graphics display controller (gdc) 3 - 12 bit name function reset value r/w 17 vsync 0 vertical scanning synchronization pulse period 1 vertical scanning displ ay period note: in positive mode the synchronization period takes place when vsync equals logic 1. 0 r 16 hsync 0 horizontal scanning synchronization pulse period 1 horizontal scanning display period note: in positive mode the synchronization period takes p lace when hsync equals logic 1. 0 r 15:5 ? wired to zero 0 r 4 lsb 0 outputs 0 on lsb of r/g in pixel mode 1 outputs 1 on lsb of r/g in pixel mode 0 r/w 3 mode 0 dot mode: outputs dots and dot clock 1 pixel mode: outputs pixels serially and pixel clock 0 r/w 2 nsync 0 normal mode: outputs sync signals low active 1 positive mode: outputs sync signals high active 0 r/w 1 csel 0 outputs vsync signal from vsync pin 1 outputs csync signal from vsync pin 0 r/w 0 esync 0 sets hsync and vsync pins to output m ode 1 sets hsync and vsync pins to input mode 1 r/w start address register a/e, b, c, d (sara/e, sarb, sarc, sard) bit 31 21 20 3 2 1 0 name sa ac ss bit name function reset value r/w 31:21 sa segment address these bits specify the segment st art address of each layer?s frame buffer. 0 r/w 20:3 ac address counter these bits specify the start address within the segment defined by sa of each layer?s frame buffer. 0 r/w 2:0 ss dot position these bits specify the first visible dot within the firs t word addressed by ac. note that ss width differs for layer a/b and c/d and does not matter for layer e. the ss[2] bit is not relevant for layers a and b. display start position layer c/d layer a/b 000 from dot 1 from dot 1 001 from dot 2 from dot 2 010 from dot 3 from dot 3 011 from dot 4 from dot 4 100 from dot 5 from dot 1 101 from dot 6 from dot 2 110 from dot 7 from dot 3 111 from dot 8 from dot 4 ac & ss specify the display start position for each layer in units of dots. counting up ac & ss scro lls screen to the left. counting down ac & ss scrolls screen to the right. 0 r/w
chapter 3 graphics display controller (gdc) 3 - 13 the specified start address sarx is not the same address as the address on the video bus. the lowest bits (ss bits) are used internally only (!). the differences are descr ibed in figure 12: 0 sa[10:0] ac[17:0] ss[2:0] sa[10:0] ac[17:0] 31 2 sarx [31:0] video bus address [31:2] used within gdc only 30 20 19 21 20 3 2 0 31 logical address physical address figure 3.3 . 1 logical address and physical bus address note: bit 31 of video bus address is tied to 0. memory width register a/e, b, c, d (mwra/e, mwrb, mwrc, mwrd) bit 31 26 25 16 15 0 name ? mw ? bit name function reset value r/w 31:26 ? wired to zero 0 r 25:16 mw specifies the line widths of each layer on the frame buffer in one - word units. for example, where the line width is 320 dots: mw = 28 he x for layer c and d mw = 50 hex for layer a and b mw = a0 hex for layer e 0 r/w 15:0 ? wired to zero 0 r horizontal transfer number register (htn) for layers a/e, b and c bit 31 21 20 16 15 0 name ? htn ? bit name function reset value r/w 31 :21 ? wired to zero 0 r 20:16 htn line size of layer a/e, b and c these specify the number of data transfers for one line. sets the number of display dots for one line divided by 32. 0 r/w 15:0 ? wired to zero 0 r note: htn is always rounded to the hig her integer value.
chapter 3 graphics display controller (gdc) 3 - 14 horizontal transfer number register (htnd) for layer d bit 31 21 20 16 15 0 name ? htnd ? bit name function reset value r/w 31:21 ? wired to zero 0 r 20:16 htnd line size of layer d these specify the number of data transfer s for one line. sets the number of display dots for one line divided by 32. 0 r/w 15:0 ? wired to zero 0 r note: htnd is always rounded to the higher integer value. it is for layer d only as layer d may have a different size. horizontal display start/ end register (hdser) for layers a/e, b and c bit 31 24 23 16 15 10 9 0 name ? hds ? hde bit name function reset value r/w 31:24 ? wired to zero 0 r 23:16 hds these specify the horizontal display start position using the number of dot clocks, st arting from the hsync * signal falling edge. 0x2d r/w 15:10 ? wired to zero 0 r 9:0 hde these specify the horizontal display end position using the number of dot clocks, starting from the hsync * signal falling edge. number of dots displayed during one per iod = hde ? hds 0x15d r/w note: the lowest value allowed for hds and hde is 2 hex . due to internal data structures effective values are hds+9 and hde+8. horizontal display start/ end register (hdserd) for layer d bit 31 24 23 16 15 10 9 0 name ? hd sd ? hded bit name function reset value r/w 31:26 ? wired to zero 0 r 25:16 hdsd these specify the horizontal display start position using the number of dot clocks, starting from the hsync * signal falling edge. 0x2d r/w 15:10 ? wired to zero 0 r 9:0 hded these specify the horizontal display end position using the number of dot clocks, starting from the hsync * signal falling edge. number of dots displayed during one period = hded - hdsd 0x15d r/w note: the lowest value allowed for hdsd and hded is 2 hex . due to internal data structures effective values are hds+9 and hde+8.
chapter 3 graphics display controller (gdc) 3 - 15 horizontal cycle register (hcr) bit 31 26 25 16 15 0 name ? hc ? bit name function reset value r/w 31:26 ? wired to zero 0 r 25:16 hc specifies the total number of dot s and dot clocks within one horizontal cycle. hc = horizontal cycle time (s) dot clock frequency (mhz) 0x189 r/w 15:0 ? wired to zero 0 r vertical cycle register (vcr) bit 31 26 25 16 15 0 name ? vc ? bit name function reset value r/w 31 :26 ? wired to zero 0 r 25:16 vc specifies total number of lines within one vertical cycle. vc = vertical cycle time (ms) / horizontal cycle time (ms) 0x107 r/w 15:0 ? wired to zero 0 r horizontal synchronous pulse width register (hswr) bit 31 23 22 16 15 0 name ? hsw ? bit name function reset value r/w 31:23 ? wired to zero 0 r 22:16 hsw specifies the horizontal sync signal pulse width using the number of dot clocks. 0x11 r/w 15:0 ? wired to zero 0 r
chapter 3 graphics display controller (gdc) 3 - 16 vertical synchronous pulse width register (vswr) bit 31 21 20 16 15 0 name ? vsw ? bit name function reset value r/w 31:21 ? wired to zero 0 r 20:16 vsw specifies the vertical sync signal pulse width using the number of lines. 0x03 r/w 15:0 ? wired to zero 0 r vertical di splay start register (vdsr) for layers a/e, b and c bit 31 22 21 16 15 0 name ? vds ? bit name function reset value r/w 31:21 ? wired to zero 0 r 21:16 vds these bits specify the vertical display start position using the number of lines, start ing from the vsync * signal falling edge. 0x04 r/w 15:0 ? wired to zero 0 r note: the lowest value allowed for vds is 2 hex . vertical display start register (vdsrd) for layer d bit 31 26 25 16 15 0 name ? vdsd ? bit name function reset value r /w 31:26 ? wired to zero 0 r 25:16 vdsd these bits specify the vertical display start position using the number of lines, starting from the vsync * signal falling edge. 0x0f6 r/w 15:0 ? wired to zero 0 r note: the lowest value allowed for vdsd is 2 hex .
chapter 3 graphics display controller (gdc) 3 - 17 vertical display end register (vder) for layers a/e, b and c bit 31 26 25 16 15 0 name ? vde ? bit name function reset value r/w 31:26 ? wired to zero 0 r 25:16 vde these specify the vertical display end position using the number of lines, starting from the vsync * signal falling edge. number of display period lines = vde - vds 0x0f6 r/w 15:0 ? wired to zero 0 r note: the lowest value allowed for vde is 2 hex . vertical display end register (vderd) for layer d bit 31 26 25 16 15 0 name ? vded ? bit name function reset value r/w 31:26 ? wired to zero 0 r 25:16 vded these specify the vertical display end position using the number of lines, starting from the vsync * signal falling edge. number of display period lines = vded ? vdsd 0x0f6 r/w 15:0 ? wired to zero 0 r note: the lowest value allowed for vded is 2 hex .
chapter 3 graphics display controller (gdc) 3 - 18 3.4 setting example display characters: horizontal synchronous cycle is 64 sec/line, vertical synchronous cycle is 16.678 msec/screen. if dotclk = 3 mhz t dckps = 0x9, hc = 64 s 3 mhz = 192 dots, vc = 16.768 ms 1/64 s = 262 lines. when displaying a 160 - dot 225 - line (32 dots 32 lines for layer d) picture out of a 368 270 - frame, and the frame buffer is sdram, then sara=0xa0000000, (physical: 0x50000000) sarb=0 xa0400000, (physical: 0x50200000) sarc=0xa0800000, (physical: 0x50400000) sard=0xa0c00000, (physical: 0x50600000) mwra=0x5c, mwrb=0x5c, mwrc=0x2e, mwrd=0x0a. please note that the defined start addresses are logical addresses. the physical start addr ess is defined as the right shifted logical address and a zero as msb (see chapter 3.3 ?start address register? figur e 3.4 . 1 ). the following are example register settings while internal synchronizatio n signals hsync and vsync are used: htn = 0x05, htnd = 0x01, hds = 0x17, hde = 0xb7, hdsd = 0x37, hded = 0x57, hc = 0xc0, vc = 0x106, hsw = 0x0f, vsw = 0x04, vds = 0x1b, vde = 0xfc, vdsd = 0x3b, vded = 0x5b.
chapter 3 graphics display controller (gdc) 3 - 19 display area layer a, b or c frame buffer layer a, b or c frame buffer layer d display area layers a, b and c blanking area display area layer d dot 1 dot 64 dot 87 dot 192 dot 191 dot 32 line 1 line 27 line 59 line 91 line 252 line 262 display area layer a, b or c display area layer d hdser mwrd hdserd mwra, mwrb or mwrc display view memory view figur e 3.4 . 1 picture composition from frame buffer to display using example register settings
chapter 3 graphics display controller (gdc) 3 - 20 d1 d2 d3 dn dn-2 horizontal invalid data period horizontal invalid data period hsw = 15 hds (23) + 9 = 32 hde(183) + 8 = 191 htn(5) 32 = 160 hc = 192 dot clock hsync hdisp display data l1 l2 l3 ln ln-1 vertical invalid data period vertical invalid data period vsw = 4 vds = 27 vde = 252 vc = 262 hsync vsync display data 1 15 32 191 192 4 1 27+15 252 262 hde ? hds = 160 vde - vds = 225 dn-1 vdisp figure 3.4 . 2 display signals using inte rnal dot clock and internal sync signals; signals hdisp and vdisp show active display area in horizontal and vertical direction respectively (note that vdisp is an internal signal only)
chapter 3 graphics display controller (gdc) 3 - 21 the following are example register settings while external synch ronization signals hsync and vsync are used: same as internal synchronization signals: htn = 0x05, htnd = 0x01, vds = 0x1b, vde = 0xfc, vdsd = 0x3b, vded = 0x5b. different from settings using internal synchronization signals: hds = 0x14, hde = 0x b4, hdsd = 0x34, hded = 0x54. not relevant registers: hc, vc, hsw, vsw. the display shows the same picture with the selected external synchronization signals hsync and vsync as in case of internal synchronization signal described before.
chapter 3 graphics display controller (gdc) 3 - 22 vds = 27 vde = 252 vde - vds = 225 d1 d2 d3 dn dn-1 horizontal invalid data period horizontal invalid data period hds (19) + 9 = 32 hde(179) + 8 = 191 htn(5) x 32 = 160 dot clock external hsync hdisp display data l1 l2 l3 ln ln-1 vertical invalid data period vertical invalid data period vertical cycle time = 16,768 ms hsync external vsync display data 1 16 32 191 192 4 1 27+15 252 262 hde ? hds = 160 internal vsync internal hsync 4 horizontal cycle time = 64 s vdisp figure 3.4 . 3 display signals using internal dot clock and external sync signals (note that vdisp is an internal signal only)
chapter 4 interrupt controller (intc) 4 - 1 4. interrupt controller (intc) the interrupt controller has the following purpose: show the cause of an interrupt make it possible for software to mask all interrupts, except the nmi handle 3 external interrupt pins handle non - maskable - interrupt (nmi) 4.1 basic interrupt handling the following list shows the basic steps of an interrupt handler: 1. change status register of cpu to inhibit interrupts with equal or lesser priority. 2. read cause register of cpu to get cause of interrupt. (see also table below) 3. read irqr o f interrupt controller to get more information about interrupt source. 4. run interrupt routine. 5. reset interrupt in source. 6. reset bit of interrupt source in irqr of interrupt controller. 7. restore status register of cpu and jump back to program. the following table shows all interrupt sources and the corresponding interrupt pin on the cpu: interrupt source interrupt pin of cpu interrupt source interrupt pin of cpu external interrupt 0 int2 dmac int2 external interrupt 1 int3 gdc int2 external interrupt 2 int3 port int4 pwm timer int1 txcan int4 periodic timer 0 int0 txsei int4 periodic timer 1 int1 uart int5
chapter 4 interrupt controller (intc) 4 - 2 4.2 registers register overview name phys. address (hex) function irqr 1c04 0000 indicates interrupt sources imaskr 1c04 0004 enables/ disab les interrupts ilext 1c04 0008 edge/ level detection of external interrupts interrupt request register (irqr), interrupt mask register (imaskr) irqr : if an interrupt occurs, the corresponding bit is set to 1. writing 0 to a bit resets the contents. writing 1 to a bit does not change the contents. imaskr : 1 = enables interrupt 0 = disables interrupt (an incoming interrupt will be stored in irqr, but no interrupt request will be sent to cpu) bit 31 30 29 28 27 26 25 24 name ext2 ext1 ext0 gdc d mac1 dmac0 t1 t0 bit 23 22 21 20 19 18 17 16 name mpwm (1) seiexc can1exc can0exc sio3exc sio2exc sio1exc sio0exc bit 15 14 13 12 11 10 9 8 name pwm port seitx seirx can1tx can1rx can0tx can0rx bit 7 6 5 4 3 2 1 0 name sio3tx sio3rx sio2tx sio2rx sio1tx sio1rx sio0tx sio0rx (1) only in imaskr, in irqr this bit is wired to zero bit name cause of interrupt reset value r/w 31 ext2 external interrupt 2 0 r/w 30 ext1 external interrupt 1 0 r/w 29 ext0 external interrupt 0 0 r/w 28 gdc vertical o r horizontal sync. on gdc 0 r/w 27 dmac0 dma on channel 0 finished or error on channel 0 0 r/w 26 dmac1 dma on channel 1 finished or error on channel 1 0 r/w 25 t1 periodic timer 1 0 r/w 24 t0 periodic timer 0 0 r/w 23 mpwm overflow on pwm timer enabl e (only in imaskr, in irqr this bit is wired to zero) 0 r/w 22 sei exc exception during txsei transfer 0 r/w 21 can1 exc status change in txcan1 0 r/w 20 can0 exc status change in txcan0 0 r/w 19 sio3 exc exception during serial i/o on uart channel 3 0 r/w 18 sio2 exc exception during serial i/o on uart channel 2 0 r/w 17 sio1 exc exception during serial i/o on uart channel 1 0 r/w 16 sio0 exc exception during serial i/o on uart channel 0 0 r/w
chapter 4 interrupt controller (intc) 4 - 3 bit name cause of interrupt reset value r/w 15 pwm p wm counter reached compare value or overflow of pwm counter if enabled by bit 23 of imaskr 0 r/w 14 port interrupt from port module 0 r/w 13 sei tx transmission on txsei finished 0 r/w 12 sei rx reception on txsei finished 0 r/w 11 can1 tx transmissio n on txcan1 finished 0 r/w 10 can1 rx reception on txcan1 finished 0 r/w 9 can0 tx transmission on txcan0 finished 0 r/w 8 can0 rx reception on txcan0 finished 0 r/w 7 sio3 tx transmission on uart channel 3 finished 0 r/w 6 sio3 rx reception on uart c hannel 3 finished 0 r/w 5 sio2 tx transmission on uart channel 2 finished 0 r/w 4 sio2 rx reception on uart channel 2 finished 0 r/w 3 sio1 tx transmission on uart channel 1 finished 0 r/w 2 sio1 rx reception on uart channel 1 finished 0 r/w 1 sio0 tx transmission on uart channel 0 finished 0 r/w 0 sio0 rx reception on uart channel 0 finished 0 r/w ilext the register ilext controls edge or level detection of all external interrupt pins. when edge detection is enabled, an interrupt is caused on fall ing edge. when level detection is enabled, an interrupt is caused on low level. on level detection the bits in irqr show the current level of the external interrupt pin. before you can clear the interrupt, the external interrupt signal must be set to 1. bit 31 30 29 28 27 0 name ? lext2 lext1 lext0 ? bit name function reset value r/w 31 ? wired to zero 0 r 30 lext2 0 = edge detection on external interrupt 2 (falling edge) 1 = level detection on external interrupt 2 (low level) 0 r/w 29 lext1 0 = edge detection on external interrupt 1 (falling edge) 1 = level detection on external interrupt 1 (low level) 0 r/w 28 lext0 0 = edge detection on external interrupt 0 (falling edge) 1 = level detection on external interrupt 0 (low level) 0 r/w 27:0 ? wired to zero 0 r
chapter 4 interrupt controller (intc) 4 - 4 4.3 non maskable interrupt the TMPR3916F generates a non - maskable interrupt exception of the transition from high to low of the nmi* signal. to generate the next non - maskable interrupt exception, the nmi* signal must be set to high again a nd then to low. the tx39 core completes the current bus operation, before it acknowledges the non - maskable interrupt exception. when the tx39 is not owner of the bus at the moment, the non - maskable interrupt occurs, the non - maskable interrupt must wait un til tx39 regains the busmastership.
chapter 5 timer 5 - 1 5. timer the timer module contains the following features: two periodic timers with variable intervals a pwm timer with variable interval / pulse width (pwm = pulse width modulation) 5.1 pwm timer the pwm timer contains a 16 bit counter. the timer module sends a n interrupt, when the counter reaches a programmable compare value. in addition an interrupt can be sent on the overflow of the counter, if the bit 23 (mpwm) of imaskr in the interrupt controller is set. the pwm counter starts after the bit 15 (pwm) of ima skr in the interrupt controller is set. setting bit 15 of imaskr to 0 will clear the pwm counter. ff mux f / 2 pwmpre[2:0] 16 bit counter en comparator pwmval[15:0] programmable register f p mask ? mpwm irqr[15] -> 1 int[1] t1 int clr carry & mpwmcarry ff ff ff ff ff / 4 / 8 / 16 / 32 / 64 f t figure 5.1 . 1 block diagram for interrupt generation
chapter 5 timer 5 - 2 use the following formula to calculate the time between start of the pwm counter and send of pwm interrupt (pulse width): pwmval = compare value of pwm timer (see register description of pwmval) pwmval time to pwm interrupt = ------------------------ 1 / prescaler system freq uency use the following formula to calculate the time between start and overflow of the pwm counter: 65536 time to pwm interrupt = ------------------------ 1 / prescaler system frequency register overview name phys. address (hex) function pwmva l 1c01 0008 compare value for 16 bit pwm counter pwm value register (pwmval) bit 31 16 15 3 2 1 0 name pwmval ? pwmpre bit name function reset value r/w 31:16 pwmval compare value of pwm counter if the pwm counter reaches the value of this r egister an interrupt is generated. 0x007f r/w 15:3 ? wired to zero 0 r 2:0 pwmpre prescaler of pwm counter the following clock is used to provide pwm counter: 000 = 1/2 system clock 001 = 1/4 system clock 010 = 1/8 system clock 011 = 1/16 system clock 10 0 = 1/32 system clock 101,110,111 = 1/64 system clock 101 r/w
chapter 5 timer 5 - 3 5.2 periodic timers both periodic timers are running all the time. every time they reach the end of the interval, they cause an interrupt. the interrupt is maskable in the interrupt controller ( intc). both periodic timers use the same prescaler. use the following formula to calculate the interval: t0int = interval settings of periodic timer 0 (see register description of titr) t1int = interval settings of periodic timer 1 (see register descript ion of titr) 2 (t0int + 8) interval of timer 0 = ------------------------ 1 / prescaler system frequency 2 (t1int + 9) interval of timer 1 = ------------------------ 1 / prescaler system frequency note that at the same settings timer 0 has tw ice the speed of timer 1. example: t0int = interval setting of periodic timer 0 = 010 (bin) = 2 (dec) tpre = prescaler setting = 100 (bin) t prescaler = 1 / 32 (dec) 2 (2 + 8) 32768 interval of timer 0 = -------------- 32 = ------------ = 0.55 msec 60 mhz 60 mhz register overview name phys. address (hex) function timer 1c01 0000 16 bit free - running counter titr 1c01 0004 settings for periodic timer timer register bit 31 16 15 0 name t ? bit name function reset value r/w 3 1:16 t free running counter the free running counter provides the periodic timers. the counter runs all time on output clock of the prescaler (bits [2:0] of titr) 0x0000 r/w 15:0 - wired to zero 0x0000 r
chapter 5 timer 5 - 4 titr bit 31 27 26 25 24 23 19 18 17 16 name ? t1int ? t0int bit 15 3 2 1 0 name ? tpre bit name function reset value r/w 31:27 ? wired to zero 0 r 26:24 t1int interval of periodic timer 1 for interval calculation see above formula 000 r/w 23:19 ? wired to zero 0 r 18:16 t0int interva l of periodic timer 0 for interval calculation see above formula 000 r/w 15:3 ? wired to zero 0 r 2:0 tpre prescaler for timer 0 and timer 1 the following clock is used to provide the periodic timer: 000 = 1/2 system clock 001 = 1/4 system clock 010 = 1/ 8 system clock 011 = 1/16 system clock 100 = 1/32 system clock 101, 110, 111 = 1/64 system clock 101 r/w
chapter 6 direct memory access controller (dmac) 6 - 1 6. direct memory access controller (dmac) the purpose of the direct memory access controller (dmac) is to accelerate system speed and to make it easier for software to transfer data between memory and peripheral devices. the dma controller contains the follow ing features : the dmac consists of two independent channels: channel 0 and channel 1. channel 0 has higher priority than channel 1 on gbus transfers. dma transactions are only possible from device to memory or from memory to device . devices are for exampl e uart and txsei. the dma transfer will start after request of a peripheral device. that?s why only data transfer will happen, when the device needs data. the uarts, the txsei or an external device can send a request. on the end of a transaction or at the occurrence of an error an interrupt will be caused. the interrupt is only maskable in the interrupt controller (intc). the following sequence shows the principle use of the dma controller to transfer data between memory and a peripheral device: 1. configure the dma and the peripheral device. set the number of bytes to be transferred. 2. the dma controller waits for a request of the peripheral device. 3. the dma controller transfers data between memory and the peripheral device. 4. the dma controller sends an acknowle dge to the peripheral device. 5. if there are more bytes left to transfer go to point 2. 6. the dma controller causes an interrupt.
chapter 6 direct memory access controller (dmac) 6 - 2 6.1 programming the dma controller the programming of both channels are done in the same way. all register values are given in hexad ecimal format. 6.1.1 start dma transaction between memory and txsei/ uart the dma transaction between memory and txsei/ uart is the main application of the dma controller. these transactions are only possible as 32 - bit word transfers . one data piece fills the l ower bits of the memory word. for example : the bytes 0x6e and 0x37 shall be transmitted over the uart. first these bytes have to be stored in bits [7:0] of the words in the memory. the first word in the memory is then 0x0000006e and the second word is 0x0 0000037. in case of a receive, the data will be stored in the memory in the same way. the rest of the word (higher bits) will be filled with a random value. execute the following steps to start a dma transaction: 1. write the table value in bits [3:0] of th e chip configuration register (ccr) for channel 0 : bits [7:4] of the chip configuration register (ccr) for channel 1 : device memory >> device (transmit) device >> memory (receive) sio 0 0x0 0x1 sio 1 0x2 0x3 sio 2 0x4 0x5 sio 3 0x6 0x7 txsei 0x8 0x 9 2. memory >> device: write the start pointer of your sending data into the source address register (sar). write the address of the device data register into the destination address register (dar). device >> memory: write the address of the device data register into the source address register (sar). write the start pointer of your receiving data into the destination address register (dar). note : you must write the physical addresses into the registers sar and dar. all addresses have to be word aligne d. 3. write the number of bytes you want to transfer into the byte count register (bcr). note : the dma controller transfers a 32 - bit word in every step. that?s why the byte count must be at least 4. in addition, the contents of the byte count register must b e a multiple of 4.
chapter 6 direct memory access controller (dmac) 6 - 3 4. memory >> device: write the value 0xa9 into the operation definition register (odr). device >> memory: write the value 0x69 into the operation definition register (odr). write the value 0x11 into the channel control register (ccr). no w the dma controller waits for a request of the external device to start the first transfer. 5. configure and start the devices txsei or uart. after dma transaction has finished, the dma controller sets the opc bit (bit 0) in the channel status register (csr ) and generates an interrupt. each channel has its own interrupt signal. the interrupts are only maskable in the interrupt controller. to terminate a running dma transaction, set bit 22 (abt) in the channel control register (ccr). 6.1.2 start dma with external device the capricorn2 has one pin for an external dma request signal. for instance the external request makes sense together with a port module. the procedure is similar to a uart/ txsei transaction. for details of the procedure see section ?start dma tra nsaction between memory and txsei/uart? and the register description. the following steps are executed to start a dma transaction: 1. write the hexadecimal - value 0xa in bits [3:0] of the chip configuration register (ccr) for channel 0 bits [7:4] of the chip configuration register (ccr) for channel 1 2. define source and destination address in registers sar and dar. 3. write the number of bytes you want to transfer into bcr. 4. write the following value into odr: application memory >> device (transmit) device >> mem ory (receive) edge detection on external request 0xa8 0x68 level detection on external request 0xa9 0x69 write the following value into ccr: application memory >> device (transmit) device >> memory (receive) positive logic on external request 0x19 0x1 9 negative logic on external request 0x11 0x11 now the dma controller waits for a request of the external device to start the first transfer. 5. configure and start external device. when the dma controller starts its first transfer, it sets the external a cknowledge signal to 0. after finishing the whole dma transaction, the dma controller sets the external acknowledge signal to 1.
chapter 6 direct memory access controller (dmac) 6 - 4 6.1.3 what to do, when errors occur one of the following reasons can be responsible for an error: the software has made invalid sett ings in the operation definition register (odr) or in the channel control register (ccr). the software has defined an address in the source or destination address register (sar or dar), that does not exist. the access to this address has caused a bus error . either the byte count, the source address or the destination address is not correct aligned. the dma controller sends an interrupt, when an error occurs. these steps need to be executed in case of an error: 1. read the contents of the channel error regist er (cer) to get the cause of the error. 2. for details see the register description. 3. write 0x80 into the channel control register (ccr). 4. write 0x00 into the channel status register (csr). 5. start the whole dma programming procedure from the first point.
chapter 6 direct memory access controller (dmac) 6 - 5 6.2 re gisters overview: register (short name) physical address (hex) name function odr0 odr1 1c060000 1c060010 operation definition register basic channel settings ccr0 ccr1 1c060001 1c060011 channel control register controls channel operations cer0 cer1 1c0 60002 1c060012 channel error register cause of an error or interrupt csr0 csr1 1c060003 1c060013 channel status resister channel operating status sar0 sar1 1c060004 1c060014 source address register specifies the address, where to get data from dar0 dar1 1c060008 1c060018 destination address register specifies the address, where to write data to bcr0 bcr1 1c06000c 1c06001c byte count register specifies the number of transfer data in byte units operation definition register (odr) bit 31 30 29 28 27 2 6 25 24 name sac dac psiz osiz msiz bst bit name function reset value r/w 31 sac specifies, if the source address register should count up. 0 = source address does not count up (device to memory transfer) 1 = source address counts up on each transfer (memory to device transfer) this bit should be set to 0, when the dac bit is set to 1. 0 r/w 30 dac specifies, if the destination address register should count up. 0 = destination address does not count up (memory to device transfer) 1 = source address co unts up on each transfer (device to memory transfer) this bit should be set to 0, when the sac bit is set to 1. 0 r/w 29:28 psiz specifies the size of the device data register. 00 = 8 bits, register bits [31:24] 01 = 16 bits, register bits [31:16] 10 = 3 2 bits, register bits [31:0] 11 = setting prohibited 00 r/w 27:26 osiz specifies the width of dma transfer. 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = setting prohibited 00 r/w 25 msiz specifies the bus width of the memory. 0 = 32 bits 1 = 16 bits (t here is no use for this setting) 0 r/w 24 bst specifies the detection mode for the request signal from the device. 0 = edge detection 1 = level detection for uart and txsei request signals you must use level detection. 0 r/w
chapter 6 direct memory access controller (dmac) 6 - 6 channel control register (cc r) bit 23 22 21 20 19 18 17 16 name rst abt ? cen rpl ? ? ete bit name function reset value r/w 23 rst performs a software reset on all of the channel registers. 0 = normal operation 1 = executes software reset 0 r/w 22 abt termination of channel op erations regardless of the operating status. 0 = normal operation 1 = termination of current dma transaction 0 r/w 21 ? unused 0 r/w 20 cen sets the channel to operating mode. 0 = channel is inactive 1 = start dma transaction 0 r/w 19 rpl specifies the polarity of the device request signal. 0 = negative logic (low level / falling edge) 1 = positive logic (high level / rising edge) uart and txsei use negative logic. 0 r/w 18:17 ? wired to zero 00 r 16 ete decides if the request signal from a device is p rovided to the dmac. 0 = no request signal is provided to the dmac 1 = request signal is provided to the dmac without setting this bit to 1, the dma controller does not start a transaction. 0 r/w channel error register (cer) bit 15 14 13 12 11 10 9 8 name swa ber ace conf sbe dbe bce aer bit name function reset value r/w 15 swa software abort: if this bit is set to 1, the software has terminated the current dma transaction 0 r 14 ber bus error: if this bit is set to 1, a bus error has occurred on dma transfer. 0 r 13 ace address or count error: (ace = bce + aer) if this bit is set to 1, a byte count error (bce, bit 9) or an address boundary error (aer, bit 8) has occurred. 0 r 12 conf configuration error: if this bit is set to 1, the software has made invalid settings in the operation definition register (odr) or in the channel control register (ccr). 0 r 11 sbe bus error on source address access: if this bit is set to 1, a bus error has occurred during read from a source. 0 r 10 dbe bus error o n destination address access: if this bit is set to 1, a bus error has occurred during write to a destination. 0 r
chapter 6 direct memory access controller (dmac) 6 - 7 bit name function reset value r/w 9 bce byte count error: if this bit is set to 1, the software has stored a value in the byte count reg ister, which is not correct aligned. for example: when the dma controller transfers 32 bit words, it must be possible to divide the contents of the byte count register by 4. 0 r 8 aer address error: if this bit is set to 1, the software has stored a value in the source - or destination address register, which is not correct aligned. for example: when the dma controller transfers 32 bit words, the lower two bits of the source - and the destination address register must be zero. 0 r channel status register (csr) bit 7 6 5 4 3 2 1 0 name ? ? ? ? ? act exc opc bit name function reset value r/w 7:3 ? wired to zero 0 r 2 act channel operation status if this bit is set to 1, the channel is executing a dma. 0 r 1 exc exception if this bit is set to 1, an e rror has occurred during dma transfer. the cause of error is shown in the channel error register (cer). you can delete the exception by writing 0 to this bit. writing 1 to this bit shows no effect. 0 r/w 0 opc operation successful completed if this bit is set to 1, the dma transaction has finished without any errors. 1 r source address register (sar) bit 31 24 23 0 name sal sac bit name function reset value r/w 31:24 sal base address this part of the source address will not count up. 0 r/w 23:0 sac address offset this part of the source address will count up on every read, when the dma controller transfers data from memory to a peripheral device. 0 r/w
chapter 6 direct memory access controller (dmac) 6 - 8 destination address register (dar) bit 31 24 23 0 name dal dac bit name function reset value r/w 31:24 dal base address this part of the destination address will not count up. 0 r/w 23:0 dac address offset this part of the destination address will count up on every write, when the dma controller transfers data from a periphe ral device to the memory. 0 r/w byte count register (bcr) bit 31 24 23 0 name ? bc bit name function reset value r/w 31:24 ? unused 0 r 23:0 bc these bits contain the number of bytes left to transfer. the dma controller decrements the con tents of this register after every transfer. 0 r/w
chapter 7 can module (txcan) 7 - 1 7. can module (txcan) outline and features of txcan: 2.0 b active standard identifier and remote frames extended identifier and remote frames full - can controller 16 mailboxes (15 receive & transmit + 1 receive - only) baud rate up to 1mbit/sec on the can bus at minimum 8 mhz system clock extended prescaler bit timing parameter like intel 82527? selectable mechanism for internal arbitration of transmit messages time - stamp for receive and transmit messages readable error counters warning level irq, error passive irq, bus - off irq local loop back test mode (self acknowledge) programmable glob al mask for mailboxes 0 - 14 programmable local mask for mailbox 15 acceptance mask register for identifier extension bit flexible interrupt structure flexible status interface sleep mode halt mode wake - up on can - bus activity or mcu access
chapter 7 can module (txcan) 7 - 2 7.1 block diagram register bank & interrupt logic can protocol controller txcan state machine mcu interface & access arbiter mailbox ram 16 * 128 temporary transmit buffer acceptance filter time stamp counter reset controller, clock & sleep logic address / data control signals goes to the whole design rx / tx control add / data clock / reset txcan temporary receive buffer figure 7.1 . 1 block diagram can module 7.1.1 message buffers the message storage is implemented in a single - port ram, which can be addressed by the inner can core and the mcu. the mcu cont rols the can controller by modifying the various mailboxes in the ram or the configuration registers. in order to initiate a transfer, the transmission request bit has to be set in the corresponding register. afterwards the entire transmission procedure a nd possible error handling is done without any mcu involvement. if a mailbox has been configured as receive the mcu reads the mailbox data using mcu read instructions. the mailbox can be configured to interrupt the mcu after every successful message transm ission or reception. the mailbox module provides 16 mailboxes of 8 - byte data length, 29 bit identifier and several control bits. each mailbox can be configured as either transmit or receive, except for mailbox 15. this mailbox is a receive - only buffer wit h a special acceptance mask designed to select groups of message identifiers to be received. the mailbox area is implemented in a single - port - ram. 7.1.2 electrical can - interface the interface to the can bus is a simple two - wire line consisting of an input pin rx and an output pin tx. the pins are thought to operate with can bus transceivers according to iso/dis 11989 (e.g. philips pca 82c252, bosch cf150 or siliconix si 9200).
chapter 7 can module (txcan) 7 - 3 7.2 txcan registers txcan local memory map physical base address channel 1 = 1c07 0000 (hex) physical base address channel 2 = 1c07 8000 (hex) offset address name description 0x000 dpram mailbox ram (mailbox 0) : 0x0f0 dpram mailbox ram (mailbox 15) 0x100 mc mailbox configuration register 0x104 md mailbox direction register 0x108 tr s transmit request set register 0x10c trr transmit request reset register 0x110 ta transmission acknowledge register 0x114 aa abort acknowledge register 0x118 rmp receive message pending register 0x11c rml receive message lost register 0x120 lam loca l acceptance mask register 0x124 gam global acceptance mask register 0x128 mcr master control register 0x12c gsr global status register 0x130 bcr1 bit configuration register 1 0x134 bcr2 bit configuration register 2 0x138 gif global interrupt flag re gister 0x13c gim global interrupt mask register 0x140 mbtif mailbox transmit interrupt flag register 0x144 mbrif mailbox receive interrupt flag register 0x148 mbim mailbox interrupt mask register 0x14c cdr change data request 0x150 rfp remote frame p ending register 0x154 cec can error counter register 0x158 tsp time stamp counter prescaler 0x15c tsc time stamp counter
chapter 7 can module (txcan) 7 - 4 7.2.1 mailbox structure the following picture shows the structure of the mailbox ram: id0 id1 id2 id3 tsv1 tsv0 mcf d0 d1 d2 d3 d7 d6 d5 d4 0 7 8 15 16 24 23 31 id0 id1 id2 id3 tsv1 tsv0 mcf d0 d1 d2 d3 d7 d6 d5 d4 address 0x000 0x004 0x008 0x00c 0x0f0 0x0f4 0x0f8 0x0fc mailbox 0 mailbox 15 byte 0 byte 1 byte 2 byte 3 halfword 0 halfword 1 word figure 7.2 . 1 mailbox ram structure each mailbox consists of 16 bytes. the first 4 bytes id0 to id3 contain the identifier. byte 4 (mcf) contains the message control field and byte 5 is unused. byte 6 and 7 are reserved for the time stamp value tsv of an implemented free running counter that indicates when a message was received or transmitted. the data field consists of the bytes d0 to d7. one mailbox includes the following data: the 29 bit identifier, 11 bit base id and 18 bit extended id (id0 - id3) the identifier extension bit (ide) (id3, bit7) the global (local) acceptance mask enable bit game (lame) (id3, bit6) the remote frame handling bit rfh (id3, bit5) the remote transmission request bit (rtr) (mcf, bit4) the data length code (dlc) (mcf, bit0 - 3) up to eight bytes for the data field (d0 - d7) two bytes for the time stamp value (tsv)
chapter 7 can module (txcan) 7 - 5 message identifier (id0 .. id3) bit 31 30 29 28 18 17 0 name ide game rfh id bit name function 31 ide kind of frame (length of identi fier) 0 = standard frames (can 2.0a), 11 bit identifier 1 = extended frames (can 2.0b), 29 bit identifier 30 game use of global acceptance mask (mailbox 0 to 14) 0 = the received message will only be stored, when the received identifier is identically to that in the mailbox. 1 = the global acceptance mask will be used for acceptance filtering. the bit 30 of mailbox 15 is called lame and determines, if the local acceptance mask will be used for acceptance filtering. 29 rfh remote frame handling (only for t ransmit mailboxes) 0 = software must handle remote frames 1 = the mailbox will automatically response to remote frames 28:18 id identifier contains standard identifier or first bits of extended identifier 17:0 id identifier contains the last bits of exte nded identifier message control field (mcf) bit 31 5 4 3 2 1 0 name ? rtr dlc bit name function 31:5 ? no function 4 rtr remote frame 0 = normal frame 1 = remote frame 3:0 dlc data length these bits contain the number of data bytes transfer red by the frame. only the values 0000(bin) to 1000(bin) are allowed. if these bits are set to 1001(bin) or more, the txcan will send 8 data bytes.
chapter 7 can module (txcan) 7 - 6 7.2.2 control registers mailbox configuration register (mc) bit 15 0 name mc bit name function re set value mode 15:0 mc mailbox enable 0 = the corresponding mailbox mbn is disabled for the can module and the write access to the identifier field of the mailbox is possible. 1 = the mailbox is enabled for the txcan state machine. write access to the id entifier field of an enabled mailbox is denied. write access to the data field and control field of a mailbox is always possible. after power - up, all bits in mc are cleared and all mailboxes are disabled. 0 r/w mailbox direction register (md) bit 15 14 0 name md15 md0 .. md14 bit name function reset value mode 15 md15 mailbox direction of mailbox 15 mailbox 15 is receive - only. this bit is always 1 and can not be changed. 1 r 14:0 md0 to md14 mailbox direction of mailboxes 0 to 14 each mai lbox can be configured as transmit mailbox or receive mailbox. 0 = transmit mailbox 1 = receive mailbox 0 r/w
chapter 7 can module (txcan) 7 - 7 7.2.3 message transmission the transmission control consists of two registers. one register for setting (trs) and one for resetting (trr) the transmi ssion request. in this manner it is possible to clear the transmission request without generating a conflict in the handling of the transmit mailboxes in the state - machine. this mechanism also prevents the clearing of the transmission request of a mailbox which transmission is already in progress. the data to be transmitted will be stored in a mailbox configured as transmit mailbox (mdn = 0). after writing the data and the identifier into the mailbox ram, the message will be sent if the corresponding trs b it has been set and the mailbox is enabled (mcn = 1). if there is more than one mailbox configured as transmission mailbox and more than one corresponding trs is set, then the messages will be sent in the selected order. the order of transmission can be s elected in the master control register (mcr). if mtos is set to ?0?, the mailbox with the lower number has the higher priority. for example: if the mailboxes mb0, mb2 and mb5 are configured for transmission and the corresponding trs bits are set, then the messages will be transmitted in the following order: mb0, mb2 and mb5. if a new transmission request is set for mb0 during the processing of mb2 then in the next internal arbitration - run mb0 will be selected for the next transmission. this will also happe n, when the txcan loses arbitration while transmitting mb2. in this case, mb0 will be sent at the next opportunity instead of mb2. if mtos is set to ?1?, the priority of the identifier stored in the mailbox will determine the sending order. the mailbox wi th the higher priority identifier will be sent first. in case of a lost arbitration on the can bus line a new internal arbitration run will be started and the message with the highest priority will be sent at the next possible time. transmission request set register (trs) bit 15 14 0 name ? trs bit name function reset value mode 15 ? wired to zero 0 r 14:0 trs setting trsn causes the particular message ?n? to be transmitted. several bits can be set simultaneously. the messages will be sen t one after the other in the selected transmission order. the transmission order can be selected by the mtos bit in the master control register (mcr). the bits in trs will be set by writing ?1? at the corresponding bit position from the mcu. writing a ?0? has no effect. after power - up, all bits are cleared. 0 r/s the trs bits can only be set by the mcu and will be reset by internal logic in case of a successful transmission or an aborted transmission (if requested by setting the corresponding trr bit) or a hard/software reset. bit 15 is not implemented because the mailbox 15 is the receive - only mailbox. if a mailbox is configured as receive the corresponding bit in trs can not be set by mcu.
chapter 7 can module (txcan) 7 - 8 transmission request reset register (trr) bit 15 14 0 name ? trr bit name function reset value mode 15 ? wired to zero 0 r 14:0 trr setting trrn causes a transmission request to be cancelled that was initiated by the corresponding bit trsn, provided that, the transmission of this mailbox is not currentl y in process. if the corresponding message is currently processed the bit will be reset in the following cases: a successful transmission (normal operation), an aborted transmission in case of a lost arbitration or an error condition detected on the can bu s line. in case of an aborted transmission, the corresponding status bit aan will be set and in case of a successful transmission, the status bit tan will be set. the bits in trr will be set by writing a ?1? from the mcu. writing a ?0? has no effect. afte r power - up, all bits are cleared. 0 r/s these bits can only be set by the mcu and reset by the internal logic. they will be reset by internal logic in case of a successful transmission or an aborted transmission. bit 15 is not implemented because the mai lbox 15 is the receive - only mailbox. if trrn is set the write access to the corresponding mailbox is denied. if a mailbox is configured as receive the corresponding bit in trr can not be set by mcu. note: when trsn is set, after setting trrn to ?1?: a tra nsmission request of a message, which is not currently in process, will be cleared immediately (trsn ? 0, trrn ? 0, aan ? 1). a transmission request of a message which is currently processed will be cleared in case of a lost arbitration or an error conditi on on the can bus (trsn ? 0, trr ? 0, aan ? 1). a transmission request of a message which is currently processed will not be cleared if there is no lost arbitration and no error condition on the can bus (trsn ? 0, trrn ? 0, tan ? 1). transmission acknow ledge register (ta) bit 15 14 0 name ? ta bit name function reset value mode 15 ? wired to zero 0 r 14:0 ta if the message of mailbox ?n? has been transmitted successfully, the bit ?n? of this register will be set and a transmission success ful interrupt is generated, if it is enabled. the bits in ta will be reset by writing a ?1? from the mcu to ta or trs. writing a ?0? has no effect. after power - up, all bits are cleared. 0 r/c
chapter 7 can module (txcan) 7 - 9 abort acknowledge register (aa) bit 15 14 0 name ? aa bit name function reset value mode 15 ? wired to zero 0 r 14:0 aa if the transmission of the message in mailbox ?n? has been aborted, the bit ?n? of this register will be set and a transmission abort interrupt is generated, if it is enabled. the bi ts in aa will be reset by writing a ?1? from the mcu to aa or trs. writing a ?0? has no effect. after power - up, all bits are cleared. 0 r/c change data request (cdr) bit 15 14 0 name ? cdr bit name function reset value mode 15 ? wired to zero 0 r 14:0 cdr if the cdr bit of a transmit mailbox is set, a transmission request for this mailbox will be ignored. that means, that a mailbox with trs and cdr set will not be considered in the internal arbitration - run: the mailbox is locked for trans mission. the processing of this mailbox in the arbitration - run will be considered again after clearing the cdr bit. after power - up, all bits are cleared. 0 r/c cdr is useful for dealing with remote frames. it is intended for updating the data field of a transmit mailbox, which is configured for automatic reply to remote frames (rfh bit set). by using the cdr bit, the user can update the data field without a need of taking additional care of the data consistency. see also section "handling of message - obje cts".
chapter 7 can module (txcan) 7 - 10 7.2.4 message reception the identifier of each incoming message is compared to the identifiers held in the receive mailboxes. the comparison of the identifiers depends on the value of the global/local acceptance mask enable bit (game/lame) stored in the mailbox and the data held in the global/local acceptance mask (gam/lam). when a matching identifier is detected, the received identifier, the control bits and the data bytes are written into the matching ram location. at the same time the corresponding re ceive message pending bit rmpn is set and a receive - interrupt is generated, if it is enabled. after finding a matching identifier, no further compare will be done. if no match is detected, the message is rejected. the rmp bit has to be reset by the mcu aft er reading the data. if a second message has been received for this mailbox and the rmp bit is already set, the corresponding message lost bit (rml) is set. in this case, the stored message will be overwritten with the new data. only if an incoming messag e does not match to one of the mailboxes 0 to 14, this message will be stored in the receive - only mailbox in case of a matching identifier (acceptance filter). the following figure shows the timing of the flags and the write to the mailbox during message reception: s o f message 1 for mailbox ?n? can bus message is valid set rmp set rml copy id and data to mailbox rmpn register rmln register e o f i f s s o f message 2 for mailbox ?n? e o f i f s figure 7.2 . 2 timing for writing received message to mailbox, including flags
chapter 7 can module (txcan) 7 - 11 receive message pending register (rmp) bit 15 0 name rmp bit name functio n reset value mode 15:0 rmp if mailbox ?n? contains a received message, bit rmpn of this register will be set. these bits can only be reset by the mcu, and set by the internal logic. a new incoming message will overwrite the stored one. in this case, the corresponding status bit rmln will be set before overwriting begins. the bits in rmp and rml can be cleared by a write access to the register rmp with a ?1? at the corresponding bit location. after power - up, all bits are cleared. 0 r/c receive message l ost register (rml) bit 15 0 name rml bit name function reset value mode 15:0 rml if there is an overload condition for mailbox ?n?, bit rmln of this register will be set. these bits can only be reset by the mcu, and set by the internal logi c. the bits can be cleared by a write access to the register rmp with a ?1? at the corresponding bit location. after power - up, all bits are cleared. 0 r/c see also section "handling of message - objects".
chapter 7 can module (txcan) 7 - 12 7.2.5 remote frame handling if a remote frame has been r eceived, the internal fsm will compare the identifier to all identifiers of the mailboxes. the comparison of the identifiers depends on the value of the bit global/local acceptance mask enable (game/lame) stored in the mailbox and the data held in the glob al/local acceptance mask (gam/lam). if there is a matching identifier and the rfh bit in this mailbox is set and this mailbox is configured as transmit, this message object will be marked as ?to be sent? (trs will be set). if there is a matching identif ier and the mailbox is configured as receive, this message will be handled like a data frame and the corresponding bit in rmp and rfp will be set. after finding a matching identifier, no further compare will be done. remote frame pending register (rfp) bit 15 0 name rfp bit name function reset value mode 15:0 rfp if a remote frame is received in a mailbox configured as receive mailbox, the corresponding bits in rfpn and rmpn are set. the bits in rfp can be cleared by writing a ?1? to the corresponding bit position in rmp. writing a ?0? has no effect. if a remote frame in the mailbox is overwritten by a data frame, the corresponding bit in rfp is cleared. after power - up, all bits are cleared. 0 r/w see also section "handling of message - ob jects"
chapter 7 can module (txcan) 7 - 13 7.2.6 acceptance filtering for the mailboxes 0 to 14, the global acceptance mask (gam) will be used if the bit game in the mailbox is set. an incoming message will be stored in the first mailbox with a matching identifier. only if there is no matching i dentifier in the mailboxes 0 to 14, the incoming message will be compared to the receive - only mailbox (mailbox 15). if the lame bit in mailbox 15 is set, the local acceptance mask (lam) will be used. the acceptance code in the figure below is the content o f the identifier words of the current mailbox. amr 1 rxrqst identifier acceptance code register acceptance mask register acr 0 acr 0 amr 1 acr n amr n figure 7.2 . 3 acceptance filter logic local acceptance mask (lam) the local acceptance mask register will only be used for filterin g messages for mailbox 15. this feature allows the user to locally mask, or ?don?t care?, any identifier bits of the incoming message for mailbox 15. bit 31 30 29 28 0 name lami ? lam bit name function reset value mode 31 lami 0 = the identifi er extension bit stored in the mailbox determines which messages shall be received. 1 = don?t care: standard and extended frames can be received. in case of an extended frame all 29 bits of the identifier stored in the mailbox and all 29 bits of the local acceptance mask register will be used for the filter. in case of a standard frame, only the first eleven bits (bit 28 to 18) of the identifier and the local acceptance mask will be used. 0 r/w 30:29 ? wired to zero 0 r 28:0 lam incoming messages are firs t checked for an acceptance match in mailbox 0 to 14 before passing through the mailbox 15. a ?1? value means, ?don?t care? or accept a ?0? or ?1? for that bit position. a ?0? value means that the incoming bit value must match identically to the correspond ing bit in the message identifier. the global mask has no effect for mailbox 15. after power - up, all bits are cleared. 0 r/w for messages in extended format the identifier extension bit and the whole 29 bits of the identifier will be compared and for mes sages in standard format only the first 11 bits and the identifier extension bit will be compared. the local acceptance mask will only be used for mailbox 15 (receive - only mailbox).
chapter 7 can module (txcan) 7 - 14 global acceptance mask (gam) bit 31 30 29 28 0 name gami ? gam bit name function reset value mode 31 gami 0 = the identifier extension bit stored in the mailbox determines which messages shall be received. 1 = don?t care, standard and extended frames can be received. in case of an extended frame all 29 bits of the identifier stored in the mailbox and all 29 bits of the global acceptance mask register will be used for the filter. in case of a standard frame, only the first eleven bits (bit 28 to 18) of the identifier and the global acceptance mask will be used. 0 r/ w 30:29 ? wired to zero 0 r 28:0 gam for each incoming message, the global acceptance mask will be used if the bit game is set. a received message will only be stored in the first mailbox with a matching identifier. 0 r/w the global acceptance mask wil l only be used for the mailboxes 0 to 14. after power - up, all bits are cleared. master control register (mcr) bit 15 14 13 12 11 10 9 8 name ? sur intlb tstlb tsterr bit 7 6 5 4 3 2 1 0 name ccr smr hmr wuba mtos ? tscc sres bit name function r eset value mode 15:12 ? wired to zero 0 r 11 sur suspend mode request 0 = normal operation requested 1 = suspend mode is requested 0 r/w 10 intlb internal loop back enable 0 = internal loop back is disabled in test mode 1 = internal loop back is enabled in test mode 0 r/w 9 tstlb test loop back 0 = normal operation requested 1 = test loop back mode is requested. this mode supports stand - alone operation. 0 r/w 8 tsterr test error 0 = normal operation requested 1 = test error mode is requested. in this m ode, it is possible to write the error counters (cec). 0 r/w 7 ccr change configuration request. 0 = normal operation requested 1 = write access to the configuration registers (bcr1 and bcr2) requested. 1 r/w 6 smr sleep mode request 0 = the sleep mode i s not requested (normal operation). 1 = the sleep mode is requested. 0 r/w
chapter 7 can module (txcan) 7 - 15 bit name function reset value mode 5 hmr halt mode request 0 = the halt mode is not requested (normal operation). 1 = the halt mode is requested. 0 r/w 4 wuba wake up on bus a ctivity 0 = the module leaves the sleep mode only by detecting a write access to mcr 1 = the module leaves the sleep mode by detecting any bus activity or by detecting a write access to mcr. 0 r/w 3 mtos mailbox transmission order select 0 = mailbox trans mission order by mailbox number. the mailbox with the lower number will be sent first. 1 = mailbox transmission order by identifier priority. the mailbox with the higher priority identifier will be sent first. 0 r/w 2 ? wired to zero 0 r 1 tscc time stam p counter clear 0 = no effect 1 = the time stamp counter will be cleared. this bit can only be written and will always be read as zero. 0 w 0 sres software reset 0 = no effect 1 = a write access to this register causes a software reset of the module (all parameters will be reset to their initial values). this bit can only be written and will always be read as zero. 0 w
chapter 7 can module (txcan) 7 - 16 7.2.7 bit configuration registers bit configuration register 1 (bcr1) bit 15 8 7 0 name ? brp bit name function reset value mod e 15:8 ? wired to zero 0 r 7:0 brp brp is the value of the baud rate prescaler. 0 r/w bit configuration register 2 (bcr2) bit 15 14 13 12 11 10 9 8 name ? sjw bit 7 6 5 4 3 2 1 0 name sam tseg2 tseg1 bit name function reset value mode 15:10 ? wired to zero 0 r 9:8 sjw indicates by how many units of time - quantums a bit is allowed to be lengthened or shortened when re - synchronising. 00 = 1 time quantum 01 = 2 time quantums 10 = 3 time quantums 11 = 4 time quantums 0 r/w 7 sam sample point set ting (see below) 0 r/w 6:4 tseg2 timing setting for sampling point (see below) 0 r/w 3:0 tseg1 timing setting for sampling point (see below) 0 r/w
chapter 7 can module (txcan) 7 - 17 the length of a bit is determined by the parameters tseg1, tseg2 and brp. all controllers on the can bus must have the same baud rate and bit length. at different clock frequencies of the individual controllers, the baud rate has to be adjusted by the mentioned parameters. in the bit timing logic, the conversion of the parameters to the required bit timing i s realized. the configuration registers (bcr1, bcr2) contain the data about the bit timing. its definition corresponds to the can specification 2 (like intel 82527). the register content is zero after a reset. nominal bit time sjw tseg2 tseg1 sjw syncseg transmit point sample point figure 7.2 . 4 required timing parameters for can transmission the length of t scl (can bus system clock) is defined by: osc scl f brp t 1 + = q scl t t * = * 1 1 ( t q = time quantum) f osc is the tx can system clock frequency (input clock of the txcan module). the synchronization segment syncseg has always the length of ?1 t scl ?. the baud rate is defined by: scl t tseg tseg br * + + + + = ) 1 ) 1 2 ( ) 1 1 (( 1 ipt (information processing time) is the time segment starting with the sample point reserved for processing of the sampled bit level. the information processing time is equal to 3 txcan system clock cycles. the parameter sjw (2 bits) indicates, by how many units of t q a bit is allowed to be lengthened or shortened when r e - synchronizing. values between ?1? (sjw = 00b) and ?4? (sjw = 11b) are adjustable. the bus line is sampled and a synchronization is performed at each falling edge of the bus signal within a bit grid. with the corresponding bit timing, it is possible to r each a multiple sampling of the bus line at the sample point by setting sam. the level determined by the can bus then corresponds to the result from the majority decision of the last three values. the sample points are at the rising edges of the external s ampoint signal and twice before with a distance of one txcan system clock cycle.
chapter 7 can module (txcan) 7 - 18 this leads to the following restrictions: restrictions for tseg2 brp t q length (txcan clock cycles) ipt length (txcan clock cycles) tseg2 minimum length (in t q ) 0 1 3 3 1 2 3 2 >1 brp+1 3 2 restrictions for tseg1 the length of tseg1 should be equal or greater than the length of tseg2: tseg1 3 tseg2 restrictions for sjw the maximum length of the synchronization jump width is equal to the length of tseg2: sjw 3 tseg2 r estrictions for sam the three - time sampling is not allowed for brp<4. for brp<4 always a one - time sampling will be performed regardless of the value of sam. example: a transmission rate of 1mbit/s will be adjusted, i.e. a bit has a length of 1 s. the clo ck frequency f osc is 10 mhz. the baud rate prescaler is set to ?0?. that means a bit for this data transmission rate has to be programmed with a length of 10* t q . according to the above formula, the values to be set are always by one smaller than the calcu lated values. e.g. brp = 1 (brp_reg = 0); tseg1 = 5 (tseg1_reg = 4), tseg2 = 4 (tseg2_reg = 3). with this setting a threefold sampling of the bus is not possible (brp<4), thus sam = 0 should be set. sjw is not allowed to be greater than tseg2, so the ma ximum value could be set to 4 units (sjw = 3). 7.2.8 time stamp feature there is a free - running 16 - bit timer implemented in the module to get an indication of the time of reception or transmission of messages. the content of the timer is written into the time s tamp register of the corresponding mailbox (tsv) when a received message has been stored or a message has been transmitted. the counter is driven from the bit clock of the can bus line. when the txcan is in configuration mode or in sleep mode, the timer w ill be stopped. after power - up reset the free running counter can be cleared by writing a value to the time stamp counter prescaler. the counter can be written and read by the mcu in configuration mode and in normal operation mode.
chapter 7 can module (txcan) 7 - 19 time stamp counter reg ister bit 15 0 name tsc overflow of the counter can be detected by the time stamp counter overflow interrupt flag of the global interrupt flag register gif and the status flag tso in gsr. both flags can be cleared by writing a ?1? to the corr esponding bit location in gif. there is a 4 - bit prescaler for the time stamp counter. after power - up the time stamp counter is driven directly from the bit clock (tsp = 0). the period t tsc for the time stamp counter will be calculated with the following f ormula: ) 1 ( + * = tsp t t bit tsc time stamp counter prescaler register bit 15 4 3 2 1 0 name ? tsp to be sure, that the value of the counter will not change during the write cycle to the mailbox ram, there is a hold register implemented. the val ue of the counter will be copied to this register if a message has been received or transmitted successfully. the reception is successful for the receiver, if there is no error until the last but one bit of end - of - frame. the transmission is successful for the transmitter, if there is no error until the last bit of end - of - frame. (refer to the can specification 2.0b) the following figure shows the structure of the time stamp counter: prescaler register (4 bit) mcu read / write prescaler (4 bit) free running time stamp counter (16 bit) time stamp hold register (16 bit) mcu read / write transmission / reception successful can bus bit clock count-up clock hardware / software reset entering sleep mode entering configuration write to prescaler clear load clear hardware / software reset clear re-load value mailbox ram re-load entering sleep mode entering configuration mode write to prescaler figure 7.2 . 5 time stamp counter
chapter 7 can module (txcan) 7 - 20 the free running time stamp counter and the time stamp hold register will be cleared in the following cases: after reset (power - up reset or software reset) when the module enters configuration mode when the module enters sleep mode when a write access to the time stamp prescale register is performed 7.2.9 status registers global status register (gsr) bit 15 14 13 12 11 10 9 8 name msginslot rm tm ? sua bit 7 6 5 4 3 2 1 0 name cce sma hma ? tso bo ep ew bit name funct ion reset value mode 15:12 msg inslot message in slot 1111 = no transmit message in slot 0000 = message 0 is in the transmission slot ... 1110 = message 14 is in the transmission slot 1111 r 11 rm receive mode 1 = txcan is receiving a message. that means txcan is not the transmitter of the message and the bus is not idle. 0 = the can module is not receiving a message 0 r 10 tm transmit mode 1 = txcan is transmitting a message. the module stays transmitter until the bus is idle or it loses arbitration. 0 = the can module is not transmitting a message 0 r 9 ? wired to zero 0 r 8 sua suspend mode acknowledge 1 = txcan is in suspend mode 0 = txcan is not in suspend mode 0 r 7 cce change configuration enable 1 = the mcu is allowed to do write accesses to th e configuration registers. 0 = write accesses to the configuration registers are denied. 1 r 6 sma sleep mode acknowledge 1 = txcan has entered the sleep mode. 0 = normal operation 0 r 5 hma halt mode acknowledge 1 = txcan has entered the halt mode. 0 = normal operation r 4 ? wired to zero 0 r 3 tso time stamp overflow flag 1 = there was at least one overflow of the time stamp counter since this bit has been cleared. to clear this bit, clear the tsoif bit in the gif register. 0 = there was no overflow of the time stamp counter 0 r
chapter 7 can module (txcan) 7 - 21 bit name function reset value mode 2 bo bus off status 1 = there is an abnormal rate of occurrences of errors on the can bus. this condition occurs when the transmit error counter tec has reached the limit of 256. during ?bus off?, no messages can be received or transmitted. the can module will go to ?bus on? automatically after the ?bus off recovery sequence? . after entering ?bus off?, the error counters are undefined. 0 = normal operation 0 r 1 ep error passive status 1 = the can module is in the error passive mode. 0 = the can module is in the error active mode. 0 r 0 ew warning status 1 = at least one of the error counters has reached the warning level of 97. 0 = both values of the error counters are less than 97. 0 r can error counter register (cec) bit 15 8 7 0 name tec rec bit name function reset value mode 15:8 tec transmit error counter 0 r 7:0 rec receive error counter 0 r the can module contains two error counters: receive error counter (rec) and transmit error counter (tec). the values of both counters can be read via the mcu interface. these counters are incremented or decremented according to the can specification version 2.0b. a write access to the error counters is only possible in the te st error mode (tsterr bit in mcr is set). the receive error counter is not increased after exceeding the error passive limit (128). after the correct reception of a message, the counter is set to a value between 119 and 127 (see can specification). after reaching the ?bus off? status, the error counter are undefined. if the status ?bus off? is reached, the receive error counter is incremented after 11 consecutive recessive bits on the bus. these 11 bits correspond to the gap between two telegrams on the b us. if the counter reaches the count 128, the module changes automatically to the status error active. all internal flags are reset and the error counters are deleted. the configuration registers keep the programmed values. the values of the error counters are undefined during ?bus off? status. when txcan enters configuration mode (see paragraph configuration mode ) the error counters will be cleared.
chapter 7 can module (txcan) 7 - 22 7.3 txcan interrupt logic the txcan has the following interrupt sources: transmit interrupt: a message has been transmitted successfully receive interrupt: a message has been received successfully warning level interrupt: at least one of the two error counters is greater than or equal to 97 error passive interrupt: txcan enter s the error passive mode bus off interrupt: txcan enters the bus off mode time stamp overflow interrupt transmission abort interrupt receive message lost interrupt wake - up interrupt: after wake - up from sleep mode this interrupt will be generated remote fra me pending interrupt these interrupt sources are divided in three groups: transmit interrupts, receive interrupts and global interrupts. there is one interrupt output line for each group. canrx is dedicated for receive interrupts, cantx is dedicated for t ransmit interrupts and canexc for the global interrupts. global interrupt flag register (gif) the interrupt flag bits will be set if the corresponding interrupt condition has occurred. if the corresponding interrupt mask bit is set in the gim register, the interrupt line irq2 will go active high. as long as an interrupt flag in the gif register is set and the corresponding mask bit is also set, the interrupt line irq2 will stay active high (?1?). bit 15 8 7 6 5 4 3 2 1 0 name ? rfpf wuif rmlif trmabf tsoif boif epif wlif bit name function reset value mode 15:8 ? wired to zero 0 r 7 rfpf remote frame pending flag 1 = a remote frame has been received (in a receive - mailbox). this bit will not be set if the identifier of the remote frame matches to a transmit - mailbox with rfh set. 0 = no remote frame has been received. 0 r/c 6 wuif wake - up interrupt flag 1 = the module has left the sleep mode. 0 = the module is still in sleep mode or normal operation. 0 r/c 5 rmlif receive message lost interrupt fla g 1 = at least for one of the mailboxes, configured as receive, an overload condition has been occurred. 0 = no message has been lost. 0 r/c 4 trmabf transmission abort flag 1 = transmission aborted interrupt - flag. at least one of the bits in the aa regis ter is set. 0 = no transmission has been aborted. 0 r/c
chapter 7 can module (txcan) 7 - 23 bit name function reset value mode 3 tsoif time stamp counter overflow interrupt flag 1 = there was at least one overflow of the time stamp counter since this bit has been cleared. 0 = there was no overflow of the time stamp counter since this bit has been cleared. 0 r/c 2 boif bus off interrupt flag 1 = the can has entered the bus off mode. 0 = the can module is still in bus on mode. 0 r/c 1 epif error passive interrupt flag 1 = the can module has entered the error passive mode. 0 = the can module is still in error active mode. 0 r/c 0 wlif warning level interrupt flag 1 = at least one of the error counters has reached the warning level. 0 = none of the error counters has reached the warning le vel. 0 r/c note: all interrupt flags in gif are independent of the interrupt mask bits. the interrupt flags in gif can be cleared by writing a ?1? to the corresponding bit position. writing a ?0? has no effect. global interrupt mask register (gim) bit 15 8 7 6 5 4 3 2 1 0 name ? rfpf wuif rmlif trmabf tsoif boif epif wlif the attachment of bits in gim to the interrupt conditions is equal to that in gif. each interrupt flag bit in gif is masked by the corresponding mask bit in gim. after power - up , all bits are cleared. 7.3.1 mailbox interrupts there are two separate interrupt output lines for the mailboxes. one interrupt output for mailboxes, which are configured as transmit and one for mailboxes, which are configured as receive. there are two interru pt flag registers and one interrupt mask register. one interrupt flag register is for receive mailboxes and one for transmit mailboxes. the interrupt mask register is used for transmit and receive mailboxes. mailbox interrupt mask register (mbim) the sett ings in mbim determine, for which mailbox the interrupt generation is enabled or disabled. if a bit in mbim is ?0?, the interrupt generation for the corresponding mailbox is disabled and if it is ?1?, the interrupt generation is enabled. reset value of mbi m is 0. bit 15 0 name mbim
chapter 7 can module (txcan) 7 - 24 mailbox interrupt flag registers (mbtif / mbrif) bit 15 14 0 name ? mbtif bit 15 0 name mbrif there are two interrupt flag registers. one for receive mailboxes and one for transmit mailbo xes. if a mailbox is configured as receive, the corresponding bits in the transmit interrupt flag register mbtif will always be read as ?0?. in mbtif, bit 15 is not implemented, because mailbox 15 is the receive - only mailbox. bit 15 of mbtif will always be read as ?0?. if a mailbox is configured as transmit, the corresponding bits in mbrif will always be read as ?0?. if a message has been received for mailbox ?n? and the mask bit is set to ?1? the corresponding interrupt flag ?n? of mbrif will be set to ?1 ? and the interrupt line irq0 goes active high (?1?). if a message has been transmitted from mailbox ?n? and the mask bit is set to ?1? the corresponding interrupt flag ?n? of mbtif will be set to ?1? and the interrupt line irq1 goes active high (?1?). i f the mask bit in mbim is set to ?0?, the interrupt flag in mbrif or mbtif will not be set and no interrupt will be generated. the information about a successful transmission or reception could be read from the ta or rmp register respectively. the interru pt output lines irq0 and irq1 will stay at ?1? as long as one of the interrupt flags in mbrif or mbtif are ?1? respectively and the corresponding bits in mbim are set to ?1?. the interrupt flags in mbtif will be cleared by writing a ?1? from the mcu to mb tif and the interrupt flags in mbrif will be cleared by writing a ?1? to mbrif. writing a ?0? has no effect. the corresponding status flags in ta or rmp have to be cleared separately. after power - up, all interrupt flags are cleared.
chapter 7 can module (txcan) 7 - 25 7.4 txcan operation modes 7.4.1 configuration mode the txcan has to be initialized before activation. the bit timing parameters can only be modified when the module is in configuration mode. after reset, the configuration mode is active and the ccr bit of mcr and the cce bit of gsr are set to ?1?. the txcan could be set to normal operation mode by writing a ?0? to ccr. after leaving configuration mode, the cce bit will be set to ?0? and the power - up sequence will start. the power - up sequence consists of detecting eleven consecutive reces sive bits on the can bus line. after the power - up sequence, txcan is bus on and ready for operation. to enter configuration mode from normal operation mode the change configuration request bit (ccr) has to be set to ?1?. after the txcan has entered config uration mode, the change configuration enable bit (cce) will be set to ?1?. see also the following flowchart. when the txcan enters configuration mode the error counters, the time stamp counter and the time stamp hold register will be cleared. txcan is in configuration mode: ccr=1 & cce=1 normal operation requested? set ccr to ?0? yes no switch to configuration mode from normal operation mode initialize txcan after reset set bit timing parameters in bcr1 & bcr2 cce = 0 ? yes txcan is in normal operation mode and starts power-up sequence 11 consecutive recessive bits detected? txcan is bus on and ready for operation no txcan is in normal operation mode: ccr=0 & cce=0 configuration mode requested? yes set ccr to ?1? cce = 1 ? no no yes yes no figure 7.4 . 1 configuration flow chart for txcan
chapter 7 can module (txcan) 7 - 26 7.4.2 sleep mode the sleep mode will be requested by writing a ?1? to smr (mcr register). when the module enters the sleep mode, the status bit ? sleep mode acknowledge? (sma, gsr register) will be set. during sleep mode, the internal clock of txcan is switched off. only the wake up logic will be active. the read value of the gsr will be f040h, this means, there is no message in slot and the sleep mode is active (sma is set). read accesses to all other registers will deliver the value 0000h. write accesses to all registers but the mcr will be denied. the module leaves the sleep mode if a write access to mcr has been detected or there is any bus act ivity detected on the can bus line (if the wake - up on bus activity is enabled). the automatic ?wake up on bus activity? can be enabled/disabled with the configuration bit wuba in mcr. if there is a write access to mcr or any activity on the can bus line (with wuba = 1), the module begins its power - up sequence. the module waits until detecting 11 consecutive recessive bits on the rx input line, afterwards it goes to bus active. the first message that initiates the bus activity can not be received. in slee p mode, the can error counters and all ?transmission requests? (trs) and ?transmission reset requests? (trr) will be cleared. after leaving the sleep mode, smr and sma will be cleared. if the sleep mode is requested while txcan is transmitting a message, the module will not switch to the sleep mode immediately. it will continue until a successful transmission or after losing the arbitration, until a successful transmission or after loosing the arbitration a successful reception occurs.
chapter 7 can module (txcan) 7 - 27 7.4.3 suspend mode th e suspend mode will be requested by writing a ?1? to sur (mcr register). when the module enters the suspend mode the status bit sua (gsr register) will be set to ?1?. if the can bus line is not idle, the current transmission/reception of the message will b e finished before the suspend mode will be activated. in suspend mode the txcan is not active on the can bus line. that means error flags and acknowledge flags will not be sent. the error counters and the error passive flag will not be cleared in the susp end mode. if the suspend mode is requested during the bus off recovery sequence, the module stops after the bus off recovery sequence was finished. the module remains inactive until suspend mode request sur is deactivated. the suspend mode acknowledge fla g is not activated, although the sur bit is ?1? and the module is inactive. to restart the module, the sur bit has to be programmed to ?0?. after leaving the bus off state or the inactive state, the module will restart its power - up sequence. txcan leaves the suspend mode by writing a ?0? to sur. 7.4.4 halt mode the halt mode will be requested by writing a ?1? to hmr. when the module enters the halt mode, the status bit hma will be set. during halt mode the module does not send or receive any messages. the modul e is still active on the can bus line. error flags and acknowledge flags will be sent. the module leaves the halt mode if the command bit hmr is reset to zero. if the module is transmitting a message when the hmr is set, the transmission will be continued until a successful transmission or in case of a lost arbitration until a successful reception. therefore, the module initiates no error condition on the can bus line.
chapter 7 can module (txcan) 7 - 28 7.4.5 test loop back mode in this mode txcan can receive its own transmitted message and will generate its own acknowledge bit. no other can node is necessary for the operation. when the intlb bit of the mcr register is ?0?, the internal loop back is disabled. the supposition that txcan receives its own messages is that the rx and tx lines must b e connected to a can bus transceiver or directly together. when the intlb bit of the mcr register is set to ?1?, the internal loop back is enabled. in this case, there is no need to connect the rx and tx lines together or to a can bus transceiver to make the txcan able to receive its own messages. the ?test loop back mode? shall only be enabled or disabled when txcan is in suspend mode. the following figure shows the set - up procedure. in ?test loop back mode? txcan can transmit a message from one mailbox and receive it in another mailbox. the set - up for the mailboxes is the same as in normal operation mode. enable/disable test loop back mode and/or test error mode no yes txcan is in normal operation mode: ccr=0 & cce=0, sur=0 & sua=0 sua = 1 ? suspend mode request: set sur to ?1? back to normal operation mode with enabled/disabled tstlb and/or tsterr: set sur to ?0? setup tstlb and/or tsterr bit: ?1? enable, ?0? disable sua = 0 ? end of setup; txcan is in normal operation mode with enabled/disabled test loop back and/or test error mode yes no figure 7.4 . 2 internal test flow chart
chapter 7 can module (txcan) 7 - 29 7.4.6 test error mode the error counte rs can only be written when txcan is in test error mode. the ?test error mode? shall only be enabled or disabled when txcan is in suspend mode. the figure on the right side shows the set - up procedure. when txcan is in ?test error mode? both error counter s will be written at the same time with the same value. the maximum value that can be written into the error counters is 255. thus, the error counter value of 256 which forces txcan into bus off mode can not be written into the error counters. 7.4.7 special mod es for dual channel can modifications due to adding a second can channel bits are required from the ccr register. singlechannelemu and cantstinternal. setting the cantstinternal to ?1? switches to an internal testmode, which is a internal connection indep endent from any external pins or transceivers. internal test mode txcan1 & txcan2 rxcan1 rxcan2 chip border figure 7.4 . 3 internal test mode the signal ?singlechannelemu? connects 2 channels to be able to work on only 1 transceiver. single transceiver mode txcan1 & txcan2 tx rxcan1 transceiver rx rxcan2 chip border figure 7.4 . 4 single transceiver mode the following table shows the bit function of canm in the chip configuration register (ccr): canm can mode 00 normal operation x1 internal tes t mode 10 1 transceiver - mode
chapter 7 can module (txcan) 7 - 30 7.5 handling of message - objects in the following sections, there are suggestions how to handle message objects. 7.5.1 receiving messages the following flowchart shows the handling of receive objects using receive interrupt irq0. setup a mailbox for message reception configure mailbox for reception: set mdn to ?1? setup mailbox identifier and ide bit for standard or extended id enable mailbox: set mcn to ?1? enable interrupts: set mbimn to ?1? end of setup receiving messages wait for irq0 check rmp or mbrif to determine the mailbox with rmp set read out the mailbox clear rmpn rmln = 1 ? clear rmln and read out mailbox again rmpn = 1 ? clear mbrif and return from interrupt service routine yes no no yes no yes new setup for the mailbox? disable mailbox: set mcn to ?0? yes no special user tasks ... set lame / game of the mailbox if necessary setup lam / gam if necessary figure 7.5 . 1 receiving objects using irq0 it is also possible to use polling. in this case, the ?waiting for irq0? in above flowchart must be replaced by polling rmp. enabling int errupts and clearing mbrif must be removed from the flow.
chapter 7 can module (txcan) 7 - 31 7.5.2 transmitting messages the following flowchart shows the handling of transmit objects by using the transmit interrupt irq1. it is also possible to use polling. in this case, the ?waiting for irq1? in the flowchart must be replaced by polling ta. enabling interrupts and clearing mbtif must be removed from the flow. setup a mailbox for message transmission configure mailbox for transmission: set mdn to ?0? disable mailbox: set mcn to ?0? setup mailbox identifier and ide bit for standard or extended id enable interrupts: set mbimn to ?1? enable mailbox: set mcn to ?1? end of setup transmitting messages new setup for the mailbox? yes update mailbox data? no write new data to the mailbox yes set transmission request: set trsn to ?1? transmission requested? no no yes no yes check ta to determine the mailbox with ta set choose transmission order: setup mtos special user tasks ... (update mailbox data?) clear ta and mbtif and return from interrupt service routine wait for irq1 figure 7.5 . 2 transmitting objects using irq1
chapter 7 can module (txcan) 7 - 32 7.5.3 remote frame handling the following flowchart shows the handling of remote frames by using the automatic reply feature. this feature is available when the rfh bit of a mailbox, which is configured for transmission, is set. to avoid data inconsistency problems when upda ting the mailbox data the cdr register is used. setup a mailbox for automatic reply to remote frames configure mailbox for transmission: set mdn to '0' disable mailbox: set mcn to '0' setup mailbox identifier and ide bit for standard or extended id enable mailbox: set mcn to '1' end of setup automatic reply to remote frames new setup for the mailbox? yes update mailbox data? no yes choose transmission setup mtos set rfh bit of the mailbox; set game if necessary setup gam if necessary change data requested: set cdrn to '1' reset cdrn: set cdrn to '0' no order: write new data to the mailbox figure 7.5 . 3 remote frame handling using the automatic reply feature
chapter 8 parallel interface (port) 8 - 1 8. parallel interface (port) the port - module is a general - purpose parallel interface. the port - module contains the following features: 30 pins each pin can be configured independently as input or output each pin can generate an interrupt on rising or falling edge of input - signal the port module shares its pins with modules gdc, txsei and uart. bit assignment of all port registers: bit 31 30 29 28 27 26 25 24 pin wired to zero pio29 pio28 pio27 pio26 pio25 pio24 access ro r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 pin pio23 pio22 pio21 pio20 pio19 pio18 pio17 pio16 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 pin pio15 pio14 pio13 pio12 pio11 pio10 pio9 pio8 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 pin pio7 pio6 pio5 pio4 pio3 pio2 pio1 pio0 access r/w r/w r/w r/w r/w r/w r/w r/w register function: each bit of the following registers is assigned to the corresponding pin. the table below describes the function of each register for one pin. regis ter physical address (hex) function of one bit reset value pamux 1c03 0014 determines, which module uses the pins 0 = port module uses the pin 1 = gdc, txsei or uart uses the pin further descriptions see section ?pin assignment? on next side. 0 pa 1c03 0 000 this register contains data read from port pins or written to port pins. when a pin is used as input, then the corresponding bit in this register is read only. 0 pacr 1c03 0004 direction of pin 0 = input 1 = output the contents of this bit shows no ef fect, when pamux = 1. 0 pamsk 1c03 0010 interrupt enable 0 = disable interrupt 1 = enable interrupt whether the interrupt caused on falling or rising edge of input signal, depends on the contents of palmx register. when the pin is used by another resource or the pin is used as output, the interrupt is inhibited. 0
chapter 8 parallel interface (port) 8 - 2 register physical address (hex) function of one bit reset value palmx 1c03 000c controls edge detection for interrupt generation 0 = cause an interrupt on falling edge 1 = cause an interrupt on rising edge the contents of this register show no effect, if pamsk is set to 0. 0 pal 1c03 0008 interrupt flag 0 = no interrupt has occurred on pin 1 = interrupt has occurred on pin after detection of signal change on pin and when interrupt is enabled , the hardware writes a 1 to this register. by writing 0 to the pal register you can reset the interrupt flag. before you can reset a port - interrupt in the interrupt controller, you must reset the interrupt flag in pal register. writing 1 to this register has no effect. 0 pin assignment the pamux register in the port module and the seimux bits in the chip configuration register (ccr) determine the use of the pio pins. the following table shows the pin use and the corresponding bit settings: register se ttings pio0 .. pio15 pio16 .. pio29 pamux = 0 port port pamux = 1 and seimux = 0 gdc uart pamux = 1 and seimux = 1 gdc txsei example for register configuration: task solution pins 0 to 15 are used by gdc, pins 16 to 29 are used by port => pamux = 0x0000ffff pins 16 to 20 are used as outputs, pins 21 to 29 are used as inputs => pacr = 0x000f0000 following pins should cause an interrupt - a signal change from low to high on pin 24 - a signal change from high to low on pin 25 => pamsk = 0x03000000 p almx = 0x01000000
chapter 9 synchronous serial i/o (txsei) 9 - 1 9. synchronous serial i/o (txsei) the toshiba tx serial expansion interface is a synchronous communication unit and compatible to peripheral devices, which can be connected to an spi/sei type interface. txsei?s flexible clock control logic allows the selecti on of clock polarity and phase for the transfer protocol. when txsei is configured as a master, a large number of different bit rates with up to 15 mhz clock rate in the master mode can be selected. in slave mode transmissions up to 7.25 mhz are possible ( assuming the TMPR3916F is operating with 60 mhz) the built - in error detection logic allows the detection of various error situations, which can occur during sei transfers. txsei also offers dma support for automated data transfers to its shift registers . by the use of dma a larger number of transfers can be scheduled at once. in particular, the usage of dma allows a more cost - effective implementation than usual large queue or buffer structures. txsei is able to perform seamless transfers of consecutive f rames. alternatively, the minimum delay between two consecutive transfers is programmable for master mode. feature overview: phase and polarity selection transfer sizes of 5 to 16 bits dma operation: full - duplex 2 channels, half - duplex 1 channel built - in error detection logic 4 frame transmit, 4 frame receive buffers compatible with spi type interfaces master and slave operation 15 mbps data - rate when operated with 60 mhz clock rate. inter frame space delay feature seamless transfer of large values without delay between consecutive frames integrated msb / lsb first reordering stop and flush buffer functionality for fast event response programmable buffer - fill - level dependent receive / transmit interrupts
chapter 9 synchronous serial i/o (txsei) 9 - 2 9.1 txsei structure the following figure roughly shows t he internal structure of the txsei and the connectivity to the outside of the chip via the port - multiplexer: mcu interface & configuration registers tx-fifo rx-fifo shift-register control logic p o r t c o n t r o l clk tx(sei) rx(sei) ssi io-directions dependent on mode (slave/master) port-muliplexer pios 16,17,18,19, 22 connection to internal system bus output enables chip configuration r. seimux sso figure 9.1 . 1 internal structure of txsei
chapter 9 synchronous serial i/o (txsei) 9 - 3 9.2 registers the following tab le shows a map of the txsei i/o - space: register (short name) physical address (hex) name function semcr 1c00 8000 master control register mode settings secr0 1c00 8004 sei control register 0 general settings secr1 1c00 8008 sei control register 1 defin ition of bite - rate and transfer - size sefs 1c00 800c sei inter frame space register definition of space between frames sess 1c00 8010 sei slave select space register slave select timer settings sesr 1c00 8014 sei status register status information sedr 1c00 8018 sei data register transmit and receive data sers 1c00 801c sei read start register alternative register to read received data txsei?s registers can be accessed using byte, half - word and word instructions. bits [31:16] are unused in all registe rs. these bits are wired to zero and read - only.
chapter 9 synchronous serial i/o (txsei) 9 - 4 sei master control register (semcr) bit 7 6 5 4 3 2 1 0 name opmode ? loop sestp bclr bit name function reset value r/w 7:6 opmode operation mode 00 = don?t care. writing this value to the opmode bits doesn?t change anything 01 = configuration mode: use this mode to change the settings of the bits mstr, sbos, spol and spha in secr0 and also the secr1 register. 10 = active mode: normal operation mode 11 = reserved. do not use this setting in configuratio n mode the setp and loop bit and also the receive and transmit fifo will be cleared. the master and slave control modules will be kept in reset. running transfers are immediately aborted, even within the current frame. 01 r/w 5:3 ? wired to zero 000 r 2 loop loop enable: if txsei is configured as a master, this bit can be used to switch a loop - back from the tx to the rx pin for diagnostic purpose. it could be set only when the txsei is in active mode and configured as a master. setting the txsei in config uration mode will clear this bit. 0 = loop disabled, normal operation 1 = loop enabled 0 r/w 1 sestp sei stop this bit is used only during master mode. if this flag is asserted, the module will stop the transfer after the current frame has been completed. this bit could be set only when the txsei is in active mode and configured as a master. setting the txsei in configuration mode will clear this bit. 0 = normal operation 1 = module will stop after completion of the current transfer 0 r/w 0 bclr sei buffe r clear this flag is used to clear the receive and transmit fifo and can only be used in master mode. the internal buffers can only be cleared, if the module is already in stop mode. in this case, the fifo logic can be reset by writing a ?1? value to this bit. the module can be taken out of the stop mode in the same access. a stop of txsei and clearance of the buffers might become necessary to guarantee a fast response to events. it is recommended to wait until the txsei module is idle (sidle=1) before acti vating the bclr bit. this register will always be read as ?0?. 0 r/w
chapter 9 synchronous serial i/o (txsei) 9 - 5 sei control register 0 (secr0) bit 15 14 13 12 11 10 9 8 name txifl rxifl silie soeie sueie stfie bit 7 6 5 4 3 2 1 0 name ? ssival ifspse mstr sbos spha spol bit name function reset value r/w 15:14 txifl transmit interrupt fill level (seitx): 00 = interrupt, if one or more tx values can be stored 01 = interrupt, if two or more tx values can be stored 10 = interrupt, if three or more tx values can be stored 11 = interrupt, if four or more tx values can be stored 00 r/w 13:12 rxifl receive interrupt fill level (seirx): 00 = interrupt, if one or more rx values are stored 01 = interrupt, if two or more rx values are stored 10 = interrupt, if three or more rx values are stored 11 = interrupt, if four or more rx values are stored 00 r/w 11 silie sei idle interrupt enable: 0 = disable sidle as an interrupt source for seiexc 1 = enable sidle as an interrupt source for seiexc 0 r/w 10 soeie sei overflow error interrupt enable: 0 = di sable seoe as an interrupt source for seiexc 1 = enables seoe as an interrupt source for seiexc 0 r/w 9 sueie sei underflow error interrupt enable: 0 = disable seue as an interrupt source for seiexc 1 = enables seue as an interrupt source for seiexc 0 r/w 8 stfie sei transfer format error interrupt enable: 0 = disable setf as an interrupt source for seiexc 1 = enable setf as an interrupt source for seiexc 0 r/w 7:6 ? wired to zero 0 r 5 ssival ssi valid determines if the slave select input signal is val id in master mode or not. if valid, the ssi signal will be observed in master mode to generate a transfer format error. 0 = ssi not valid in master mode 1 = ssi valid in master mode 0 r/w 4 ifspse inter frame space prescaler enable (valid only in master m ode). 0 = ifs prescaler disabled 1 = ifs prescaler enabled 0 r/w 3 mstr master / slave mode select 0 = txsei is configured as slave 1 = txsei is configured as master 0 r/w 2 sbos sei bit order select 0 = lsb first operation, the least significant bit is shifted first 1 = msb first operation, the most significant bit is shifted first 0 r/w 1 spha sei polarity 0 = active high clocks selected; sclk idles low 1 = active low clocks selected; sclk idles high 0 r/w 0 spol sei phase this flag selects one of two fundamentally different transfer formats. 0 = sample on 1 st edge, shift on 2 nd edge 1 = shift on 1 st edge, sample on 2 nd edge. 0 r/w note : the bits of this register could only be changed in configuration mode.
chapter 9 synchronous serial i/o (txsei) 9 - 6 sei control register 1 (secr1) the number of bits per frame is configured using this register. this register could only be written, when the module is in configuration mode. bit 15 14 13 12 11 10 9 8 name ser bit 7 6 5 4 3 2 1 0 name ? ssz bit name function reset value r/w 15:8 ser in mas ter - mode, this setting controls the bit - rate for transmission. the internal clock rate generator is implemented as a down counter. the ser setting specifies the reload value for this counter. 0x01 r/w 7:5 ? wired to zero 0 r 4:0 ssz transfer size 0x05 = 5 bits 0x06 = 6 bits ... ... 0x10 = 16 bits others = invalid setting note: if ssz has an invalid setting, the txsei will not work properly. 0 r/w this register can only be written, if txsei is in configuration mode. the clock - rate on the sei bus can be calculated using the following formula: ) 1 ( 2 + = n f f system sei
chapter 9 synchronous serial i/o (txsei) 9 - 7 as an example, some common settings for f system =60 mhz are shown in the table below: ser setting sei clock rate (f sei ) sustained peak data rate half - duplex sustained peak data ra te full - duplex 0x00 invalid setting invalid setting invalid setting 0x01 15 mhz 15 mbps 30 mbps 0x02 10 mhz 10 mbps 20 mbps 0x03 7.5 mhz 7.5 mbps 15 mbps 0x04 6 mhz 6 mbps 12 mbps 0x05 5 mhz 5 mbps 10 mbps 0x09 3 mhz 3 mbps 6 mbps 0x13 1.5 mhz 1.5 mbps 3 mbps 0xff 117.1875 khz 117.1875 kbps 234.375 kbps in slave mode, the setting is ignored and the clock is derived from the clock on the sei bus. note: due to the internal over - sampling, if the module is operated in slave mode, the input baud - rate must be slightly less than 1/8 of the input system clock to the module. (e.g. 60 mhz system input clock => spi slave baud rate max. 7.25 mbps) sei inter frame space register (sefs) bit 15 10 9 0 name ? ifs this register is used to configure the amount of time, which is inserted between two consecutive frames. the time is guaranteed by an internal 10 - bit down counter. the counter can be operated with or without prescaler. the ifspse bit of the secr0 register determines whether the prescaler sh ould be used or not. when operating without prescaler, the counter runs on sei system clock. when operating with prescaler, the counter runs on 1/32 of sei system clock. this counter is implemented as a down counter. it is reloaded each time a transfer is completed. when another transfer is buffered, the new transfer value will be loaded to the shift buffer after the timer has expired and the transmission will start. the inter frame space timer can be disabled by setting this register to ?0? and two conse cutive transfers will be sent using only the minimum amount of time required to load the buffers between consecutive frames (seamless transfer). when the counter reload value in the ifs register is ?0? the inter frame space will be one system clock cycle ( 16.67 ns at 60 mhz system clock). when the prescaler is not used, the inter frame space can be calculated using the following formula: sei ifs f n t = (range: 16.67 ns up to 17.07 m s at 60 mhz system clock)
chapter 9 synchronous serial i/o (txsei) 9 - 8 when using the prescaler, the inter fra me space can be calculated using the following formula: sei ifs f n t = 32 (range: 533.33 ns up to 546.13 m s at 60 mhz system clock) the ifs register can be written in configuration mode and in active mode. writing to the ifs register always clears th e inter frame space counter. therefore, if the shift buffer contains a message, which is waiting to be transferred, this message will be sent immediately, as soon as the ifs register is being written. this will also be the case, if the old value is rewritt en to the register. if this behavior is not intended, it is possible to wait for sidle flag becoming ?0?, before writing to the register. the ifsd flag in the sesr register is asserted for the time the transfer is delayed by the ifs mechanism. sei slave select space register (sess) bit 7 6 5 4 3 2 1 0 name sess the content of this register is the reload value of the slave select timer. write accesses to this register are possible in configuration mode and in active mode. writing to this register clea rs the slave select counter. this register is used to configure the amount of time, which is inserted between activating the slave select output signal in master mode and starting the transfer and between the transfer end and deactivating the slave select output signal. the time is guaranteed by an internal 8 - bit down counter. the counter runs on sei system clock. when writing to the sess register while the shift buffer contains a message, which is waiting to be transferred, this message will be sent imme diately, since the counter is cleared to ?0?. the slave select space can be calculated using the following formula: pre - transfer time: sei pre ssc f n t + = 2 _ (range: 33.33 ns up to 4.28 m s at 60 mhz system clock) post - transfer time: sei post ssc f n t + = 3 _ (range: 50 ns up to 4.3 m s at 60 mhz system clock) the slave select space timer can be disabled by setting this register to ?0?. the minimum time between setting the slave select signal and starting the transfer is 2 system clock cycles and the minimum time between the transfer end and deactivating the slave select signal is 3 system clock cycles. this is the case when sess is set to ?0?. the minimum time between two consecutive transfers is the sum of the minimum values of t scc_pre , t ifs and t scc_post : this is 6 system clock cycles.
chapter 9 synchronous serial i/o (txsei) 9 - 9 sei status register (sesr) in the sei status register, the status flags can only be read, while error flags are cleared by writing a ?1? value to the respective bit position. writing a ?0? to the error flags has no effect . bit 15 14 13 12 11 10 9 8 name tbsi rbsi tbs rbs bit 7 6 5 4 3 2 1 0 name seoe seue setf ? ifsd sidle strdy srrdy bit name function reset value r/w 15 tbsi transmit buffer status indicator this register indicates a transmit fill level interrupt 1 r 14 rbsi receive buffer status indicator this register indicates a receive fill level interrupt 0 r 13:11 tbs transmit buffer status this register shows the status of the transmit buffer. 000 = transmit buffer empty 001 = 1 transfer stored 010 = 2 tra nsfers stored 011 = 3 transfers stored 100 = 4 transfers stored, buffer full 000 r 10:8 rbs receive buffer status this register shows the status of the receive buffer. 000 = receive buffer empty 001 = 1 transfer stored 010 = 2 transfers stored 011 = 3 tra nsfers stored 100 = 4 transfers stored, buffer full 000 r 7 seoe sei overflow error: this flag indicates that a value in the receive buffer has been overwritten, before it could be read. this flag always reads ?0? in master mode. in slave mode, it can be cleared by writing a ?1? value to it. this flag will be cleared by setting the module in configuration mode. 0 r/c 6 seue sei underflow error: this flag indicates that an external master tried to shift the shift register, while no new output values were s pecified by writing to the data register. this flag always reads ?0? in master mode. in slave mode it is cleared by writing a ?1? to it. this flag will be cleared by setting the module in configuration mode. 0 r/c 5 setf sei transfer format error: this fl ag indicates a violation of the transfer format. see paragraph "transfer format error". it can be cleared by writing a ?1? to it. this flag will be cleared by setting the module in configuration mode. 0 r/c 4 ? 0 r 3 ifsd sei inter frame space delay ind icator: this flag is asserted during the time, where one frame has been processed and the next frame is being delayed by the inter - frame - space timer. 0 r 2 sidle sei idle indicator: this flag is asserted, if no transfer is in progress and if the transmit buffer is empty or the stop mode (sestp=1) is activated in master mode. 1 r
chapter 9 synchronous serial i/o (txsei) 9 - 10 bit name function reset value r/w 1 strdy sei transmit ready: this flag indicates, that the transmit buffer is ready to receive new data. the flag is cleared, if the transmit buffer is full. 1 r 0 srrdy sei receive ready: this flag indicates, that there is valid data stored in the receive buffer. this flag is cleared when emptying the receive buffer while reading sedr or sers register 0 r sei data register (sedr) bit 15 0 name dr receive buffer transmit buffer mcu bus in clk out shift buffer sedr read write sers other registers read & start figure 9.2 . 1 data paths in txsei the actual shift register is buffered for both transmission and reception. the receive and transmit buffers are implemented as fifo with a depth of four frames. a write to sedr register writes the value to the transmit buffer. from there, the data will be transferred to the shift register as soon as txsei is ready for the next transfer. reading the sedr register delivers the curre nt value from the receive fifo and increments the receive fifo pointer, if there are other values stored in the fifo. the shift - buffer is the physical register, which is used during sei transfers for shifting in/out the data. besides sedr, the sers regist er offers a second method to access the transfer values. data in both the sedr and the sers register are stored right aligned. e.g.: for eight bit transfers, only the lower eight bits of the sedr register are used. for 16 bit transfers all 16 bits of sedr are used.
chapter 9 synchronous serial i/o (txsei) 9 - 11 sei read start register (sers) bit 15 0 name rs the sers register offers a second method to fetch values from the receive buffer. reading this register returns the value from the receive buffer. just like a read from the data registe r would. in contrast to reading the data register, the read from the sers register counts for two register accesses: a read from the data register and a write of value 0xffff to the data register. therefore, in master mode a read access to this register w ill not only return the value from the receive buffer, but will also start a new transfer. in slave mode, the received data will be delivered and the data 0xffff will be written to the data register, but the transfer will start when the master activates t he slave select signal and switches on the sclk clock. in order not to have tx buffer underruns the user should initially write some data via the sedr into the tx buffer. the register is useful during half - duplex operations, where data is read from spi, w hile ?don?t care data? is shifted out. it can be specified as dma source address to save a valuable dma channel during half - duplex transfers. the register can only be read. do not write to this register.
chapter 9 synchronous serial i/o (txsei) 9 - 12 9.3 txsei operations there are five signals associated with sei transfers multiplexed on the pio pins. the use of each signal depends on the mode (master/slave) of the sei device. because the sei signals are on a shared pin it is necessary to deactivate pios 16, 17, 18, 19 and 22 by writing a zero to bits 16, 17, 18, 19 and 22 in the pmux register. furthermore the selection whether txsei or uart0 functionality is mapped to the corresponding pins has to be done via the chip configuration register (ccr). a typical configuration consists out of one master device , which controls several slave devices. only the master and one slave device are active at once. the master selects one slave for communication using the port pins to select each slave separately. only the selected slave enables its port driver for the rx signal. txsei offers a dedicated slave select input, which allows it to act on busses with multiple master devices. the dedicated slave select input guarantees a fast response to master?s device selection on the bus. pio16/ clk(sei) /clk(sio0) pin: in mas ter mode the clk pin is used as an output, in slave mode it functions as input. when txsei is co n figured as master, the clk signal is derived from the internal txsei clock generator d e pending on the sei polarity and clock rate settings. when the master ini tiates a transfer, a programmable number of 5 to 16 clock cycles are automatically generated on the clk pin. when txsei is co n figured as a slave, the clk pin synchronizes data output and input to and from the external master. in both the master and slave s ei device, data is shifted on one edge of the clk signal and is sampled on the opposite edge where data is stable. the edge polarity is dete r mined by the sei transfer protocol. pio18/ tx(sei) /tx(sio0) and pio17/ rx(sei) /rx(sio1) the rx and tx data pins are used for receiving and transmitting s e rial data. when the sei is configured as a master, rx is the data input line, and tx is the master data output line. when the sei is configured as a slave, these pins reverse roles. pio19/ ssi(sei) /clk(sio1) pin the s lave select input port is used in slave mode. the slave select input signal is active low. if txsei?s slave select input is inactive, txsei will not follow the transmissions on the sei bus. if the slave select signal goes inactive during a running transfe r and there are still other bits of the current transfer expected to receive, a transfer format error will be signaled. the current value of the shift buffer will be transferred to the receive buffer despite of this error. when txsei is configured to be t he master and the ssi pin is asserted a transmission error will be recognized. this function can be disabled with the ssival bit in the secr0 register. pio22/ sso(sei) /rts(sio1) pin pio22 is the dedicated slave select output signal and is asserted during t ransfer in master mode by the txsei device. in the case that the protocol of the connected device expects that the ss signal idles low for longer than 16 bits this signal must be generated using the port module.
chapter 9 synchronous serial i/o (txsei) 9 - 13 9.3.1 txsei transfer format during an sei trans fer, data is simultaneously transmitted (shifted out serially) and received serially (shifted in serially). the serial clock synchronizes shifting and sampling of the information on the two serial data lines. the transfer format depends on the settings of the spha and spol registers in the secr0 register. spha switches between two fundamentally different transfer protocols, which are described below. 9.3.1.1 spha equals 0 format sck (spol = 0) sck (spol = 1) tx rx ss cycle # srrdy n= 5,6,...,16 1 2 3 4 n-3 n-2 n-1 n sample point figure 9.3 . 1 protocol timing for spha=0 in this transfer format, the bit value is captured on the first clock edge. this will be on a rising edge when spol equals zero and on a falling edge when spol equals one. the levels on the tx and rx signals change with the second clock edge on sck. this clock edge will be a falling edge when spol equals zero and a rising edge, when spol equals one. with spol equal to zero, the shift clock will idle low. with spol equals 1 it will idle high. in master mode, when a transfer is initiated by writing a new value to the sedr register the new data is placed on the tx signal for half a clock cycle before the shift clock starts to operate. after the last shift cycle, the strdy and srrdy flags will be asserted.
chapter 9 synchronous serial i/o (txsei) 9 - 14 9.3.1.2 spha equals 1 format clk (spol = 0) clk (spol = 1) tx rx ss cycle # n=5,6,...,16 1 2 3 4 n-3 n-2 n-1 n sample point srrdy figure 9.3 . 2 protocol timing for spha=1 in this transfer format, the first bit is shifted in on the second clock edge. this will be on a falling edge when spol equals 0 and on a rising edge when spol equals 1. if spol equals 0, the shift clock will idle low; with spol equals 1 it will idle high. in master mode, when a transfer is initiated by writing a new value to the sedr register the new data is placed on the tx signal with th e first edge of the shift clock. 9.3.1.3 inter - frame space delay mechanism due to its dma support and its buffered shift register, txsei is able to sustain high data rates, with only a minimum amount of space between two consecutive frames. however, between cons ecutive transfers it still has to be ensured that the slave device can keep up with the transfer rate of the sei master. if txsei is configured as a master, the slave device typically has to write new values to its transmit buffer, before the next transfer can be started. to allow this, usually a minimum inter - frame space is specified considering interrupt response and data fetch time of the slave device. txsei eases the implementation of this inter - frame space by offering an automated mechanism to guarant ee inter - frame delays between consecutive frames. the inter - frame space counter is implemented as a 10 bit down counter. the counter is reloaded with the value from the sefs register after each transfer. the next transfer will not start before the ifs cou nter reaches a value of zero. the internal ifs counter is reset every time the sefs register is written. therefore, if the module is in the inter - frame space the next transfer will start immediately, if the register is written, even if the same value is re written to the register.
chapter 9 synchronous serial i/o (txsei) 9 - 15 the following figure shows the function of the inter - frame space timer: transfer 1 wait ifs transfer 2 sck transfer ifscounter storerxval loadtxval seifs seifs-1 0 1 2 figure 9.3 . 3 waveform while using inter - frame space timer 9.3.2 txsei buffer structure txsei has both a transmit and a receive buffer. the buffers are implemented as fifo and are able to store four frames each (one frame has a 16 - bit length). when a new txse i transfer is started by writing the data register, the transfer value is first stored in txsei?s transmit buffer. from there the value will be fetched by the shift register immediately, if the module is idle or after the currently running transfer has com pleted. a receive value from the shift register is stored in the receive buffer every time a transfer completes. txsei is able to generate interrupts depending on the fill - level of these buffers. therefore, it is possible to refill the buffers with sever al values within one interrupt service routine, if desired. 9.3.2.1 txsei system errors txsei is able to detect the following system errors during transfer: 9.3.2.2 seoe ? overflow error an overflow error will be generated, when the receive buffer is completely filled, while a new value has been completely received on the sei bus. in this case the data of the last transfer in the receive buffer is overwritten with the new value and the seoe flag in the sesr register is asserted. the seoe register gives the programmer an indication, that data consistency during the transfer was lost. 9.3.2.3 seue ? underflow error an underflow error is generated, if the module is in slave mode and the bus master performs a shift, when no output value has been specified by writing to the data reg ister.
chapter 9 synchronous serial i/o (txsei) 9 - 16 9.3.2.4 setf ? transfer format error this error is generated, if the transfer format is violated. there are two different scenarios, in which a transfer format error could occur. in slave mode, a transfer format error will be signaled, if: the slave sel ect pin is used for txsei purpose (configured in the port register) and txsei is in the middle of a transfer and the number of bits received yet is smaller than the number specified in the ssz (secr1) register and if the slave select signal is set inactive at this point. it signals the user, that the master ended the transfer before the expected end of the transfer. a possible cause for this error could be different transfer length settings for master and slave devices. the partially received value will not be stored in the receive buffer since it is not complete. in master mode, a transfer format error will be signaled, if: the slave select input signal is enabled in master mode (ssival bit in secr0 register) and both the master bit is set to one (mstr bit in secr0) and the system is in active mode (opmode=?10? in semcr) and the slave select signal is asserted. 9.4 interrupts txsei connects to three interrupt signals. seiexc: system error flags seoe, seue, setf, sidle (separately maskable) seirx rx buffer fill level interrupt, flag rbsi (not maskable) seitx tx buffer fill level interrupt, flag tbsi (not maskable) interrupt seiexc is used for error detection purpose (seoe, seue, setf) and idle state interrupt (sidle). the interrupts seirx and seitx are used to fetch and setup new data in an interrupt service routine for transferring data. all the interrupts will occur one system clock cycle later than the internal flags, which are visible in the status register.
chapter 10 asynchronous serial interface (uart) 10 - 1 10. asynchronous serial interface (uart) the asynchronous serial interface (uart) contains the following features: four channels full - duplex transfer baud rate generator modem flow control (cts/rts) transmit and receive fifo, each of size 2 tiers multi control ler system support (master/slave operation capable) 10.1 registers overview register (short name) physical address (hex) name function silcr 1c00 0000 line control register specify data format sidicr 1c00 0004 interrupt control register controls settings ab out interrupt and dma requests sidisr 1c00 0008 interrupt status register shows status information about interrupt and dma requests siscisr 1c00 000c status change register shows status information of uart transfer sifcr 1c00 0010 fifo control register controls settings of transmit/ receive fifo siflcr 1c00 0014 flow control register controls running transmission sibgr 1c00 0018 baud rate control register contains baud rate settings sitfifo 1c00 001c transmitter fifo register transmit data sirfifo 1c 00 0020 receiver fifo register received data this table includes the addresses of uart channel 0. channel 1 uses the addresses 1c00 0040 to 1c00 0060. channel 2 uses the addresses 1c00 0080 to 1c00 00a0. channel 3 uses the addresses 1c00 00c0 to 1c00 00e0.
chapter 10 asynchronous serial interface (uart) 10 - 2 line control register (silcr) bit 31 16 name ? bit 15 14 13 12 11 10 9 8 name rwub twub uode ? outsel irda lsbf bit 7 6 5 4 3 2 1 0 name ? scs ueps upen usbl umode bit name function reset value r/w 31:16 ? wired to zero 0 r 15 rwu b wake up bit for receive 0 = the uart does not wait for a wake - up - bit 1 = the uart is looking for a wake - up - bit used only in multi controller mode. 0 r/w 14 twub wake up bit for transmit 0 = next frame contains data (wake - up - bit = 0) 1 = next frame conta ins address (wake - up - bit = 1) the contents of this bit make only sense in multi controller mode. 1 r/w 13 uode open drain enable 0 = standard serial output on tx 1 = open drain serial output on tx when the uart is slave in a multi controller system, the serial output should set to open drain. 0 r/w 12:11 ? wired to zero 00 r 10 outsel clock output select 0 = clock frequency is the same as in baud rate register (sibgr) specified 1 = clock frequency is 16 times the value specified in baud rate register (s ibgr) 0 r/w 9 irda irda clock 0 = no output of irda clock 1 = output of irda clock it has no meaning when outsel = 1. 0 r/w 8 lsbf lsb first 0 = reads or sends the msb first 1 = reads or sends the lsb first 0 r/w 7 ? wired to zero 0 r 6:5 scs sio clock select 00 = internal system clock 01 = baud rate generator provided by internal clock 10 = external clock 11 = baud rate generator provided by external clock 10 r/w 4 ueps uart parity select 0 = odd parity 1 = even parity 0 r/w 3 upen uart parity enab le 0 = disable parity check 1 = enable parity check the bit should be 0 in the multi controller system mode (umode = 10, 11). 0 r/w 2 usbl uart stop bit length 0 = 1 bit 1 = 2 bit 0 r/w
chapter 10 asynchronous serial interface (uart) 10 - 3 bit name function reset value r/w 1:0 umode uart mode for the sio mode setting. 00 = 8 - bit data length 01 = 7 - bit data length 10 = multi controller 8 - bit data length 11 = multi controller 7 - bit data length 00 r/w note: the reception of a 1 - bit length stop bit while in a 2 - bit stop bit length setting does not generat e a frame error. interrupt control register (sidicr) bit 31 16 name ? bit 15 14 13 12 11 10 9 8 name tdr rdr tir rir spir ctsac ? bit 7 6 5 4 3 2 1 0 name ? sioe sicts sibrk sitr sias siub bit name function reset value r/w 31:16 ? wired to zero 0 r 15 tdr transmit dma request 0 = no dma request when free space in transmit fifo 1 = dma request when free space in transmit fifo 0 r/w 14 rdr receive dma request 0 = no dma request when data in receive fifo 1 = dma request when data in recei ve fifo 0 r/w 13 tir transmit interrupt request 0 = no interrupt when free space in transmit fifo 1 = send siotx interrupt when free space in transmit fifo 0 r/w 12 rir receive interrupt request 0 = no interrupt when error or time out occurs 1 = when err or or time - out occurs send siorx interrupt, when rdr=0, sioexc interrupt, when rdr=1 0 r/w 11 spir special interrupt request 0 = no interrupt when errors occur 1 = send sioexc interrupt, when errors occur 0 r/w 10:9 ctsac ctss status active conditi on sets condition of cts. 00 = disable cts 01 = cts terminal rising edge 10 = cts terminal falling edge 11 = both edges 0 r/w 8:6 ? wired to zero 0 r 5 sioe special interrupt on overrun error 0 = no actions on overrun error 1 = when an overrun error occu rs, send sioexc interrupt and set stis bit in interrupt status register (sidisr) 0 r/w
chapter 10 asynchronous serial interface (uart) 10 - 4 bit name function reset value r/w 4 sicts special interrupt on receive of cts 0 = no actions on cts 1 = when receiving cts, send sioexc interrupt and set stis bit in interrupt status register (sidisr) 0 r/w 3 sibrk special interrupt on break of uart transfer 0 = no actions on break 1 = when a break occurs, send sioexc interrupt and set stis bit in interrupt status register (sidisr) 0 r/w 2 sitr special interrupt on free space in transmit fifo (rbrkd) 0 = no actions on free space in transmit fifo 1 = when free space is detected, send sioexc interrupt and set stis bit in interrupt status register (sidisr) 0 r/w 1 sias special interrupt, when all data sent 0 = no actio ns, when all data sent 1 = when all data sent, transmit sioexc interrupt and set stis bit in interrupt status register (sidisr) 0 r/w 0 siub special interrupt on break of uart transfer (ubrkd) 0 = no actions on break 1 = when a break occurs, send sioexc interrupt and set stis bit in interrupt status register (sidisr) 0 r/w note: transmit interrupt request (sitxreq): the output is used as the interrupt output of scon for the transmit data empty. see table in section ?host interface? for possible settings. interrupt status register (sidisr) bit 31 16 name ? bit 15 14 13 12 11 10 9 8 name ubrk uvalid ufer uper uoer eri tout tdis bit 7 6 5 4 3 2 1 0 name rdis stis ? rfdn bit name function reset value r/w 31:16 ? wired to zero 0 r 15 ubrk break this bit will be set to 1, when break is detected 0 r 14 uvalid no data available this bit will be set to 1, when the receiver fifo contains no data. 1 r 13 ufer frame error this bit will be set to 1, when an error occurred during transfer of the current frame. 0 r 12 uper parity error this bit will be set to 1, when a parity error has been detected. 0 r 11 uoer over run error this bit will be set to 1, when an overrun error has occurred. 0 r
chapter 10 asynchronous serial interface (uart) 10 - 5 bit name function reset value r/w 10 eri error in terrupt this bit will be set to 1, when a framing error, parity error or overrun error has occurred. writing 0 to this bit clears it. writing 1 does not change contents of this bit. 0 r/w 9 tout receive time out this bit will be set to 1 immediately after a receive time out occurs. writing 0 to this bit clears it. writing 1 does not change contents of this bit. 0 r/w 8 tdis transmit dma/interrupt status this bit will be set to 1, when there is free space in the transmit fifo. 1 r/w 7 rdis receive dma/int errupt status this bit will be set to 1, when there are valid data in the receive fifo. 0 r/w 6 stis status interrupt status this bit will be set to 1, when the status, selected in stir of interrupt control register (sidice), has changed. 0 r/w 5 ? wired to zero 0 r 4:0 rfdn receive fifo data number status indicating the number of received data frames stored in the receiver fifo (0 to 2 tiers). 00000 r/w note: ubrk, uper and uoer show the status of the upper fifo tier. when software reads the next data tier, the uart will update the status information in ubrk, uper and uoer. thats the reason, why the software must read status information before reading the data. status change register (siscisr) bit 31 8 name ? bit 7 6 5 4 3 2 1 0 name ? oers ctss rbrkd trdy txals ubrkd bit name function reset value r/w 31:6 ? wired to zero 0 r 5 oers overrun error this bit will be set to 1, when an overrun error occurs. cleared by writing 0 0 r/w 4 ctss cts terminal indicates the cts terminal status. 0 = cts is deasserted 1 = cts is asserted 0 r 3 rbrkd receive break this bit will be set to 1, when the uart is in break status. 0 r 2 trdy tx ready set to 1 when the transmitter fifo has free space at least for one tier of data. 1 r 1 txals tx all set to 1 when transmitter fifo and transmitter shift register are empty. 1 r 0 ubrkd uart break detect set to 1 immediately when a break is detected. cleared by writing 0. 0 r/w
chapter 10 asynchronous serial interface (uart) 10 - 6 fifo control register (sifcr) bit 31 16 name ? bit 15 14 13 12 11 10 9 8 name swrst ? rdil bit 7 6 5 4 3 2 1 0 name rdil ? tdil tfrst rfrst frstew bit name function reset value r/w 31:16 ? wired to zero 0 r 15 swrst software reset 0 = normal operation 1 = softreset of uart this software reset lasts for 4 clock cycles . the channel will not react to any requests during this time period. warning: while using instruction cache of tx39 the following problem occurs: as it takes about 5 clock cycles to activate software reset this might affect the next write action to a regi ster of the channel being reset. solution: insert other instructions between resetting command and next write command of the same channel. 0 w 14:9 ? wired to zero 0 r 8:7 rdil receive dma/interrupt trigger level these bits determine at which fill level of the receive fifo the uart sends an interrupt or dma request. 00 = if 1 byte in receive fifo make a request 01 = if 2 bytes in receive fifo make a request others = invalid setting 00 r/w 6:5 ? wired to zero 0 r 4:3 tdil transmit dma/interrupt trigger l evel these bits determine at which fill level of the transmit fifo the uart sends an interrupt or dma request. 00 = if 1 byte in transmit fifo make a request 01 = if 2 bytes in transmit fifo make a request others = invalid setting 00 r/w 2 tfrst transmit fifo reset 0 = normal operation 1 = reset of transmit fifo (only when frstew = 1) 0 r/w 1 rfrst receive fifo reset 0 = normal operation 1 = reset of receive fifo (only when frdtew = 1) 0 r/w 0 frstew fifo reset enable 0 = resets of receive and transmit f ifo are inhibited 1 = resets of receive and transmit fifo are possible 0 r/w
chapter 10 asynchronous serial interface (uart) 10 - 7 flow control register (siflcr) bit 31 16 name ? bit 15 14 13 12 11 10 9 8 name ? rcs trs ? rtssc rsdr bit 7 6 5 4 3 2 1 0 name tsdr ? rtstl tbrk bit name funct ion reset value r/w 31:13 ? wired to zero 0 r 12 rcs rts control select selects the method to control the rts terminal. 0 = software control 1 = software or hardware control 0 r/w 11 trs tx request select selects the transmit request. 0 = control by tra nsmit serial data request (tsdr). 1 = control by transmit request command or the cts terminal (hardware control) 0 r/w 10 ? wired to zero 0 r 9 rtssc rts software control determines the output of the rts terminal. 0 = sets the rts terminal to 0 1 = sets the rts terminal to 1 0 r/w 8 rsdr receive serial data request 0 = received data will stored 1 = received data will throwed away 1 r/w 7 tsdr transmit serial data request 0 = transmission runs 1 = halts transmission. a running transmission will be finish ed. 1 r/w 6:5 ? wired to zero 0 r 4:1 rtstl rts trigger level sets the rts hardware control assert level at the number of receive data tiers in the receiver fifo. possible settings: 0001, 0010 0001 r/w 0 tbrk transmitter break 0 = normal operation 1 = t ransmit a break 0 r/w
chapter 10 asynchronous serial interface (uart) 10 - 8 baud rate control register (sibgr) bit 31 16 name ? bit 15 11 10 9 8 7 0 name ? bclk brd bit name function reset value r/w 31:11 ? wired to zero 0 r 10:8 bclk baud rate generator clock specifies the prescaler f or the input clock of baud rate generator. 000 = 1/2 system frequency 001 = 1/8 system frequency 010 = 1/32 system frequency 011 = 1/128 system frequency 1xx = system frequency (prescaler bypass) 011 r/w 7:0 brd baud rate divisor set the baud rate divisor . 0xff r/w transmitter fifo register (sitfifo) bit 31 8 7 0 name ? txd bit name function reset value r/w 31:8 ? wired to zero 0 r 7:0 txd transmit data data written to this register are carried to transmit fifo. note: the bits are write - onl y. 0 w receiver fifo register (sirfifo) bit 31 8 7 0 name ? rxd bit name function reset value r/w 31:8 ? wired to zero 0 r 7:0 rxd receive data read this register to get next data item from the receiver fifo. 0 r note: the receiver fifo re gister can only be read by a 32 - bit - word access.
chapter 10 asynchronous serial interface (uart) 10 - 9 10.2 operations on serial interface 10.2.1 outline the uart converts serial input data to parallel data by a shift register. the converted parallel data is stored in the receiver buffer. the stored data is fetched by a dma transfer or an interrupt. during transmission parallel data from memory is written to a transmitter buffer by a dma transfer or an interrupt. the parallel data is converted to serial output data using a shift register. the clock has an elementary fu nction during transmitting and receiving. it is generated by the baud rate generator. the frequency is set by a register (sibgr).
chapter 10 asynchronous serial interface (uart) 10 - 10 10.2.2 data format the applicable data format for sio is as follows: data length 7/8/9 - bit (9 - bit data is practicable for a multi controller system) stop bit 1/2 - bit parity bit provided / not provided parity system even/odd start bit 1 - bit fixed data format msb/lsb first (switchable by the register setting) the data frame structure is described on the next page. please note that sen ding a parity bit is not allowed for address transmission in a multi - controller system. 8-bit data start bit0 bit1 bit5 bit4 bit3 bit2 bit6 bit7 stop stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 bit7 stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 stop stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 stop parity stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 stop parity 7-bit data 1 2 3 4 5 6 7 8 9 10 11 12 start bit0 bit1 bit5 bit4 bit3 bit2 bit6 bit7 stop parity stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 bit7 stop parity 1 2 3 4 5 6 7 8 9 10 11 12 stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 bit7 stop wub start bit0 bit1 bit5 bit4 bit3 bit2 bit6 bit7 stop wub 1 2 3 4 5 6 7 8 9 10 11 12 7-bit data multi control system 8-bit data multi control system start bit0 bit1 bit5 bit4 bit3 bit2 bit6 stop wub stop start bit0 bit1 bit5 bit4 bit3 bit2 bit6 stop wub 1 2 3 4 5 6 7 8 9 10 11 12 wub=wake up bit 1: address (id) frame 0: data frame figure 10.2 . 1 data formats for uart transmissions
chapter 10 asynchronous serial interface (uart) 10 - 11 10.2.3 serial clock generator the transmit/rec eive clock regulating the transferrate for the serial interface is selected from: baud rate generator output, internal system clock or external clock the following figure shows principle structure of the serial clock generator: sioclk t0 t2 t4 t6 clk select divider baud rate divider value select o r select o r external clock sioclk select silcr scs[0]> baud rate generator sibgr sibgr prescaler system clock select o r sioclk select silcr scs[1]> 1/16 f igure 10.2 . 2 serial clock generator structure the baud rate generator creates the transmit/receive clock which regulates the transfer rate for the serial interface. the baud rate can be calculate by the fol lowing formula: 8 generator rate baud of divisor prescaler frequency input rate baud = select the prescaler for the baud rate generator input clock. the selected clock is divided by the value corresponding to the setting in the baud rate control register (divisor: 1, 2, 3, ?, 255). the following table shows the output frequency of the baud rate generator (sioclk) in depending of the baud rate divisor and the prescaler: baud generator input baud generator divisor precaler 1/2 (t0) prescaler 1/8 (t2) prescaler 1/32 (t4) prescaler 1/128 (t6) 60 mhz 5 750 .00 khz 187.50 khz 46.88 khz 11.72 khz 60 mhz 10 375.00 khz 93.75 khz 23.44 khz 5.86 khz 60 mhz 25 150.00 khz 37.50 khz 9.38 khz 2.34 khz
chapter 10 asynchronous serial interface (uart) 10 - 12 10.2.4 receiver control after accepting the receive enable, the receive control is looking for the start bit on the seria l input line (rx). a ?0? on serial input only will be recognized as start bit, if a ?1? was detected in the bit before. when the receive control detects a start bit, the receiving operation will start. the output of the baud rate generator (sioclk) is 16 times the frequency of the data transfer rate on serial interface. the serial data input (rx) will be sampled on 7 th , 8 th and 9 th clock of sioclk. a majority logic determines the input value. the receiver shift register consists of an 8 - bit shift register . on the end of transfer bit 0 of the shift register contains the bit which was received at first. the receiver read buffer resides between the receiver shift register and the receiver fifo buffer. after receiving a data frame, the parity check will be do ne in this register. 10.2.5 transmitter control the output of the baud rate generator (sioclk) is 16 times the frequency of the data transfer rate on serial interface. the transmitter shift register is an 8 - bit shift register. the transmitter shift register get s its data from the transmitter fifo. bit 0 of the shift register will be send first. 10.2.6 host interface the data transfer to the transmitter fifo can be handled via interrupt processing or via dma transfer. if the transmitter fifo has as much free space as s et in the transmit dma interrupt trigger level (tdil in fifo control register), an interrupt or dma request is generated. afterwards the dma controller or the software fetches data from memory and writes the data to the transmitter fifo. the data transfer from the receiver fifo can be handled via interrupt processing or via dma transfer. if the receiver fifo has as much free space as set in the transmit dma interrupt trigger level (rdil in fifo control register), an interrupt or dma request is generated. a fterwards the dma controller or the software fetches data from the receive fifo and writes it to the memory. the following settings of tdr, rdr, tir and rir of interrupt control register ( sidicr ) are allowed: tdr rdr tir rir transmit receive 0 0 0 0 tdi s polling rdis polling 0 0 0 1 tdis polling interrupt 0 0 1 0 interrupt rdis polling 0 0 1 1 interrupt interrupt 0 1 0 0 tdis polling dma 0 1 1 0 interrupt dma 1 0 0 0 dma rdis polling 1 0 0 1 dma interrupt 1 1 0 0 dma dma
chapter 10 asynchronous serial interface (uart) 10 - 13 10.2.7 flow control transmissi on enable can be set either via software control by a transmit serial data request of the cpu (tsdr) or via hardware control by applying a logical or to the signals rts and cts. when the transmit enable becomes inactive, the transmission will be suspende d after the completion of the current data transmission. reception is enabled either via rts software control of the cpu (rtssc) or via hardware control by applying a logical or to the signals rts and cts. for hardware control, the flow control offers t he possibility of a dma transfer or an interrupt request. this can be configured using register sidicr. during reception, the transmitter can request temporary suspension by turning the rts signal to high. the transmission is resumed by turning rts signal to low when reception is ready. frame by frame data transfer is available by setting the transmitter to hardware control (tes=1) and the receiver rtstr to 1 (handshaking). 10.2.8 parity control during transmission , the parity is generated when the data is writ ten to the transmitter shift register. the parity is stored in bit 7 of the transmitter shift register for the 7 - bit data length or in twub of the line control register for the 8 - bit data length. during reception , the parity check is executed when the da ta is written from the receiver shift register to the receiver read buffer. a parity error occurs when a difference between received and calculated parity bit is found. the parity is stored in bit 7 of the read buffer for the 7 - bit data length or in rwub of the line control register for the 8 - bit data length. 10.2.9 error flags the following error flags can be handled: overrun error occurs on overflow of transmit or receive buffer. parity error occurs when the received parity and the calculated parity are not t he same. framing error occurs when 0 is detected at the stop bit during receive.
chapter 10 asynchronous serial interface (uart) 10 - 14 10.2.10 receiver break when a framing error occurs in the received data and every bit in a data frame is "0", the frame is interpreted as a break and the rbrkd bit in the status ch ange register ( siscisr ) is set. 10.2.11 receive time out a receive time out occurs when the receiver fifo has received at least 1 - byte and an equivalent of a 2 - byte receive time is elapsed from the previous reception. that sets the receive time - out bit (tout) in the dma/interrupt status (sidisr). 10.2.12 handling of receive data transfer and status bit in receiver fifo the following status information is stored in the receiver fifo along with the received data: uart receiver break (ubrk) uart available status (uvalid) u art frame error (ufer) uart parity error (uper) uart overrun error (uoer) the software can read the status in the dma/interrupt status register (sidisr). the status is updated when data from receiver fifo will be read (sirfifo). the receive data, which i s transferred without errors, can be read from the receiver fifo. new tiers in receiver fifo will be indicated by a receive interrupt request. errors during receive will be indicated by an exception interrupt request. only received data without errors are transferable via dma. when an error (ufer, uper, uoer) or a receive time - out (tout) occurs, the receive data transfer request is asserted and the receive error is notified. 10.2.13 multi controller system when umode in the line control register (silcr) is 10 or 11, the uart changes into the multi controller system mode. in a multi controller system, the master controller sends data to the selected slave controllers. the slaves will be selected by sending an address id before sending the data. non - selected slave c ontrollers will ignore the data. the transmission of the address id is indicated by setting wub in the frame to 1. for data transmission set wub to 0. the software makes the address id comparison. protocol of multi controller system: 1. the master and slave controllers set the umode to 10 or 11 in the line control register to get into multi controller mode. 2. each slave controller sets the rwub in the line control register to 1 to be ready to receive the address id frame from the master controller. 3. the master controller sets the wub of the transmit frame to 1 (line control register wub=1) to send the slave controller address id (7 or 8 - bit length). 4. an interrupt is generated in a slave controller when rwub in line control register is 1 and wub
chapter 10 asynchronous serial interface (uart) 10 - 15 of the received data frame is 1 (receive data is an address frame). the software compares its address id with the received address id and set rwub to 0 when both match. 5. when the master controller sends data frames to the specified slave controllers, the wub in the data f rame is set to 0 (line control register twub=0). 6. the selected slave controller generates an interrupt, when it receives data. in the non - selected slave controller, where rwub is still set to 1, no interrupt will be generated. in this case the received dat a is ignored. the slave controllers can send data only to the master controller. an example of the multi controller system configuration is shown below: master sout sin sin sout slave#1 sin sout slave#2 sin sout slave#3 figure 10.2 . 3 example for multi controller system the slave output (tx) must be open drain. the serial output of TMPR3916F becomes open drain when the uode in line control register is set to 1.
chapter 10 asynchronous serial interface (uart) 10 - 16 10.3 timing receive operation: (7, 8 - bit data length) 1 7 8 9 16 bit0 bit7 16 7 8 9 sioclk sin valid bit0 valid bit7 10 11 10 11 7 8 9 10 11 parity bit sintreq * sintreq * 1 16 7 8 9 10 11 1 16 stop bit data sintreq * if framing error occur if parity error occur dma/interrupt status reg. < eri >=1 overrun error dma/interrupt status reg. < eri >=1 dma/interrupt status reg. < eri >=1 figure 10.3 . 1 receiving 7 or 8 bit data receive operation: (7, 8 - bit length multi controller system; rwub=1 for id receive standby) 1 7 8 9 16 bit0 bit7 16 7 8 9 sioclk sin valid bit0 valid bit7 10 11 10 11 7 8 9 10 11 wake up bit =1 s p intreq * s p intreq * 1 16 7 8 9 10 11 1 16 stop bit data s pi ntreq * if framing error occur overrun error dma/interrupt status reg. < eri >=1 dma/interrupt status reg. < eri >=1 figure 10.3 . 2 receiving 7 or 8 bit id in multi controller environment receive operation: (7, 8 - bit length multi controller system; rwub=0 for data receive standby) 1 7 8 9 16 bit0 bit7 16 7 8 9 sioclk sin valid bit0 valid bit7 10 11 10 11 7 8 9 10 11 wake up bit = 0 s p intreq * s p intreq * 1 16 7 8 9 10 11 1 16 stop bit data s p intreq * if framing error occur overrun error dma/interrupt status reg. < eri >=1 dma/interrupt status reg. < eri >=1 figure 10.3 . 3 receiving 7 o r 8 bit data in multi controller environment
chapter 10 asynchronous serial interface (uart) 10 - 17 receive operation: (7, 8 - bit length multi controller system; rwub=1 for data skip) 1 7 8 9 16 bit0 bit7 16 7 8 9 sioclk sin valid bit0 valid bit7 10 11 10 11 7 8 9 10 11 wake up bit = 0 s p intreq * s p intreq * 1 16 7 8 9 10 11 1 16 stop bit data s p intreq * if framing error occur over run error dma/interrupt status reg. < eri >=1 dma/interrupt status reg. < eri >=1 figure 10.3 . 4 receiving 7 or 8 bit data skip multi co ntroller environment transmit operation 1 1 16 bit0 bit7 16 sioclk sout trans. fifo to trans. shift reg. shift-out timing 16 1 start bit 16 1 1 16 1 16 (wake up bi t ) stop bit 16 bit n parity bit figure 10.3 . 5 transmitting 8 bit data transmit halt timing by cts* 1 1 16 bit0 16 sioclk sout trans. fifo to trans. shift reg. shift-out timing 16 start bit 16 1 1 16 bit n cts * stop bit trans. halt trans,start figure 10.3 . 6 transmitting halt command when cts becomes 1 during data transmission, the data transfer halts after completing the current data transmission. despite the halt, the next data is stored in the transmitter shift register. the transmission i s restarted at the first shift out pulse after cts becomes low.
chapter 10 asynchronous serial interface (uart) 10 - 18
capter 11 electrical characteristics 11 - 1 11. electrical characteristics 11.1 dc characteristics of TMPR3916F parameter symbol min typ max unit supply voltage v dd 3.0 3.3 3.6 v operating temperature ta - 40 85 c power dissipation (normal mode) p d mw operating current normal mode standby mode i dd i dds ma a low level input voltage ttl inputs (1) (2) others v il - 0.3 - 0.3 0.8 0.2 v dd v v high level input voltage standard ttl inputs (1) 5 v tolerant ttl inputs (2) 5 v tolerant cmos inputs (3) others v ih 2.0 2.0 0.8 v dd 0.8 v dd v dd + 0.3 7 7 v dd + 0.3 v v v v low level input current standard input buffer input buffer with pull - up (4) i il 10 200 a a high level input current i ih 10 a low level output voltage v ol 0.4 v high level output voltage v oh 2.4 v output curre nt pio, can, hdisp others i ol 4 8 ma ma output buffer capacity c in 6.81 pf input buffer capacity c out 6.81 pf i/o buffer capacity c io 6.81 pf (1) the following inputs are ttl inputs: sdi, buserr, ack, rxcan1, rxcan0 (2) the following inputs are 5v - tolerant ttl inputs: sdi, buserr, ack, rxcan1, rxcan0 (3) the following inputs are 5v - tolerant cmos inputs: pio0 .. pio29, vsync, hsync, dotclk, hdisp, txcan0, txcan1, rxcan0, rxcan1 (4) the following inputs have an integrated pull - up resistance: vsync, hsync, do tclk, dreq0, d0, reset, ext0, ext1, ext2, nmi, dbge, dreset, buserr, ack, rxcan0, rxcan1, pio16, pio18, pio19, pio21, pio22, pio23, pio25, pio26, pio27, pio29
chapter 11 electrical characteristics 11 - 2 11.2 power up sequence vdd plloff * pllcircuit output clken output clock external reset a26 value(1) internal reset t staosc t stapll t a26sample note 1: a26 stabilization determined by rc delay consider load on a26 for selection of pull-up/pull-down value t resetintdelay figure 11.2 . 1 waveform for TMPR3916F?s power - up sequence parameter symbol min typ max unit oscillator starting time t staosc 500 s pll starting time t stapll 500 s reset hold time t resethold 25 cycles (1) a26 sample time t a26sample 4 cycles (1) initial delay after reset t resetintdelay 1000 1050 cycles (1) (1) cycle means one systemcycle of TMPR3916F (at 60 mhz one cycle is 16,7 ns)
capter 11 electrical characteristics 11 - 3 11.3 crystal oscillator an example of application circuit: tx3903bf xtal1 xtal2 r fb xtal r d c out1 c in c out2 l out figure 11.3 . 1 connecting crystal oscillator parameter symbol min typ max unit oscillator frequency f 8 10 mhz oscillation starting voltage v sta v oscillation holding voltage v hold v supply current i dd ma oscilla tion starting time t sta ms feedback resistor r fb m w output resistor r d w external capacitor c in c out1 c out2 pf pf pf external inductance l out h
chapter 11 electrical characteristics 11 - 4 11.4 view dac dc characteristics: parameter symbol min typ max unit resolution (each dac) 8 (1) bits accuracy (each dac) integral linearity error differential linearity error i l d l ? ? lsb lsb analog output current white level white level from black level black level blank level 19.05 17.61 1.44 0.00 ma ma ma ma lsb size 69.06 a voltage - reference input current 1.66 ma stand - by current 0.00 ma (1) only upper six bits are used in TMPR3916F, lower two bits are wired to zero ac characteristics: parameter symbol min typ max unit clock rate f max 175 mhz clock cycle time t ck 5.72 ns analog output full scale delay t od 1.8 ns full scale rise/fall time (10% to 90%) t or 0.78 ns glitch impulse 32.5 pv - sec power supply current i aa 70 ma connectivity of viewdac: tx3916f 0.1 d v c c d g n d a g n d 4 a g n d 3 a g n d 2 v r e f v b s f s a d j r o u t a v c c 3 g o u t a v c c 2 b o u t a v c c 1 a g n d 1 3.3 v rgb output 10 10 0.1 0.1 0.1 0.1 745 37.5 37.5 37.5 1.235v * to reduce the noise, please place ceramic capacitors of 0.1uf between dvcc/dgnd, avcc3/agnd3, avcc2/agnd2 and avcc1/agnd1 as close as possible to the pads * us e seperate ground lines/planes for the digital and the analog ground in order to avoid analog ground level shift as a result of the current through the dgnd terminal 3.3 k figure 11.4 . 1 applying external connectivity for digital/analog converter
capter 11 electrical characteristics 11 - 5 11.5 standby mode timing to resume the pll circuit operations, set the plloff* pin to ?high? and the clken pin to high. at that time, a period of 500 m s is required for the pll circuit oscillation to stabilize. the following diagram shows the corresponding timing: sysclk clken min 500 m s plloff * pll oscillation pllstop figure 11.5 . 1 standby mode waveform 11.6 boot device by using the following application circuit, the user can choose between 16 bit and 32 bit boot device. tx3916f a26 memory device r= 47kohm vcc vss jumper jumper connected to ... vcc => boot by 16 bit device vss => boot by 32 bit device figure 11.6 . 1 applying external boot mode selection circuit
chapter 11 electrical characteristics 11 - 6 11.7 sdram timing a[31:0] be[3:0] we ras, cas sysclk d out [31:0] write access read access a[31:0] be[3:0] we ras,cas sysclk d in [31:0] t dos sample point t doh t dis t dih figure 11.7 . 1 sdram interface timing diagram parameter symbol min typ max unit output setup time t dos 6 11 14 ns output hold time t doh 2.5 3 5 ns input setup time t dis tbd ns input h old time t dih tbd ns 11.8 rom / sram timing write access a[31:0] wr be[3:0] cs a[31:0] wr be[3:0] cs read access sample point d out [31:0] d in [31:0] t roc t roh t dis t dih figure 11.8 . 1 memc interface timing diagram parameter symbol min typ max unit cycle length t roc 2 cycles (1) output hold time t ro h 1 cycles (1) input setup time t ris tbd ns input hold time t rih tbd ns (1) cycle means one systemcycle of tx3903bf (at 60 mhz one cycle is 16,7 ns)
capter 11 electrical characteristics 11 - 7 11.9 external slave write timing: a[31:0] sysclk t eos1 cs be[3:0] bstart last wr ack t eos2 d out [31:0] t eoh1 t eis2 t eih2 t eoh2 parameter symbol min typ max unit out put setup time of cs, a, be, d t eos1 4.5 10.5 13 ns output hold time of cs, a, be, d t eoh1 3.4 6 11 ns output setup time of bstart, last, wr, dack t eos2 7.5 12 14 ns output hold time of bstart, last, wr, dack t eoh2 2.5 4.5 8.5 ns input setup time of ac k t eis2 tbd ns input hold time of ack t eih2 tbd ns read timing: a[31:0] sysclk d in [31:0] t eis1 cs be[3:0] bstart last wr ack sample point t eis1 parameter symbol min typ max unit input setup time of d[31:0] t eis1 tbd ns input hold time of d[31:0] t eih1 tbd ns
chapter 11 electrical characteristics 11 - 8 dma timing: dreq sysclk t mis dack t mih t mos t moh parameter symbol min typ max unit output setup time of dack t mos 9 12 14 ns output hold time of dack t moh 2 4 7 ns input setup time of dreq t mis tbd ns input hold time of dreq t mih tbd ns 11.10 external interrupts and nmi the external i nterrupts (ext0, ext1, ext2) and the nmi can set asynchronous to system clock. all interrupt inputs are low active. parameter symbol min typ max unit length of asynchronous interrupt t irql 2 cycles (1) (1) cycle means one systemcycle of TMPR3916F (at 60 mhz one cycle is 16,7 ns) 11.11 general purpose i/os (port module) the inputs to the general purpose i/os can given asynchronous to system clock. parameter symbol min typ max unit length of input signal t gpl 10 cycles (1) sample frequency f gps 7.5 (2) mhz (1) cycle means one systemcycle of TMPR3916F (at 60 mhz one cycle is 16,7 ns) (2) at 60 mhz system clock
capter 11 electrical characteristics 11 - 9 11.12 txsei timing tx rx ssi / sso clk t sss 1/f sei t sts t sth t srs t srh figure 11.12 . 1 timing diagram for dma request parameter symbol min typ max unit sei clock frequency f sei 15 (1) mhz output setup time on tx t sts ? sei clock output hold time on tx t sth ? sei clock input setup time on rx t srs tbd ns input hold time on rx t sth tbd ns driver setup time on sso/ ssi t sss 2 cycles (2) (1) at 60 mhz system clock (2) cycle means one systemcycle of TMPR3916F (at 60 mhz one cycle is 16,7 ns)
chapter 11 electrical characteristics 11 - 10
chapter 12 package dimension 12 - 1 12. package dimension 12.1 pin assignment 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 clken plloff an39vdd vdd3 xtal2 xtal1 vss3 an39gnd vss vdd vss2 d8 d7 d6 d5 d4 vdd vss d3 d2 d1 d0 pio0 pio1 pio2 pio3 pio4 vdd3 vss3 pio5 pio6 vss pio7 pio8 pio9 vss2 vdd pio10 pio11 pio12 pio13 pio14 vss pio15 pio16 pio17 pio18 pio19 pio20 pio21 vdd3 vss3 157 d9 vdd 104 158 d10 vss 103 159 d11 pio22 102 160 d12 pio23 101 161 d13 pio24 100 162 d14 pio25 99 163 vss pio26 98 164 d15 pio27 97 165 d16 vss2 96 166 d17 vdd 95 167 d18 pio28 94 168 vdd pio29 93 169 vss2 dotclk 92 170 d19 hsync 91 171 d20 vsync 90 172 d21 hdisp 89 173 vss3 vss 88 174 vdd3 vdd3 87 175 d22 vss3 86 176 vss dreset 85 177 d23 sdi 84 178 d24 dbge 83 179 d25 sdao 82 180 d26 pcst0 81 181 d27 pcst1 80 182 d28 pcst2 79 183 d29 dclk 78 184 vdd vss 77 185 d30 rxcan0 76 186 vss txcan0 75 187 d31 rxcan1 74 188 a2 txcan1 73 189 a3 vdd 72 190 vss3 vss 71 191 vdd3 vss2 70 192 a4 dgnd 69 193 a5 dvcc 68 194 a6 avcc1 67 195 a7 agnd3 66 196 a8 avcc2 65 197 vss vref 64 198 a9 vbs 63 199 vss2 agnd2 62 200 vdd fsadj 61 201 a10 agnd1 60 202 a11 bout 59 203 a12 gout 58 204 a13 rout 57 205 a14 agnd5 56 206 a15 agnd4 55 207 a16 avcc3 54 208 a17 not connected 53 a18 a19 vss2 vdd a20 a21 a22 a23 a24 a25 a26 rd wr vss vdd last bstart burst cke we be3 be2 be1 be0 reset vss vdd vss2 buserr dreq0 dack0 vdd3 vss3 ext2 ext1 ext0 ack nmi sysclk ras cas cs5 vss2 vdd vss cs4 cs3 cs2 cs1 cs0 vdd test0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 tx3916f figure 12.1 . 1 TMPR3916F?s pin assignment
cha pter 12 package dimension 12 - 2 the following table divides the different pins into functional groups. TMPR3916F provides pins, which h ave a shared functionality. therefore you can find one and the same pin up to three times in different groups (like pio18/tx(sei)/tx(sio0) pin). classification pin name pin no. i/o level active a[26] / boot16 11 i/o ? a[25:20] 10 ~ 5 o ? a[19:18 ] 2 ~ 1 o ? a[17:10] 208 ~ 201 o ? a[9] 198 o ? a[8:4] 196 ~ 192 o ? a[3:2] 189 ~ 188 o ? be[3:0] * 21 ~ 24 o low d[31] 187 i/o ? d[30] 185 i/o ? d[29:23] 183 ~ 177 i/o ? d[22] 175 i/o ? d[21:19] 172 ~170 i/o ? d[18:15] 167 ~ 164 i/o ? d[14:9] 162 ~ 157 i/o ? d[8:4] 145 ~ 141 i/o ? d[3:0] 138 ~ 135 i/o ? control signals rd * 12 o low wr * 13 o low last * 16 o low bstart * 17 o low burst * 18 o low buserr * 29 i low ack * 37 i low reset * 25 i low clock signals xtal1 151 i ? xtal2 152 o ? sysclk 39 o ? plloff * 155 i low core clken 156 i high cs1 * 49 o low cs0 * 50 o low ras * 40 o low cas * 41 o low cke 19 o high sdram we * 20 o low cs5 * 42 o low cs4 * 46 o low cs3 * 47 o low memc cs2 * 48 o low hsyn c * 91 i/o low vsync * /csync * 90 i/o low hdisp 89 o high dotclk 92 i/o ? pio0/digital b out[0] 134 i/o ? pio1/digital b out[1] 133 i/o ? pio2/digital b out[2] 132 i/o ? pio3/digital b out[3] 131 i/o ? gdc pio4/digital b out[4] 130 i/o ?
chapter 12 package dimension 12 - 3 classi fication pin name pin no. i/o level active pio5/digital b out[5] 127 i/o ? pio6/digital g out[1] 126 i/o ? pio7/digital g out[2] 124 i/o ? pio8/digital g out[3] 123 i/o ? pio9/digital g out[4] 122 i/o ? pio10/digital g out[5] 119 i/o ? pio 11/digital r out[1] 118 i/o ? pio12/digital r out[2] 117 i/o ? pio13/digital r out[3] 116 i/o ? pio14/digital r out[4] 115 i/o ? pio15/digital r out[5] 113 i/o ? rout 57 a. o ? gout 58 a. o ? bout 59 a. o ? vbs 63 ? vref 64 ? gdc fsadj 61 ? dreq0 * 30 i low dmac dack0 * 31 o low tx(can1) 73 o ? rx(can1) 74 i ? tx(can0) 75 o ? txcan rx(can0) 76 i ? pio18/tx(sei)/tx(sio0) 110 i/o ? pio17/rx(sei)/rx(sio0) 111 i/o ? pio16/clk(sei)/clk(sio0) 112 i/o ? pio19/ssi * (sei)/clk( sio1) 109 i/o low txsei pio22/sso * (sei)/rts * (sio1) 102 i/o low pio29/tx(sio3) 93 i/o ? pio28/rx(sio3) 94 i/o ? pio27/cts * (sio2) 97 i/o low pio26/rts * (sio2) 98 i/o low pio25/tx(sio2) 99 i/o ? pio24/rx(sio2) 100 i/o ? pio23/cts * (sio1) 101 i/o l ow pio22/sso * (sei)/rts * (sio1) 102 i/o low pio21/tx(sio1) 107 i/o ? pio20/rx(sio1) 108 i/o ? pio19/ssi * (sei)/clk(sio1) 109 i/o ? pio18/tx(sei)/tx(sio0) 110 i/o ? pio17/rx(sei)/rx(sio0) 111 i/o ? uart pio16/clk(sei)/clk(sio0) 112 i/o ? pio29/ tx(sio3) 93 i/o ? pio28/rx(sio3) 94 i/o ? pio27/cts * (sio2) 97 i/o ? pio26/rts * (sio2) 98 i/o ? pio25/tx(sio2) 99 i/o ? pio24/rx(sio2) 100 i/o ? pio23/cts * (sio1) 101 i/o ? pio22/sso * (sei)/rts * (sio1) 102 i/o ? pio21/tx(sio1) 107 i/o ? pio20/ rx(sio1) 108 i/o ? pio19/ssi * (sei)/clk(sio1) 109 i/o ? port pio18/tx(sei)/tx(sio0) 110 i/o ?
cha pter 12 package dimension 12 - 4 classification pin name pin no. i/o level active pio17/rx(sei)/rx(sio0) 111 i/o ? pio16/clk(sei)/clk(sio0) 112 i/o ? pio15/digital r out [5] 113 i/o ? pio14/digital r out [4] 115 i/o ? pio13/digital r out [3] 116 i/o ? pio12/digital r out [2] 117 i/o ? pio11/digital r out [1] 118 i/o ? pio10/digital g out [5] 119 i/o ? pio9/digital g out [4] 122 i/o ? pio8/digital g out [3] 123 i/o ? pio 7/digital g out [2] 124 i/o ? pio6/digital g out [1] 126 i/o ? pio5/digital b out [5] 127 i/o ? pio4/digital b out [4] 130 i/o ? pio3/digital b out [3] 131 i/o ? pio2/digital b out [2] 132 i/o ? pio1/digital b out [1] 133 i/o ? port pio0/ digital b out [0] 134 i/o ? ext2 * 34 i low ext1 * 35 i low ext0 * 36 i low intc nmi * 38 i low vdd 4, 15, 27, 44, 51, 72, 95, 104, 120, 140, 147, 168, 184, 200 ? vdd3 32, 87, 106, 129, 153, 174, 191 ? vss 14, 26, 45, 71, 77, 88, 103, 114, 125, 13 9, 148, 163, 176, 186, 197 ? vss2 3, 28, 43, 70, 96, 121, 146, 169, 199 ? vss3 33, 86, 105,128, 150, 173, 190 ? avcc1 67 avcc2 65 avcc3 54 dvcc 68 dgnd 69 an39vdd 154 ? an39gnd 149 ? agnd1 60 ? agnd2 62 ? agnd3 66 ? agnd4 55 ? power agnd5 56 ? dclk 78 o ? pcst2 79 o ? pcst1 80 o ? pcst0 81 o ? sdao/tpc 82 o ? dbge * 83 i low sdi/dint * 84 i low dsu dreset * 85 i low test test0 52 i high not connected n/c (1) 53 (1) recommendation: connect unconnected pins to ground!
chapter 12 package dimension 12 - 5 12.2 pin functions classification pin name pin function a[26:2] address signal output pins. the a26 pin has a special functionality. the level supplied to this pin is latched with the rising edge of the reset * signal. the level determin es whether to boot from a device with 16 - bit or 32 - bit width. supplying ?high? lets the TMPR3916F boot from a 16 - bit device. be[3:0] * byte enable output pins the byte enable signals are used to select the bytes within the word, which are accessed by the current write or read access. the following list shows the relationship between byte enable signals and the valid bytes on the data bus. be * [0] low => d[7:0] valid be * [1] low => d[15:8] valid be * [2] low => d[23:16] valid be * [3] low => d[31:24] valid d[31 :0] data input/output pins rd * the rd * signal is asserted during a read access to the external bus interface. wr * the wr * signal is asserted during a write access to the external bus interface. last * the last * signal is asserted if the final data of the current bus operation is read or written. bstart * the bstart * signal is asserted for one cycle at the beginning of an external bus interface access. burst * the burst * signal indicates that the current access is a burst access. buserr * bus operati on input pin. if an error occurs during the current transaction the external device has the opportunity to signal this event to the TMPR3916F by asserting the buserr * signal. thereupon the TMPR3916F will finish the access and will create a bus - error except ion. ack * acknowledge signal input pin. during a read access the external device acknowledges data - transfers of a transaction by asserting the ack * signal. the data on the external bus interface will be sampled on the rising edge of system clock. during a write access the external device signals the TMPR3916F that the data was captured by asserting the ack * signal. the TMPR3916F will complete the transaction. core reset * if a low level is applied to the reset * signal the chip will go into the reset state. xtal1 input pin for the crystal. xtal2 feedback output pin for the crystal. sysclk output of system clock, which is the reference clock for bus operation. plloff * master clock switching pin. inputting a ?high? signal to this pin uses the built - in pll circuit as the master clock. master clock frequency is eight times the external clock. inputting a low signal to this pin halts the built - in pll circuit oscillation and uses the external clock as master clock. clock generator clken the clock enable pin enables supply of crystal input to internal pll. this signal is high active. cs1 * chip select 1 * signal for the external sdram device. cs0 * chip select 0 * signal for the external sdram device. ras * cas * we * the three signals row access strobe (r as * ), column access strobe (cas * ) and write enable (we * ) are used to supply the sdram with commands. sdram cke the clock enable pin is an output to sdram used for power saving purposes.
cha pter 12 package dimension 12 - 6 classification pin name pin function cs5 * the chip select signal 5 will be asserted if an access to the address range specified in the rccr5 register will take place. cs4 * the chip select signal 4 will be asserted if an access to the address range specified in the rccr4 register will take place. cs3 * the chip select s ignal 3 will be asserted if an access to the address range specified in the rccr3 register will take place. mc cs2 * the chip select signal 2 will be asserted if an access to the address range specified in the rccr2 register will take place. hsync * hori zontal sync signal input/output pin. vsync * /csync * vertical sync signal input/output pin or the composite sync signal output pin. the composite sync signal is the logic ex - nor (exclusive nor) operation on signals hsync * and vsync * hdisp while the viewa ble area of the current line is output by the gdc the hdisp is set to logic one. data can be read with one cycle latency to this signal. dotclk dot clock input/output pin. the dot clock is the reference clock for the display. this clock is either input t o or output by the TMPR3916F. pio15/digital r out[5] pio14/digital r out[4] pio13/digital r out[3] pio12/digital r out[2] pio11/digital r out[1] the general purpose input/output signals pio11 to pio15 (5bit) can be switched in that way that the red inten sity of the current pixel is output. pio15/digital r out[5] is the msb. pio10/digital g out[5] pio9/digital g out[4] pio8/digital g out[3] pio7/digital g out[2] pio6/digital g out[1] the general purpose input/output signals pio6 to pio10 (5 bit) can be switched in that way that the green intensity of the current pixel is output. pio10/digital g out[5] is the msb. pio5/digital b out[5] pio4/digital b out[4] pio3/digital b out[3] pio2/digital b out[2] pio1/digital b out[1] pio0/digital b out[0] the gene ral purpose input/output signals pio0 to pio5 (6 bit) can be switched in that way that the blue intensity of the current pixel is output. pio5/digital b out[5] is the msb. rout gout bout output pins for the three primary color video (analog) signals used as color source for display. rout is the red video signal output pin, gout the green and bout the blue. all these signal are analog signals output by the viewdac. vbs this terminal is used for noise rejection of dac?s current adjustment bias. it is reco mmended to connect a capacitance of 0.1 * f to the ground. vref external voltage reference - bias input for the digital - to - analog converter. gdc fsadj current - mirror output. this pin is used to set the current level in the dac outputs via an internal current - mirror. this pin is usually connected to ground via a 745 ohm resistor. dreq0 external dma request signal. dmac dack0 dma acknowledge signal output pin. tx(can1) transmit pin of can channel 1 rx(can1) receive pin of can channel 1 tx(can0) tr ansmit pin of can channel 0 txcan rx(can0) receive pin of can channel 0 pio18/tx(sei)/tx(sio0) in master mode this pin is the data output of the sei interface. in slave mode this is the data input pin of the sei interface. pio17/rx(sei)/rx(sio0) in m aster mode this pin is the data input pin of the txsei device. in slave mode this pin is the data output. txsei pio16/clk(sei)/clk(sio) in master mode the clock is output during transmission from the txsei module. in slave mode the clock is received from the d evice the TMPR3916F is communicating with.
chapter 12 package dimension 12 - 7 classification pin name pin function pio19/ssi * (sei)/clk(sio1) when the txsei module is configured as a slave the ssi * (slave - select - input) signal shows that the txsei module is accessed in the current transfer. in master mode this pin can be used to check the bus for a second master on the bus. by definition more than one master is not allowed because such a configuration might damage the circuits! txsei pio22/sso * (sei)/rts * (sio1) during master mode the sso * (slave - select output) is used to enable the outputs of an sei device connected to the TMPR3916F. pio29/tx(sio3) pio25/tx(sio2) pio21/tx(sio1) pio18/tx(sei)/tx(sio0) serial data transmit (output) pin. pio28/rx(sio3) pio24/rx(sio2) pio20/rx(sio1) pio17/rx(sei)/rx(sio0) serial data receive (input) pin. pio26/rts * (sio2) pio22/sso * (sei)/rts * (sio1) request to send signal output pin. pio27/cts * (sio2) pio23/cts * (sio1) clear to send signal output pin. uart pio19/ssi * (sei)/clk(sio1) pio16/clk(sei)/clk(si o0) uart clock output for synchronous transfer mode port pio[29:0] 30 - bit parallel i/o port pins. ext[2:0] * interrupt request signal input pins. intc nmi * non - maskable interrupt signal input pin. if this signal is asserted the tx39 core jumps to the n on - maskable - interrupt service routine. dclk debug clock this pin outputs a clock for a real time debug system. pcst[2:0] pc trace status outputs pc trace status information and the mode of the serial monitor bus. sdao/tpc serial data and address o utput / target pc dbge * debugger enable the external real time debug system signals to the dsu by asserting this pin, that it is connected. sdi/dint * serial data input / debug interrupt dsu dreset * debug reset a reset input for a real - time debug system. when dreset * is asserted, the debug support unit (dsu) is initialized. test test0 this pin is used for manufacturing test purposes. for regular operation this pin must be tied to zero. otherwise the TMPR3916F and connected devices may be damaged.
cha pter 12 package dimension 12 - 8
appendix a register overview of TMPR3916F a - 1 appendix a. register overview of TMPR3916F classification address register name function 1c00 0000h silcr0 sio control register (ch0) 1c00 0004h sidicr0 sio interrupt control register (ch0) 1c00 0008h sidisr0 sio interrupt status register (ch0) 1c00 000ch siscisr0 sio status change register (ch0) 1c00 0010h sifcr0 sio fifo control register (ch0) 1c00 0014h siflcr0 sio flow control register (ch0) 1c00 0018h sibgr0 sio baud rate control register (ch0) 1c00 001ch sitfifo0 sio transmit fifo register (c h0) 1c00 0020h sirfifo0 sio receive fifo register (ch0) 1c00 0040h silcr1 sio control register (ch1) 1c00 0044h sidicr1 sio interrupt control register (ch1) 1c00 0048h sidisr1 sio interrupt status register (ch1) 1c00 004ch siscisr1 sio status cha nge register (ch1) 1c00 0050h sifcr1 sio fifo control register (ch1) 1c00 0054h siflcr1 sio flow control register (ch1) 1c00 0058h sibgr1 sio baud rate control register (ch1) 1c00 005ch sitfifo1 sio transmit fifo register (ch1) 1c00 0060h sirfifo 1 sio receive fifo register (ch1) 1c00 0080h silcr2 sio control register (ch2) 1c00 0084h sidicr2 sio interrupt control register (ch2) 1c00 0088h sidisr2 sio interrupt status register (ch2) 1c00 008ch siscisr2 sio status change register (ch2) 1c0 0 0090h sifcr2 sio fifo control register (ch2) 1c00 0094h siflcr2 sio flow control register (ch2) 1c00 0098h sibgr2 sio baud rate control register (ch2) 1c00 009ch sitfifo2 sio transmit fifo register (ch2) 1c00 00a0h sirfifo2 sio receive fifo regis ter (ch2) 1c00 00c0h silcr3 sio control register (ch3) 1c00 00c4h sidicr3 sio interrupt control register (ch3) 1c00 00c8h sidisr3 sio interrupt status register (ch3) 1c00 00cch siscisr3 sio status change register (ch3) 1c00 00d0h sifcr3 sio fifo control register (ch3) 1c00 00d4h siflcr3 sio flow control register (ch3) 1c00 00d8h sibgr3 sio baud rate control register (ch3) 1c00 00dch sitfifo3 sio transmit fifo register (ch3) uart 1c00 00e0h sirfifo3 sio receive fifo register (ch3) 1c00 80 00h semcr sei master control register 1c00 8004h secr0 sei control register 0 1c00 8008h secr1 sei control register 1 1c00 800ch sefs sei inter frame space register 1c00 8010h sess sei slave select space register 1c00 8014h sesr sei status regis ter 1c00 8018h sedr sei data register txsei 1c00 801ch sers sei read start register 1c01 0000h timer free running counter of periodic timers 1c01 0004h titr timer interval time register timer 1c01 0008h pwmval compare value for pwm counter 1c02 0010h rccr2 rom channel control register 2 1c02 0014h rccr3 rom channel control register 3 1c02 0018h rccr4 rom channel control register 4 memc 1c02 001ch rccr5 rom channel control register 5
appendix a register overview of TMPR3916F a - 2 classification address register name function 1c02 8 000h dccr configuration register 1c02 8004h dcba base address register 1c02 8008h dcam address mask register sdramc 1c02 800ch dctr timing register 1c03 0000h pa port data register 1c03 0004h pacr port control register 1c03 0008h pal port interrup t flag 1c03 000ch palmx port edge select for interrupt 1c03 0010h pamsk port interrupt enable port 1c03 0014h pamux output select for port/ txsei/ uart 1c04 0000h irqr interrupt request register 1c04 0004h imaskr interrupt mask register intc 1c04 000 8h ilext external interrupt detection register 1c05 0000h dcr display control register 1c05 0010h sara start address register layer a 1c05 0014h sarb start address register layer b 1c05 0018h sarc start address register layer c 1c05 001ch sard start address register layer d 1c05 0020h mwra memory width register layer a 1c05 0024h mwrb memory width register layer b 1c05 0028h mwrc memory width register layer c 1c05 002ch mwrd memory width register layer d 1c05 0030h htn horizontal tran sfer number 1c05 0034h htnd horizontal transfer number layer d 1c05 0038h hdser horizontal display start register 1c05 003ch hdserd horizontal display start register layer d 1c05 0040h hcr horizontal cycle register 1c05 0044h hswr horizontal sync hronous pulse width 1c05 0048h vcr vertical cycle register 1c05 004ch vswr vertical synchronous pulse width 1c05 0050h vdsr vertical display start register 1c05 0054h vdsrd vertical display start register layer d 1c05 0058h vder vertical display end register 1c05 005ch vderd vertical display end register layer d 1c05 0800h cplta0 color palette register layer a number 0 ? ? ? 1c05 0bfch cplta255 color palette register layer a number 255 1c05 0c00h cpltb0 color palette register layer b num ber 0 ? ? ? 1c05 0ffch cpltb255 color palette register layer b number 255 1c05 0180h cpltc0 color palette register layer c number 0 ? ? ? 1c05 01bch cpltc15 color palette register layer c number 15 1c05 01c0h cpltd0 color palette register layer d number 0 ? ? ? gdc 1c05 01fch cpltd15 color palette register layer d number 15 1c06 0000h odr0 operation definition register 0 1c06 0001h ccr0 channel control register 0 1c06 0002h cer0 channel error register 0 1c06 0003h csr0 channel status register 0 1c06 0004h sar0 source address register 0 1c06 0008h dar0 destination address register 0 1c06 000ch bcr0 byte control register 0 dmac 1c06 0010h odr1 operation definition register 1
appendix a register overview of TMPR3916F a - 3 classification address register name function 1c06 0011h ccr1 channel control register 1 1c06 0012h cer1 channel error register 1 1c06 0013h csr1 channel status register 1 1c06 0014h sar1 source address register 1 1c06 0018h dar1 destination address register 1 dmac 1c06 001ch bcr1 byte control regist er 1 1c07 0000h ? 1c07 00f0h dpram0 mailbox ram (ch0) 1c07 0100h mc0 mailbox configuration register (ch0) 1c07 0104h md0 mailbox direction register (ch0) 1c07 0108h trs0 transmit request set register (ch0) 1c07 010ch trr0 transmit request re set register (ch0) 1c07 0110h ta0 transmission acknowledge register (ch0) 1c07 0114h aa0 abort acknowledge register (ch0) 1c07 0118h rmp0 receive message pending register (ch0) 1c07 011ch rml0 receive message lost register (ch0) 1c07 0120h lam0 l ocal acceptance mask register (ch0) 1c07 0124h gam0 global acceptance mask register (ch0) 1c07 0128h mcr0 master control register (ch0) 1c07 012ch gsr0 global status register (ch0) 1c07 0130h bcr10 bit configuration register 1 (ch0) 1c07 0134h bc r20 bit configuration register 2 (ch0) 1c07 0138h gif0 global interrupt flag register (ch0) 1c07 013ch gim0 global interrupt mask register (ch0) 1c07 0140h mbtif0 mailbox transmit interrupt flag register (ch0) 1c07 0144h mbrif0 mailbox receive inte rrupt flag register (ch0) 1c07 0148h mbim0 mailbox interrupt mask register (ch0) 1c07 014ch cdr0 change data request (ch0) 1c07 0150h rfp0 remote frame pending register (ch0) 1c07 0154h cec0 can error counter register (ch0) 1c07 0158h tsp0 time s tamp counter prescaler (ch0) 1c07 015ch tsc0 time stamp counter (ch0) 1c07 8000h ? 1c07 80f0h dpram1 mailbox ram (ch1) 1c07 8100h mc1 mailbox configuration register (ch1) 1c07 8104h md1 mailbox direction register (ch1) 1c07 8108h trs1 transmit re quest set register (ch1) 1c07 810ch trr1 transmit request reset register (ch1) 1c07 8110h ta1 transmission acknowledge register (ch1) 1c07 8114h aa1 abort acknowledge register (ch1) 1c07 8118h rmp1 receive message pending register (ch1) 1c07 811c h rml1 receive message lost register (ch1) 1c07 8120h lam1 local acceptance mask register (ch1) 1c07 8124h gam1 global acceptance mask register (ch1) 1c07 8128h mcr1 master control register (ch1) 1c07 812ch gsr1 global status register (ch1) 1c07 8130h bcr11 bit configuration register 1 (ch1) 1c07 8134h bcr21 bit configuration register 2 (ch1) 1c07 8138h gif1 global interrupt flag register (ch1) 1c07 813ch gim1 global interrupt mask register (ch1) 1c07 8140h mbtif1 mailbox transmit interrup t flag register (ch1) txcan 1c07 8144h mbrif1 mailbox receive interrupt flag register (ch1)
appendix a register overview of TMPR3916F a - 4 classification address register name function 1c07 8148h mbim1 mailbox interrupt mask register (ch1) 1c07 814ch cdr1 change data request (ch1) 1c07 8150h rfp1 remote frame pending register (ch1) 1c07 8154h cec1 can error counter register (ch1) 1c07 8158h tsp1 time stamp counter prescaler (ch1) txcan 1c07 815ch tsc1 time stamp counter (ch1) ccr 1c08 0000h ccr chip configuration register

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