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IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 1/ 28 features ? programmable angle resolution from 1 to 256 steps per period ? interpolation factors from x0.25 to x64 ? input frequency to 115 khz with x64, to 230 khz with x32, to 460 khz with x16 ? latency of less than 1 s ? selectable gain permits single-ended and differential input signals from 10 mv to 1.5 v peak-peak ? index gating input with ?ne adjustable offset ? programmable index pulse output position and width ? four incremental output modes: quadrature encoder with index, up/down clock, incr./direction, 3 phase commutation ? programmable ?lter and hysteresis ? direct sensor connection, minimized count of external components ? non-volatile setup due to internal eeprom ? fully re-programmable via serial 1- and 2-wire interfaces ? power-on reset circuit and on-chip oscillator ? esd protection and ttl-/cmos-compatible outputs ? operation at 3.0 v to 5.5 v, from -40 c to +125 c applications ? interpolation ic for position data acquisition from analog sine/cosine sensors ? optical linear and rotary encoders ? magneto resistive sensors and encoders packages qfn24 (4 mm x 4 mm) block diagram copyright ? 2007, 2013 ic-haus http://www.ichaus.com i n t e r f a c e z i n i c - t w 2 + i n d e x e n a b l e + a b z - / g n d a s i g n a l p r o c e s s i n g i n t e r n a l e e p r o m u v w - v d d a c l k e x t n b _ n v n r s t 1 w - / 2 w - n i n z p i n a v c p i n z s d a t b _ v p i n b - o n 1 w g n d + v d d c o n v e r s i o n c l o c k z _ w s c l k - n i n b + a _ u n a _ n u - p o w e r - - c l k s e l r e s e t n z _ n w s i n / d g e n e r a t o r b a n d g a p r e g i s t e r s h y s t e r e s i s f i l t e r s y s t e m - + n i n a - +
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 2/ 28 description IC-TW2s interpolation engine accepts two fully differ- ential sensor bridges delivering sine and cosine input signals to produce a highly interpolated output sig- nal. no further external components are required. single-ended sensor signals are supported by tying the negative input terminals to the signal reference, usually vdd/2. IC-TW2 generates one index pulse for every input period. the position in respect to the start of the period as well as the width of the pulse is fully pro- grammable. there are four different output modes provided, in- cluding 3-phase commutation output for brushless dc motors. to meet requirements for a wide range of applications, IC-TW2 is highly programmable. two serial interfaces have been included to permit con?guration of the device, also accessing the inter- nal eeprom. both interfaces allow complete con- ?guration of the device including transfer of setup data to internal registers and the on-chip eeprom for non-volatile storage. contents packaging information 3 pin configuration qfn24 4 mm x 4 mm 3 absolute maximum ratings 4 thermal data 4 electrical characteristics 5 register map 8 programming 9 description of interpolation 10 interpolation vs. resolution . . . . . . . . . . 10 input stage 11 programmable gain ampli?er . . . . . . . . . 11 offset adjustment . . . . . . . . . . . . . . . 11 output modes 12 ab quadrature and up/down and incr/dir modes . . . . . . . . . . . . . . . . . . . 13 3 phase commutation mode . . . . . . . . . 14 index gating 15 calibration 16 a/b gain and offset calibration . . . . . . . . . 16 oscillator and index window calibration . . . 16 configuration dependencies 17 selecting con?guration parameters . . . . . . 17 clock tuning . . . . . . . . . . . . . . . . . . . 17 accuracy modes . . . . . . . . . . . . . . . . 17 device identification 18 start up 19 power-on-reset . . . . . . . . . . . . . . . . 19 reset . . . . . . . . . . . . . . . . . . . . . . 19 1w- / 2w-interface and eeprom access 20 memory map . . . . . . . . . . . . . . . . . . 20 2w-interface . . . . . . . . . . . . . . . . . . 20 2w-interface timing . . . . . . . . . . . . . . . 23 trouble shooting . . . . . . . . . . . . . . . . 23 1w-interface . . . . . . . . . . . . . . . . . . 24 1w-interface write sequence . . . . . . . . . 24 writing the register bank to the eeprom . . 24 test modes 25 production test control bits . . . . . . . . . . 25 typical applications 26 pcb layout guidelines 27
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 3/ 28 packaging information pin configuration qfn24 4 mm x 4 mm pin functions no. name function 1 vdd +3 v to +5.5 v digital supply voltage 2 b_v b signal / v signal output 3 nb_nv inverted b / inverted v signal output 4 a_u a signal / u signal output 5 na_nu inverted a / inverted u signal output 6 gnd digital ground 7 nz_nw inverted z / inverted w signal output 8 z_w z signal / w signal output 9 1w 1w-interface, signal input 10 vdda +3 v to +5.5 v analog supply voltage 11 gnda analog ground 12 n.c. pin not connected 13 pinb signal input b+ 14 ninb signal input b- 15 clksel system clock selection input 16 nrst external reset input (active low) 17 nina signal input a- 18 pina signal input a+ 19 vc 1.2 v reference voltage output 20 ninz signal input z- (index) 21 pinz signal input z+ (index) 22 sclk 2-wire interface, clock input 23 clkext external clock input 24 sdat 2-wire interface, serial data in/out tp thermal pad (bottom side) the thermal pad of the qfn package (bottom side) is to be connected to a ground plane on the pcb which must have gnd potential. gnda must be wired to gnd. only pin 1 marking on top or bottom de?nes the package orientation; label and lot codes can be subject to changes.
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 4/ 28 absolute maximum ratings these ratings do not imply operating conditions; functional operation is not guaranteed. beyond these ratings device damage may occur. item symbol parameter conditions unit no. min. max. g001 vdd, vdda voltage at vdd, vdda referenced to gnd -0.3 6.0 v g002 vdda voltage difference vdd vs. vdda vdda = vdd - vdda 0 0.5 v g003 v() voltage at pina, nina, pinb, ninb, pinz, ninz, b_v, nb_v, a_u, na_u, z_w, nz_w, 1w, sdat, sclk, clksel, clkext referenced to gnd -0.3 vdd + 0.5 v v g004 i() current in pina, nina, pinb, ninb, pinz, ninz, b_v, nb_v, a_u, na_u, z_w, nz_w, 1w, sdat, sclk, clksel, clkext, vc -20 20 ma g005 vd esd susceptibility of signal outputs hbm, 100 pf discharged through 1.5 k
; pins a_u, na_u, b_v, nb_v, z_w, nz_w 1.5 kv g006 vd esd susceptibility (remaining pins) hbm, 100 pf discharged through 1.5 k
1 kv g007 tj junction temperature -40 125 c g008 ts storage temperature -40 125 c thermal data item symbol parameter conditions unit no. min. typ. max. t01 ta operating ambient temperature -40 125 c t02 rthja thermal resistance chip to ambient qfn24 surface mounted to pcb, following jedec 51 32 k/w all voltages are referenced to ground unless otherwise stated. all currents ?owing into the device pins are positive; all currents ?owing out of the device pins are negative.
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 5/ 28 electrical characteristics operating conditions: vdd = vdda = 3.0...5.5 v, tj = -40...125 c, unless otherwise stated item symbol parameter conditions unit no. min. typ. max. total device 001 vdd, vdda permissible supply voltage vdd, vdda 3.0 5.5 v 002 i(vdd, vdda) total supply current vdd = 3.3 v at 0 hz 5 ma vdd = 3.3 v at 100 khz 20 ma vdd = 5.5 v at 0 hz 8 ma vdd = 5.5 v at 100 khz 40 ma 003 vc()hi clamp-voltage hi at all pins vc()hi = v() - vdd; i() = 10 ma 0.5 1.3 v 004 vc()lo clamp-voltage lo at all pins i() = -10 ma -1.3 -0.3 v input ampli?er pina, nina, pinb, ninb 101 vin()sig permissible input voltage range 1.4 vdd - 1.2 v 102 step(gc) nominal coarse gain step size 6.0 db 103 agabs(gc) coarse gain absolute accuracy -1.0 3.5 db 104 step(gf) nominal fine gain step size 0.7 db 105 agabs(gf) fine gain absolute accuracy -0.3 0.3 db 106 cgm gain matching g(cha)/g(chb) 0.85 1.15 107 vin()os input referred offset voltage -15 15 mv 108 vout()ossc output referred offset correc- tion step accuracy -10 10 mv 109 step(ofsx) nominal offset correction step size 13 mv 110 vout()os output referred offset voltage -40 40 mv 111 fr permissible input frequency; frequency ratio fr = f cal / f in inter = 1 . . . 64, freq = 0 64 inter = 1 . . . 64, freq = 1 128 inter = 1 . . . 64, freq = 2 . . . 127 256 inter = 65 . . . 128, freq = 0 128 inter = 65 . . . 128, freq = 1 . . . 127 256 inter = 129 . . . 255 256 inter = 0 256 oscillator 201 f cal permissible user calibrated oscillator frequency measured at pin a_u in calib mode 2 as 1/32; vdd = 3.6 v, tj = 25 c 25 mhz vdd = 5.5 v, tj = 25 c 30 mhz 202 f osc oscillator frequency vdd = 3.0 v, tj = 25 c, clock = 0 25 mhz vdd = 3.0 v, tj = 25 c, clock = 31 35 mhz vdd = 5.5 v, tj = 25 c, clock = 0 28 mhz vdd = 5.5 v, tj = 25 c, clock = 31 40 mhz 203 tc osc oscillator frequency temperature drift vdd = 5.0 v +/- 2 % -0.12 0 %/k 204 vc osc oscillator frequency power supply dependency tj = 25 c 10 %/v 205 df osc osc. frequency variation 3.3 v supply voltage 3.3 v +/-10%, tj = 25 c +/-3 % 206 df osc osc. frequency variation 5 v supply voltage 5 v +/-10%, tj = 25 c +/-2 % eeprom 301 tret data retention time tj = 125 c 10 years tj = 85 c 100 years 302 ncycles number of erase/write cycles tj = 25 c 1000 303 nread number of read cycles 10 6 reference voltage output vc 401 vref(vc) reference voltage c l = 100 nf, i(vc) = 0 ma 1.15 1.21 1.27 v
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 6/ 28 electrical characteristics operating conditions: vdd = vdda = 3.0...5.5 v, tj = -40...125 c, unless otherwise stated item symbol parameter conditions unit no. min. typ. max. digital inputs nrst 501 vt()hi input threshold voltage hi vdd = 3.3 v +/- 10 % 1.5 v vdd = 5.0 v +/- 10 % 3.3 v 502 vt()lo input threshold voltage lo vdd = 3.3 v +/- 10 % 0.8 v vdd = 5.0 v +/- 10 % 1.0 v 503 ipu() input pull-up current v() = 0...vdd - 1 v -3 a 504 vpu() input pull-up voltage vpu() = vdd - v(), i() = -3 a 500 mv digital inputs clksel, clkext 601 vt()hi input threshold voltage hi vdd = 3.3 v +/- 10 % 1.5 v vdd = 5.0 v +/- 10 % 3.3 v 602 vt()lo input threshold voltage lo vdd = 3.3 v +/- 10 % 0.8 v vdd = 5.0 v +/- 10 % 1.0 v 603 ipd() input pull-down current v() = 1 v...vdd 4 a 604 vpd() input pull-down voltage i() = 3 a 500 mv digital outputs a_u, na_nu, b_v, nb_nv, z_w, nz_nw 701 vs()hi output saturation voltage hi vs()hi = v(vdd) - v(), i() = -6 ma; vdd = 3.3 v +/- 10 % 0.5 v vdd = 5.0 v +/- 10 % 0.4 v 702 isc()hi short-circuit current hi v() = gnd -100 -15 ma 703 vs()lo output saturation voltage lo i() = 6 ma; vdd = 3.3 v +/- 10 % 0.3 v vdd = 5.0 v +/- 10 % 0.25 v 704 isc()lo short-circuit current lo v() = vdd 20 140 ma 705 tr() output rise time vdd = 3.0 v, cl() = 10 pf 4 ns 706 tf() output fall time vdd = 3.0 v, cl() = 10 pf 4 ns 707 i()max permissible load current source and sink -10 10 ma 708 twhi duty cycle at output a, b referred to period t, see fig. 1 50 % 709 tab output phase a vs. b referred to period t, see fig. 1 25 % 710 tmtd minimum transition distance see fig. 1 1/ f core signal processing 801 aaabs absolute angular accuracy referred to 360 input signal -6 6 deg gc(2:0) = 1 inter(7:0) = 0 freq(6:0) = 127 f() < 50 hz 802 aarel relative angular accuracy referred to period of a, b -20 20 % gc(2:0) = 1 inter(7:0) = 0 freq(6:0) = 127 f() < 50 hz 803 abrel relative angular accuracy a vs. b 1/2 aarel % index comparator pinz, ninz 901 vin()sig permissible input voltage range 0.0 vdd v 902 vin()os input referred offset voltage -15 +15 mv 903 vin()step comparator offset step size ofsz = 0..7 1.5 mv ofsz = 8..15 -1.5 mv power-down-reset a01 vddon turn-on threshold vdd (power on release) 1.8 v a02 tbusy()cfg duration of startup con?guration 20 ms
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 7/ 28 electrical characteristics operating conditions: vdd = vdda = 3.0...5.5 v, tj = -40...125 c, unless otherwise stated item symbol parameter conditions unit no. min. typ. max. 2-wire interface sdat, sclk b01 vt()hi input threshold voltage hi vdd = 3.3 v +/- 10 % 1.5 v vdd = 5.0 v +/- 10 % 3.3 v b02 vt()lo input threshold voltage lo vdd = 3.3 v +/- 10 % 0.8 v vdd = 5.0 v +/- 10 % 1.0 v b03 ipd() input pull-down current v() = 1 v...vdd 4 a b04 vpd() input pull-down voltage i() = 3 a 500 mv b05 vs()lo saturation voltage lo at sdat i() = 2 ma 450 mv b06 vs()hi saturation voltage hi at sdat vs()hi = vdd - v(); i() = -2 ma 700 mv b07 isc()lo short-circuit current lo at sdat 3 ma b08 isc()hi short-circuit current hi at sdat -2.5 ma b09 fclk(sclk) permissible clock frequency sclk scales with oscillator frequency timing, see table 32 1.25 mhz b10 tbusy()e2p max. duration of eeprom ac- cess scales with oscillator frequency timing, see table 32 20 ms 1-wire interface 1w c01 vt()hi input threshold voltage hi vdd = 3.3 v +/- 10 % 1.5 v vdd = 5.0 v +/- 10 % 3.3 v c02 vt()lo input threshold voltage lo vdd = 3.3 v +/- 10 % 0.8 v vdd = 5.0 v +/- 10 % 1.0 v c03 ipu() input pull-up current v() = 0...vdd - 1 v -3 a c04 vpu() input pull-up voltage vpu() = vdd - v(), i() = -3 a 500 mv figure 1: relative phase distance a b t ab t mtd t whi t aarel aarel t whi
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 8/ 28 register map register map addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device indenti?cation 0x00 ida(3:0) idb(3:0) operating modes 0x01 reset (p. 19 ) calib1 (p. 16 ) startup(1:0) (p. 19 ) dir (p. 12 ) mode(1:0) (p. 12 ) interpolation rate 0x02 inter(7:0) (p. 12 ) index position 0x03 ipos(7:0) (p. 13 ) index width 0x04 iwidth(7:0) (p. 13 ) conversion settings 0x05 granu- lar (p. 25 ) freq(6:0) (p. 17 ) 0x06 filter(1:0) (p. 17 ) hyst(1:0) (p. 17 ) gain and offset 0x07 gfb(1:0) (p. 11 ) gfa(1:0) (p. 11 ) gc(2:0) (p. 11 ) 0x08 ofsa(5:0) (p. 11 ) 0x09 ofsb(5:0) (p. 11 ) bias and oscillator trimming 0x0a vc(1:0) (p. 25 ) clock(4:0) (p. 16 ) index computation and miscellaneous 0x0b ofsz(3:0) (p. 16 ) en_mon (p. 25 ) clkdly (p. 25 ) clkdiv (p. 17 ) clkmode (p. 25 ) reserved and calibration 0x0c reserved (p. 25 ) calib2 0x0d reserved (p. 25 ) eeprom control 0x0e ee_read (p. 25 ) ee_write (p. 24 ) reserved (p. 25 ) test register 0x0f monitor(7:0) (p. 25 ) table 4: register map
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 9/ 28 programming input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 11 gc: coarse gain control (p. 11 ) gfa/b: fine gain control on channel a/b (p. 11 ) ofsa/b: offset control on channel a/b (p. 11 ) output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 12 mode: output mode selection (p. 12 ) dir: count direction (p. 12 ) inter: interpolation rate selection (p. 12 ) ipos: index pulse position (p. 13 ) iwidth: index pulse width selection (p. 13 ) index gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 15 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 16 calib1: calibration mode 1 select (p. 16 ) calib2: calibration mode 2 select (p. 16 ) ofsz: index comparator offset control (p. 16 ) clock: oscillator tune (p. 16 ) con?guration dependencies . . . . . . . . . . . . . . page 17 freq: maximum input frequency (p. 17 ) clkdiv: master clock divider (p. 17 ) hyst: hysteresis control (p. 17 ) filter: datapath ?lter control (p. 17 ) device identi?cation . . . . . . . . . . . . . . . . . . . . . . . page 18 ida: major device revision (p. 18 ) idb: minor device revision (p. 18 ) start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 19 startup: startup sequence selection (p. 19 ) reset: restart interpolation engine (p. 19 ) 1w- / 2-w-interface and eeprom access . page 20 ee_write: eeprom store command (p. 24 ) test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 25 granular: a/b output edge granularity control (p. 25 ) vc: reference voltage ?ne tuning (p. 25 ) clkmode: clock source selection (p. 25 ) clkdly: clock distribution delay line selection (p. 25 ) en_mon: position data monitor control (p. 25 ) monitor: monitor register (p. 25 ) ee_read: eeprom read command (p. 25 )
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 10/ 28 description of interpolation IC-TW2 is a monolithic a/d converter which converts sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data. the interpola- tion function is shown in figure 2 . figure 2: interpolation function interpolation vs. resolution there is a difference between interpolation factor and resolution. resolution (interpolation rate) is deter- mined by the sum of edges at the incremental outputs (ab quadrature output) within one input signal period . dividing the resolution by the existing edges of the sine and cosine signals (= 4) equals to the interpola- tion factor. the interpolation factor equals to the the resolution divided by 4. example: an interpolation factor of x8 brings a resolution of 32 (edges). to operate with an interpolation factor of 8 con?gure inter(7:0) to 32. gain channel b gc(2:0) and gfb(1:0) gain channel a gc(2:0) and gfa(1:0) offset channel a ofsa(5:0) pina pinb a_u b_v pinz offset channel b ofsb(5:0) z_w index pulse position ipos(7:0) index pulse width iwidth(7:0) interpolation inter(7:0) (interpolation of x5 shown) index pulse is disabled through pin pinz low
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 11/ 28 input stage programmable gain ampli?er a programmable gain ampli?er (pga) with output re- ferred offset adjustment is used as input stage, shown in figure 3 . the coarse gain is common for both channel a and b and is programmed through register gc(2:0). fine tuning gain is applied individually to channel a and b by programming registers gfa(1:0) and gfb(1:0) respectively. figure 3: input stage gc(2:0) addr. 0x07; bit 2:0 r/w code input signal range v in peak-peak [ v in peak-peak diff. ] 000 400 mv - 750 mv [ 800 mv - 1.5 v ] 400 mv max. @vdd = 3.0 v 001 200 mv - 400 mv 010 100 mv - 200 mv 011 50 mv - 100 mv 100 25 mv - 50 mv 101 12.5 mv - 25 mv 110 5 mv - 12.5 mv 111 not de?ned ( defaults to eeprom setting ) table 5: coarse gain control of channel a/b gfa(1:0) addr. 0x07; bit 4:3 r/w gfb(1:0) addr. 0x07; bit 6:5 r/w code fine gain ( defaults to eeprom setting ) 00 0 db 01 0.7 db 10 1.4 db 11 2.1 db table 6: fine gain control of channel a/b offset adjustment offset adjustment is provided at the output of the input ampli?er. it is individually programmed through regis- ter ofsa(5:0) and ofsb(5:0). adjustment is made in steps of 13 mv and the corresponding register values are sign magnitude encoded. input referred offset be- comes gain dependent and is de?ned as follows: v ofs (a input referred) = 13 mv ofsa (5 : 0) gc (2 : 0) ofsa(5:0) addr. 0x08; bit 5:0 r/w ofsb(5:0) addr. 0x09; bit 5:0 r/w code offset correction ( defaults to eeprom setting ) 111111 maximum negative adjust: -403 mv 111110 -390 mv 100001 -13 mv 100000 no correction 000000 no correction 000001 13 mv 011110 390 mv 011111 maximum positive adjust: 403 mv table 7: offset control of channel a/b consider table 8 regarding the relationship between coarse gain, permissible peak-to-peak input amplitude and the resulting offset correction range. coarse input signal range input-referred input-ref. gain offset corr. range offset step gc(2:0) v in peak-peak v ofs max dv ofs 0 400 mv - 750 mv 806 mv 26 mv 400 mv max. @3 v 1 200 mv - 400 mv 403 mv 13 mv 2 100 mv - 200 mv 202 mv 6.5 mv 3 50 mv - 100 mv 101 mv 3.25 mv 4 25 mv - 50 mv 50 mv 1.63 mv 5 12.5 mv - 25 mv 25 mv 0.81 mv 6 5 mv - 12.5 mv 12.6 mv 0.41 mv table 8: input signal and offset correction ranges. figure 4: permissible input voltage range at vdd = 5 v +/- 10 %. + i n p u t n i n b g f b ( 1 : 0 ) g f a ( 1 : 0 ) n i n a + o f s a ( 5 : 0 ) e n g i n e p i n a g c ( 2 : 0 ) t o i n t e r p o l a t i o n - + x a - o f s b ( 5 : 0 ) a m p l i f i e r x b p i n b + 5v 3v 2v 4v 1.4 v 3.3 v 1v v cm vdd= 4.5 v v in v ofs +in -in
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 12/ 28 output modes the IC-TW2 provides four different output modes, which are con?gured by programming bits mode(1:0) of register 0x01. modes 0, 1 and 2 are incremental modes whereas mode 3 is a 3-phase commutation out- put for brushless dc motors. consider figure 5 for a comparison of the 3 incremental output modes. mode(1:0) addr. 0x01; bit 1:0 r/w code function, defaults to eeprom setting 00 ab quadrature (mode 0) 01 up / dn (mode 1) 10 inc / dir (mode 2) 11 3 phase commutation (mode 3) table 9: output mode selection in increment / direction mode the count direction can be inverted via control bit dir of register 0x01. dir addr. 0x01; bit 2 r/w code function, defaults to eeprom setting 0 normal count direction 1 inverted count direction table 10: count direction selection inter (7:0) adr 0x02, bit 7:0 r/w code step angle steps per period ipf interpolation factor ?n()max max. permissible input frequency * 0x00 256 64 115 khz** 0x01 1 0.25 460 khz 0x02 2 0.5 460 khz 0x03 3 0.75 460 khz 0x04 4 1 460 khz 0x05 5 1.25 460 khz . . . . . . . . . 460 khz 0x3c 60 15 460 khz 0x3d 61 15.25 460 khz 0x3e 62 15.5 460 khz 0x3f 63 15.75 460 khz 0x40 64 16 460 khz 0x41 65 16.25 230 khz 0x42 66 16.5 230 khz 0x43 67 16.75 230 khz 0x44 68 17 230 khz 0x45 69 17.25 230 khz . . . . . . . . . 230 khz 0x7c 124 31 230 khz 0x7d 125 31.25 230 khz 0x7e 126 31.5 230 khz 0x7f 127 31.75 230 khz 0x80 128 32 230 khz 0x81 129 32.25 115 khz 0x82 130 32.5 115 khz 0x83 131 32.75 115 khz 0x84 132 33 115 khz 0x85 133 33.25 115 khz . . . . . . . . . 115 khz 0xfa 250 62.5 115 khz 0xfb 251 62.75 115 khz 0xfc 252 63 115 khz 0xfd 253 63.25 115 khz 0xfe 254 63.5 115 khz 0xff 255 63.75 115 khz notes *) for f osc = 29.4 mhz, freq = 0, clkdiv = 0. **) 115 khz is ?n()max for commutation operation (mode = 3). table 11: converter resolution
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 13/ 28 ab quadrature and up/down and incr/dir modes figure 5: incremental output modes (mode 0, 1, 2) ipos(7:0) addr. 0x03; bit 7:0 r/w code function, defaults to eeprom setting 0 no offset 1 1 increment offset 2 2 increments offset . . . . . . index pulse will be shifted by iwidth(7:0) increments. programmed value is within the range of 0 to inter(7:0) - 1. . . . . . . 255 255 increments offset note: a ?xed phase relation to a/b is guaranteed only with startup(1:0) = 0b10 (absolute) or startup(1:0) = 0b11 (burst). table 12: index pulse position iwidth(7:0) addr. 0x04; bit 7:0 r/w code function, defaults to eeprom setting 0 disable pulse generation 1 1 increment width 2 2 increments width . . . . . . any other value n index pulse will extend over iwidth(7:0) increments. programmed value is within the range of 0 to inter(7:0) - 1. . . . . . . 255 255 increments width table 13: index pulse width selection 0 1 2 3 5 4 3 4 5 6 2 sensor position a/b mode 0 a_u b_v a_u b_v a_u b_v up / dn mode 1 inc / dir mode 2
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 14/ 28 3 phase commutation mode the 3 phase commutation output (mode 3) is shown in figure 6 . it is important that register inter(7:0) is programmed with the value 0x00 in order for the commutation mode to work. the mode = 3 requires an internal interpolation inter(7:0) of 256. register ipos(7:0) is used to accurately position the commu- tation. iwidth(7:4) and iwidth(3:0) is subsequently used to ?ne tune v and w in respect to u. all used offsets within the commutation mode (mode 3) as are ipos(7:0), iwidth(3:0) and iwidth(7:4) operate in this step width of 1.4 . there is no other pole count commutation possible to con?gure as the described 3 phase commutation. figure 6: 3-phase commutation output (mode 3) ipos(7:0) addr. 0x03; bit 7:0 r/w code function, defaults to eeprom setting 0 0 1 1.40 2 2.81 . . . . . . programmed value is within the range of 0 to inter(7:0) - 1. . . . . . . 255 358,59 table 14: uvw commutation signal position offset iwidth(3:0) addr. 0x04; bit 3:0 r/w code v output offset, defaults to eeprom setting 0111 9.84 . . . . . . 0010 2.81 0001 1.40 0000 0 1111 -1.40 1110 -2.81 . . . . . . 1111 11.25 table 15: v commutation signal position offset iwidth(7:4) addr. 0x04; bit 7:4 r/w code w output offset, defaults to eeprom setting 0111 9.84 . . . . . . 0010 2.81 0001 1.40 0000 0 1111 -1.40 1110 -2.81 . . . . . . 1111 11.25 table 16: w commutation signal position offset a_u b_v z_w 0 120 240 0 ipos (7:0) iwidth (7:4) iwidth (3:0)
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 15/ 28 index gating the IC-TW2 can interface to a wide range of index gat- ing sources. most commonly used are the digital hall sensor and the mr sensor bridge. the digital hall sensor provides a large swing input sig- nal to the IC-TW2. depending on the polarity of the hall it is either connected to pin ninz or pinz. most hall sensors use an open drain stage pulling the out- put low in the presence of a magnetic ?eld. the un- used terminal pinz or ninz should be biased to an adequate mid voltage level to guarantee good noise margin. the IC-TW2 provides a constant 1.21 v at pin vc that can be used for this purpose (refer to figure 7 ). figure 7: digital hall sensor index con?guration figure 8: mr sensor index con?guration an mr sensor differential bridge can also be used to gate the index. typically, the mr sensor provides a small signal amplitude. in addition, residual side lobes are present that can trigger double indexing. the ic- tw2 provides offset control capability to ?ne tune the threshold voltage of the index comparator. this greatly simpli?es end product calibration as variation in sensor offset can be compensated for. figure 9 shows a correctly set threshold when using an mr gating sensor. the side lobes are below the threshold line and no parasitic triggering occurs. figure 9: index gating and calibration index gating should be calibrated at sine/cosine input frequencies below 5 khz to minimize the effect of la- tency. timings shown in table 17 are valid for input frequencies below 5 khz and f system of 25 mhz. once the timings are satis?ed according to table 17 , correct operation is guaranteed up to the maximum input fre- quency as speci?ed in table 26 on page 18 . parameter description condition * min t setup index window setup time before rising edge of z_w no ?lter 8 average 16 average 0.4 s 0.5 s 0.7 s t hold index window hold time after falling edge of z_w no ?lter 8 average 16 average 0.4 s 0.5 s 0.7 s *) according to register filter(1:0) f system = 25 mhz, all timings scale with f system . refer to table 26 for more information table 17: index gating and timing p i n b _ v ( a ) ( b ) p i n z _ w t s e t u p t h o l d s i g n a l o f m r i n d e x s e n s o r i n t e r n a l g a t i n g w i n d o w o b s e r v e d d u r i n g i n d e x c a l i b r a t i o n ( m o d e 2 ) . i n t e r n a l t h r e s h o l d g a t e d i n d e x o u t p u t , 1 i n c r e m e n t w i d e .
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 16/ 28 calibration in order to facilitate system gain and offset calibration, two calibration modes can be enabled by either setting bit calib1 of register 0x01 or calib2 of register 0x0c. calib2 addr. 0x0c; bit 0 r/w calib1 addr. 0x01; bit 5 r/w calib2;1 function, defaults to eeprom setting 00 normal operation, no calibration 01 a/b gain and index calbration 10 oscillator and index window calibration 11 not permitted table 18: calibration modes a/b gain and offset calibration in calibration mode 1 the sin/cos input is directly passed through two zero-cross comparators to output pin a and b respectively. in addition, the sum of the input signals sin + cos p 2 is also fed through a comparator and driven on pin z. the actual calibration process must be carried out in several steps. 1. select proper coarse gain by programming register gc(2:0). set gfa(1:0) and gfb(1:0) to 0. 2. adjust offset register ofsa(5:0) and ofsb(5:0) un- til output a and b are 50% duty cycle. 3. adjust ?ne gain register gfa(1:0) and gfb(1:0) until output z is equidistant between output a and b. 4. repeat step 1 and 2 until no more improvement can be achieved. figure 10: output signals for a/b gain and offset ad- justment in calibration mode 1. oscillator and index window calibration when calibration mode 2 is enabled, the output of the index comparator is driven on pin b_v. in conjunction with the actual index output on pin z_w, the gating window can be centered around the output pulse (see figure 9 ). fine offset adjustment applied to the input of the index comparator is possible through ofsz(3:0) which is sign magnitude encoded. this is bene?cial when using small amplitude index sources such as an mr sensor. simultaneously, the oscillator frequency f osc /32 can be observed on pin a_u. register clock(4:0) is used to tune the oscillator to its desired frequency. ofsz(3:0) addr. 0x0b; bit 7:4 r/w code function, defaults to eeprom setting 1111 maximum negative adjust, -10.5 mv 1110 -9 mv 1001 -1.5 mv ... ... 1000 no correction 0000 no correction 0001 1.5 mv ... ... 0110 9 mv 0111 10.5 mv 1 calibration mode 2 activated table 19: index comparator offset control clock(4:0) addr. 0x0a; bit 4:0 r/w code function, defaults to eeprom setting 00000 slowest clock ... ... 11111 fastest clock table 20: oscillator tuning pinb pina (a+b) / sqrt(2) a_u b_v z_w
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 17/ 28 configuration dependencies this section describes the dependencies between the chip con?guration and the systems performance. it is vital to understand the implication of system parame- ters to be able to tune the IC-TW2 for full performance. it is especially important to correctly program regis- ter freq(6:0), since this directly affects accuracy and maximum allowed input frequency. selecting con?guration parameters to select a proper con?guration follow the outlined pro- cedure below. refer to table 26 for reference. 1. determine the maximum input frequency f in()max as required by the application. 2. calculate f core based on f in()max and resolution inter(7:0). 3. select f system based on the accuracy requirements. accuracy is a function of resolution inter(7:0) and clock scaling freq(6:0). always use the highest ac- curacy possible to still satisfy f in()max . 4. determine f osc . selecting the slowest possible f osc lowers power consumption and improves jitter perfor- mance. clock tuning 1. observe f osc /32 on pin a_u during calibra- tion mode 2. 2. use clock(4:0) to tune the oscillator to the desired f cal frequency. (f pina = f osc /32) 3. be aware that the oscillator can have as much as 20 % frequency variation over the operating tem- perature range (-40 c to 125 c). the oscillator runs slower at higher temperatures. to guarantee perfor- mance at 125 c it is necessary to tune the oscillator to typ. 12 % higher frequency at room temperature of 25 c. accuracy modes the converter resolution inter(7:0) in conjunction with the clock scaling freq(6:0) de?ne IC-TW2s ac- curacy mode. based on the selected accuracy mode other system parameters are de?ned as shown in ta- ble 26 . inter(7:0) freq(6:0) accuracy mode theoretical absolute accuracy 129 to 256; 0 0 to 127 high accuracy 2.8 65 to 128 0 medium acc. 5.6 1 to 127 high accuracy 2.8 1 to 64 0 low accuracy 11.2 1 medium acc. 5.6 2 to 127 high accuracy 2.8 table 21: accuracy modes clkdiv addr. 0x0b; bit 1 r/w code function ( defaults to eeprom setting ) 0 f system = f osc 1 f system = f osc / 2 note it is recommended to use the divider when support for high input frequencies is not required. table 22: master clock divider freq(6:0) addr. 0x05; bit 6:0 r/w code clock scaling ( defaults to eeprom setting ) 0x00 f core = f system . . . f core = f system / (1 + freq(6:0)) 0x7f f core = f system / 128 table 23: clock scaling hyst(1:0) addr. 0x06; bit 1:0 r/w function ( defaults to eeprom setting ) code high accuracy medium / low accuracy 00 no hysteresis no hysteresis 01 1.4 2.8 10 2.81 5.6 11 5.63 11.3 table 24: hysteresis control filter(1:0) addr. 0x06; bit 3:2 r/w code function ( defaults to eeprom setting ) 00 ?lter disabled 01 average of 8 samples 10 average of 16 samples 11 unde?ned notes it is recommended to enable the ?lter in almost all cases as it removes loop instability noise. however, enabling the ?lter increases the sin/cos input to a/b output latency (see table 26 for details). table 25: datapath ?lter control
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 18/ 28 description parameter requirement or relationship control bit oscillator frequency f osc [hz] clock(4:0) calibrated osc. frequ. f cal [hz] < 30 mhz at vdd = 5.5 v, < 25 mhz at vdd = 3.6 v; see elec. char. item 201 system clock f system [hz] f system = f osc , if clkdiv = 0 f system = f osc /2, if clkdiv = 1 clkdiv core clock f core [hz] f core = f system / (1 + freq(6:0)) freq(6:0) front-end frequency limit* f front [hz] f front = f system / 256, if high accuracy f front = f system / 128, if medium accuracy f front = f system / 64, if low accuracy freq(6:0) inter(7:0) f front is the maximum sin/cos input frequency which can be processed by the front-end. back-end frequency limit* f back [hz] f back = f core / inter(7:0) inter(7:0) f back is the maximum sin/cos input frequency which can be processed by the a/b generator back-end. max. input frequency f in()max [hz] f in()max = min(f front , f back ) the permissible max. sin/cos input frequency is determined by f back or f front , whatever means the lower limit. max. a/b output frequency f out(ab)max [hz] f out(ab)max = 1 / f core f out(ab)max = 0.25 / t edge a/b edge separation, min. transition distance t edge , t mtd t edge = t mtd = 1 / f core a/b edge granularity t gran t gran = 1 / f system sin/cos to a/b output latency t latency [s] 10 / f system [mhz] + 0.2, if no ?lter 18 / f system [mhz] + 0.2, if 8 sample average 26 / f system [mhz] + 0.2, if 16 sample average filter(1:0) *) parameter does not represent a functional ic parameter, paramter introduced for calculation purposes only. table 26: con?guration dependencies device identification ida(3:0) addr. 0x00; bit 7:4 r/w code function, major device identi?cation mask programmed value identi?es major revision table 27: major device revision idb(3:0) addr. 0x00; bit 3:0 r/w code function, minor device identi?cation mask programmed value identi?es minor revision table 28: minor device revision
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 19/ 28 start up power-on-reset the IC-TW2 contains a built-in power-on-reset (por) circuitry. the por keeps the IC-TW2 in reset as long as the applied power supply voltage does not allow reliable operation. once the power supply ramps up above 1.8 v, the por releases the reset and the ic- tw2 starts the con?guration cycle. 20 ms after the de- vice goes out of reset, normal operation begins. figure 11: power supply ramp-up to avoid a/b output toggling it is important that the power supply and the input signals are stable as soon as normal operation begins. in applications with a slowly rising power supply, it might be necessary to connect an external rc reset to pin nrst to prolong the reset. in applications where startup a/b toggling is acceptable, no precaution must be taken as the ic- tw2 will properly power up on an inde?nitely slow sup- ply rise time. the IC-TW2 startup behaviour is controlled by pro- gramming the two control bits startup(1:0) in reg- ister 0x01. three possible startup con?gurations are allowed, shown in figure 12 . the default behaviour must be speci?ed by the eeprom. figure 12: startup behaviour startup(1:0) addr. 0x01; bit 4:3 r/w code function 00 relative a/b output signals are kept low during startup. this resembles true relative operation since there is no relationship between a/b levels and sensor position (and therefore z output) on startup. 01 reserved 10 absolute a/b output signals are phase-related to z output. a/b output levels are de?ned by the absolute sensor position within a period. the register ipos can be used to program the desired a/b to z phase relationship. 11 burst the absolute sensor position within the period is output by an a/b burst. table 29: startup sequence selection reset a control bit reset is provided to block any burst a/b pulses during chip recon?guration by a microcon- troller. while reset is set a/b/z output generation is stopped. access to the interface and register bank is not affected. reset addr. 0x01; bit 6 r/w code function 0 a/b/z output according to startup default 1 a/b/z output halted following reset notes reset = 1 may be programmed to the eeprom or can be used temporarily to avoid spurious a/b/z output pulses when recon?guration by an external microcontroller is intended. table 30: restart of interpolation engine following power-on or software initiated reset. time volts v dd 3.3 or 5.0 v 1.8 v 0.0 v 20 ms power- on- reset releases, IC-TW2 starts configuration IC-TW2 starts a/b pulse generation. power supply and sensor input signals should be stable to avoid a/b toggling. a_u b_v z_w a_u b_v z_w a_u b_v z_w reset power supply ramp-up true relative operation, a/b phase relation to z is unknown a/b has known phase relation to z (same on each startup) burst output to absolute position within period startup(1:0) = 00 startup(1:0) = 10 startup(1:0) = 11 relative absolute burst
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 20/ 28 1w- / 2w-interface and eeprom access memory map figure 13 depicts the IC-TW2 memory map and inter- face diagram. a 2-wire read/write interface and a 1- wire write-only interface allow access to the register bank and the eeprom bank. the register bank is 8 bits wide and it is used to control all chip functional- ity. refer to section "register map" on page 8 for an overview of all registers. nb: the 1w-interface and the 2w-interface do not feature a timeout. the eeprom bank on the other hand is 32 bits wide. address 0x05, 0x06 and 0x07 (3 * 4 bytes = 12 bytes) can be used to store user data such as product serial numbers, calibration and manufacturing information. figure 13: memory map 2w-interface the ?rst control interface is a standard 2-wire serial interface. it uses an external clock and bidirectional data line. it allows read and write access to all internal registers as well as access to the user eeprom. the interface consists of two pins, a dedicated input sclk, the shifting clock and sdat for bidirectional serial data. the interface handles four types of access requests: 1. write to control register 2. read from control register 3. write to eeprom register (including block ac- cess and erase) 4. read from eeprom register control register access is shown in figure 14 (write) and figure 15 (read) respectively. if sdat is 00 af- ter the start bit a write access is requested. the data word d(7:0) will be written into register a(4:0). please note that a(4) is always 0 since the IC-TW2 only has 16 addressable registers. 1- wire interface write only 2- wire interface read and write sdat sclk 1w addr 0 addr 1 addr 2 addr 3 addr 4 addr 5 addr 6 addr 7 addr 8 addr 9 addr 10 addr 11 addr 12 addr 13 addr 14 addr 15 addr 0 - reserved addr 1 - reserved addr 2 - reserved addr 3 - reserved addr 4 - reserved addr 5 - user data addr 6 - user data addr 7 - user data register bank 8 bit wide eeprom bank 32 bit wide
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 21/ 28 figure 14: register bank write access on 2w-interface on a register read access the register content is shifted out on sdat. a read access is indicated by sdat 10 after the start bit. there is an idle clock re- quired between the last address bit a(0) and the ?rst data bit d(7) returned on sdat. this clock cycle is used to avoid any bus contention while turning around the bus driver. figure 15: register bank read access on 2-wire interface write access to the eeprom follows the procedure depicted in figure 16 . a start bit is followed by four command bits c-1-e-b. the encoding of the command bits is shown in table 31 . the most useful command is 0100 which performs an erase followed by a write therefore allowing the user to write a new value to the eeprom with only one interface access. figure 16: eeprom write access on 2-wire interface d6 d7 a0 a1 a2 a4 sdat is sampled on falling edge of sclk 00 indicates write extra clocks before new access a3 d0 d1 0 0 0 0 1 sclk sdat new access 5 bit address 8 bit data sdat is externally driven d6 d7 a0 a1 a2 a4 sdat is sampled on falling edge of sclk 10 indicates read extra clocks before new access a3 d0 0 1 0 0 1 sclk sdat new access 5 bit address 8 bit data sdat is externally driven sdat is driven by IC-TW2 c d30 d31 a0 a1 a2 e sdat is sampled on falling edge of sclk command select extra clocks before new access b 0 0 1 sclk sdat wait for at least 20ms before any new access 3 bit address 32 bit data sdat is externally driven d0 d1 1 20 ms erase control block operation
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 22/ 28 figure 17: eeprom read access on 2-wire interface the 3 bit address a(2:0) selects the eeprom register to write to (figure 13 ). each eeprom register is 32 bits wide, therefore 32 data bits d(31:0) are sent across the interface. at least 20 ms delay is required after ev- ery transaction before any new access can start. eeprom read access is shown in figure 17 . the start bit is followed with the 4 bit read command 1100 and the 3 bit address a(2:0). an idle clock cycle is used to avoid any contention on sdat while reversing data ?ow direction. finally d(31:0) is shifted out on sdat. eeprom read access is slow. at least one extra clock with sdat low is required after every transaction on the 2-wire interface before a new access is started. the interface will not work correctly if this clock cycle is omitted. refer to table 32 regarding timings requirements. please note, given timing speci?cations scale with f osc . for instance, with f osc = 22 mhz timings are reduced by 10%. eeprom commands c 1 e b description purpose 0 1 0 0 erase followed by write normal eeprom programming 0 1 0 1 block erase followed by block write test only 0 1 1 0 write special production environment 0 1 1 1 block write test only 1 1 0 0 read. please refer to figure 17 for more details 1 1 0 1 reserved. do not use this command 1 1 1 0 erase test only 1 1 1 1 block erase special production environment table 31: eeprom commands a0 a1 a2 sdat is sampled on falling edge of sclk extra clocks before new access 0 0 1 sclk sdat 3 bit address 32 bit data sdat is driven externally d0 d30 d31 sdat is driven by IC-TW2 new access 0 0 1 1
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 23/ 28 2w-interface timing the timing of the 2w-interface is dependent on the type of access performed. register bank access and eeprom write access can be performed at full speed. eeprom read access requires a slow sclk. also a 20 ms delay is required after every eeprom write ac- cess before a new transaction of any kind is started (this includes read and write to the register bank). figure 18: 2w-interface timing diagram 2w-interface timing parameter description condition min max t sclkhigh sclk high eeprom read access 8 s any other access 400 ns t sclklow sclk low eeprom read access 8 s any other access 400 ns t sdatset sdat setup before falling edge of write access 100 ns sclk t sdathold sdat hold after falling edge of write access 100 ns sclk t sclk2sdat sclk to sdat valid delay eeprom read access 5 ns 7s after rising edge of sclk any other access 5 ns 105 ns notes timings given above are valid for f osc = 20 mhz and scale with f osc . for instance, f osc = 22 mhz reduces all given timings by 10%. table 32: 2w-interface timing trouble shooting to transfer IC-TW2s con?guration data from ram to eeprom command ee_write must be used. power must be available over the whole process taking approx. 100 ms. the suggested 1 f bypass capaci- tors are important. gui button must deliver reliable contents. to help IC-TW2s 2-wire interface not to receive distur- bances, an external pull-down resistor at sclk (e.g. 1 k
) may be used to support its internal pull-down keeping the idle state. IC-TW2s interface does not feature a timeout, and there is no enable pin (as for spi). a certain risk for loosing the synchronisation does exist. for instance, connecting a programming cable may introduce edges to sclk, so that the interface is not synchronized for communication anymore. in case of communication problems try to reset IC-TW2 by pulling pin nrst low. when doing so, there should be no communication. another solution can be to clear the interface by ap- plying approx. 50 clock pulses to sclk while sdat is held low. data write t sclkhigh t sclklow data read t sclk2sdat t sclk2sdat t sdathold t sdatset
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 24/ 28 1w-interface the 1w-interface provides a write-only access port to the register bank. it is intended as a minimal con- ?guration interface to program the internal eeprom during in-?eld service or production. an infrared pho- totransistor can directly connect to the pin to build a cost effective wireless write port. the input bit stream is pulse-width modulated (or duty-cycle modulated) as shown in figure 19 . a zero-bit is encoded as a short low followed by a long high. a one-bit is encoded as a long low followed by a short high. the modulated sig- nal is independent of the receiver or transmitter clock frequency. since the IC-TW2 uses a free-running oscil- lator, it is important to implement a robust, frequency- insensitive protocol. figure 19: pulse width modulated bit stream the interface timing is speci?ed in the following table. parameter description min max t 0low low time bit 0 40 s 100 s t 0hi high time bit 0 120 s 200 s t 1low low time bit 1 120 s 200 s t 1high high time bit 1 40 s 100 s table 33: 1w-interface timing 1w-interface write sequence figure 20 describes the write sequence to the regis- ter bank, which uses the same protocol as the 2w- interface. on an idle wire, a write sequence is initiated by writing a start bit (1) followed by the write command (00) followed by the address and register data. at the end of the sequence, a stop-bit (0) is required. 1w-interface write access to the eeprom bank is shown in figure 21 . the 4 bit eeprom command af- ter the start bit is decoded in table 31 . writing the register bank to the eeprom to permanently store a con?guration in the internal eeprom the following procedure should be followed. 1. the 1w- / 2w-interface is used to fully write the desired con?guration into the register bank. 2. a logic one is written to bit ee_write of regis- ter 0x0e. this will initiate a write sequence which copies all registers into the internal eeprom. a complete write takes 100 ms. during this time, no access to the register bank through either the 1w- / 2w-interface is allowed or data corruption might occur. 3. finally the register content, after a device reset and con?guration, should be veri?ed to ensure a successfull eeprom write sequence. writing the registers to the eeprom using ee_write takes up to 100 msec. during this access to the reg- ister bank either through the 1w- or 2w-interface is prohibited. any access will corrupt data written to the eeprom. ee_write addr. 0x0e; bit 6 w code function, bit is automatically reset upon completion of operation 0 normal operation (default) 1 store registers into eeprom table 34: eeprom store command figure 20: 1w-interface register bank write se- quence figure 21: 1w-interface eeprom write sequence t 1low idle idle 1 t 0low t 0hi 0 t 1hi 1 0 0 0 0 0 1 address(4:0) data(7:0) idle idle start bit write to regbank register bank address 8 bit register data stop bit address(2:0) b e 0 c 1 1 data(31:0) idle idle start bit eeprom command eeprom bank address 32 bit eeprom data stop bit
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 25/ 28 test modes the IC-TW2 provides various control bits located in dif- ferent registers to enable or disable certain test modes. the majority of these is only required for extended chip testing capability, others are required for production test. granular addr. 0x05; bit 7 r/w code function, test mode only 0 normal operation 1 test mode only table 35: a/b output edge granularity control vc(1:0) addr. 0x0a; bit 6:5 r/w code function, test mode only register must be set to 0 for correct device functionality table 36: reference voltage ?ne tuning clkmode addr. 0x0b; bit 0 r/w code function, test mode only 0 select comparator clock default 1 select direct oscillator clock table 37: clock source select clkdly addr. 0x0b; bit 2 r/w code function 0 normal operation 1 add clock delay table 38: clock distribution delay line selection enabling the position monitor will allow access to the internal absolute period position. the position can be read through register 0x0f. this is considered a test mode and should not be used during normal opera- tion. en_mon addr. 0x0b; bit 3 r/w code function 0 position monitor disabled default 1 monitor enabled table 39: position monitor control monitor(7:0) addr. 0x0f; bit 7:0 r/w code function access to the internal absolute period position. rt only! table 40: monitor register ee_read addr. 0x0e; bit 7 w code function 0 normal operation 1 read all IC-TW2 registers from the eeprom. bit is automatically reset upon completion. not required during normal operation since this is done automatically on start-up. table 41: eeprom read command register production test control bits production test control bits are reserved bits. do not use the production test control bits during normal op- eration. keep reserved bits 0. reserved addr. 0xc; bit 7:1 r/w reserved addr. 0xd; bit 7:0 r/w reserved addr. 0xe; bit 2:0 r/w code function 0 normal operation 1 . . . do not use or alter to table 42: test modes
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 26/ 28 typical applications the circuit in figure 22 depicts a typical application. differential sensor signals (or differential sine/cosine encoder signals) are directly connected to the IC-TW2. index gating is single ended active low as is frequently the case when using a hall switch. the vc signal of 1.21 v is used to bias the positive input pinz. it is rec- ommended to decouple pin vc with a small capacitor when it is used as a reference. when pin vc is left unconnected, no capacitor is required. although IC-TW2 features internal pull-down current sources to de?ne default pin levels, an additional pull- down resistor at pin sclk can be recommended to reduce its disturbance and cross talk sensitivity. when using pins nrst (low active reset input) and 1w (programming) is not intended, r1 and r2 can be re- placed by shorts to vdd. figure 22: application circuit with differential sin/cos sensor bridges and a hall switch for index sensing. i n d e x s e n s o r a c t i v e l o w d i g i t a l h a l l , s e n s o r b r i d g e b i c - t w 2 g a t e d i n d e x o u t p u t d i f f e r e n t i a l a / b o u t p u t b r i d g e a s e n s o r 1 f c 2 r 2 1 0 k 5 . 6 v d 1 t v s - d i o d e - a r r a y c 3 1 0 0 n f 1 f c 1 r 3 1 0 k 1 0 k 1 k r 4 r 1 + 5 v g n d a ( 1 1 ) n i n a ( 1 7 ) p i n a ( 1 8 ) g n d c l k e x t ( 2 3 ) s d a t ( 2 4 ) n i n z ( 2 0 ) v c ( 1 9 ) v d d ( 1 ) b _ v ( 2 ) n b _ n v ( 3 ) a _ u ( 4 ) n a _ n u ( 5 ) 1 w ( 9 ) z _ w ( 8 ) n . c . ( 1 2 ) c l k s e l ( 1 5 ) p i n b ( 1 3 ) g n d ( 6 ) n z _ n w ( 7 ) n i n b ( 1 4 ) n r s t ( 1 6 ) s d a t s c l k s c l k ( 2 2 ) p i n z ( 2 1 ) n b p a n z p z p b n a 0 v v d d a ( 1 0 ) + 5 v r 4 1 k 1 0 k r 3 1 0 0 n f c 3 c 1 1 f t v s - d i o d e - a r r a y d 1 5 . 6 v 1 0 k r 2 c 2 1 f 1 0 k r 1
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 27/ 28 pcb layout guidelines the IC-TW2 is a noise sensitive mixed signal device, which requires careful pcb layout considerations. vi- olating the layout guidelines can result in poor perfor- mance. please consider figure 23 . power pins vdda (pin 10) and vdd (pin 1) must be decoupled with 1 f. trace length to vdd pins must be no longer than 3 mm. the decoupling caps can be placed on the bottom side of the pcb directly connecting it to the IC-TW2 pads using vias. ground pins gnd (pin 6) and gnda (pin 11) must be tied to the center exposed pad. the exposed pad is then directly connected to the pcb ground plane using several vias. figure 23: pcb layout guidelines ic-haus expressly reserves the right to change its products and/or speci?cations. an info letter gives details as to any amendments and additions made to the relevant current speci?cations on our internet website www.ichaus.de/infoletter ; this letter is generated automatically and shall be sent to registered users by email. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the speci?cation and does not assume liability for any errors or omissions in these materials. the data speci?ed is intended solely for the purpose of product description. no representations or warranties, either express or implied, of merchantability, ?tness for a particular purpose or of any other nature are made hereunder with respect to information/speci?cation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. max 3 mm from vdd pin 1 and 10 to 1 f decoupling caps. vss pin 6 and 11 tied to exposed pad. ep strapped to ground plane using several vias . 1 f c603 1 f c603
IC-TW2 8-bit sin/cos interpolation ic with integrated eeprom rev e2, page 28/ 28 ordering information type package order designation IC-TW2 24 pin qfn, 4 mm x 4 mm IC-TW2 qfn24 evaluation board pcb 100 mm x 80 mm IC-TW2 eval tw2_2d for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (61 35) 92 92-0 am kuemmerling 18 fax: +49 (61 35) 92 92-192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.com/sales_partners

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