surface mount package super high density cell design for extremely low r ds(on) c c f l inverter drain-source voltage v ds 60 v gate-source voltage v gs 20 v continuous dr ain c urrent (note 1) i d 4. a pulsed drain cu rrent (tp=10us ) i dm 1 a continous source-drai n diode current i s 4. a drain-source voltage v ds -60 v gate-source voltage v gs 20 v continuous dr ain c urrent (note 1) i d -3 a pulsed drain cu rrent (tp=10us ) i dm -1 a continous source-drai n diode current i s -3 a power diss ipation p d w thermal resistance from junction to ambient (note 1) r ja /w junction temperature t j 150 storage temperature t stg -55~+150 lead temperature for solderi ng purposes( 1/8 from case for 10 s) t l 260 equivalent circuit v (br) dss r ds(on) max i d 3 ma r 6 soli d dot = green molding compound device, if none,the normal device. q4559 = device code yy =da t e code solid dot = pin1 indicator
drain-source breakdown voltage v (br)dss v gs = 0v, i d =250a 60 v zero gate voltage drain curren t i dss v ds =60v,v gs = 0v 1 a gate-body leakage current i gss v gs =20v, v ds = 0v 100 na gate threshold voltage (note 2) v gs(th) v ds =v gs , i d =250a 1 2.1 3 v drain-source on-resistan ce (note 2) r ds(on) v gs =10v, i d =4.3a 40 58 m v gs =4.5v, i d =3.9a 55 72 m forward tranc onductance (note 2) g fs v ds =15v, i d =4.3a 15 s diode forward voltage v sd i s =1.7a, v gs = 0v 1.2 v input capacitance c iss v ds =15v,v gs =0v,f =1mhz 665 pf output capacitance c oss 75 pf reverse transfer capacitance c rss 40 pf gate resistance r g f=1mhz 3 turn-on delay time t d(on) v gen =4.5v,v dd =30v, i d =3.4a, r g =1 ?r l =8.8 ? 25 ns turn-on rise time t r 100 ns turn-off delay time t d(off) 25 ns turn-off fall time t f 15 ns total gate charge q g v ds =30v,i d =4.3a, v gs =4.5v 9 nc gate-source charge q gs 2.3 nc gate-drain charge q gd 2.6 nc drain-source breakdo wn voltage v (br)dss v gs = 0v, i d =-250a -60 v zero gate voltage drain curren t i dss v ds =-60v,v gs = 0v -1 a gate-body leakage current i gss v gs =20v, v ds = 0v 100 na gate threshold voltage (note 2) v gs(th) v ds =v gs , i d =-250a -1 -2.8 -3 v drain-source on-resistan ce (note 2) r ds(on) v gs =-10v, i d =-3.1a 60 0 m v gs =-4.5v, i d =-0.2a 92 100 m forward tranc onductance (note 2) g fs v ds =-15v, i d =-3.1a 8.5 s diode forward voltage v sd i s =-2a, v gs = 0v -1.2 v input capacitance c iss v ds =-15v,v gs =0v,f =1mhz 650 pf output capacitance c oss 95 pf reverse transfer capacitance c rss 60 pf gate resistance r g f=1mhz 20 turn-on delay time t d(on) v gen =-4.5v,v dd =-30v, i d =-2.4a,r g =1 r l =12.5 ? 45 ns turn-on rise time t r 105 ns turn-off delay time t d(off) 60 ns turn-off fall time t f 45 ns total gate charge q g v ds =-30v,i d =-3.1a, v gs =-4.5v 12 nc gate-source charge q gs 2.2 nc gate-drain charge q gd 3.7 nc 1.surface mounted on fr 4 board using the minimum recommended pad size. 2. pulse test : pulse width=300s, duty cycle2%. 3. switching characteristics are independent of operating junction temperature. 4. graranted by design not subject to producting. 3r6
outpu t characteristics transfer c haracteristics v gs r ds(on) ?? ?? i d r ds(on) v sd i s ?? t hr e s hol d voltage n-channel 7 \ s l f d o & k d u d f w h u l v w l f v 3r6
v sd i s ? ? outpu t characteristics i d ?? r ds(on) v gs ?? r ds(on) t r an sf er c haracteristics threshold voltage 7 \ s l f d o & k d u d f w h u l v w l f v -channel 3r6
www.cj-elec.com 5 a- 3 , ma r ,2016 sop8 package outline dimensions sop8 suggested pad layout mi n max mi n max a a1 0.100 0.2 50 0.004 0.010 a2 1.3 50 1.5 5 0 0.053 0.0 61 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.007 0.010 d 4.800 5.000 0.189 0.197 e e 5.800 6.200 0.228 0.244 e1 3.800 4.000 0.150 0.157 l 0.400 1.270 0.016 0.050 0 8 0 8 sy m bo l dimensions in millimeters dimensions in inches 0.050bsc 1.270bsc 1.350 1.750 0.053 0.069
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