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revision history AS4C64M16MD2-25BCN / as4c32m32md2-25bcn 134 ball fbga package revision details date rev 1.0 preliminary datasheet july. 2016 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 1/129 - rev.1.0 july 2016
key feature ? double - data rate architecture; two data transfers per clock cycle ? bidirectional data strobes (dqs, dqs#), these are transmitted/received with data to be used in capturing data at the receiver ? differential clock inputs (ck and ck#) ? differential data strobes (dqs and dqs#) ? commands & addresses entered on both positive and negative ck edges; data and data mask referenced to both edges of dqs ? 8 internal banks for concurrent operation ? data mask (dm) for write data ? burst length: 4 (default), 8 or 16 ? burst type: sequential or interleave ? read & write latency : refer to table 47 ? auto precharge option for each burst access ? configurable drive strength ? auto refresh and self refresh modes ? partial array self refresh and temperature compensated self refresh ? deep power down mode ? hsul_12 compatible inputs ? vdd1/vdd2/vddq : 1.8v/1.2v/1.2v ? no dll : ck to dqs is not synchronized ? edge aligned data output, center aligned data input ? auto refresh duty cycle : - 7.8us for - 30 to 85 c table 1. ordering information part number org temperature maxclock (mhz) package as4c 64 m16m d2-25 b c n 64mx16 commercial -30c to + 85c 400 134-ball fbga table 2. speed grade information speed grade clock frequency rl trcd (ns) trp (ns) ddr2l-800 400mhz 6 18 18 as4c32m32md2-25bcn 32mx32 commercial -30c to +85c 400 134 - ball fbga wl 3 AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 2/129 - rev.1.0 july 2016
1. functional block diagrams command / address multiplex & decode control logic mode registers cke ck ck# cs# ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 refresh counter row address mux bank control logic column address counter /latch sense amplifier sense amplifier sense amplifier sense amplifier sense amplifier sense amplifier sense amplifier sense amplifier column decoder i/o gating dm mask logic mem array bank0 bank1 bank2 bank3 bank4 bank5 bank6 bank7 bank0 bank1 bank2 bank3 bank4 bank5 bank6 bank7 read latch mux drvrs rcvrs ck out ck in write fifo & drivers input registers dqs generator x 3 3 x row address latch & decoder y-1 1 4n n 4n n n n n dqs,dqs# data 8 4n data mask n n n n 4 4 4 4 4 4 4 4 n n n n 4 n dqs, dqs# dq0 - dqn-1 dm ck, ck# col0 col0 AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 3/129 - rev.1.0 july 2016
2. ball descriptions 2-1. pad definition and description name type description ck, ck# input clock : ck and ck# are differential clock inputs. all double data rate (ddr) ca inputs are sampled on both positive and negative edge of ck. single data rate (sdr) inputs, cs# and cke, are sampled at the positive clock edge. clock is defined as the differential pair, ck and ck #. the positive clock edge is defined by the crosspoint of a rising ck and a falling ck#. the negative clock edge is defined by th e crosspoint of a falling ck and a rising ck#. cke input clock enable: cke high activates and cke low deactivates internal clock signals and therefore device input buffers and output drivers. power savings modes are entered and exited through cke transitions. cke is considered part of the command code. see command truth table for command code descriptions. cke is sampled at the positive clock edge. cs # input chip select: cs # is considered part of the command code. see command truth table for command code descriptions. cs # is sampled at the positive clock edge. ca0 - ca9 input ddr command/address inputs: uni-directional command/address bus inputs. ca is considered part of the command code. see command truth table for command code descriptions. dq0 - dq15 (x16) dq0 - dq31 (x32) i/o data inputs/output: bi -directional data bus dqs0, dqs0#, dqs1, dqs1# (x16) dqs0 - dqs3, dqs0# - dqs3 (x32) i/o data strobe (bi-directional, differential): the data strobe is bi-directional (used for read and write data) and differential (dqs and dqs#). it is output with read data and input with write data. dqs is edge-aligned to read data and centered with write data. for x16, dqs0 and dqs0# correspond to the data on dq0 - dq7; dqs1 and dqs1# to the data on dq8 - dq15. for x32 dqs0 and dqs0# correspond to the data on dq0 - dq7, dqs1 and dqs1# to the data on dq8 - dq15, dqs2 and dqs2# to the data on dq16 - dq23, dqs3 and dqs3# to the data on dq24 - dq31. dm0-dm1 (x16) dm0 - dm3 (x32) input input data mask: for lpddr2 devices that do not support the dnv feature, dm is the input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm is for input only, the dm loading shall match the dq and dqs (or dqs#). dm0 is the input data mask signal for the data on dq0- 7. for x16 and x32 devices, dm1 is the input data mask signal for the data on dq8-15. for x32 devices, dm2 is the input data mask signal for the data on dq16-23 and dm3 is the input data mask signal for the data on dq24-31. vdd1 supply core power supply 1: core power supply v dd2 supply core power supply 2: core power supply v ddq supply i/o power supply: power supply for data input/output buffers. v ref(ca) supply reference voltage for ca command and control input receiver: reference voltage for all ca0-9, cke, cs#, ck , and ck# input buffers. v ref(dq) supply reference voltage for dq input receiver: reference voltage for all data input buffers v ss supply ground v ssq supply i/o ground zq i/o reference pin for output drive strength calibration note : data includes dq and dm ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 4/129 - rev.1.0 july 2016
lpddr2 sdram addressing item 1gb number of banks 8 bank address pins ba0~ ba 2 auto precharge pin a10/ap x16 row addresses r0 -r12 column addresses c0 - c9 trefi(s) 7.8 x 32 row addresses r0 -r12 column addresses c0- c8 trefi(s) 7.8 note 1. the least-significant column address c0 is not transmitted on the ca bus, and is implied to be zero. note 2. trefi values for all bank refresh is tc = -25~85 , tc means operating case temperature. note 3. row and column address values on the ca bus that are not used are dont care. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 5/129 - rev.1.0 july 2016
2-2. package dimen sion : 134-ball fbga C 10mm x 11.5m m x 1.0m m (max) AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 6/129 - rev.1.0 july 2016
2-3. package ballout 1st row power ground 2nd row zq nc/dnu nb x32 device x16 device 1 2 3 4 5 6 7 8 9 10 a dnu dnu nb nb nb nb nb nb dnu dnu b dnu nc nc nb vdd2 vdd1 dq31 nc dq29 nc dq26 nc dnu c vdd1 vss nc nb vss vssq vddq dq25 nc vssq vddq d vss vdd2 zq0 nb vddq dq30 nc dq27 nc dqs3 nc dqs3# nc vssq e vss ca9 ca8 nb dq28 nc dq24 nc dm3 nc dq15 vddq vssq f nc ca6 ca7 nb vssq dq11 dq13 dq14 dq12 vddq g vdd2 ca5 vref(ca) nb dqs1# dqs1 dq10 dq9 dq8 vssq h nc vss ck# nb dm1 vddq nb nb nb nb j vss nc ck nb vssq vddq vdd2 vss vref(dq) nb k cke nc nc nb dm0 vddq nb nb nb nb l cs# nc nc nb dqs0# dqs0 dq5 dq6 dq7 vssq m ca4 ca3 ca2 nb vssq dq4 dq2 dq1 dq3 vddq n vss nc ca1 nb dq19 nc dq23 nc dm2 nc dq0 vddq vssq p vss vdd2 ca0 nb vddq dq17 nc dq20 nc dqs2 nc dqs2# nc vssq r vdd1 vss nc nb vss vssq vddq dq22 nc vssq vddq t dnu nc nc nb vdd2 vdd1 dq16 nc dq18 nc dq21 nc dnu u dnu dnu nb nb nb nb nb nb dnu dnu 134ball fbga [top view] AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 7/129 - rev.1.0 july 2016
3. functional description lpddr2 is a high-speed sdram device internally configured as a 8-bank memory. these devices contain the following number of bits: 1 gb has 1,073,741,824 bits lpddr2-s4 uses a double data rate architecture on the command/address (ca) bus to reduce the number of input pins in the system. the 10-bit ca bus contains command, address, and bank information. each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock. lpddr2-s4 uses a double data rate architecture on the dq pins to achieve high speed operation. the double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per dq every clock cycle at the i/o pins. a single read or write access for the lpddr2-s4 effectively consists of a single 4n -bit wide, one clock cycle data transfer at the internal sdram core and four corresponding n-bit wide, one- half - clock-cy cle data transfers at the i/o pins. read and write accesses to the lpddr2 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. for lpddr2-s4 devices, accesses begin with the registration of an activate command, which is then followed by a read or write c ommand. the address and ba bits registered coincident with the activate command are used to select the row and the bank to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access.prior to normal operation, the lpddr2 must be initialized. . AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 8/129 - rev.1.0 july 2016
3.1 simplified lpddr2 bus interface state diagram the simplified lpddr2 bus interface state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. for a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth tables and timing specification. the truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. for the command definition, see lpddr2 command definitions and timing diagrams AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 9/129 - rev.1.0 july 2016
simplified lpddr2 bus interface state diagram figure 3.1 lpddr2 : simplified bus interface state diagram note 1 these transitions apply for lpddr2-sx devices only. note 2 for lpddr2-sdram in the idle state, all banks are precharged. note 3 use caution with this diagram. it is intented to provide a floorplan of the possible state transitions and commands to control them, not all details. in particular, situations involving more than one bank/row AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 10/129 - rev.1.0 july 2016
3.2 power-up, initialization, and power- off lpddr2 devices must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation 3.2.1 power ramp and device initialization the following sequence shall be used to power up an lpddr2 device. 1. power ramp while applying power (after ta ), cke shall be held at a logic low level (=< 0.2 x vdd2), all other inputs shall b e be tween vilmin and vihmax. the lpddr2 device will only guarantee that outputs are in a high impedance state while cke is held low. on or before the completion of the power ramp ( tb ) cke must be held low. dq, dm, dqs and dqs# voltage levels must be between vssq and vddq during voltage ramp to avoid latch-up. ck , ck# , cs#, and ca input levels must be between vssca and vdd2 during voltage ramp to avoid latch- up. the following conditions apply: ta is the point where any pow er supply first reaches 300 mv. after ta is reached, vdd1 must be greater than vdd2 - 200 mv. after ta is reached, vdd1 and vdd2 must be greater than vdd2 - 200 mv. after ta is reached, vdd1 and vdd2 must be greater than vddq - 200 mv. after ta is reached, vref must always be less than all other supply voltages. the voltage difference between any of vss, vssq, and vssca pins may not exceed 100 mv. the above conditions apply between ta and power-off (controlled or uncontrolled). tb is the point when all supply voltages are within their respective min/max operating conditions. reference voltages shall be within their respective min/max operating conditions a minimum of 5 clocks before cke goes high. power ramp duration tinit0 ( tb - ta ) must be no greater than 20 ms. note vdd2 is not present in some systems. rules related to vdd2 in those cases do not apply. 2. cke and clock: beginning at tb , cke must remain low for at least t init1 = 100 ns, after which it may be asserted high. clock must be stable at least t init2 = 5 x tck prior to the first low to high transition of cke ( tc ). cke, cs# and ca inputs must observe setup and hold time (tis, tih) requirements with respect to the first rising clock edge (as well as to the subsequent falling and rising edges). the clock period shall be within the range defined for t ck b (18 ns to 100 ns), if any mode register reads are performed. mode register writes can be sent at normal clock operating frequencies so long as all ac timings are met. furthermore, some ac parameters (e.g. t dqsck ) may have relaxed timings (e.g. t dqsck b ) before the system is appropriately configured. while keeping cke high, issue nop commands for at least t init3 = 200 us. ( td ). 3. reset command: after t init3 is satisfied, a mrw(reset) command shall be issued ( td ). the memory controller may optionally issue a precharge-all command (for lpddr2-sx) to the mrw reset command . wait for at least t init4 = 1 us while keeping cke asserted and issuing nop commands. 4. mode registers reads and device auto-initialization (dai) polling: after tinit4 is satisfied ( te ) only mrr commands and power-down entry/exit commands are allowe d. therefore, after te , cke may go low in accordance to power-down entry and exit specification (see powerdown ). the mrr command may be used to poll the dai-bit to acknowledge when device auto-initialization is complete or the memory controller shall wait a minimum of tinit5 before proceeding. as the memory output buffers are not properly configured yet, some ac parameters may have relaxed timings before the system is appropriately configured. after the dai- bit (mr0, dai) is set to zero dai complete by the memory device, the device is in idle state ( tf ). the state of the dai status bit can be determined by an mrr command to mr0. all sdram devices will set the dai-bit no later than tinit5 (10 us) after the reset command. the memory controller shall wait a minimum of tinit5 or until the dai-bit is set before proceeding. after the dai-bit is set, it is recommended to determine the device type and other device characteristics by issuing mrr commands (mr0 device information etc.). 5. zq calibration: after tinit5 ( tf ), an mrw zq initialization calibration command may be issued to the memory (mr 10 ). for ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 11/129 - rev.1.0 july 2016
lpddr2 devices which do not support the zq calibration command, this command shall be ignored. this command is used to calibrate the lpddr2 output drivers (ron) over process, voltage, and temperature. optionally, the mrw zq initialization calibration command will update mr0 to indicate rzq pin connection. in systems in which more than one lpddr2 device exists on the same bus, the controller must not overlap zq calibration commands. the device is ready for normal operation after tzqinit. 6. normal operation: after tzqinit ( tg ), mrw commands shall be used to properly configure the memory, for example the output buffer driver strength, latencies etc. specifically, mr1, mr2, and mr3 shall be set to configure the memory for the target frequency and memory configuration. the lpddr2 device will now be in idle state and ready for any valid comman d. after tg , the clock frequency may be changed according to the clock frequency change procedure described in section input clock stop and frequency change of this specification. table 1 C timing parameters for initialization s y m b o l v a l u e u n i t c o m m e n t m i n m a x tinit0 20 ms maximum power ramp time tinit1 100 ns minimum cke low time after completion of power ramp tinit2 5 tck minimum stable clock before first cke high tinit3 200 us minimum idle time after first cke assertion tinit4 1 us minimum idle time after reset command tinit5 10 us maximum duration of device auto-initialization tzqinit 1 us zq initial calibration for lpddr2-s4 devices tckb 18 100 ns clock cycle time during boot ck/ck# cke tb tc td te tf tg ta ca r tt dq supplies reset mrr mrw zqcal valid t init2 t init0 t init1 t init3 t iscke t init5 t init4 t zqinit figure 3.2 power ramp and initialization sequence 3. 2.2 initialization after reset (without power ramp): if the reset command is issued outside the power up initialization sequence, the reinitialization procedure shall begin with step 3 (td). 3. 2.3 power-off sequence the following sequence shall be used to power off the lpddr2 device. unless specified otherwise, these steps are mandatory and apply to s4 devices. while removing power, cke shall be held at a logic low level (=< 0.2 x vdd2), all other inputs shall be between vilmin and vihmax. the lpddr2 device will only guarantee that outputs are in a high impedance state while cke is held low. dq, dm, dqs, and dqs# voltage levels must be between vssq and vddq during power off sequence to avoid latch-up. ck , ck#, cs#, and ca input levels must be between vssca and vdd2 during power off sequence to avoid latch- up. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 12/129 - rev.1.0 july 2016
tx is the point where any power supply decreases under its minimum value specified in the dc operating condition table. tz is the point where all power supplies are below 300 mv. after tz, the device is powered off. the time between tx and tz (tpoff) shall be less than 2s. the following conditions apply: between tx and tz, vdd1 must be greater than vdd2 - 200 mv. between tx and tz, vdd1 and vdd2 must be greater than vdd2 - 200 mv. between tx and tz, vdd1 and vdd2 must be greater than vddq - 200 mv. between tx and tz, vref must always be less than all other supply voltages. the voltage difference between any of vss, vssq, and vssca pins may not exceed 100 mv. table 2 C timing parameters power- off symbol value unit comment min max tpoff - 2 s maximum power-off ramp time 3. 2.4 uncontrolled power- off sequence the following sequence shall be used to power off the lpddr2 device under uncontrolled condition. tx is the point where any power supply decreases under its minimum value specified in the dc operating condition table. after turning off all power supplies, any power supply current capacity must be zero, except for any static charge remaining in the system. tz is the point where all power supply first reaches 300 mv. after tz, the device is powered off. the time between tx and tz (tpoff) shall be less than 2s. the relative level between supply voltages are uncontrolled during this period. vdd1 and vdd2 shall decrease with a slope lower than 0.5 v/usec between tx and tz. uncontrolled power off sequence can be applied only up to 400 times in the life of the device. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 13/129 - rev.1.0 july 2016
3. 3 mode register definition 3. 3.1 mode register assignment and definition in lpddr2 sdram table 3 shows the 16 common mode registers for lpddr2 sdram table 4 shows only lpddr2 sdram mode registers. additionally table 5 shows rfu mode registers and reset command. each register is denoted as r if it can be read but not written, w if it can be written but not read, and r/w if it can be read and written. mode register read command shall be used to read a register. mode register write command shall be used to write a register. table 3 C mode register assignment in lpddr2 sdram mr# ma<7:0> function access op7 op6 op5 op4 op3 op 2 op1 op0 0 00h device info. r (rfu) rzqi (rfu) di dai 1 01h device feature 1 w nwr(for ap) wc bt bl 2 02h device feature 2 w (rfu) rl & wl 3 03h i/o config-1 w (rfu) ds 4 04h refresh rate r tuf (rfu) refresh rate 5 05h basic config-1 r lpddr2 manufacturer id 6 06h basic config-2 r revision id1 7 07h basic config-3 r revision id2 8 08h basic config-4 r i/o width density type 9 09h test mode w vendor-specific test mode 10 0ah io calibration w calibration code 11:15 0bh~0fh (reserved) (rfu) table 4 mode register assignment in lpddr2 sdram mr# ma<7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 16 10h pasr_bank (s4) w bank mask 17 11h pasr_seg w segment mask 18:19 12h:13h (reserved) (rfu) mode register assignment in lpddr2 sdram (nvm part) mr# ma<7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 20:31 14h~1fh (do not use) AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 14/129 - rev.1.0 july 2016
table 5 C mode register assignment in lpddr2 sdram mr# ma<7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 32 20h dq calibration pattern a r see " dq calibration: 33:39 21h:27h (do not use) 40 28h dq calibration pattern b r see " dq calibration: 41:47:00 29h:2fh (do not use) 48:62 30h~3eh (reserved) (rfu) 63 3fh reset w x 64:126 40h:7eh (reserved) (rfu) 127 7fh (do not use) 128:190 80h: beh reserved for vendor use) (rfu) 191 bfh (do not use) 192:254 c0h:feh reserved for vendor use) (rfu) 255 ffh (do not use) the following notes apply to tables 3-5: note 1 rfu bits shall be set to 0 during mode register writes. note 2 rfu bits shall be read as 0 during mode register reads. note 3 all mode registers that are specified as rfu or write-only shall return undefined data when read and dqs,dqs# shall be toggled. note 4 all mode registers that are specified as rfu shall not be written. note 5 writes to read-only registers shall have no impact on the functionality of the device. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 15/129 - rev.1.0 july 2016
mr0 device information (ma <7:0> =00h) : op7 op6 op5 op4 op3 op2 op1 op0 rfu rzqi (optional) rfu di dai dai(device auto-initialization status) read-only op0 0 b : dai complete 1 b : dai still in progress di (device information) read-only op1 0 b : s4 sdram 1 b : do not use rzqi ( built in self test for rzq information) read -only op4:op3 00 b : rzq self test not supported) 01 b : zq-pin may connect to vdd2 or float 10 b : zq-pin may shor t to gnd 11 b : zq-pin sel f test completed, no error condition de tected (zq -pin may not connect to vdd2 or float nor short to gnd) 1 note 1 rzqi, if supported, will be set upon completion of the mrw zq initialization calibration command. note 2 if zq is connected to vdd2 to set default calibration, op[4:3] shall be set to 01. if zq is not connected to vdd2, either op[4:3]=01 or op[4:3]=10 might indicate a zq-pin assembly error. it is recommended that the assembly error is corrected. note 3 in the case of possible assembly error (either op[4:3]=01 or op[4:3]=10 per note 4), the lpddr2 device will default to factory trim settings for ron, and will ignore zq calibration commands. in either case, the system may not function as intended. note 4 in the case of the zq self-test returning a value of 11b, this result indicates that the device has detected a resistor connection to the zq pin. however, this result cannot be used to validate the zq resistor value or that the zq resistor tolerance meets the specified limits (i.e., 240-ohm +/-1%). AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 16/129 - rev.1.0 july 2016
mr1 device feature 1 (ma <7:0> =01h) : op7 op6 op5 op4 op3 op2 op1 op0 nwr (for ap) wc bt bl bl write - only op<2:0> 010 b : bl4 (default) 011 b : bl8 110 b : bl16 all others : reserved bt write - only op<3> 0 b : sequential (default) 1 1 b : interleaved wc write - only op<4> 0 b : wrap (default) 1 b : no wrap (allowed for sdram bl4 only) nwr write - only op<7:5> 001 b : nwr =3(default) 010 b : nwr =4 011 b : nwr =5 100 b : nwr =6 101 b : nwr =7 110 b :nwr =8 all others : reserved 2 note 1 bl 16, interleaved is not an official combination to be supported. note 2 programmed value in nwr register is the number of clock cycles which determines when to start internal precharge operation for a write burst with ap enabled. it is determined by ru(twr/tck). AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 17/129 - rev.1.0 july 2016
table 6 - burst sequence by bl,bt, and wc c3 c2 c1 c0 w/c bt bl burst cycle number are burst address sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 0 b 0 b wrap any 4 0 1 2 3 x x 1 b 0 b 2 3 0 1 x x x 0 b nw any y y+1 y+2 y+3 x 0 b 0 b 0 b wrap seq 8 0 1 2 3 4 5 6 7 x 0 b 1 b 0 b 2 3 4 5 6 7 0 1 x 1 b 0 b 0 b 4 5 6 7 0 1 2 3 x 1 b 1 b 0 b 6 7 0 1 2 3 4 5 x 0 b 0 b 0 b int 0 1 2 3 4 5 6 7 x 0 b 1 b 0 b 2 3 0 1 6 7 4 5 x 1 b 0 b 0 b 4 5 6 7 0 1 2 3 x 1 b 1b 0 b 6 7 4 5 2 3 0 1 x x x 0 b nw any illegal (not allowed) 0 b 0 b 0 b 0 b wrap seq 16 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 b 0 b 1 b 0 b 2 3 4 5 6 7 8 9 a b c d e f 0 1 0 b 1 b 0 b 0 b 4 5 6 7 8 9 a b c d e f 0 1 2 3 0 b 1 b 1 b 0 b 6 7 8 9 a b c d e f 0 1 2 3 4 5 1 b 0 b 0 b 0 b 8 9 a b c d e f 0 1 2 3 4 5 6 7 1 b 0 b 1 b 0 b a b c d e f 0 1 2 3 4 5 6 7 8 9 1 b 1 b 0 b 0 b c d e f 0 1 2 3 4 5 6 7 8 9 a b 1 b 1 b 1 b 0 b e f 0 1 2 3 4 5 6 7 8 9 a b c d x x x 0 b int illegal (not allowed) x x x 0 b nw any illegal (not allowed) 1. c0 input is not present on ca bus. it is implied zero. 2. for bl=4, the burst address represents c1 - c0. 3. for bl=8, the burst address represents c2 - c0. 4. for bl=16, the burst address represents c3 - c0. 5. for no-wrap (nw), bl4, the burst shall not cross the page boundary and shall not cross sub-page boundary. the variable y may start at any address with c0 equal to 0 and may not start at any address in table 7 for the respective density and bus width combinations. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 18/129 - rev.1.0 july 2016
table 7 C lpddr2- sx non wrap restrictions 1 gb not across full page boundary x16 3fe, 3ff, 000, 001 x32 1fe, 1ff, 000, 001 not across sub page boundary x16 1fe, 1ff, 200, 201 x32 none note 1 non - wrap bl =4 data-orders shown above are prohibited mr2 device feature 2 (ma <7:0> =02h) : op7 op6 op5 op4 op3 op2 op1 op0 (rfu) rl & wl rl & wl write- only op<3:0> 0001 b : rl =3 /wl=1(default) 0010 b : rl =4 /wl=2 0011 b : rl =5 /wl=2 0100 b : rl =6 /wl=3 0101 b : rl =7 /wl=4 0110 b :rl =8 /wl=4 all others : reserved mr3 i/o configuration 1 (ma <7:0> =03h) : op7 op6 op5 op4 op3 op2 op1 op0 (rfu) ds ds write- only op<3:0> 0000 b : reserved 0001 b : 34.3-ohm typical 0010 b : 40-ohm typical (default) 0011 b : 48-ohm typical 0100 b : 60-ohm typical 0101 b : reserved for 68.6-ohm typical 0110 b :80-ohm typical 0111 b :120-ohm typical (optional) all others : reserved mr4 device temperature (ma <7:0> =04h) : op7 op6 op5 op4 op3 op2 op1 op0 tuf (rfu) sdram refresh rate sdram refresh rate read - only op<2:0> 000 b : sdram low temperature operating limit exceeded 001 b : 4x t ref , 4x t reflqb , 4x t refw 010 b : 2x t ref , 2x t reflqb , 2x t refw 011 b : 1x t ref , 1x t reflqb , 1x t refw ( 100 b : reserved 101 b : 0.25x t ref , 0.25x t reflqb , 0.25x t refw , do not de - rate sdram ac timing 110 b :0 .25x t ref , 0.25x t reflqb , 0.25x t refw , de - rate sdram ac timing 111 b :sdram high temperature operating limit exceeded temperature update flag (tuf) read - only op<7> 0 b : op<2:0> value has not changed since last read of mr4 1 b : op<2:0> value has changed since last read of mr4 note 1 a mode register read from mr4 will reset op7 to 0. note 2 op7 is reset to 0 at power-up. op<2:0> bits are undefined after power- up. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 19/129 - rev.1.0 july 2016
note 3 if op2 equals 1 , the device temperature is greater than 85 note 4 op7 is set to 1 if op2:op0 has changed at any time since the last read of mr4. note 5 lpddr2 might not operate properly when op[2:0] = 000b or 111b. note 6 lpddr2-sx devices shall be de-rated by adding 1.875 ns to the following core timing parameters: trcd, trc, tras, trp, and trrd. tdqsck shall be de-rated according to the tdqsck de-rating in table 52. prevailing clock frequency spec and related setup and hold timings shall remain unchanged. note 8 see temperature sensor for information on the recommended frequency of reading mr4. mr5 basic configuration 1 (ma <7:0> =05h) : op7 op6 op5 op4 op3 op2 op1 op0 lpddr2 manufacture id lpddr2 manufacture id read- only op<7:0> 0000 0000 b : reserved 0000 0001 b : samsung 00 00 0010 b : qimonda 00 00 0011 b : elpida 00 00 0100 b : etron 00 00 0101 b : nanya 00 00 0111 b : mosel 00 00 1000 b : winbond 00 00 1001 b : esmt 00 00 1010 b : reserved 00 00 1011 b : spansion 00 00 1100 b : sst 0000 1101 b : zmos 0000 1110 b : intel 0001 1100 b : alliance 1111 1110 b : numonyx 1111 1111 b : micron all others : reserved mr6_basic configuration 2 (ma<7:0> = 06h): op7 op6 op5 op4 op3 op2 op1 op0 revision id1 revision id1 read- only op<7:0> 000 1 0001 b : q-version note 1 mr6 is vendor specific AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 20/129 - rev.1.0 july 2016
mr7 basic configuration 3 (ma <7:0> =07h) : op7 op6 op5 op4 op3 op2 op1 op0 revision id2 revision id2 read - only op<7:0> 0000 0000 b : a - version note 1 mr7 is vendor specific mr8_basic configuration 4 (ma<7:0> = 08b h ): op7 op6 op5 op4 op3 op2 op1 op0 i/o width density type type read - only op<1:0> 00 b : s4 sdram 01 b : reserved 10 b : do not use 11 b : reserved density read - only op<5:2> 0000 b : 64mb 0001 b : 128mb 0010 b : 256mb 0011 b : 512mb 0100 b : 1gb 0101 b : 2gb 0110 b : 4gb 0111 b 8gb 1000 b : 16gb 1001 b : 32gb all others : reserved i/o width read - only op<7:6> 00 b : x32 01 b : x16 10 b : x8 11 b : not used h ): op7 op6 op5 op4 op3 op2 op1 op0 vendor - specific test mode h ): op7 op6 op5 op4 op3 op2 op1 op0 calibration code calibration code write- only op<7:0> 0xff b : calibration command after initialization 0xab b : long calibration 0x56 b : short calibration 0xc3 b : zq reset others : reserved note 1 host processor shall not write mr10 with reserved values note 2 lpddr2 devices shall ignore calibration command when a reserved value is written into mr10. note 3 see ac timing table for the calibration latency. note 4 if zq is connected to vssca through rzq, either the zq calibration function (see mode register write zq calibration command ) or default calibration (through the zqreset command) is supported. if zq is connected to vdd2, the device operates with default calibration, and zq calibration commands are ignored. in both cases, the zq connection shall not change after power is applied to the AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 21/129 - rev.1.0 july 2016
device. note 5 lpddr2 devices that do not support calibration shall ignore the zq calibration command. not e 6 optionally, the mrw zq initialization calibration command will update mr0 to indicate rzq pin connection. mr11:15_(reserved) (ma<7:0> = 0b h - 0f h ): mr16_pasr_bank mask (ma<7:0> = 010 h ): s2 and s4 sdram only op7 op6 op5 op4 op3 op2 op1 op0 s4 sdram bank mask (4-bank or 8 bank) s4 sdram : bank <7:0> mask write- only op<7:0> 0 b : refresh enable to the bank (=unmasked, default) 1 1 b : refresh blocked (=masked) 1. for 4-bank s4 sdram, only<3:0> are used. op bank mask 4- bank s4 sdram 8- bank s4 sdram 0 xxxx xxx1 bank 0 bank 0 1 xxxx xx1x bank 1 bank 1 2 xxxx x1xx bank 2 bank 2 3 xxxx 1xxx bank 3 bank 3 4 xxx1 xxxx - bank 4 5 xx1x xxxx - bank 5 6 x1xx xxxx - bank 6 7 1xxx xxxx - bank 7 mr17_pasr_segment mask (ma<7:0> = 011 h ): 1gb ~ 8gb s4 sdram only op7 op6 op5 op4 op3 op2 op1 op0 segment mask segment <7:0> mask write- only op<7:0> 0 b : refresh enable to the segment (=unmasked, default) 1 b : refresh blocked (=masked) 1gb 2gb, 4gb 8gb segment op segment mask r12 : 10 r13 : 11 r14 : 12 0 0 xxxx xxx1 000 b 1 1 xxxx xx1x 001 b 2 2 xxxx x1xx 010 b 3 3 xxxx 1xxx 011 b 4 4 xxx1 xxxx 100 b 5 5 xx1x xxxx 101 b 6 6 x1xx xxxx 110 b 7 7 1xxx xxxx 111 b note this table indicates the range of row addresses in each masked segment x is do not care for a particular segment mr18-19_reserved (ma<7:0> = 012 h - 013 h ): mr20- 31 _do not use, nvm only mr32_dq calibration pattern a (ma<7:0> = 20 h ): reads to mr32 return dq calibration pattern a. see dq calibration . mr33:39_(do not use) (ma<7:0> = 21 h - 27 h ): mr40_dq calibration pattern b (ma<7:0> = 28 h ): reads to mr40 return dq calibration pattern b. see dq calibration . ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 22/129 - rev.1.0 july 2016
mr41:47_(do not use) (ma<7:0> = 29 h - 2f h ): mr48:62_(reserved) (ma<7:0> = 30 h - 3e h ): mr63_reset (ma<7:0> = 3f h ): mrw only op7 op6 op5 op4 op3 op2 op1 op0 x note1 for additional information on mrw reset see " mode register write command " mr64:126_(reserved) (ma<7:0> = 40 h - 7e h ): mr127_(do not use) (ma<7:0> = 7f h ): mr128:190_(reserved for vendor use) (ma<7:0> = 80 h - be h ): mr191_(do not use) (ma<7:0> = bf h ): mr192:254_(reserved for vendor use) (ma<7:0> = c0 h - fe h ): mr255_(do not use) (ma<7:0> = ff h ): ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 23/129 - rev.1.0 july 2016
4. lpddr2 command definitions and timing diagrams 4.1 active command 4.1.1 lpddr2-sx: activate command the sdram activate command is issued by holding cs# low, ca0 low, and ca1 high at the rising edge of the clock. the bank addresses ba0 - ba2 are used to select the desired bank. the row address r0 through r14 is used to determine which row to activate in the selected bank. the activate command must be applied before any read or write operation can be executed. the lpddr2 sdram can accept a read or write command at time trcd after the activate command is sent. once a bank has been activated it must be precharged before another activate command can be applied to the same bank. the bank active and precharge times are defined as tras and trp, respectively. the minimum time interval between successive activate commands to the same bank is determined by the ras cycle time of the device (trc). the minimum time interval between activate commands to different banks is trrd. certain restrictions on operation of the 8-bank devices must be observed. there are two rules. one for restricting the number of sequential activate commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are as follows: ?8 -bank device sequential bank activation restriction : no more than 4 banks may be activated (or refreshed, in the case of refpb) in a rolling tfaw window. converting to clocks is done by dividing tfaw[ns] by tck[ns], an d r ounding up to next integer value. as an example of the rolling window, if ru{ (tfaw / tck) } is 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued at or between clock n+1 and n+9. refpb also counts as bank-activation for the purposes of tfaw. ?8 -bank device precharge all allowance : trp for a precharge all command for an 8-bank device shall equal trpab, which is greater than trppb. ck# ck # ca[9:0] cmd t0 t1 t2 t3 tn tn+1 tn+2 tn+3 nop bank m addr row bank n addr row addr bank n col addr col addr activate bank n bank n row addr row addr t rrd t rcd t ras t rp precharge t rc read activate nop nop activate figure 4.1 lpddr2-sx: activate command cycle: t rcd = 3, t rp = 3, t rrd = 2 note 1 a precharge-all command uses trpab timing, while a single bank precharge command uses trppb timing. in this figure, trp is used to denote either an all-bank precharge or a single bank precharge. ck# ck # ca[9:0] cmd tn tn+ tm tm+ tx tx+ ty ty+1 ty+2 tz tz+1 tz+2 activate bank a bank a bank b bank b bank c bank c bank d bank d bank e bank e nop activate nop activate nop activate nop nop nop activate nop t rrd t rrd t rrd t faw figure 4.2 lpddr2- sx: t f aw timing note 1: for 8-bank devices only. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 24/129 - rev.1.0 july 2016
4.2 lpddr2 command input signal timing definition 4.2.1 lpddr2 command input setup and hold timing ck# ck # cs# ca[9:0] cmd t0 t1 t2 t3 nop nop command command ca fall ca rise ca fall ca rise ca fall ca rise ca fall ca rise t is t ih t is t ih t is t ih t is t ih v il(ac) v il(dc) v ih(ac) v ih(dc) transitioning data don t care note : setup and hold conditions also apply to the cke pin. see section related to power down for timing diagrams related to the cke pin. figure 4.3 lpddr2: command input setup and hold timing ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 25/129 - rev.1.0 july 2016
4.3 read and write access modes 4.3.1 lpddr2-sx: read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting cs# low, ca0 high, and ca1 low at the rising edge of the clock. ca2 must also be defined at this time to determine whether the access cycle is a read operation (ca2 high) or a write operation (ca2 low). the lpddr2 sdram provides a fast column access operation. a single read or write command will initiate a burst read or write operation on successive clock cycles. for lpddr2-s4 d evices, a new burst access must not interrupt the previous 4-bit burst operation in case of bl = 4 setting. in case of bl = 8 and bl = 16 settings, reads may be interrupted by reads and writes may be interrupted by writes provided that this occurs on even clock cycles after the read or write command and tccd is met. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 26/129 - rev.1.0 july 2016
4.4 burst read command the burst read command is initiated by having cs# low, ca0 high, ca1 low and ca2 high at the rising edge of the clock. the command address bus inputs, ca5r-ca6r and ca1f-ca9f, determine the starting column address for the burst. the read latency (rl) is defined from the rising edge of the clock on which the read command is issued to the rising edge of the clock from which the tdqsck delay is measured. the first valid datum is available rl * tck + tdqsck + tdqsq after the rising edge of the clock where the read command is issued. the data strobe output is driven low trpre before the first rising valid strobe edge. the first bit of the burst is synchronized with the first rising edge of the data strobe. each subsequent data-out appears on each dq pin edge aligned with the data strobe. the rl is programmed in the mode registers. timings for the data strobe are measured relative to the crosspoint of dqs and its complement, dqs#. ck# ck # dqs# dqs # dq rl-1 rl rl+bl/2 t ch t cl t lz(dqs) t rpre t dqsckmax t rpst t hz(dqs) dout dout dout dout t qh t dqsqmax t qh t dqsqmax t hz(dq) t lz(dq) transitioning data figure 4.4 data output (read) timing (t dqsckmax ) note 1 t dqsck may span multiple clock periods. note 2 an effective burst length of 4 is shown. ck# ck # dqs# dqs # dq rl-1 rl rl+bl/2 t ch t cl t rpre t dqsckmin t rpst t hz(dqs) dout dout dout dout t qh t dqsqmax t qh t dqsqmax t hz(dq) t lz(dq) t lz(dqs) transitioning data figure 4.5 data output (read) timing (t dqsckmin ) note 1 an effective burst length of 4 is shown. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 27/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd dqs# dqs # dq rl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 bank n col addr col addr read nop nop nop nop nop nop nop nop dout a1 dout a2 dout a3 dout a0 t dqsck transitioning data figure 4.6 lpddr2- sx: bu rst read: rl = 5, bl = 4, t dqsck > t ck ck# ck # ca[9:0] cmd dqs# dqs # dq rl = 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 bank n col addr col addr read nop nop nop nop nop nop nop nop t dqsck dout a1 dout a2 dout a3 dout a4 dout a5 dout a6 dout a7 dout a0 transitioning data figure 4.7 lpddr2- sx: bu rst read: rl = 3, bl = 8, t dqsck < t ck ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 28/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd dqs# dqs # dq ck# ck # ca[9:0] cmd dqs# dqs # dq transitioning data rl = 5 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 tn+7 tn+8 col addr read nop nop nop nop nop nop nop nop t dqsckn dout a1 dout a2 dout a3 dout a0 32ms maximum... 1 bank n col addr rl = 5 tm tm+1 tm+2 tm+3 tm+4 tm+5 tm+6 tm+7 tm+8 col addr read nop nop nop nop nop nop nop t dqsckm dout a1 dout a2 dout a3 dout a0 nop 1 ...32ms maximum bank n col addr figure 4.8 lpddr2: t dqsckdl timing note 1 t dqsckdlmax is defined as the maximum of abs( t dqsckn - t dqsckm ) for any { t dqsck n , t dqsckm } pair within any 32ms rolling window. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 29/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd dqs# dqs # dq ck# ck # ca[9:0] cmd dqs# dqs # dq rl = 5 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 tn+7 tn+8 col addr read nop nop nop nop nop nop nop nop t dqsckn dout a1 dout a2 dout a3 dout a0 1.6us maximum... 1 bank n col addr rl = 5 tm tm+1 tm+2 tm+3 tm+4 tm+5 tm+6 tm+7 tm+8 col addr read nop nop nop nop nop nop nop t dqsckm dout a1 dout a2 dout a3 dout a0 nop 1 ...1.6us maximum bank n col addr transitioning data figure 4.9 lpddr2: t dqsckdm timing note 1 t dqsckdmmax is defined as the maximum of abs( t dqsckn - t dqsckm ) for any { t dqsckn , t dqsckm } pair within any 1.6us rolling window ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 30/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd dqs# dqs # dq ck# ck # ca[9:0] cmd dqs# dqs # dq transitioning data rl = 5 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 tn+7 tn+8 col addr read nop nop nop nop nop nop nop nop t dqsckn dout a1 dout a2 dout a3 dout a0 160ns maximum... 1 bank n col addr dou a rl = 5 tm tm+1 tm+2 tm+3 tm+4 tm+5 tm+6 tm+7 tm+8 col addr read nop nop nop nop nop nop nop t dqsckm dout a0 dout a1 dout a2 dout a3 nop 1 ...160ns maximum bank n col addr dout a0 dout a1 dout a2 dout a3 dout a0 dout a1 dout a2 dout a0 dout a1 dout a2 dout a3 dout a2 dout a3 dout a3 figure 4. 10 lpddr2: t dqsckds timing note 1 t dqsckdsmax is defined as the maximum of abs( t dqsckn - t dqsckm ) for any { t dqsckn , t dqsckm } pair for reads within a consecutive burst within any 160ns rolling window. transitioning data ck# ck # ca[9:0] cmd dqs# dqs # dq rl = 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 read nop nop nop nop nop write nop bank n col addr col addr bank n col addr col addr wl = 1 dout a1 dout a2 dout a3 dout a0 nop din a1 din a0 d t dqssmin bl/2 t dqsck figure 4. 11 lpddr2- sx: bu rst read followed by burst write: rl = 3, wl = 1, bl = 4 the minimum time from the burst read command to the burst write command is defined by the read latency (rl) ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 31/129 - rev.1.0 july 2016
and the burst length (bl). minimum read to write latency is rl + ru(tdqsckmax/tck) + bl/2 + 1 - wl clock cycles. note that if a read burst is truncated with a burst terminate (bst) command, the effective burst length of the truncated read burst should be used as bl to calculate the minimum read to write delay. transitioning data ck# ck # ca[9:0] cmd dqs# dqs # dq rl = 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 read nop read nop nop nop nop nop nop bank n col addr a col addr a bank n col addr b col addr b t ccd = 2 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout a0 figure 4.12 lpddr2- sx: s eamless burst read: rl = 3, bl = 4, t ccd = 2 the seamless burst read operation is supported by enabling a read command at every other clock for bl = 4 operation, every 4 clocks for bl = 8 operation, and every 8 clocks for bl=16 operation. for lpddr2- sdram, this operation is allowed regardless of whether the accesses read the same or different banks as long as the banks are activated. 4.4.1 reads interrupted by a read for lpddr2-s4 burst read can be interrupted by another read on even clock cycles after the read command, provided that tccd is met ck# ck # ca[9:0] cmd dqs# dqs # dq transitioning data rl = 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 read nop read nop nop nop nop nop nop bank n col addr a col addr a bank n col addr b col addr b t ccd = 2 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout a0 dout b5 dout b4 figure 4.13 lpddr2-sx: read burst interrupt example: rl = 3, bl = 8, t ccd = 2 note 1 for lpddr2-s4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16. note 2 for lpddr2-s4 devices, read burst interrupt may only occur on even clock cycles after the previous commands, provided that tccd is met. note 3 reads can only be interrupted by other reads or the bst command. note 4 read burst interruption is allowed to any bank inside dram. note 5 read burst with auto-precharge is not allowed to be interrupted note 6 the effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 32/129 - rev.1.0 july 2016
4.5 burst write operation the burst write command is initiated by having cs# low, ca0 high, ca1 low and ca2 low at the rising edge of the clock. the command address bus inputs, ca5r-ca6r and ca1f-ca9f, determine the starting column address for the burst. the write latency (wl) is defined from the rising edge of the clock on which the write command is issued to the rising edge of the clock from which the tdqss delay is measured. the first valid datum shall be driven wl * tck + tdqss from the rising edge of the clock from which the write command is issued. the data strobe signal (dqs) should be driven low twpre prior to the data input. the data bits of the burst cycle must be applied to the dq pins tds prior to the respective edge of the dqs , dqs# and held valid until tdh after that edge. the burst data are sampled on successive edges of the dqs, dqs# until the burst length is completed, which is 4, 8, or 16 bit burst. for lpddr2 -sdram devices, twr must be satisfied before a precharge command to the same bank may be issued after a burst write operation. input timings are measured relative to the crosspoint of dqs and its complement, dqs#. don t care dqs # dqs# dq dm d in d in d in d in t wpre t dqsh t dqsl t wpst t ds t dh t ds t dh t ds t dh t ds t dh dqs# dqs v ih(ac) v ih(dc) v il(ac) v il(dc) v ih(ac) v ih(dc) v il(ac) v il(dc) v ih(ac) v ih(dc) v il(ac) v il(dc) v ih(ac) v ih(dc) v il(ac) v il(dc) figure 4.14: data input (write) timing transitioning data ck# ck # ca[9:0] cmd dqs# dqs # t0 t1 t2 t3 t4 tx tx+1 ty ty+1 bank n col addr col addr write nop nop nop wl = 1 dqs# dqs # dq dq no p nop din a1 din a2 din a3 din a0 din a1 din a2 din a3 din a0 bank n row addr row addr bank n precharge activate nop case 1: t dqssmax case 2: t dqssmin t dqssmax t dss t dss completion of burst write t wr t wr t rp t dqssmin t dsh t dsh figure 4.15 lpddr2- sx: bu rst write : wl = 1, bl = 4 ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 33/129 - rev.1.0 july 2016
transitioning data ck# ck # ca[9:0] cmd dqs# dqs # dq t0 t1 t2 t3 t4 t5 t6 t7 t8 bank m col addr a col addr a write nop nop nop nop nop read nop nop bank n col addr b col addr b wl = 1 rl = 3 t wtr din a1 din a2 din a3 din a0 figure 4.16 lpddr2- sx: bu rst write followed by burst read: rl=3, wl = 1, bl = 4 note 1 the minimum number of clock cycles from the burst write command to the burst read command for any bank is [wl + 1 + bl/2 + ru( twtr/tck)]. note 2 twtr starts at the rising edge of the clock after the last valid input datum. note 3 if a write burst is truncated with a burst terminate (bst) command, the effective burst length of the truncated write burst should be used as bl to calculate th e minimum write to read delay. 4.5.1 writes interrupted by a write for lpddr2-s4 devices, burst write can only be interrupted by another write on even clock cycles after the write comman d, provided that tccd(min) is met. transitioning data ck# ck # ca[9:0] cmd dqs# dqs # dq t0 t1 t2 t3 t4 t5 t6 t7 t8 bank m col addr a col addr a write nop write nop nop nop nop nop nop wl = 1 bank n col addr b col addr b t ccd = 2 din a1 din a2 din a3 din a0 din b1 din b2 din b3 din b0 din b5 din b6 din b7 din b4 figure 4.17 lpddr2- sx: w rite burst interrupt timing: wl = 1, bl = 8, t ccd = 2 note 1 for lpddr2-s4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16. note 2 for lpddr2-s4 devices, write burst interrupt may only occur on even clock cycles after the previous write commands, provided that tccd(min) is met. note 3 writes can only be interrupted by other writes or the bst command. note 4 write burst interruption is allowed to any bank inside dram. note 5 write burst with auto-precharge is not allowed to be interrupted note 6 the effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting write. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 34/129 - rev.1.0 july 2016
4.6 burst terminate the burs t terminate (bst) command is initiated by having cs# low, ca0 high, ca1 high, ca2 low, and ca3 low at the rising edge of clock. a burst teminate command may only be issued to terminate an active read or write burst. therefore, a burst terminate command may only be issued up to and including bl/2 - 1 clock cycles after a read or write command. the effective burst length of a read or write command truncated by a bst command is as follows: effective burst length = 2 x {number of clock cycles from the read or write command to the bst command} note that if a read or write burst is truncated with a burst terminate (bst) command, the effective burst length of the truncated burst should be used as bl to calculate the minimum read to write or write to read delay. the bs t command only affects the most recent read or write command. the bst command truncates an ongoing read burst rl * tck + tdqsck + tdqsq after the rising edge of the clock where the burst terminate command is issued. the bst command truncates an ongoing write burst wl * tck + tdqss after the rising edge of the clock where the burst terminate command is issued. for lpddr2-s4 devices, the 4-bit prefetch architecture allows the bst command to be issued on an even number of clock cycles after a write or read command. therefore, the effective burst length of read or write command truncated by a bst command is an integer multiple of 4. transitioning data bst prohibited ck# ck # ca[9:0] cmd dqs# dqs # dq t0 t1 t2 t3 t4 t5 t6 t7 t8 bank m col addr a col addr a write nop nop nop bst nop nop nop nop din a1 din a2 din a3 din a0 wl = 1 din a5 din a6 din a7 din a4 wl x t ck + t dqss figure 4.18 lpddr2-s4: burst write truncated by bst: wl = 1, bl = 16 note 1 the bst command truncates an ongoing write burst wl * t ck + t dqss after the rising edge of the clock where the burst terminate command is issued. note 2 for lpddr2-s4 devices, bst can only be issued an even number of clock cycles after the write command. note 3 additional bst commands are not allowed after t4 and may not be issued until after the next read or write command. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 35/129 - rev.1.0 july 2016
figure 4.19 lpddr2-s4: burst read truncated by bst: rl=3, bl = 16 note 1 the bst command truncates an ongoing read burst rl * t ck + t dqsck + t dqsq after the rising edge of the clock where the burst terminate command is issued. note 2 for lpddr2-s4 devices, bst can only be issued an even number of clock cycles after the read command. note 3 additional bst commands are not allowed after t4 and may not be issued until after the next read or write command. transitioning data bst prohibited ck# ck # ca[9:0] cmd dqs# dqs # dq t0 t1 t2 t3 t4 t5 t6 t7 t8 bank n col addr a col addr a read nop nop nop bst nop nop bl = 3 nop nop rl x t ck + t dqsck + t dqsq dout a1 dout a2 dout a3 dout a0 dout a5 dout a6 dout a7 dout a4 ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 36/129 - rev.1.0 july 2016
4.7 write data mask one write data mask (dm) pin for each data byte (dq) will be supported on lpddr2 devices, consistent with the implementation on lpddr sdrams. each data mask (dm) may mask its respective data byte (dq) for any given cycle of the burst. data mask has identical timings on write operations as the data bits, though used as input only, is int ernally loaded identically to data bits to insure matched system timing. data mask timing cmd dqs # dqs# dq t ds t dh v ih(ac) v il(ac) v ih(dc) v il(dc) v ih(ac) v il(ac) v ih(dc) v il(dc) t ds t dh don t care data mask function, wl = 2, bl = 4 shown, second dq masked ck# ck # cmd dqs# dqs # dq dm dqs# dqs # dq dm write wl = 2 t wr t wtr case 1: t dqssmin case 2: t dqssmax dout 0 dout 1 dout 2 dout 3 t dqssmin t dqssmax dout 0 dout 1 dout 2 dout 3 don t care figure 4.20 lpddr2- sx: write data mask ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 37/129 - rev.1.0 july 2016
4.8 lpddr2-sx: precharge operation the precharge command is used to precharge or close a bank that has been activated. the precharge command is initi at ed by having cs# low, ca0 high, ca1 high, ca2 low, and ca3 high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. for 4- bank devices, the ab flag, and the bank address bits, ba0 and ba1, are used to determine which bank(s) to precharge. for 8-bank devices, the ab flag, and the bank address bits, ba0, ba1, and ba2, are used to determine which bank(s) to precharge. the bank(s) will be available for a subsequent row access trpab after an all- ba nk precharge command is issued and trppb after a single-bank precharge command is issued. in order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices, the row precharge time (trp) for an all-bank precharge for 8-bank devices (trpab) will be longer than the row precharge time for a single-bank precharge (trppb). for 4-bank devices, the row precharge time (trp) for an all-bank precharge (trpab) is equal to the row precharge time for a single-bank precharge (trppb). figure 4-1 shows activate to precharge timing. table 8 C bank selection for precharge by address bits ab (ca4r) ba2 (ca9r) ba1 (ca8r) ba0 (ca7r) precharged bank(s) precharged bank(s) 4 - bank device 8 - bank device 0 0 0 0 bank 0 only bank 0 only 0 0 0 1 bank 1 only bank 1 only 0 0 1 0 bank 2 only bank 2 only 0 0 1 1 bank 3 only bank 3 only 0 1 0 0 bank 0 only bank 4 only 0 1 0 1 bank 1 only bank 5 only 0 1 1 0 bank 2 only bank 6 only 0 1 1 1 bank 3 only bank 7 only 1 don't care don't care don't care all banks all banks 4.8.1 lpddr2-sx: burst read operation followed by precharge for the earl i est possible precharge, the precharge command may be issued bl/2 clock cycles after a read command. for an untruncated burst, bl is the value from the mode register. for a truncated burst, bl is the effective burst length. a new bank active (command) may be issued to the same bank after the row precharge time (trp). a precharge command cannot be issued until after tras is satisfied. for lpddr2-s4 devices, the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a read command. this time is called trtp (r ead t o p recharge). for lpddr2-s4 devices, trtp begins bl/2 - 2 clock cycles after the read command. if the burst is truncated by a bst command or a read command to a different bank, the effective bl shall be used to calculate when trtp begins. see table 9 for read to precharge timings for lpddr2-s4 AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 38/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd dqs# dqs # dq bank m col addr a col addr a bank m bank m row addr row addr read nop nop nop precharge nop nop activate nop dout a1 dout a2 dout a3 dout a4 dout a5 dout a6 dout a7 dout a0 t0 t1 t2 t3 t4 t5 t6 t7 t8 bl/2 rl = 3 t rtp t rp transitioning data figure 4.21 lpddr2-s4: burst read followed by precharge: rl = 3, bl = 8, ru(t rtp (min)/t ck ) = 2 ck# ck # ca[9:0] cmd dqs# dqs # dq bank m col addr a col addr a bank m bank m row addr row addr read nop nop precharge nop nop activate nop t0 t1 t2 t3 t4 t5 t6 t7 t8 bl/2 rl = 3 t rtp=3 t rp dout a1 dout a2 dout a3 dout a0 nop transitioning data figure 4.22 lpddr2-s4: burst read followed by precharge: rl = 3, bl = 4, ru(t rtp (min)/t ck ) = 3 4.8.2 lpddr2-sx: burst write followed by precharge for write cycles, a delay must be satisfied from the time of the last valid burst input data until the precharge command may be issued. this delay is known as the write recovery time (twr) referenced from the completion of the burst write to the precharge command. no precharge command to the same bank should be issued prior to the twr delay. lpddr2-s4 devices write data to the array in prefetch quadruples (prefetch = 4). the beginning of an internal write operation may only begin after a prefetch group has been latched completely. therefore, the write recovery time (twr) starts at different boundaries for lpddr2-s4 devices. for lpddr2-s4 devices, minimum write to precharge command spacing to the same bank is wl + bl/2 + 1 + ru(twr/tck) clock cycles. for an untruncated burst, bl is the value from the mode register. for an truncated burst, bl is the effective burst length. see table 9 for write to precharge timings for lpddr2-s4 ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 39/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd dqs# dqs # dq bank m col addr a col addr bank n row addr write nop nop t0 t1 t2 t3 t4 tx tx+1 ty ty+1 wl = 1 t wr t rp dout a1 dout a2 dout a3 dout a0 nop dqs# dqs # dq case 1: t dqssmax case 2: t dqssmin activate nop precharge nop nop row addr bank n dout a1 dout a2 dout a3 dout a0 t dqssmax t dqssmin completion of burst write transitioning data figure 4.23 lpddr2-sx: burst write followed by precharge: wl = 1, bl = 4 4.8.3 lpddr2-sx: auto precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto-precharge function. when a read or a write command is given to the lpddr2 sdram, the ap bit (ca0f) may be set to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if ap is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst. if ap is high when the read or write command is issued, then the auto-precharge function is engaged. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon read or write latency) thus improving system performance for random data access. 4.8.3.1 lpddr2-sx: burst read with auto-precharge if ap (ca0f) is high when a read command is issued, the read with auto-precharge function is engaged. lpddr2-s4 devices start an auto-precharge operation on the rising edge of the clock bl/2 or bl/2 - 2 + ru(trtp/tck) clock cycles later than the read with ap command, whichever is greater. refer to table 9 for equations related to auto-precharge for lpddr2-s4. a new bank activate command may be issued to the same bank if both of the following two conditions are satisfied simultaneously. the ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. the ras cycle time (trc) from the previous bank activation has been satisfied. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 40/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd dqs# dqs # dq bank m col addr a col addr a read w/ap nop nop nop nop activate nop t0 t1 t2 t3 t4 t5 t6 t7 t8 bl/2 rl t rtp t rppb dout a1 dout a2 dout a3 dout a0 nop nop bank m addr row addr transitioning data figure 4.24 lpddr2-s4: burst r ead with auto - precharge: rl = 3, bl = 4, ru(t rtp (min)/t ck ) = 2 4.8.3.2 lpddr2-sx: burst write with auto-precharge if ap (ca0f) is high when a write command is issued, the write with auto-precharge function is engaged. the lpddr2 sdram starts an auto precharge operation on the rising edge which is twr cycles after the completion of the burst write. a new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied. the ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. the ras cycle time (trc) from the previous bank activation has been satisfied. ck# ck # ca[9:0] cmd dqs# dqs # dq bank n col addr a col addr bank n row addr write nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 wl = 1 t wr t rppb dout a1 dout a2 dout a3 dout a0 nop activate nop nop nop row addr nop transitioning data figure 4.25 lpddr2- sx: burst write w/auto precharge: wl = 1, bl = 4 ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 41/129 - rev.1.0 july 2016
table 9 C lpddr-s4 : precharge & auto precharge clarification from to command minimum delay between unit notes command " from command " to "to command " read precharge (to same bank as read) bl/2 + max(2,ru(t rtp /t ck )) - 2 clks 1 precharge all bl/2 + max(2,ru(t rtp / tck )) - 2 clks 1 bst precharge (to same bank as read) 1 clks 1 (for reads) precharge all 1 clks 1 read w/ap precharge (to same bank as read w/ap) bl/2 + max(2,ru(t rtp /t ck )) - 2 clks 1.2 precharge all bl/2 + max(2,ru(t rtp /t ck )) - 2 clks 1 activate (to same bank as read w/ap) bl/2 + max(2,ru(t rtp /t ck )) - 2 + ru(t rppb /t ck ) clks 1 write or write w/ap (same bank) illegal clks 3 write or write w/ap (different bank) rl+bl/2+ru(t dqsck max/t ck ) - wl+1 clks 3 read or read w/ap (same bank) illegal clks 3 read or read w/ap (different bank) bl/2 clks 3 write precharge (to same bank as write) wl + bl/2 + ru(t wr /t ck )+1 clks 1 precharge all wl + bl/2 + ru(t wr /t ck )+1 clks 1 bst precharge (to same bank as write) wl + ru(t wr /t ck )+1 clks 1 (for writes) precharge all wl + ru(t wr /t ck )+1 clks 1 write w/ap precharge (to same bank as write w/ap) wl + bl/2 + ru(t wr /t ck )+1 clks 1 precharge all wl + bl/2 + ru(t wr /t ck )+1 clks 1 activate (to same bank as write w/ap) wl + bl/2 + ru(t wr /t ck )+1 +ru(t rppb /t ck ) clks 1 write or write w/ap (same bank) illegal clks 3 write or write w/ap (different bank) bl/2 clks 3 read or read w/ap (same bank) illegal clks 3 read or read w/ap (different bank) w/l + bl/2 + ru(t wtr /t ck )+1 clks 3 precharge precharge (to same bank as precharge) 1 clks 1 precharge all 1 clks 1 precharge all precharge 1 clks 1 precharge all 1 clks 1 note 1 for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. the precharge period is satisfied after trp depending on the latest precharge command issued to that bank, note 2 any command issued during the minimum delay time as specified in table 51 is illegal. note 3 after read with ap, seamless read operations to different banks are supported. after write with ap, seamless write operation to different banks are supported. read w/ap and write w/ap may not be interrupted or truncated. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 42/129 - rev.1.0 july 2016
4.9 lpddr2-sx: refresh command the refresh command is initiated by having cs# low, ca0 low, ca1 low, and ca2 high at the rising edge of clock. per b ank refresh is initiated by having ca3 low at the rising edge of clock and all bank refresh is initiated by having ca3 high at the rising edge of clock. per bank refresh is only allowed in devices with 8 banks. a per bank refresh command, refpb performs a refresh operation to the bank which is scheduled by the bank counter in the memory device. the bank sequence of per bank refresh is fixed to be a sequential round-robin: 0-1- 2-3-4- 5-6-7-0-1-.... the bank count is synchronized between the controller and the sdram upon issuing a reset command or at every exit from self refresh, by resetting bank count to zero. the bank addressing for the per bank refresh count is the same as established in the single-bank precharge command (see table 8 , bank selection for precharge by address bits). a bank must be idle before it can be refreshed. it is the responsibility of the controller to track the bank being refreshed by the per bank refresh comma nd. as shown in table 10 , the refpb command may not be issued to the memory until the following conditions are met: a) trfcab has been satisified after the prior refab command b) trfcpb has been satisfied after the prior refpb command c) trp has been satisified after the prior precharge command to that given bank trrd has been satisfied after the prior activate command (if applicable, for example after activating a row in a different bank than affected by the refpb command). the target bank is inaccessable during the per bank refresh cycle time (trfcpb), however other banks within the device are accessable and may be addressed during the per bank refresh cycle. during the refpb operation, any of the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write command. when the per bank refresh cycle has completed, the affected bank will be in the idle state. as shown in table 10 , after issuing refpb: a) trfcpb must be satisified before issuing a refab command b) trfcpb must be satisfied before issuing an activate command to the same bank c) trrd must be satisified before issuing an activate command to a different bank d) trfcpb must be satisified before issuing another refpb command an all bank refresh command, refab performs a refresh operation to all banks. all banks have to be in idle state when refab is issued (for instance, by precharge all-bank command). refab also synchronizes the bank count between the controller and the sdram to zero. as shown in table 10 , the refab command may not be issued to the memory until the following conditions have been met: a) trfcab has been satisified after the prior refab command b) trfcpb has been satisified after the prior refpb command c) trp has been satisified after prior precharge commands when the all bank refresh cycle has completed, all banks will be in the idle state. as shown in table 10 , after issuing refab: a) the trfcab latency must be satisfied before issuing an activate command b) the trfcab latency must be satisfied before issuing a refab or refpb command. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 43/129 - rev.1.0 july 2016
table 10 C command scheduling separations related to refresh symbol minimum delay from to notes t rfcab refab refab activate cmd to any bank refpb t rfcpb refpb refab activate cmd to same bank as refpb refpb t rrd refpb activate cmd to different bank than refpb activate reffpb affecting an idle bank (different bank than activate) 1 activate cmd to different bank than prior activate note 1 a bank must be in the idle state before it is refreshed. therefore, after activate, refab is now allowed and refpb is allowed only if it affects a bank which is in the idle state. 4.9.1 lpddr2 sdram refresh requirements ( 1) mi nimum number of refresh commands: the lpddr2 sdram requires a minimum number of r refresh (refab) commands within any rolling refresh window (trefw = 32 ms @ mr4[2:0] = 011 or tcase 85 c). see table 50 for actual numbers per density . t he resulting average refresh interval (trefi) is given in table 50 . s ee mode register 4 for trefw and trefi refresh multipliers at different mr4 settings. for lpddr2-sdram devices supporting per-bank-refresh, a refab command may be replaced by a full cycle of eight refpb commands. ( 2) bu rst refresh limitation: to limit maximum current consumption, a maximum of 8 refab commands may be issued in any rolling trefbw (trefbw = 4 x 8 x trfcab). this condition does not apply if refpb commands are used. ( 3) ref resh requirements and self-refresh: if any time within a refresh window is spent in self-refresh mode, the number of required refresh commands i n thi s particular window is reduced to: r* = r - ru{tsrf / trefi} = r - ru{r * tsrf / trefw}; where ru stands for the round-up function. cke cke cke cke example a example b example c example d t srf t refw t refw t srf t srf t refw t srf1 t srf2 t refw enter self refresh mode exit self refresh mode enter self refresh mode exit self refresh mode exit self refresh mode exit self refresh mode enter self refresh mode exit self refresh mode figure 4.26 lpddr2-sx: definition of t srf several examples on how to t srf is calculated: ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 44/129 - rev.1.0 july 2016
a: with the time spent in self-refresh mode fully enclosed in the refresh window ( t refw), b: at self-refresh entry c: at self-refresh exit d: with several different intervals spent in self refresh during one t refw interval in contrast to jesd79 and jesd79-2 and jesd79-3 compliant sdram devices, lpddr2-sx devices allow significant flexibiliy in scheduling refresh commends, as long as the boundary conditions above are met. in the most straight forward case a refresh command should be scheduled every trefi. in this case self- refresh may be entered at any time. the users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are required. in the extreme (e.g., lpddr2-s4 1gb) the user may choose to issue a refresh burst of 4096 refresh commands with the maximum allowable rate (limited by trefbw) followed by a long time without any refresh commands, until the refresh window is complete, then repeating this sequence. the achieveable time without refresh commands is given by trefw - (r / 8) * trefbw = trefw - r * 4 * trfcab. (e.g., for a lpddr2-s4 1gb device @ tcase <= 85 c this can be up to 32 ms - 4096 * 4 * 130 ns ~ 30 ms). while both - the regular and the burst/pause - patterns can satisfy the refresh requirements per rolling refresh interval, if they are repeated in every subsequent 32 ms window, extreme care must be taken when transitioning from one pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition. figure 4.28 shows an example of an allowable transition from a burst pattern to a regular, distributed pattern. if this transition happens directly after the burst refresh phase, all rolling trefw intervalls will have at least the required number of refreshes. figure 4.29 shows an example of a non-allowable transition. in this case the regular refresh pattern starts after the completion of the pause-phase of the burst/pause refresh pattern. for several rolling trefw intervals the minimmun number of refresh commands is not satisfied. the understanding of the pattern transition is extremly relevant (even if in normal operation only one pattern is employed), as in self-refresh-mode a regular, distributed refresh pattern has to be assumed, which is reflected in the equation for r* above. therefore it is recommended to enter self-refresh-mode only directly after the burst-phase of a burst/pause refresh pattern as indicated in figure 75 and begin with the burst phase upon exit from self-refresh. 0ms 32ms 64ms 96ms 4,096 8,192 12,288 16,384 12,289 8,193 4,097 t refi t refi t refbw t refbw figure 4.27 lpddr2-sx: regular, distributed refresh pattern vs. repetitive burst refresh with subsequent refresh pause ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 45/129 - rev.1.0 july 2016
note 1 for a (e.g.) lpddr2-s4 1 gb device @ tcase less than or equal to 85c the distributed refresh pattern would have one refresh command per 7.8 us; the burst refresh pattern would have an average of one refresh command per 0.52 us followed by ~30 ms without any refresh command figure 4.28 lpddr2 - sx: allowable transition from repetitive burst refresh with subsequent refresh pause to regular, distributed refresh pattern note 1 for a (e.g.) lpddr2-s4 1 gb device @ tcase less than or equal to 85 c the distributed refresh pattern would have one refresh command per 7.8 us; the burst refresh pattern would have an average of one refresh command per 0.52 us followed by ~30 ms without any refresh command. 0ms 32ms 64ms 96ms 4,096 8,192 4,097 10,240 12,288 16,384 t refbw t refbw t refi t refi AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 46/129 - rev.1.0 july 2016
figure 4.29 lpddr2 - sx: not - allowable transition from repetitive burst refresh with subsequent refresh pause to regular, distributed refresh pattern note 1 only ~2048 refresh commands (AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 47/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd t0 t1 t2 t3 t4 tx tx+1 ty ty+1 ab precharge nop nop refab nop refab nop valid nop t rpab t rfcab t rfcab figure 4.31 lpddr2- sx: all bank refresh operation ck# ck # ca[9:0] cmd t0 t1 tx tx+1 tx+2 ty ty+1 tz tz+1 ab precharge nop nop refpb nop refpb nop activate nop t rpab t rfcpb t rfcpb bank 1 row a row a refresh to bank 0 refresh to bank 1 activate command to bank 1 note 1 in the beginning of this example, the refpb bank is pointing to bank 0. note 2 operations to other banks than the bank being refreshed are allowed during the t rfcpb period. figure 4.32 lpddr2- sx: p er bank refresh operation ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 48/129 - rev.1.0 july 2016
4.10 lpddr2-sx: self refresh operation the self refresh command can be used to retain data in the lpddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the lpddr2 sdram retains data without external clocking. the lpddr2 sdram device has a built-in timer to accommodate self refresh operation. the self refresh command is defined by having cke low, cs# low, ca0 low, ca1 low, and ca2 high at the rising edge of the clock. cke must be high during the previous clock cycle. a nop command must be driven in the clock cycle following the power-down command. once the command is registered, cke must be held low to keep the device in self refresh mode. lpddr2-sx devices can operate in self refresh in both the standard or extended temperature ranges. lpddr2- sx devices will also manage self refresh power consumption when the operating temperature changes, lower at low temperatures and higher at high temperatures. see lpddr2 idd specification parameters and operating conditions for details. once the lpddr2 sdram has entered self refresh mode, all of the external signals except cke, are dont care. for proper self refresh operation, power supply pins (vdd1, vdd2, and vdd2) must be at valid levels. vddq may be turned off during self-refresh. prior to exiting self-refresh, vddq must be within specified limits. vrefdq and vrefca may be at any level within minimum and maximum levels (see absolute maximum dc ratings ). however prior to exiting self-refresh, vrefdq and vrefca must be within specified limits (see recommended dc operating conditions ). the sdram initiates a minimum of one all-bank refresh command internally within tckesr period once it enters self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the lpddr2 sdram must remain in self refresh mode is tckesr. the user may change the external clock frequency or halt the external clock one clock after self refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock shall be stable and within specified limits for a minimum of 2 tck prior to the positive clock edge that registers cke high. once self refresh exit is registered, a delay of at least txsr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self refresh exit period txsr for proper operation except for self refresh re-entry. nop commands must be registered on each positive clock edge during the self refresh exit interval txsr. the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, it is required that at least one refresh command (8 per-bank or 1 all-bank) is issued before entry into a subsequent self refresh. for lpddr2 sdram, the maximum duration in power-down mode is only limited by the refresh requirements outlined in section lpddr2 sdram refresh requirements , since no refresh operations are performed in power- down mode ck# ck # cke cs# cmd valid enter sr nop exit sr nop nop valid t ihcke t iscke t iscke t xsr t ckesr (min) t ihcke enter self refresh mode exit self refresh mode input clock frequency can be changed or clock can be stopped during self refresh. don t care figure 4.33 lpddr2- sx: self -refresh operation note 1 input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 2 clocks of stable clock are provided and the clock frequency is between the minimum and maximum frequency for the particular speed grade. note 2 device must be in the all banks idle state prior to entering self refresh mode. note 3 t xsr begins at the rising edge of the clock after cke is driven high. note 4 a valid command may be issued only after t xsr is satisfied. nops shall be issued during t xsr . 4.10.1 lpddr2-s4: partial array self-refresh: bank masking ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 49/129 - rev.1.0 july 2016
lpddr2-s4 sdram has 4 or 8 banks. for lpddr2-s4 devices, 64mb to 512mb lpddr2 sdram has 4 banks, while 1gb and higher density has 8. each bank of lpddr2 sdram can be independently configured whether a self refresh operation is taking place. one mode register unit of 8 bits accessible via mrw command is assigned to program the bank masking status of each bank up to 8 banks. for bank masking bit assignments, see mode register 16. the mask bit to the bank controls a refresh operation of entire memory within the bank. if a bank is masked via mrw, a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh mode. to enable a refresh operation to a bank, a coupled mask bit has to be programmed, unmasked. when a bank mask bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits, which is decribed in the following chapter. 4.10.2 lpddr2-s4: partial array self-refresh: segment masking segment masking scheme may be used in lieu of or in combination with bank masking scheme in lpddr2- s4 sdram. the number of segments differ by the density and the setting of each segment mask bit is applied across all the banks. for segment masking bit assignments, see mode register 17. for those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is blocked when the mask bit to this segment is programmed, masked. programming of segment mask bits is similar to the one of bank mask bits. lpddr2 sdram whose density is 64mb, 128mb, 256mb, or 512mb does not support segment masking. only bank masking scheme is available. for 1gb and larger densities, 8 segments are used as listed in mode register 17. one mode register unit is used for the programming of segment mask bits up to 8 bits. one more mode register unit may be reserved for future use. these 2 mode register units are noted as not used for low-density lpddr2-s4 sdram and a programming of mask bits has no effect on the devi ce operation. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 50/129 - rev.1.0 july 2016
table 11 C example of bank and segment masking use in lpddr2-s4 devices segment mask (mr17) bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank mask (mr16) 0 1 0 0 0 0 0 1 segment 0 0 m m segment 1 0 m m segment 2 1 m m m m m m m m segment 3 0 m m segment 4 0 m m segment 5 0 m m segment 6 0 m m segment 7 1 m m m m m m m m note 1 this table illustrates an example of an 8-bank lpddr2-s4 device, when a refresh operation to bank 1 and bank 7, as well as segment 7 are masked. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 51/129 - rev.1.0 july 2016
4.11 mode register read command the mode register read command is used to read configuration and status data from mode registers. the mode register read (mrr) command is initiated by having cs# low, ca0 low, ca1 low, ca2 low, and ca3 high at the rising edge of the clock. the mode register is selected by {ca1f-ca0f, ca9r- ca4r}. the mode register contents are available on the first data beat of dq0-dq7, rl * tck + tdqsck + tdqsq after the rising edge of the clock where the mode register read command is issued. subsequent data beats contain valid, but undefined content, except in the case of the dq calibration function dqc, where subsequent data beats contain valid content as described in dq calibration . all dqs , dqs# shall be toggled for the duration of the mode register read burst. the mrr command has a burst length of four. the mode register read operation (consisting of the mrr command and the corresponding data traffic) shall not be interrupted. the mrr command period (tmrr) is 2 clock cycles. mode register reads to reserved and write-only registers shall return valid, but undefined content on all data beats and dqs, dqs# shall be toggled transitioning data undefined ck# ck # ca[9:0] cmd dqs# dqs # t0 t1 t2 t3 t4 t5 t6 t7 t8 register a register a mrr 1 nop 2 mrr 1 nop 2 valid rl = 3 t mrr = 2 register b register b t mrr = 2 dout a dout b dq[max:8] dq[7:0] 3 figure 4.34 mode register read timing example: rl = 3, t mrr = 2 note 1 mode register read has a burst length of four. note 2 mode register read operation shall not be interrupted. note 3 mode register data is valid only on dq[0-7] on the first beat. subsequent beats contain valid, but undefined data. dq[8-max] contain valid, but undefined data for the duration of the mrr burst. note 4 the mode register command period is t mrr . no command (other than nop) is allowed during this period. note 5 mode register reads to dq calibration registers mr32 and mr40 are described in the section on dq calibration. note 6 minimum mode register read to write latency is rl + ru(t dqsck max/t ck ) + 4/2 + 1 - wl clock cycles. note 7 minimum mode register read to mode register write latency is rl + ru(t dqsck max/t ck ) + 4/2 + 1 clock cycles. the mrr command shall not be issued earlier than bl/2 clock cycles after a prior read command and wl + 1 + bl/2 + ru( twtr/tck) clock cycles after a prior write command, because read-bursts and write-bursts shall not be truncated by mrr. note that if a read or write burst is truncated with a burst terminate (bst) command, the effective burst length of the truncated burst should be used as bl. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 52/129 - rev.1.0 july 2016
transitioning data undefined ck# ck # ca[9:0] cmd dqs# dqs # t0 t1 t2 t3 t4 t5 t6 t7 t8 bank m col addr a col addr a read mrr nop 2 valid rl = 3 register b register b t mrr = 2 dout a0 dout b dq[max:8] dq[7:0] bl/2 1 dout a1 dout a2 dout a3 dout a0 dout a1 dout a2 dout a3 figure 4.35 lpddr2: read to mrr timing example: rl = 3, t mrr = 2 note 1: the minimum number of clocks from the burst read command to the mode register read command is bl/2. note 2: the mode register read command period is t mrr . no command (other than nop) is allowed during this period. cmd not allowed ck# ck # ca[9:0] cmd dqs# dqs # dq t0 t1 t2 t3 t4 t5 t6 t7 t8 bank n col addr a col addr a write valid mrr 1 nop 2 register b register b wl=1 rl = 3 din a1 din a2 din a3 din a0 t wtr t mrr = 2 figure 4.36 lpddr2: burst write followed by mrr: rl = 3, wl = 1, bl = 4 note 1 the minimum number of clock cycles from the burst write command to the mode register read command is [wl + 1 + bl/2 + ru( twtr/tck)]. note 2 the mode register read command period is tmrr. no command (other than nop) is allowed during this period. 4.11.1 temperature sensor lpddr2-sx devices feature a temperature sensor whose status can be read from mr4. this sensor can be used to determine an appropriate refresh rate (sdram), determine whether ac timing de-rating is required in the extended temperature range (sdram), and/or monitor the operating temperature (sdram). either the temperature sensor or the device toper ( see operating temperature range ) may be used to determine whether operating temperature requirements are being met. lpddr2 devices shall monitor device temperature and update mr4 according to ttsi. upon exiting self-refresh or power-down, the device temperature status bits shall be no older than ttsi. when using the temperature sensor, the actual device case temperature may be higher than the toper sp ecification ( see operating temperature range ) that applies for the standard or extended temperature ranges. for example, tcase may be above 85o c when mr4[2:0] equals 011b. to assure proper operation using the temperature sensor, applications should consider the following factors: ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 53/129 - rev.1.0 july 2016
tempgradient is the maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2 c. readinterval is the time period between mr4 reads from the system. tempsensorinterval (ttsi) is maximum delay between internal updates of mr4. sysrespdelay is the maximum time between a read of mr4 and the response by the system. lpddr2 devices shall allow for a 2 c temperature margin between the point at which the device temperature enter s the extended temperature range and point at which the controller re - configures the system accordingly. in order to determine the required frequency of polling mr4, the system shall use the maximum tempgradient and the maximum response time of the system using the following equation: table 12 temperature sensor parameter symbol max/min value unit notes system temperature gradient tempgradient max system dependent /s mr4 read interval readinterval max system dependent ms temperature sensor interval ttsi max 32 ms system response delay sysrespdelay max system dependent ms device temperature margin tempmargin max 2 for example, if tempgradient is 10 o c/s and the sysrespdelay is 1 ms: in this case, readinterval shall be no greater than 167 ms. figure 4.37 temp sensor timing 4.11.2 dq calibration lpddr2-sx feature a dq calibration function that outputs one of two predefined system timing calibration patterns. a mode register read to mr32 (pattern a) or mr40 (pattern b) will return the specified pattern on dq[0] for x8 devices, dq[0] and dq[8] for x16 devices, and dq[0], dq[8], dq[16], and dq[24] for x32 devices. for x8 devices, dq[7:1] may optionally drive the same information as dq[0] or may drive 0b during the mrr burst. for x16 devices, dq[7:1] and dq[15:9] may optionally drive the same information as dq[0] or may drive 0b during the mrr burst. device temp margin temp mr4 trip level host mr4 read mr4 = 0x03 mr4 = 0x86 mr4 = 0x86 mr4 = 0x86 time readinterval mrr mr4 = 0x03 mrr mr4 = 0x86 temperture sensor update mr4 = 0x86 <( t tsi + readinterval + sysrespdelay t tsi tempgradient sysrespdelay 2c AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 54/129 - rev.1.0 july 2016
for x32 devices, dq[7:1], dq[15:9], dq[23:17], and dq[31:25] may optionally drive the same information as dq[0] or may drive 0b during the mrr burst. for lpddr2-sx devices, mrr dq calibration commands may only occur in the idle state table 13 data calibration pattern description bit time 0 bit time 1 bit time 2 bit time 3 pattern "a"(mr32) 1 0 1 0 pattern "b"(mr40) 0 0 1 1 transitioning data optionally driven the same as dq0 or 0b ck# ck # ca[9:0] cmd dqs# dqs # t0 t1 t2 t3 t4 t5 t6 t7 t8 reg 32 reg 32 mrr mrr nop nop 1 rl = 3 reg 40 reg 40 t mrr = 2 dq[7:1] dq0 t mrr = 2 dq8 dq[15:9] dq16 dq[23:17] dq24 dq[31:25] 1 0100011 10100011 1 0100011 10100011 1 0100011 1 0100011 10100011 10100011 pattern a pattern b x16 x32 figure 4.38 mr32 and mr40 dq calibration timing example: rl = 3, t mrr = 2 note 1 mode register read has a burst length of four. note 2 mode register read operation shall not be interrupted. note 3 mode register reads to mr32 and mr40 drive valid data on dq[0] during the entire burst. for x16 devices, dq[8] shall drive the same information as dq[0] during the burst. for x32 devices, dq[8], dq[16], and dq[24] shall drive the same information as dq[0] during the burst. note 4 for x8 devices, dq[7:1] may optionally drive the same information as dq[0] or they may drive 0b during the burst. for x16 devices, dq[7:1] and dq[15:9] may optionally drive the same information as dq[0] or they may drive 0b during the burst. for x32 devices, dq[7:1], dq[15:9], dq[23:17], and dq[31:25] may optionally drive the same information as dq[0] or they may drive 0b during the burst. note 5 the mode register command period is t mrr . no command (other than nop) is allowed during this period ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 55/129 - rev.1.0 july 2016
4.12 mode register write command the mode register write command is used to write configuration data to mode registers. the mode register write (mrw) command is initiated by having cs# low, ca0 low, ca1 low, ca2 low, and ca3 low at the rising edge of the clock. the mode register is selected by {ca1f-ca0f, ca9r-ca4r}. the data to be written to the mode register is contained in ca9f-ca2f. the mrw command period is defined by tmrw. mode register writes to read-only registers shall have no impact on the functionality of the device. ck# ck # ca[9:0] cmd t0 t1 t2 tx tx+2 ty+1 ty 1 ty+2 nop 2 mr addr mr data mr addr mr dara t mrw mrw mrw tx+1 t mrw nop 2 valid nop 2 nop 2 figure 4.39 mode register write timing example: rl = 3, t mrw = 5 note 1 the mode register write command period is t mrw . no command (other than nop) is allowed during this period. note 2 at time ty, the device is in the idle state. 4.12.1 lpddr2-sx: mode register write for lpddr2-s devices, the mrw may only be issued when all banks are in the idle precharge state. one method of ensuring that the banks are in the idle precharge state is to issue a precharge-all command. 4.12.2 mode register write reset (mrw reset) any mrw command issued to mrw63 initiates an mrw reset. the mrw reset command brings the device to the devic e auto-initialization (resetting) state in the power-on initialization sequence. the mrw reset command may be issued from the idle state for lpddr2-sx devices. this command resets all mode registers to their default values .. no commands other than nop may be issued to the lpddr2 device during the mrw reset period ( t init4). after mrw reset, boot timings must be observed until the device initialization sequence is complete and the device is in the idle state. array data for lpddr2-sx devices are undefined after the mrw reset command. for the timing diagram related to mrw reset. 4.12.3 mode register write zq calibration command the mrw command is also used to initiate the zq calibration command. the zq calibration command is used to calibrate the lpddr2 ouput drivers (ron) over process, temperature, and voltage. lpddr2-s4 devices support zq calibration. there are four zq calibration commands and related timings, tzqinit, tzqreset, tzqcl, and tzqcs. tzqinit corresponds to the initialization calibration, tzqreset for resetting zq setting to default, tzqcl is for long calibration, and tzqcs is for short calibration. see mode register 10 for description on the comma nd codes for the different zq calibration commands. the initialization zq calibration (zqinit) shall be performed for lpddr2-s4 devices. this initialization calibration achieves a ron accuracy of +/-15%. after initialization, the zq long calibration may be used to re-calibrate the system to a ron accuracy of +/-15%. a zq short calibration may be used periodically to compensate for temperature and voltage drift in the system. the zqreset command resets the ron calibration to a default accuracy of +/-30% across process, voltage, and temperature. this command is used to ensure ron accuracy to +/-30% when zqcs and zqcl are not used. one zqcs command can effectively correct a minimum of 1.5% (zqcorrection) of ron impedance error within tzqcs for all speed bins as suming the maximum sensitivities specified in the output driver voltage and temperature sensitivity. the appropriate interval between zqcs commands can be determined from these tables one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the lpddr2 is subject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drondt) and vsens = max(drondv) define the lpddr2 temperature and voltage ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 56/129 - rev.1.0 july 2016
sensitivities. for example, if tsens = 0.75% / oc, vsens = 0.20% / mv, tdriftrate = 1 oc / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as f or lpddr2-s4 devices, a zq calibration command may only be issued when the device is in idle state with all banks precharged. no other activities can be performed on the lpddr2 data bus during the calibration period (tzqinit, tzqcl, tzqcs). the quiet time on the lpddr2 data bus helps to accurately calibrate ron. there is no required quiet time after the zq reset command. if multiple devices share a single zq resistor, only one device may be calibrating at any given time. after calibration is achieved, the lpddr2 device shall disable the zq balls current consumption path to reduce power. in systems that share the zq resistor between devices, the controller must not allow overlap of tzqinit, tzqcs, or tzqcl between the devices. zq reset overlap is allowed. if the zq resistor is absent from the system, zq shall be connected permanently to vdd2. in this case, the lpddr2 device shall ignore zq calibration commands and the device will use the default calibration settings ( see output driver dc electrical characteristics without zq calibration ) ck# ck # ca[9:0] cmd t0 t1 t2 t3 t4 t5 tx tx+1 tx+2 mr addr mr data t zqinit mrw nop nop nop nop valid nop figure 4.40 zq calibration initialization timing example note 1 : the zq calibration initialization period is t zqinit . no command (other than nop) is allowed during this period. note 2: cke must be continuously registered high during the calibration period. note 3: all devices connected to the dq bus should be high impedance during the calibration process. ck# ck # ca[9:0] cmd t0 t1 t2 t3 t4 t5 tx tx+1 tx+2 mr addr mr data t zqcs mrw nop nop nop nop valid nop figure 4.41 zq calibration short timing example note 1 : the zq calibration short period is t zqcs . no command (other than nop) is allowed during this period. note 2: cke must be continuously registered high during the calibration period. note 3: all devices connected to the dq bus should be high impedance during the calibration process. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 57/129 - rev.1.0 july 2016
ck# ck # ca[9:0] cmd t0 t1 t2 t3 t4 t5 tx tx+1 tx+2 mr addr mr data t zqcl mrw nop nop nop nop valid nop figure 4.42 zq calibration long timing example note 1 the zq calibration long period is t zqcl . no command (other than nop) is allowed during this period. note 2 cke must be continuously registered high during the calibration period. note 3 all devices connected to the dq bus should be high impedance during the calibration process. cmd t zqreset mrw nop nop nop nop valid nop ck# ck # ca[9:0] t0 t1 t2 t3 t4 t5 tx tx+1 tx+2 mr addr mr data figure 4.43 zq calibration reset timing example note 1 the zq calibration reset period is t zqreset . no command (other than nop) is allowed during this peri note 2 cke must be continuously registered high during the calibration period. note 3 all devices connected to the dq bus should be high impedance during the calibration process. 4.12.3.1 zq external resistor value, tolerance, and capacitive loading to use the zq calibration function, a 240 ohm +/- 1% tolerance external resistor must be connected between the zq pin and ground. a single resistor can be used for each lpddr2 device or one resistor can be shared between multiple lpddr2 devices if the zq calibration timings for each lpddr2 device do not overlap. the total capacitive loading on the zq pin must be limited ( see input/output capacitance ). ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 58/129 - rev.1.0 july 2016
4.13 power-down for lpddr2 sdram, power-down is synchronously entered when cke is registered low and cs# high at the rising edge of clock. cke must be registered high in the previous clock cycle. a nop command must be driven in the clock cycle following the power-down command. cke is not allowed to go low while mode register, read, or write operations are in progress. cke is allowed to go low while any of other operations such as row activation, preactive, precharge, autoprecharge, or refresh is in progress, but power-down idd spec will not be applied until finishing those operations. timing diagrams are shown in the following pages with details for entry into power down. for lpddr2 sdram, if power-down occurs when all banks are idle, this mode is referred to as idle power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck , ck#, and cke. in power-down mode, cke must be maintained low while all other input signals are dont care. cke low must be maintained until tcke has been satisfied. vref must be maintained at a valid level during power down. vddq may be turned off during power down. if vddq is turned off, then vrefdq must also be turned off. prior to exiting power down, both vddq and vrefdq must be within their respective min/max operating ranges ( see recommended dc operating conditions ). for lpddr2 sdram, the maximum duration in power-down mode is only limited by the refresh requirements outlined in section lpddr2 sdram refresh requirements , as no refresh operations are performed in power- down mode. the power-down state is exited when cke is registered high. the controller shall drive cs# high in conjunction with cke high when exiting the power-down state. cke high must be maintained until tcke has been satisfied. a valid, executable command can be applied with power-down exit latency, txp after cke goes high. power-down exit latency is defined in the timing parameter table of this standard. don t care enter pd ck/ck# cke cs# cmd valid nop exit pd valid va lid no t ihcke t iscke t ihcke t iscke t cke (min) enter power-down mode exit power-down mode input clock frequency can be changed or the input clock can be stopped during power-down. 1 t cke (min) 2 t ck (min) t xp (min) figure 4.44 lpddr2-sx: basic power down entry and exit timing diagram note 1 input clock frequency may be changed or the input clock stopped during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. t cke t cke t cke t cke ck# ck # cke figure 4.45 example of cke intensive environment ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 59/129 - rev.1.0 july 2016
t cke ck# ck # cke cmd refresh refresh t cke t cke t cke t pefi t xp t xp figure 4.46 ref to ref timing with cke intensive environment for lpddr2 sdram note 1 the pattern shown above can repeat over a long period of time. with this pattern, lpddr2 sdram guarantees all ac and dc timing & voltage specifications with temperature and voltage drift bl = 4 ck# ck # cke 1,2 cmd dq dqs# dqs # t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 t iscke read dout dout dout dout rl bl = 8 ck# ck # cke 1,2 cmd dq dqs# dqs # t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 t iscke read dout dout dout dout rl dout dout dout dout figure 4.47 read to power-down entry note 1 cke may be registered low rl + ru(t dqsck(max) /t ck ) + bl/2 + 1 clock cycles after the clock on which the read command is registered. note 2 cke must be held high until the end of the burst operation. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 60/129 - rev.1.0 july 2016
ck# ck # cke 1,2 cmd dq dqs# dqs # bl = 4 t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 t iscke read w/ap pre 4 dout dout dout dout rl bl/2 3 bl = 8 ck# ck # cke 1,2 cmd dq dqs# dqs # t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 t iscke read w/ap pre 4 bl/2 3 rl dout dout dout dout dout dout dout dout figure 4.48 lpddr2 sdram read with autoprecharge to power- down entry note 1 cke may be registered low rl + ru(t dqsck(max) /t ck )+ bl/2 + 1 clock cycles after the clock on which the read command is registered. 2. cke must be held high until the end of the burst operatio n. 3. bl/2 with t rtp = 7.5ns and t ras (min) is satisfied. 4. 4. start internal precharge. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 61/129 - rev.1.0 july 2016
bl = 4 ck# ck # cke 1 cmd dq dqs# dqs # t0 t1 tm tm+1 tm+2 tm+3 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 t iscke write din din din din bl/2 wl t wr bl = 8 ck# ck # cke 1 cmd dq dqs# dqs # t0 t1 tm tm+m1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 tx+3 tx+4 t iscke write din din din din bl/2 wl t wr din din din din figure 4.49 write to power- down entry note 1 cke may be reg istered low wl + 1 + bl/2 + ru(twr/tck) clock cycles after the clock on which the write command is registered. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 62/129 - rev.1.0 july 2016
bl = 4 bl = 8 ck# ck # cke 1 cmd dq dqs# dqs # t0 t1 tm tm+1 tm+2 tm+3 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 t iscke write w/ap din din din din bl/2 wl t wr pre 2 ck# ck # cke 1 cmd dq dqs# dqs # t0 t1 tm tm+1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 tx+3 tx+4 t iscke write w/ap din din din din bl/2 wl t wr pre 2 din din din din figure 4.50 lpddr2-sx: write with autoprecharge to power-down entry note 1 cke may be registered low wl + 1 + bl/2 + ru(t wr /t ck ) + 1 clock cycles after the write command is registered. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 63/129 - rev.1.0 july 2016
ck# ck # cke 1 cmd refresh t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t cke t cke t iscke t ihcke figure 4.51 lpddr2-sx: refresh command to power-down entry note 1 cke may go low t ihcke after the clock on which the refresh command is registered. ck# ck # cke 1 cmd active t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t cke t cke t iscke t ihcke figure 4.52 activate command to power- down entry note 1 cke may go low t ihcke after the clock on which the activate command is registered. ck# ck # cke 1 cmd pre t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t cke t cke t iscke t ihcke figure 4.53 preactive/precharge/precharge- all comman d to power - down entry note 1 cke may go low t ihcke after the clock on which the preactive/precharge/precharge-all command is registered. ck# ck # cke cmd dqs# dqs # dq t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 mrr dout dout dout dout rl t iscke figure 4.54 mode register read to power-down entry note 1 cke may be registered low rl + ru(t dqsck(max) /t ck ) + 4/2 + 1 clock cycles after the clock on which the mode register read command is registered. 2. mode register read operation starts with a mrr command and cke should be kept high until the end of burst operation ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 64/129 - rev.1.0 july 2016
ck# ck # cke 1 cmd mrw t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t mrw t iscke figure 4.55 mrw command to power-down entry note 1 cke may be registered low t mrw after the clock on which the mode register write command is registered ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 65/129 - rev.1.0 july 2016
4.14 lpddr2-sx: deep power-down deep power-down is entered when cke is registered low with cs# low, ca0 high, ca1 high, and ca2 low at the rising edge of clock. a nop command must be driven in the clock cycle following the power-down command. cke is not allowed to go low while mode register, read, or write operations are in progress. all banks must be in idle state with no activity on the data bus prior to entering the deep power down mode. during deep power-down, cke must be held low. in deep power-down mode, all input buffers except cke, all output buffers, and the power supply to internal circuitry may be disabled within the sdram. all power supplies must be within specified limits prior to exiting deep power-down. vrefdq and vrefca may be at any level within minimum and maximum levels (see absolute maximum dc ratings ). however prior to exiting deep power-down, vref must be within specified limits ( see recommended dc operating conditions ). the contents of the sdram may be lost upon entry into deep power-down mode. the deep power-down state is exited when cke is registered high, while meeting tiscke with a stable clock input. the sdram must be fully re-initialized as described in the power up initialization sequence. the sdram is ready for normal operation after the initialization sequence ck# ck # cke cs# cmd nop enter dpd nop exit dpd nop reset t iscke t iscke t dpd t ihcke enter dpd mode exit dpd mode input clock frequency can be changed or clock can be stopped during self dpd. don t care t rp 2 t ck (min) t init3 figure 4.56 lpddr2-sx: deep power down entry and exit timing diagram note 1 initialization sequence may start at any time after tc . note 2 tinit3, and tc refer to timings in the lpddr2 initialization sequence. for more detail, see 3.4 . note 3 input clock frequency may be changed or the input clock stopped during deep power-down, provided that upon exiting deep power- down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to deep power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 66/129 - rev.1.0 july 2016
4.15 input clock stop and frequency change lpddr2 devices support input clock frequency change during cke low under the following conditions: ? tck(abs)min is met for each clock cycle; ? refresh requirements apply during clock frequency change; ? during clock frequency change, only refab or refpb commands may be executing; ? any activate, preactive, or precharge commands have executed to completion prior to changing the frequency; ? the related timing conditions (trcd, trp) have been met prior to changing the frequency; ? the initial clock frequency shall be maintained for a minimum of 2 clock cycles after cke goes low; ? the clock satisfies tch(abs) and tcl(abs) for a minimum of 2 clock cycles prior to cke going high. after the input clock frequency is changed and cke is held high, additional mrw commands may be required to set the wr, rl etc. these settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. lpddr2 devices support clock stop during cke low under the following conditions: ? ck is held low and ck# is held high during clock stop; ? refresh requirements apply during clock stop; ? during clock stop, only refab or refpb commands may be executing; ? any activate, preactive, or precharge commands have executed to completion prior to stopping the clock; ? the related timing conditions (trcd, trp) have been met prior to stopping the clock; ? the initial clock frequency shall be maintained for a minimum of 2 clock cycles after cke goes low; ? the clock satisfies tch(abs) and tcl(abs) for a minimum of 2 clock cycles prior to cke going high. lpddr2 devices support input clock frequency change during cke high under the following conditions: ? tck(abs)min is met for each clock cycle; ? refresh requirements apply during clock frequency change; ? any activate, read, write, preactive, precharge, mode register write, or mode register read commands must have executed to completion, including any associated data bursts prior to changing the frequency; ? the related timing conditions (trcd, twr, twra, trp, tmrw, tmrr, etc.) have been met prior to changing the frequency; ? cs# shall be held high during clock frequency change; ? during clock frequency change, only refab or refpb commands may be executing; ? the lpddr2 device is ready for normal operation after the clock satisfies tch(abs) and tcl(abs) for a minimum of 2tck + txp. after the input clock frequency is changed, additional mrw commands may be required to set the wr, rl etc. these settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. lpddr2 devices support clock stop during cke high under the following conditions: ? ck is held low and ck# is held high during clock stop; ? cs# shall be held high during clock clock stop; ? refresh requirements apply during clock stop; ? during clock stop, only refab or refpb commands may be executing; ? any activate, read, write, preactive, precharge, mode register write, or mode register read commands must have executed to completion, including any associated data bursts prior to stopping the clock; ? the related timing conditions (trcd, twr, twra, trp, tmrw, tmrr, etc.) have been met prior to stopping the clock; ? the lpddr2 device is ready for normal operation after the clock is restarted and satisfies tch(abs) and tcl(abs) for a minimum of 2tck + txp. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 67/129 - rev.1.0 july 2016
4.16 no operation command the purpose of the no operation command (nop) is to prevent the lpddr2 device from registering any unwanted command between operations. only when the cke level is constant for clock cycle n-1 and clock cycle n, a nop command may be issued at clock cycle n. a nop command has two possible encodings: 1. cs# high at the clock rising edge n. 2. cs# low and ca0, ca1, ca2 high at the clock rising edge n. the no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 68/129 - rev.1.0 july 2016
4.17 truth tables operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the lpddr2 device must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4.17.1 command truth table table 14 command truth table sdram cke cs# ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 ck command ck(n - 1) ck (n) edge mrw h h l l l l l ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 op0 op1 op2 op3 op4 op5 op6 op7 mr r h h l l l l h ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 x r efresh (per bank)* 10 h h l l l h l x x refresh (all bank) h h l l l h h x x enter self refresh h l l l l h x x activate (bank) h h l l h r8 r9 r10 r11 r12 ba0 ba1 ba2 r0 r1 r2 r3 r4 r5 r6 r7 r13 r14 write (bank) h h l h l l rfu rfu c1 c2 ba0 ba1 ba2 ap 3 c3 c4 c5 c6 c7 c8 c9 c10 c11 read (bank) h h l h l h rfu rfu c1 c2 ba0 ba1 ba2 ap 3 c3 c4 c5 c6 c7 c8 c9 c10 c11 precharge ( bank) h h l h h l h ab x ba0 ba1 ba2 x bst h h l h h l l x x enter deep power down h l l h h l x x no p h h l h h h x x maintain pd, sref, dpd (nop) l l h h h h x x nop h h h x x maintain pd, sref, dpd (nop) l l h x x enter power down h l h x x ex it pd, sref, dpd l h h x x notes to table 14 note 1 all lpddr2 commands are defined by states of cs#, ca0, ca1, ca2, ca3, and cke at the rising edge of the clock. note 2 for lpddr2 sdram, bank addresses ba0, ba1, ba2 (ba) determine which bank is to be operated upon. note 3 ap high during a read or write command indicates that an auto-precharge will occur to the bank associated with the read ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 69/129 - rev.1.0 july 2016
or write command. note 4 x means h or l (but a defined logic level) note 5 self refresh exit and deep power down exit are asynchronous. note 6 vref must be between 0 and vddq during self refresh and deep power down operation. note 7 caxr refers to command/address bit x on the rising edge of clock. note 8 caxf refers to command/address bit x on the falling edge of clock. note 9 cs# and cke are sampled at the rising edge of clock. note 10 per bank refresh is only allowed in devices with 8 banks. note 11 the least-significant column address c0 is not transmitted on the ca bus, and is implied to be zero. note 12 ab highduring precharge command indicates that all bank precharge will occur. in this case, bank address is do- not -care. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 70/129 - rev.1.0 july 2016
4.18 lpddr2-sdram truth tables the truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. table 15 C lpddr2-s4 : cke table device current state *3 cke n - 1 *1 cke n *1 cs# *2 command n *4 operation n *4 device next state notes active power down l l x x maintain active power down active power down l h h nop exit active power down active 6,9 idle power down l l x x maintain idle power down idle power down l h h nop exit idle power down idle 6,9 resetting power down l l x x maintain resetting power down resetting power down l h h nop exit resetting power down idle or resetting 6,9,12 deep power down l l x x maintain deep power down deep power down l h h nop exit deep power down power on 8 self refresh l l x x maintain self refresh self refresh l h h nop exit self refresh idle 7,10 bank(s) active h l h nop enter active power down active power down all banks idle h l h nop enter idle power down idle power down h l l enter self - refresh enter self refresh self refresh h l l deep power down enter deep power down deep power down resetting h l h nop enter resetting power down resetting power down h h refer to the command truth table note 1 cken is the logic state of cke at clock rising edge n; cken-1 was the state of cke at the previous clock edge. note 2 cs# is the logic state of cs# at the clock rising edge n; note 3 current state is the state of the lpddr2 device immediately prior to clock edge n. note 4 command n is the command registered at clock edge n, and operation n is a result of command n. note 5 all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. note 6 power down exit time (txp) should elapse before a command other than nop is issued. note 7 self-refresh exit time (txsr) should elapse before a command other than nop is issued. note 8 the deep power-down exit procedure must be followed as discussed in the deep power-down section of the functional description. note 9 the clock must toggle at least twice during the txp period. note 10 the clock must toggle at least twice during the txsr time. note 11 'x means dont care. note 12 upon exiting resetting power down, the device will return to the idle state if tinit5 has expired table 16 current state bank n - command to bank n cu rrent state command operation next state notes any nop continue previous operation c urrent state idle active select and activate row active refresh(per bank) begin to refresh r efreshing (per bank) 6 refresh(all bank) begin to refresh r efreshing (all bank) 7 mrw load value to mode register mr writing 7 mrr read value from mode register idle mr reading reset begin device auto - initialization resetting 7,8 precharge deactivate row in bank or banks precharging 9,15 row active read select column, and start read burst reading write select column, and start write burst writing mrr read value from mode register active mr reading AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 71/129 - rev.1.0 july 2016
precharge deactivate row in bank or banks precharging 9 reading read select column, and start new read burst reading 10,11 write select column, and start write burst writing 10,11,12 bst read burst terminate active 13 writing write select column, and start write burst writing 10,11 read select column, and start read burst reading 10,11,14 bst write burst terminate active 13 power on reset begin device auto - initialization resetting 7,9 resetting mrr read value from mode register resetting mr reading note 1 the table applies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was power down. note 2 all states and sequences not shown are illegal or reserved. note 3 current state definitions: - idle: the bank or banks have been precharged, and trp has been met. - active: a row in the bank has been activated, and trcd has been met. no data bursts / accesses and no register accessesare in progress. - reading: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. - writing: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. note 4 the following states must not be interrupted by a command issued to the same bank. nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other banks are determined by its current state and table 16 , and according to table 17 . - precharging: starts with the registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the idle state. - row activating: starts with registration of an activate command and ends when trcd is met. once trcd is met, th e b ank will be in the active state. - read with ap enabled: starts with the registration of the read command with auto precharge enabled and ends when trp has been met. once trp has been met, the bank will be in the idle state. - write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when trp h as b een met. once trp is met, the bank will be in the idle state. note 5 the following states must not be interrupted by any executable command; nop commands must be applied to each positive clock edge during these states. - refreshing (per bank): starts with registration of an refresh (per bank) command and ends when trfcpb is met. once trfcpb is met, the bank will be in an idle state. - refreshing (all bank): starts with registration of an refresh (all bank) command and ends when trfcab is met. once trfcab is met, the device will be in an all banks idle state. - idle mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the idle state. - resetting mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the resetting state. - active mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the active state. - mr writing: starts with the registration of a mrw command and ends when tmrw has been met. once tmrw has been met, the bank will be in the idle state. - precharging all: starts with the registration of a precharge-all command and ends when trp is met. once trp is met, the bank will be in the idle state. note 6 bank-specific; requires that the bank is idle and no bursts are in progress. note 7 not bank-specific; requires that all banks are idle and no bursts are in progress. note 8 not bank-specific reset command is achieved through mode register write command. note 9 this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for precharging. note 10 a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. note 11 the new read or write command could be auto precharge enabled or auto precharge disabled. note 12 a write command may be applied after the completion of the read burst; otherwise, a bst must be used to end the read prior to asserting a write command. note 13 not bank-specific. burst terminate (bst) command affects the most recent read/write burst started by the most recent read/write command, regardless of bank. note 14 a read command may be applied after the completion of the write burst; otherwise, a bst must be used to end the write prior to asserting a read command. note 15 if a precharge command is issued to a bank in the idle state, trp shall still apply ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 72/129 - rev.1.0 july 2016
table 17 current state bank n - command to bank m current state of bank n command for bank m operation next state for bank m notes any nop continue previous operation current state of bank m idle any any command allowed to bank m - 18 row activating, active, or precharging active select and activate row in bank m active 7 read select column, and start read burst from bank m reading 8 write select column, and start write burst to bank m writing 8 precharge deactivate row in bank or banks precharging 9 mrr read value from mode register idle mr reading or active mr reading 10,11,13 bst read or write burst terminate an ongoing read/write from/to bank m active 18 reading (autoprecharge disabled) read select column, and start read burst from bank m reading 8 write select column, and start write burst to bank m writing 8, 14 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 writing (autoprecharge disabled) read select column, and start read burst from bank m reading 8,16 write select column, and start write burst to bank m writing 8 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 reading with autoprecharge read select column, and start read burst from bank m reading 8,15 write select column, and start write burst to bank m writing 8,14,15 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 writing with autoprecharge read select column, and start read burst from bank m reading 8,15,16 write select column, and start write burst to bank m writing 8,15 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 power on reset begin device auto - initialization resetting 12,17 resetting mrr read value from mode register resetting mr reading note 1 the table applies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was self refresh or power down. note 2 all states and sequences not shown are illegal or reserved. note 3 current state definitions: - idle: the bank - active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in - reading: a read burst has been initiated, with auto precharge disabled, and - note 4 refresh, self-refresh, and mode register write commands may only be issued when all bank are idle. note 5 a burst terminate (bst) command cannot be issued to another bank; it applies to the bank represented by the current state only. note 6 the following states must not be interrupted by any executable command; nop commands must be applied during each clock cycle - idle mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the - resetting mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, - active mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will b - mr writing: starts with the registration of a mrw command and ends when tmrw has been met. once tmrw has been met, the note 7 trrd must be met between activate command to bank n and a subsequent activate command to bank m. note 8 reads or writes listed in the command column include reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. note 9 this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for precharging. note 10 mrr is allowed during the row activating state (row activating starts with registration of an activate command and ends when trcd is met.) note 11 mrr is allowed during the precharging state. (precharging starts with registration of a precharge command and ends when trp is met. note 12 not bank-specific; requires that all banks are idle and no bursts are in progress. note 13 the next state for bank m depends on the current state of bank m (idle, row activating, precharging, or active). the reader shall note that the state may be in transition when a mrr is issued. therefore, if bank m is in the row activating state and precharging, the next state may be active and precharge dependent upon trcd and trp respectively. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 73/129 - rev.1.0 july 2016
note 14 a write command may be applied after the completion of the read burst, otherwise a bst must be issued to end the read prior to asserting a write command. note 15 read with auto precharge enabled or a write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictions in table 9 are followed. note 16 a read command may be applied after the completion of the write burst; otherwise, a bst must be issued to end the write prior to asserting a read command. note 17 reset command is achieved through mode register write command. note 18 bst is allowed only if a read or write burst is ongoing. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 74/129 - rev.1.0 july 2016
4.19 data mask truth table table 18 provides the data mask truth table. table 18 dm truth table name (functional) dm dqs note write enable l valid 1 write inhibit h x 1 note 1 used to mask write data, provided coincident with the corresponding data AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 75/129 - rev.1.0 july 2016
5 absolute maximum ratings 5.1 absolute maximum dc ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 19 absolute maximum dc ratings parameter symbol min max unit notes vdd1 supply voltage relative to vss vdd1 - 0.4 2.3 v 2 vdd2 supply voltage relative to vss vdd2 - 0.4 1.6 v 2 vddq supply voltage relative to vssq vddq - 0.4 1.6 v 2,3 voltage on any ball relative to vss vin, vout - 0.4 1.6 v storage temperature tstg - 55 125 5 note 1 stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability note 2 see power-ramp section for relationships between power supplies. note 3 vrefdq 0.6 x vddq; however, vrefdq may be vddq provided that vrefdq 300mv. note 4 vrefca 0.6 x vdd 2 ; however, vrefca may be vdd 2 provided that vrefca 300mv. note 5 storage temperature is the case surface temperature on the center/top side of the lpddr2 device. for the measurement conditions, please refer to jesd51-2 standard. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 76/129 - rev.1.0 july 2016
6 ac & dc operating conditions operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the lpddr2 device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue. 6.1 recommended dc operating conditions table 20 recommended lpddr2-s4 dc operating conditions symbol lpddr2 - s4b dram unit min typ max vdd1 1.70 1.80 1.95 core power1 v vdd2 1.14 1.20 1.30 core power2 v vddq 1.14 1.20 1.30 i/o buffer power v note 1 vdd1 uses significantly less power than vdd2 6.2 input leakage current table 21 input leakage current parameter / condition symbol min max unit notes input leakage current i l -2 2 ua 2 for ca, cke, cs# , ck , ck# any input 0 vin vdd 2 (all other pins not under test =0v vref supply leakage current ivref -1 1 ua 1 vrefdq = vddq/2 or vrefca = vdd2 /2 (all other pins not under test =0v note 1 the minimum limit requirement is for testing purposes. the leakage current on v refca and v refdq pins should be minimal. note 2 although dm is for input only, the dm leakage shall match the dq and dqs/dqs# output leakage specification. 6.3 operating temperature range table 22 operating temperature range parameter / condition symbol mi n max unit standard t oper - 30 85 note 1 operating temperature is the case surface temperature on the center/top side of the lpddr2 device. for the measurement conditions, please refer to jesd51-2 standard. note 2 either the device case temperature rating or the temperature sensor may be used to set an appropriate refresh rate , determine the need for ac timing de-rating and/or monitor the operating temperature. when using the temperature sensor, the actual device case temperature may be higher than the t oper rating that applies for the standard or extended temperature ranges. for example, t case may be above 85 when the temperature sensor indicates a temperature of less than 85 . AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 77/129 - rev.1.0 july 2016
7 ac and dc input measurement levels 7.1 ac and dc logic input levels for single-ended signals 7.1.1 ac and dc input levels for single-ended ca and cs# signals table 2 3 single-ended ac and dc input levels for ca and cs# inputs symbol parameter lpddr2 - 800 unit notes min max v ihca (ac) ac input logic high vref +0.220 note 2 v 1,2 v ilca (ac) ac input logic low note 2 vref - 0.2 20 v 1,2 v ihca (dc) dc input logic high vref + 0.130 vdd2 v 1 v ilca (dc) dc input logic low vss vref -0.130 v 1 v refca (dc) reference voltage for ca and cs# inputs 0.49 * vdd2 0.51 * vdd2 v 3,4 note 1 for ca and cs# input only pins vref = v refca (dc) note 2 see 8.5 overshoot and undershoot specifications. note 3 the ac peak noise on vrefca may not allow vrefca to deviate from vrefca(dc) by more than 1% vdd2 (for reference : approx. 12mv) note 4 for reference : approx. vdd2/2 12mv 7.1.2 ac and dc input levels for cke table 24 single-ended ac and dc input levels for cke symbol parameter min max unit notes v ihcke cke input high level 0.8* vdd2 note 1 v 1 v ilcke cke input low level note 1 0.2 * vdd2 v 1 note 1 see 8.5 overshoot and undershoot specifications. 7.1.3 ac and dc input levels for single-ended data signals table 25 single-ended ac and dc input levels for dq and dm symbol parameter lpddr2 - 1066 to lpddr2 - 466 unit notes min max v ihdq (ac) ac input logic high vref +0.220 note 2 v 1,2,5 v ildq (ac) ac input logic low note 2 vref - 0.220 v 1,2,5 v ihdq (dc) dc input logic high vref + 0.130 vddq v 1 v ildq (dc) dc input logic low vssq vref -0.130 v 1 v refdq (dc) reference voltage for dq , dm inputs 0.49 * vddq 0.51 * vddq v 3,4 note 1 for dq input only pins vref = vrefdq(dc) note 2 see 8.5 overshoot and undershoot specifications. note 3 the ac peak noise on vrefdq may not allow vrefdq to deviate from vrefdq(dc) by more than 1% vddq (for reference : approx. 12mv) note 4 for reference : approx. vdddq/2 12mv AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 78/129 - rev.1.0 july 2016
7.2 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vrefca and vrefdq are illustrated in figure 7.1 . it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vdd stands for vdd2 for vrefca and vddq for vrefdq. vref(dc) is the linear average of vref(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of vddq or vdd2 also over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table 24 . furthermore vref(t) may temporarily deviate from vref(dc) by no more than +/- 1% vdd. vref(t) cannot track noise on vddq or vdd2 if this would send vref outside these specifications figure 7.1 illustration of v ref(dc) t olerance and v ref ac -noise limits the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. vref shall be understood as vref(dc), as defined in figure 7.1 . this clarifies that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. devices will function correctly with appropriate timing deratings with vref outside these specified levels so long as vref is maintained between 0.44 x vddq (or vdd2) and 0.56 x vddq (or vdd2) and so long as the controller achieves the required single-ended ac and dc input levels from instantaneous vref (see the single-ended ac and dc input levels for ca and cs# inputs table and single-ended ac and dc input levels for dq and dm.) therefore, system timing and voltage budgets need to account for vref deviations outside of this range. this also clarifies that the lpddr2 setup/hold specification and derating values need to include time and voltage associated with vref ac-noise. timing and voltage effects due to ac-noise on vref up to the specified limit (+/-1% of vdd) are included in lpddr2 timings and their associated deratings. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 79/129 - rev.1.0 july 2016
7.3 input signal figure 7.2 lpddr2-800 input signal note 1 numb ers reflect nominal values. note 2 for ca0-9, ck, ck#,and cs#, vdd stands for vdd2. for dq, dm, dqs, and dqs#, vdd stands for vddq. note 3 for ca0-9, ck, ck#, and cs#, vss stands for vss. for dq, dm, dqs, and dqs#, vss stands for vssq. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 80/129 - rev.1.0 july 2016
figure 7.3 lpddr2- 20 0 to lpddr2-400 inp ut signal note 1 numbers reflect nominal values note 2 for ca0-9, ck, ck#, and cs#, vdd stands for vdd2. for dq, dm, dqs, and dqs#, vdd stands for vddq. note 3 for ca0-9, ck, ck#, and cs#, vss stands for vss. for dq, dm, dqs, and dqs#, vss stands for vssq. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 81/129 - rev.1.0 july 2016
7.4 ac and dc logic input levels for differential signals 7.4.1 differential signal definition figure 7.4 definition of differential ac-swing and time above a c-level t dvac 7.4.2 differential swing requirements for clock (ck - ck#) and strobe (dqs - dqs#) table 26 differential ac and dc input levels symbol parameter lpddr2 - 1066 to lpddr2 - 466 lpddr2 - 400 to lpddr2 - 200 unit notes min max min max v ihdiff (dc) differential input high 2 x (vih( dc)- vref) note 3 2 x (vih( dc)- vref) note 3 v 1 v ildiff (dc) differential input low note 3 2 x (vil( dc)- vref) note 3 2 x (vil( dc)- vref) v 1 v ihdiff (ac) differential input high ac 2 x (vih( ac )- vref) note 3 2 x (vih( ac )- vref) note 3 v 2 v ildiff (ac) differential input low ac note 3 2 x (vil( ac )- vref) note 3 2 x (vil( ac )- vref) v 2 note 1 used to define a differential signal slew-rate. for ck - ck# use vih/vil(dc) of ca and vrefca ; for dqs - dqs#, use vih/vil(dc) of dqs and vrefdq; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here. note 2 for ck - ck# use vih/vil(ac) of ca and vrefca; for dqs - dqs#, use vih/vil(ac) of dqs and vrefdq; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here note 3 these values are not defined, however the single-ended signals ck , ck# , dqs, and dqs# need to be within the respective limits (vih(dc) max, vil(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. refer to overshoot and undershoot specifications note 4 for ck and ck#, vref = vrefca(dc). for dqs and dqs#, vref = vrefdq(dc). AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 82/129 - rev.1.0 july 2016
table 27 allowed time before ring back (tdvac) for ck - ck# and dqs - dqs# slew rate [v/ns] tdvac [ps] tdvac [ps] @|vih/ldiff(ac)| =440mv @|vih/ldiff(ac)| =600mv min min >4.0 175 75 4.0 170 57 3.0 167 50 2.0 163 38 1.8 162 34 1.6 161 29 1.4 159 22 1.2 155 13 1.0 150 0 <1.0 150 0 7.4.3 single-ended requirements for differential signals each individual component of a differential signal ( ck , dqs , ck#, or dqs#) has also to comply with certain requirements for single-ended signals. ck and ck# shall meet vseh(ac)min / vsel(ac)max in every half-cycle. dqs , dqs# shall meet vseh(ac)min / vsel(ac)max in every half-cycle preceeding and following a valid transition. note that the applic able ac-levels for ca and dqs are different per speed-bin. figure 7.5 single-ended requirement for differential signals. note that while ca and dq signal requirements are with respect to vref, the single-ended components of differential signals have a requirement with respect to vddq/2 for dqs , dqs# and vdd ca /2 for ck , ck#; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. for single-ended components of differential signals the requirement to reach vsel( ac )max, vseh( ac )min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. the single-ended requirements for ck , ck# , dqs, and dqs# are found in tables 23 and single-ended ac and dc input levels for dq and dm in tables 25 , respectively. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 83/129 - rev.1.0 july 2016
table 28 single-ended levels for ck, dqs, ck#, dqs# symbol parameter lpddr2 - 800 unit notes min max vseh(ac) single-ended high-level for strobes (vddq/2) +0.220 note 3 v 1,2 single-ended high-level for ck , ck# (vdd2/2) +0.220 note 3 v 1,2 vsel(ac) single-ended low-level for strobes note 3 (vddq/2) - 0.220 v 1,2 single-ended low-level for ck , ck# note 3 (vdd2/2) - 0.220 v 1,2 note 1 for ck , ck# use vseh/vsel( ac ) of ca; for strobes (dqs0, dqs0#, dqs1, dqs1#, dqs2, dqs2#, dqs3, dqs3#) use vih/vil( ac ) of dqs. note 2 vih( ac )/vil( ac ) for dqs is based on vrefdq; vseh( ac )/vsel( ac ) for ca is based on vrefca; if a reduced ac-high or ac -low level is used for a signal group, then the reduced level applies also here note 3 the se values are not defined, however the single-ended signals ck , ck#, dqs0, dqs0#, dqs1, dqs1#, dqs2, dqs2#, dqs3, dqs3# need to be within the respective limits (vih( dc ) max, vil( dc )min) for single-ended signals as well as the limitations for overshoot and undershoot. refer to overshoot and undershoot specifications AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 84/129 - rev.1.0 july 2016
7.5 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals ( ck , ck# and dqs , dqs#) must meet the requirements in table 28 . the differential input cross point voltage vix is measured from the actual cross point of true and complement signals to the midlevel between of vdd and vss. figure 7.6 vix definition table 29 cross point voltage for differential input signals (ck, dqs) symbol parameter lpddr2 - 800 unit notes min max v ixca differential input cross point voltage relative to v dd2/2 for ck , ck# - 120 120 mv 1,2 v ixdq differential input cross point voltage relative to v ddq/2 for dqs , dqs# - 120 120 mv 1,2 note 1 the typical value of vix(ac) is expected to be about 0.5 vdd of the transmitting device, and vix(ac) is expected to track variations in vdd. vix(ac) indicates the voltage at which differential input signals must cross. note 2 for ck and ck#, vref = vrefca(dc). for dqs and dqs#, vref = vrefdq(dc). AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 85/129 - rev.1.0 july 2016
7.6 slew rate definitions for single-ended input signals see ca and cs# setup, hold and derating for single-ended slew rate definitions for address and command signals. see data setup, hold and slew rate derating for single-ended slew rate definitions for data signals. 7.7 slew rate definitions for differential input signals input slew rate for differential signals ( ck , ck# and dqs , dqs#) are defined and measured as shown in table 30 and figure 7.7 . table 30 differential input slew rate definition description measured defined by from to differential input slew rate for rising edge v ildiffmax v ihdiffmin [v ihdiffmin - v ildiffmax ] / deltatrdiff ( ck - ck# and dqs - dqs#) differential input slew rate for falling edge v ihdiffmin v ildiffmax [v ihdiffmin - v ildiffmax ] / deltatfdiff ( ck - ck# and dqs - dqs#) note 1 the differential signal (i.e. ck - ck# and dqs - dqs# ) must be linear between these thresholds figure 7.7 differential input slew rate definition for dqs, dqs# and ck, ck# AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 86/129 - rev.1.0 july 2016
8 ac and dc output measurement levels 8.1 single ended ac and dc output levels table 31 shows the output levels used for measurements of single ended signals. table 31 single-ended ac and dc output levels symbol parameter lpddr2 - 800 unit notes v oh(dc) dc output high measurement level (for iv curve linearity) 0.9 x vddq v 1 v oh(dc) dc output low measurement level (for iv curve linearity) 0.1 x vddq v 2 v oh(ac) ac output high measurement level (for output slew rate) vrefdq + 0.12 v v oh(ac) ac output low measurement level (for output slew rate) vrefdq - 0.12 v i oz output leakage current (dq, dm, dqs , dqs#) min -5 ua dq, dqs , dqs# are disabled ; 0v vout vddq max 5 ua mm pupd delta ron between pull-up and pull-down for dq/dm min -15 % max 15 % note 1 ioh = -0.1ma. note 2 iol = 0.1ma 8.2 differential ac and dc output levels table 3 2 shows the output levels used for measurements of diffential signals (dqs, dqs#). table 32 differential ac and dc output levels symbol parameter lpddr2 - 80 0 unit notes v ohdiff(dc) ac differential output high measurement level (for output sr) +0.20 x vddq v 1 v oldiff(dc) ac differential output low measurement level (for output sr) -0.20 x vddq v 2 note 1 ioh = -0.1ma. note 2 iol = 0.1ma AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 87/129 - rev.1.0 july 2016
8.3 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol(ac) and v oh(ac) for single ended signals as shown in table 33 and figure 8.1 . table 33 single-ended output slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) - v ol(ac )] / deltatrse single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) - v ol(ac )] / deltatfse figure 8.1 single ended output slew rate definition AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 88/129 - rev.1.0 july 2016
table 34 output slew rate (single-ended) parameter symbol lpddr2 - 8 00 units min max single-ended output slew rate (ron = 40 ? 30%) srqse 1.5 3.5 v/ns single-ended output slew rate (ron = 60 ? 30%) srqse 1.0 2.5 v/ns output slew-rate matching ratio (pull-up to pull-down) 0.7 1.4 description sr: slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals note 1 measured with output reference load. note 2 the ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. note 3 the output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac). note 4 slew rates are measured under normal sso conditions, with 1/2 of dq signals per data byte driving logic-high and 1/2 of dq signals per data byte driving logic-low. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 89/129 - rev.1.0 july 2016
8.4 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for differential signals as shown in table 35 and figure 8.2 table 35 differential output slew rate definition description measured defined by from to differential output slew rate to rising edge v oldiff(ac) v ohdiff(ac) [v ohdiff(ac) - v oldiff(ac) ] / delta trdiff differential output slew rate to falling edge v ohdiff(ac) v oldiff(ac) [v ohdiff(ac) - v oldiff(ac) ] / delta tfdiff note 1 output slew rate is verified by design and characterization, and may not be subject to production test. figure 8.2 differential output slew rate definition AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 90/129 - rev.1.0 july 2016
table 36 differential output slew rate parameter symbol lpddr2 - 800 units min max differential output slew rate (ron = 40 ? 30%) srqse 3.0 7.0 v/ns differential output slew rate (ron = 60 ? 30%) srqse 2.0 5.0 v/ns description sr: slew rate q: query output (like in dq, which stands for data-in, query-output) diff : differential signals note 1 measured with output reference load. note 2 the output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac). note 3 slew rates are measured under normal sso conditions, with 1/2 of dq signals per data byte driving logic-high and 1/2 of dq signals per data byte driving logic-low. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 91/129 - rev.1.0 july 2016
8.5 overshoot and undershoot specifications table 37 ac overshoot/undershoot specification parameter 800 units maximum peak amplitude allowed for overshoot area. max 0.35 v (see figure 8.3 ) maximum peak amplitude allowed for undershoot area max 0.35 v (see figure 8.3 ) maximum area above vdd. max 0.20 v-ns (see figure 8.3 ) maximum area below vss. max 0.20 v-ns (see figure 8.3 ) (ca0-9, cs#, cke, ck , ck#, dq, dqs, dqs#, dm) note 1 for dq, dm , dqs , and dqs#, vdd stands for vddq. note 2 for dq, dm , dqs , and dqs#, vss stands for vssq. note 3 values are referenced from actual vddq and vssq levels. figure 8.3 overshoot and undershoot definition note 1 for dq, dm, dqs, and dqs#, vdd stands for vddq. note 2 for dq, dm, dqs, and dqs#, vss stands for vssq. note 3 maximum peak amplitude values are referenced from actual vdd and vss values. note 4 maximum area values are referenced from maximum operating vdd and vss values. v dd v ss volts (v) time (ns) maximum amplitude maximum amplitude undershoot area overshoot area AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 92/129 - rev.1.0 july 2016
8.6 output buffer characteristics 8.6.1 hsul_12 driver output timing reference load these timing reference loads are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. figure 8.4 hsul_12 driver output reference load for timing and slew rate note 1: all output timing parameter values (like t dqsck , t dqsq , t qhs, t hz , t rpre etc.) are reported with respect to this reference load. this reference load is also used to report slew rate. lpddr2 v ref output 0.5 x v ddq 50 ? vtt = 0.5 x v ddq cload = 5pf AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 93/129 - rev.1.0 july 2016
8.7 ron pu and ron pd resistor definition note 1: this is under the condition that ron pd is turned off note 1: this is under the condition that ron pu is turned off figure 8.5 output driver: definition of voltages and currents chip in drive mode output driver to other circuitry (rcv, etc.) ipu ipd ronpu ronpd iout v out v ddq v ssq dq AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 94/129 - rev.1.0 july 2016
8.7.1 ron pu and ron pd characteristics with zq calibration output driver impedance ron is defined by the value of the external reference resistor rzq. nominal rzq is 240 . table 38 output driver dc electrical characteristics with zq calibration ron nom resistor vout min nom max unit notes 34.3 ? ron34pd 0.5 x vddq 0.85 1.00 1.15 rzq/7 1,2,3,4 ron34pu 0.5 x vddq 0.85 1.00 1.15 rzq/7 1,2,3,4 40.0 ? ron40pd 0.5 x vddq 0.85 1.00 1.15 rzq/6 1,2,3,4 ron40pu 0.5 x vddq 0.85 1.00 1.15 rzq/6 1,2,3,4 48.0 ? ron48pd 0.5 x vddq 0.85 1.00 1.15 rzq/5 1,2,3,4 ron48pu 0.5 x vddq 0.85 1.00 1.15 rzq/5 1,2,3,4 60.0 ? ron60pd 0.5 x vddq 0.85 1.00 1.15 rzq/4 1,2,3,4 ron60pu 0.5 x vddq 0.85 1.00 1.15 rzq/4 1,2,3,4 80.0 ? ron80pd 0.5 x vddq 0.85 1.00 1.15 rzq/3 1,2,3,4 ron80pu 0.5 x vddq 0.85 1.00 1.15 rzq/3 1,2,3,4 120.0 ? ron120pd 0.5 x vddq 0.85 1.00 1.15 rzq/2 1,2,3,4 (optional) ron120pu 0.5 x vddq 0.85 1.00 1.15 rzq/2 1,2,3,4 mismatch between mm pupd -15.00 15.00 % 1,2,3,4,5 pull-up and pull-down note 1 across entire operating temperature range, after calibration. note 2 rzq = 240 . note 3 the tolerance limits are specified after calibration with fixed voltage and temperature. for behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. note 4 pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x vddq. note 5 measurement definition for mismatch between pull-up and pu ll -down, mmpupd: measure ron pu and ron pd , both at 0.5 x vddq: for example, with mmpupd(max) = 15% and ronpd = 0.85, ronpu must be less than 1.0. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 95/129 - rev.1.0 july 2016
8.7.2 output driver temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to the tables shown below. table 39 output driver sensitivity definition resistor vout min max unit notes ronpd 0.5 x vddq 85 - ( drondt x | v|) - ( drondv x| v|) 115 + (drondt x | v|) + ( drondv x| v|) % 1,2 ronpu note 1 t = t C t (@ calibration), v = v-v (@ calibration) note 2 drondt and drondv are not subject to production test but are verified by design and characterization. table 40 output driver temperature and voltage sensitivity symbol parameter min max unit notes drondt ron temperature sensitivity 0.00 0.75 %/ drondv ron voltage sensitivity 0.00 0.75 %/ mv ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 96/129 - rev.1.0 july 2016
8.7.3 ron pu and ron pd characteristics without zq calibration output driver impedance ron is defined by design and characterization as default setting. table 41 output driver dc electrical characteristics without zq calibration ron nom resistor vout min nom max unit notes 34.3 ? ron34pd 0.5 x vddq 24.0 34.3 44.6 ? 1 ron34pu 0.5 x vddq 24.0 34.3 44.6 ? 1 40.0 ? ron40pd 0.5 x vddq 28.0 40.0 52.0 ? 1 ron40pu 0.5 x vddq 28.0 40.0 52.0 ? 1 48.0 ? ron48pd 0.5 x vddq 33.6 48.0 62.4 ? 1 ron48pu 0.5 x vddq 33.6 48.0 62.4 ? 1 60.0 ? ron60pd 0.5 x vddq 42.0 60.0 78.0 ? 1 ron60pu 0.5 x vddq 42.0 60.0 78.0 ? 1 80.0 ? ron80pd 0.5 x vddq 56.0 80.0 104.0 ? 1 ron80pu 0.5 x vddq 26.0 80.0 104.0 ? 1 120.0 ? ron120pd 0.5 x vddq 84.0 120.0 156.0 ? 1 (optional) ron120pu 0.5 x vddq 84.0 120.0 156.0 ? 1 note 1 across entire operating temperature range, without calibration. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 97/129 - rev.1.0 july 2016
8.7.4 rzq i-v curve table 42 rzq i-v curve voltage [v] ron = 240 ? (rzq) pull - down pull - up current [ma] / ron [ohms] current [ma] / ron [ohms] default value after zqreset with calibration default value after zqreset with calibration min max min max min max min max [ma] [ma] [ma] [ma] [ma] [ma] [ma] [ma] 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.05 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26 0.10 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53 0.15 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78 0.20 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04 0.25 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29 0.30 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53 0.35 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79 0.40 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03 0.45 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26 0.50 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49 0.55 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72 0.60 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94 0.65 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15 0.70 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36 0.75 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55 0.80 2.25 4.54 2.70 3.74 -2.25 -4.54 -2.70 -3.74 0.85 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91 0.90 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05 0.95 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23 1.00 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33 1.05 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44 1.10 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52 1.15 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59 1.20 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65 figure 8.6 ron = 240 ohms iv curve after zqreset AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 98/129 - rev.1.0 july 2016
figure 8.7 ron = 240 ohms iv curve after c alibration AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 99/129 - rev.1.0 july 2016
9 input/output capacitance 9.1 input/output capacitance table 43 input/output capacitance parameter symbol lpddr2 800 units notes input capacitance, cck min 1.00 pf 1,2 ck and ck# max 3 .00 pf 1,2 input capacitance delta, cdck min 0.00 pf 1,2,3 ck and ck# max 0. 20 pf 1,2,3 input capacitance, ci min 1.00 pf 1,2,4 all other input - only pins max 3 .00 pf 1,2,4 input capacitance, cdi min - 0. 5 0 pf 1,2,5 all other input - only pins max 0. 5 0 pf 1,2,5 input/output capacitance, cio min 1.25 pf 1,2,6,7 dq, dm, dqs , dqs# max 3 .50 pf 1,2,6,7 input/output capacitance delta, cddqs min 0.00 pf 1,2,7,8 dqs , dqs# max 0.25 pf 1,2,7,8 input/output capacitance delta, cdio min - 0.50 pf 1,2,7,9 dq, dm max 0.50 pf 1,2,7,9 input/output capacitance zq pin czq min 0.00 pf 1,2 max 3 .50 pf 1,2 (toper; v ddq = 1.14-1.3v; vdd2 = 1.14-1.3v; vdd1 = 1.7-1.95v, lpddr2-s4a vdd2 = 1.28-1.42v) note 1 this parameter applies to die device only (does not include package capacitance). note 2 this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147 (procedure for measuring input capacitance using a vector network analyzer (vna) with vdd1, vdd2, vddq, vss, vssca, vssq applied and all other pins floating. note 3 absolute value of c ck - cck#. note 4 ci applies to cs#, cke, ca0-ca9. note 5 cdi = ci - 0.5 * (c ck + cck#) note 6 dm loading matches dq and dqs. note 7 mr3 i/o configuration ds op3-op0 = 0001b (34.3 ohm typical) note 8 absolute value of c dqs and cdqs#. note 9 cdio = cio - 0.5 * (c dqs + cdqs#) in byte-lane. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 100/129 - rev.1.0 july 2016
10 idd specification parameters and test conditions 10.1 idd measurement conditions the following definitions are used within the idd measurement tables: low: vin vil(dc) max high: vin vih(dc) min stable: inputs are stable at a high or low level switching: see table 45 and table 46. table 44 definition of switching for ca input signals switching for ca ck (rising) / ck# (falling) ck (falling) / ck# (rising) ck (rising) / ck# (falling) ck (falling) / ck# (rising) ck (rising) / ck# (falling) ck (falling) / ck# (rising) ck (rising) / ck# (falling) ck (falling) / ck# (rising) cycle n n+1 n+2 n+3 cs# high high high high ca0 high low low low low high high high ca1 high high high low low low low high ca2 high low low low low high high high ca3 high high high low low low low high ca4 high low low low low high high high ca5 high high high low low low low high ca6 high low low low low high high high ca7 high high high low low low low high ca8 high low low low low high high high ca9 high high high low low low low high note 1 cs# must always be driven high. note 2 50% of ca bus is changing between high and low once per clock for the ca bus. note 3 the above pattern (n, n+1, n+2, n+3...) is used continuously during idd measurement for idd values that require switching on the ca bus. table 45 definition of switching for idd4r clock cke cs# clock cycle number command ca0 - ca2 ca3 - ca9 all dq rising high low n read_rising hlh lhlhlhl l falling high low n read_falling lll lllllll l rising high high n+1 nop lll lllllll h falling high high n+1 nop hlh hlhllhl l rising high low n+2 read_rising hlh hlhllhl h falling high low n+2 read_falling lll hhhhhhh h rising high high n+3 nop lll hhhhhhh h falling high high n+3 nop hlh lhlhlhl l note 1 data strobe (dqs) is changing between high and low every clock cycle. note 2 the above pattern (n, n+1...) is used continuously during idd measurement for idd4r. table 46 definition of switching for idd4w clock cke cs# clock cycle number command ca0 - ca2 ca3 - ca9 all dq rising high low n write_rising hlh lhlhlhl l falling high low n write_falling lll lllllll l rising high high n+1 nop lll lllllll h falling high high n+1 nop hlh hlhllhl l rising high low n+2 write_rising hlh hlhllhl h falling high low n+2 write_falling lll hhhhhh h h rising high high n+3 nop lll hhhhhhh h falling high high n+3 nop hlh lhlhlhl l note 1 data strobe (dqs) is changing between high and low every clock cycle. note 2 data masking (dm) must always be driven low. note 3 the above pattern (n, n+1...) is used continuously during idd measurement for idd4w. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 101/129 - rev.1.0 july 2016
10.2 idd specifications idd values are for the entire operating voltage range, and all of them are for the entire standard range, with the exception of idd6et which is for the entire extended temperature range. table 47 lpddr2 idd specification parameters and operating conditions parameter / condition symbol power supply 400 mhz units notes x32 x16 operating one bank active-precharge current (sdram): idd0 1 vdd1 6 6 ma 4 t ck = t ck(avg)min ; t rc = t rcmin ; idd0 2 vdd2 35 35 ma 4 cke is high; idd0 in vdd2 + vddq 6 6 ma 4,5 cs# is high between valid commands; ca bus inputs are switching; data bus inputs are stable idle power-down standby current: idd 2p 1 25 vdd1 0.12 ma 4 t ck = t ck(avg)min ; 85 0.2 cke is low; idd 2p 2 25 vdd2 0.3 ma 4 cs# is high; 85 0.6 all banks/rbs idle; idd 2p in 25 vdd2 + vddq 0.02 ma 4,5 ca bus inputs are switching; 85 0.1 data bus inputs are stable idle power-down standby current with clock stop: idd2ps 1 25 vdd1 0.12 ma 4 ck =low, ck# =high; 85 0.2 cke is low; idd2ps 2 25 vdd2 0.3 ma 4 cs# is high; 85 0.6 all banks/rbs idle; idd2ps in 25 vdd2 + vddq 0.02 ma 4,5 ca bus inputs are stable; 85 0.1 data bus inputs are stable idle non power-down standby current: idd2n 1 vdd1 1 1 ma 4 t ck = t ck(avg)min ; idd2n 2 vdd2 8 8 ma 4 ck e is high; idd2n in vdd2 + vddq 6 6 ma 4,5 cs# is high; all banks/rbs idle; ca bus inputs are switching; data bus inputs are stable idle non power-down standby current with clock stop: idd2ns 1 vdd1 1 1 ma 4 ck =low, ck# =high; idd2ns 2 vdd2 4 4 ma 4 ck e is high; idd2ns in vdd2 + vddq 5 5 ma 4,5 cs# is high; all banks/rbs idle; ca bus inputs are stable; data bus inputs are stable active power-down standby current: idd3p 1 vdd1 2 2 ma 4 t ck = t ck(avg)min ; idd3p 2 vdd2 4 4 ma 4 cke is low; idd3p in vdd2 + vddq 2 2 ma 4,5 cs# is high; one bank/rb active; ca bus inputs are switching; data bus inputs are stable active power-down standby current with clock stop: idd3ps 1 vdd1 2 2 ma 4 ck =low, ck#=high; idd3ps 2 vdd2 4 4 ma 4 cke is low; idd3ps in vdd2 vddq 2 2 ma 4,5 cs# is high; one bank/rb active; ca bus inputs are stable; data bus inputs are stable AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 102/129 - rev.1.0 july 2016
parameter / condition symbol power supply 400 mhz units notes x32 x16 active non power-down standby current: idd3n 1 vdd1 2 2 ma 4 t ck = t ck(avg)min ; idd3n 2 vdd2 10 10 ma 4 cke is high; idd3n in vdd2 + vddq 6 6 ma 4,5 cs# is high; one bank/rb active; ca bus inputs are switching; data bus inputs are stable active non power-down standby current with clock stop: idd3ns 1 vdd1 2 2 ma 4 ck =low, ck#=high; idd3ns 2 vdd2 6 6 ma 4 cke is high; idd3ns in vdd2 + vddq 5 5 ma 4,5 cs# is high; one bank/rb active; ca bus inputs are stable; data bus inputs are stable operating burst read current: idd4r 1 vdd1 2 2 ma 4 t ck = t ck(avg)min ; idd4r 2 vdd2 115 90 ma 4 cs# is high between valid commands; idd4r in vdd2 6 4 ma 4 one bank/rb active; idd4r q vddq 130 70 ma 4,8 bl = 4; rl = rlmin; ca bus inputs are switching; 50% data change each burst transfer operating burst write current: idd4w 1 vdd1 2 2 ma 4 t ck = t ck(avg)min ; idd4w 2 vdd2 120 85 ma 4 cs# is high between valid commands; idd4w in vdd2 + vddq 15 8 ma 4,5 one bank/rb active; bl = 4; wl = wlmin; ca bus inputs are switching; 50% data change each burst transfer all bank refresh burst current: idd5 1 vdd1 10 10 ma 1,4 t ck = t ck(avg)min ; idd5 2 vdd2 80 80 ma 1,4 cke is high between valid commands; idd5 in vdd2 vddq 6 6 ma 1,4,5 t rc = t rfcabmin ; burst refresh; ca bus inputs are switching; data bus inputs are stable; all bank refresh average current: idd5ab 1 vdd1 2 2 ma 1,4 t ck = t ck(avg)min ; idd5ab 2 vdd2 15 15 ma 1,4 cke is high between valid commands; idd5ab in vdd2 + vddq 6 6 ma 1,4,5 t rc = t refi ; ca bus inputs are switching; data bus inputs are stable; per bank refresh average current: idd5pb 1 vdd1 2 2 ma 1,2,4 t ck = t ck(avg)min ; idd5pb 2 vdd2 20 20 ma 1,2,4 cke is high between valid commands; idd5pb in vdd2 + vddq 6 6 ma 1,2,4,5 t rc = t refi/8 ; ca bus inputs are switching; data bus inputs are stable; self refresh current (standard temperature range): idd6 1 25 vdd1 0.15 ma 1,3,4,1 1,12 ck =low, ck#=high; 85 0.3 cke is low; i dd6 2 25 vdd2 0.25 ma 1,3,4,1 1,12 ca bus inputs are stable; 85 1.0 data bus inputs are stable; idd6 in 25 vdd2 + vddq 0.02 ma 1,3,4,5 ,11,12 maximum 1x self-refresh rate; 85 0.1 AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 103/129 - rev.1.0 july 2016
parameter / condition symbol power supply 400 mhz units notes x32 x16 deep power-down current: idd8 1 45 vdd1 100 ua 1,4 ck =low, ck#=high; 85 200 cke is low; idd8 2 45 vdd2 100 ua 1,4 ca bus inputs are stable; 85 200 data bus inputs are stable; idd8 in 45 vdd2 + vddq 100 ua 1,4,5 85 200 note 1 refresh currents and deep power down currents are not relevant for nvm devices. note 2 per bank refresh only applicable for lpddr2-s4 devices of 1gb or higher densities note 3 this is the general definition that applies to full array self refresh. refer to table 48 for details of partial array self refresh idd6 specification. note 4 idd values published are the maximum of the distribution of the arithmetic mean. note 5 measured currents are the summation of vddq and vdd2. note 6 to calculate total current consumption, the currents of all active operations must be considered. note 7 guaranteed by design with output load of 5pf and ron = 40ohm. note 8 idd current specifications are tested after the device is properly initialized. note 9 in addition, supplier data sheets may include additional self refresh idd values for temperature subranges within the standard or extended temperature ranges. note 10 1x self-refresh rate is the rate at which the lpddr2-sx device is refreshed internally during self-refresh before going into the extended temperature range. note 1 1 dpd (deep power down) function is an optional feature, and it will be enabled upon request. please contact alliance for more information.. table 48 idd6 partial array self-refresh current parameter symbol power lpddr2 - s4 unit supply 25 85 idd6 partial array self refresh current full array idd6 1 vdd1 150 300 ua idd6 2 vdd2 250 1000 idd6 in vdd2 + vddq 20 100 1/2 array idd6 1 vdd1 148 285 ua idd6 2 vdd2 225 830 idd6 in vdd2 + vddq 20 100 1/4 array idd6 1 vdd1 147 280 ua idd6 2 vdd2 210 730 idd6 in vdd2 + vddq 20 100 1/8 array idd6 1 vdd1 147 275 ua idd6 2 vdd2 200 690 idd6 in vdd2 + vddq 20 100 note 1 lpddr2-s4 sdram uses the same pasr scheme & idd6 current value categorization as lpddr (jesd209). note 2 idd values published are the maximum of the distribution of the arithmetic mean. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 104/129 - rev.1.0 july 2016
11 electrical characteristics and ac timing 11.1 clock specification the jitter specified is a random jitter meeting a gaussian distribution. input clocks violating the min/max values may result in malfunction of the lpddr2 device. 11.1.1 definition for tck(avg) and nck tck(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. w h e r e n = 200 unit tck(avg) represents the actual clock average tck(avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges. tck(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specs are met. 11.1.2 definition for t ck (abs) t ck (abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. t ck (abs) is not subject to production test. 11.1.3 12.1.3 definition for t ch (avg) and t cl (avg) t ch (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses w h e r e n = 200 t cl (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. w h e r e n = 200 11.1.4 definition for tjit(per) t jit(per) is the single period jitter defined as the largest deviation of any signal tck from tck(avg). t jit(per) = min/max of {tcki - tck(avg) where i = 1 to 200}. t jit(per),act is the actual clock jitter for a given system. t jit(per),allowed is the specified allowed clock period jitter. t jit(per) is not subject to production test. 11.1.5 definition for tjit(cc) tjit(cc) is defined as the absolute difference in clock period between two consecutive clock cycles. t jit(cc) = max of |{tcki +1 - tcki}|. t jit(cc) defines the cycle to cycle jitter. t jit(cc) is not subject to production test. 11.1.6 6 definition for terr(nper) t err(nper) is defined as the cumulative error across n multiple consecutive cycles from tck(avg). t err(nper),act is the actual clock jitter over n cycles for a given system. t err(nper),allowed is the specified allowed clock period jitter over n cycles. t err(nper) is not subject to production test. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 105/129 - rev.1.0 july 2016
t err (nper),min can be calculated by the formula shown below: t err (nper),max can be calculated by the formula shown below: using these equations, t err (nper) tables can be generated for each t jit (per),act value. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 106/129 - rev.1.0 july 2016
11.1.7 definition for duty cycle jitter tjit(duty) t jit(duty) is defined with absolute and average specification of tch / tcl. 11.1.8 definition for tck(abs), tch(abs) and tcl(abs) these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. table 49 definition for tck(abs), tch(abs), and tcl(abs) parameter symbol min unit absolute clock period t ck (abs) tck(avg),min + tjit(per),min ps absolute clock high pulse width t ch (abs) tch(avg),min + tjit(duty),min/ tck(avg),min t ck (abs) absolute clock low pulse width t cl (abs) tcl(avg),min + tjit(duty),min/ tck(avg),min t ck (abs) note 1 tck(avg),min is expressed is ps for this table. note 2 tjit(duty),min is a negative value. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 107/129 - rev.1.0 july 2016
11.2 period clock jitter lpddr2 devices can tolerate some clock period jitter without core timing parameter de-rating. this section describes device timing requirements in the presence of clock period jitter (tjit(per)) in excess of the values found in table 52 and how to determine cycle time de-rating and clock cycle de-rating. 11.2.1 clock period jitter effects on core timing parameters (trcd, trp, trtp, twr, twra, twtr,trc, tras, trrd, tfaw ) core timing parameters extend across multiple clock cycles. period clock jitter will impact these parameters when measured in numbers of clock cycles. when the device is operated with clock jitter within the specification limits, the lpddr2 device is characterized and verified to support tnparam = ru{tparam / tck(avg)}. when the device is operated with clock jitter outside specification limits, the number of clocks or tck(avg) may need to be increased based on the values for each core timing parameter. 11.2.1.1 cycle time de-rating for core timing parameters for a given number of clocks (tnparam), for each core timing parameter, average clock period (tck(avg)) and actual cumulative period error (terr(tnparam),act) in excess of the allowed cumulative period error (terr(tnparam),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the equation results in a positive value for a core timing parameter (tcore). a cycle time derating analysis should be conducted for each core timing parameter. the amount of cycle time derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter. 11.2.1.2 clock cycle de-rating for core timing parameters for a given number of clocks (tnparam) for each core timing parameter, clock cycle de-rating should be specified with amount of period jitter (tjit(per)). for a given number of clocks (tnparam), for each core timing parameter, average clock period (tck(avg)) and actual cumulative period error (terr(tnparam),act) in excess of the allowed cumulative period error (terr(tnparam),allowed), the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a core timing parameter (tcore). a clock cycle de -rating analysis should be conducted for each core timing parameter. 11.2.2 clock jitter effects on command/address timing parameters (tis, tih, tiscke, tihcke, tisb, tihb, tisckeb, tihckeb) these parameters are measured from a command/address signal (cke, cs, ca0 - ca9) transition edge to its respective clock signal ( ck /ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e., tjit(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of clock jitter values, these values shall be met. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 108/129 - rev.1.0 july 2016
11.2.3 12.2.3 clock jitter effects on read timing parameters 11.2.3.1 trpre when the device is operated with input clock jitter, trpre needs to be de-rated by the actual period jitter (tjit(per),act,max) of the input clock in excess of the allowed period jitter (tjit(per),allowed,max). output de-ratings are relative to the input clock. for example, if the measured jitter into a lpddr2-800 device has tck(avg) = 2500 ps, tjit(per),act,min = -172 ps and tjit(per),act,max = + 193 ps, then trpre,min,derated = 0.9 - (tjit(per),act,max - tjit(per),allowed,max)/tck(avg) = 0.9 - (193 - 100)/2500= .8628 tck(avg) 11.2.3.2 tlz(dq), thz(dq), tdqsck, tlz(dqs), thz(dqs) these parameters are measured from a specific clock edge to a data signal (dmn, dqm.: n=0,1,2,3. m=0C31) transition and will be met with respect to that clock edge. therefore, they are not affected by the amount of clock jitter applied (i.e. tjit(per). 11.2.3.3 tqsh, tqsl these parameters are affected by duty cycle jitter which is represented by tch(abs)min and tcl(abs)min. tqsh(abs)min = tch(abs)min C 0.05 tqsl(abs)min = tcl(abs)min C 0.05 these parameters determine absolute data-valid window at the lpddr2 device pin. absolute min data-valid window @ lpddr2 device pin = min {(tqsh(abs)min * tck(avg)min C tdqsqmax C tqhsmax) , (tqsl(abs)min * tck(avg)min C tdqsqmax C tqhsmax)} this minimum data -valid window shall be met at the target frequency regardless of clock jitter. 11.2.3.4 trpst trpst is affected by duty cycle jitter which is represented by tcl(abs). therefore trpst(abs)min can be specified by tcl(abs)min. trpst(abs)min = tcl(abs)min C 0.05 = tqsl(abs)min AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 109/129 - rev.1.0 july 2016
11.2.4 clock jitter effects on write timing parameters 11.2.4.1 1 tds, tdh these parameters are measured from a data signal (dmn, dqm.: n=0,1,2,3. m=0 C31) transition edge to its respective data strobe signal (dqsn_t, dqsn_c : n=0,1,2,3) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of clock jitter values, these values shall be met. 11.2.4.2 tdss, tdsh these parameters are measured from a data strobe signal (dqsx_t, dqsx_c) crossing to its respective clock signal ( ck /ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of clock jitter values, these values shall be met. 11.2.4.3 tdqss this parameter is measured from a data strobe signal (dqsx_t, dqsx_c) crossing to the subsequent clock signal ( ck /ck#) crossing. when the device is operated with input clock jitter, this parameter needs to be de-rated by the actual period jitter tjit(per),act of the input clock in excess of the allowed period jitter tjit(per),allowed. for example, if the measured jitter into a lpddr2-800 device has tck(avg)= 2500 ps, tjit(per),act,min= -172 ps and tjit(per),act,max= + 193 ps, then tdqss,(min,derated) = 0.75 - (tjit(per),act,min - tjit(per),allowed,min)/tck(avg) = 0.75 - (-172 + 100)/2500 = .7788 tck(avg) and tdqss,(max,derated) = 1.25 - (tjit(per),act,max - tjit(per),allowed,max)/tck(avg) = 1.25 - (193 - 100)/2500 = 1.2128 tck(avg) AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 110/129 - rev.1.0 july 2016
11.3 lpddr2-s4 refresh requirements by device density table 50 lpddr2-s4 refresh requirement parameters (per density) p arameter symbol 1gb unit number of banks 8 refresh window tcase 85 t refw 32 ms required number of r 4,096 refresh commands (min) average time between refresh commands refab t refi 7.8 us (for reference only) tcase 85 refpb t refipb 0.975 us refresh cycle time t rfcab 130 us per bank refresh cycle time t rfcpb 60 us burst refresh window = 4 x 8 x t recab t refbw 4.16 us AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 111/129 - rev.1.0 july 2016
11.4 ac timings table 51 lpddr2 ac timing table parameter symbol min/ max min t ck lpddr2 unit 800 max. frequency *4 ~ 400 mhz clock timing average clock period t ck (avg) min 2.5 ns max 100 average high pulse width t ch (avg) min 0.45 t ck (avg) max 0.55 average low pulse width t cl (avg) min 0.45 max 0.55 absolute clock period t ck (abs) min t ck (avg),min + t jit (per),min ps absolute clock high pulse width t ch (abs), min 0.43 t ck (avg) (with allowed jitter) allowed max 0.57 absolute clock low pulse width t cl (abs), min 0.43 (with allowed jitter) allowed max 0.57 clock period jitter (with allowed jitter) t jit (per), min - 100 ps allowed max 100 maximum clock jitter between two consecutive clock t jit (cc), max 200 ps cycle (with allowed jitter) allowed duty cycle jitter (with allowed jitter) t jit (duty), min min((t ch (abs),min - t ch (avg),min), (t cl (abs),min - t cl (avg),min)) x t ck (avg) ps allowed max min((t ch (abs),max - t ch (avg),max), (t cl (abs),max - t cl (avg),max)) x t ck (avg) ps cumulative errors across 2cycles t err (2per), min - 147 ps allowed max 147 cumulative errors across 3cycles t err (3per), min - 175 ps allowed max 175 cumulative errors across 4cycles t err (4per), min - 194 ps allowed max 194 cumulative errors across 5cycles t err (5per), min - 209 ps allowed max 209 cumulative errors across 6cycles t err (6per), min - 222 ps allowed max 222 cumulative errors across 7cycles t err (7per), min - 232 ps allowed max 232 cumulative errors across 8cycles t err (8per), min - 241 ps allowed max 241 cumulative errors across 9cycles t err (9per), min - 249 ps allowed max 249 cumulative errors across 10cycles t err (10per), min - 257 ps AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 112/129 - rev.1.0 july 2016
allowed max 257 cumulative errors across 11cycles t err (11per), min - 263 ps allowed max 263 cumulative errors across 12cycles t err (12per), min - 269 ps allowed max 269 cumulative errors across n= 13, 14, 49, 50cycles t err (nper), min terr(nper),allowed,min = (1+0.68ln(n)) x tjit(per),allowed,min ps allowed max terr(nper),allowed,max = (1+0.68ln(n)) x tjit(per),allowed,max parameter symbol min/ max min t ck lpddr2 unit 800 zq calibration parameters initialization calibration time *1 4 t zqinit min 1 us long calibration time *1 4 t zqcl min 6 360 ns short calibration time *1 4 t zqcs min 6 90 calibration reset time *1 4 t zqreset min 3 50 read parameters *1 1 dqs output access time from ck / ck# t dqsck min 2500 ps max 5500 dqsck delta short *1 5 t dqsckds max 450 dqsck delta medium *1 6 t dqsckdm max 900 dqsck delta long * 17 t dqsckdl max 1200 dqs - dq skew t dqsq max 240 data hold skew factor t qhs max 280 dqs output high pulse width t qsh min tch(abs) - 0.05 t ck (avg) dqs output low pulse width t qsl min tcl(abs) - 0.05 data half period t qhp min min(t qsh ,t qsl ) dq/dqs output hold time from dqs t qh min t qhp - t qhs ps read preamble *1 1 ,*1 2 t rpre min 0.9 t ck (avg) read postamble *1 1 ,*1 3 t rpst min t cl(abs) - 0.05 dqs low - z from clock *1 1 t lz(dqs) min t dqsck(min) - 300 ps dq low - z from clock *1 1 t lz(dq) min t dqsck(min) - (1.4 x t qhs(max) ) dqs high - z from clock *1 1 t hz(dqs) max t dqsck(max) - 100 dq high - z from clock *1 1 t hz(dq) max t dqsck(max) +(1.4 x t dqsq(max) ) AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 113/129 - rev.1.0 july 2016
parameter symbol min/ max min t ck lpddr2 unit 800 write parameters *14 dq and dm input hold time (v ref based) t dh min 270 ps dq and dm input setup time (v ref based) t ds min 270 dq and dm input pulse width t dipw min 0.35 tck(avg) write command to first dqs latching transition t dqss min 0.75 tck(avg) max 1.25 dqs input high - level width t dqsh min 0.4 tck(avg) dqs input low - level width t dqsl min 0.4 tck(avg) dqs dalling edge to ck setup time t dss min 0.2 tck(avg) dqs dalling edge hold time from ck t dsh min 0.2 tck(avg) write postamble t wpst min 0.4 tck(avg) write preamble t wpre min 0.35 tck(avg) parameter symbol min/ max min t ck lpddr2 unit 800 cke input parameters cke min. pulse width (high and low pulse width) t cke min 3 3 tck(avg) cke input setup time t iscke *2 min 0.25 tck(avg) cke input hold time t ihcke *3 min 0.25 tck(avg) command address input parameters *14 address and control input setup time (vref based) t is *1 min 290 ps address and control input hold time (vref based) t ih *1 min 290 ps address and control input pulse width t ipw min 0.4 tck(avg) boot parameters (10mhz - 55mhz) *8,10,11 clock cycle time t ckb max - 100 ns min 18 ns cke input setup time t isckeb min - 2.5 ns cke input hold time t ihckeb min - 2.5 ps address & control input setup time t isb min - 1150 ps address & control input hold time t ihb min - 1150 ps dqs output data access time from ck / ck# t dqsckb min - 2 ns max 10.0 data strobe edge to ouput data edge t dqsqb - 1.2 t dqsqb max - 1.2 ns tdqsqb max - 1.2 ns data hold skew factor t qhsb max - 1.2 ns mode register parameters mode register write command period t mrw min 5 5 tck(avg) mode register read command period t mrr min 2 2 tck(avg) AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 114/129 - rev.1.0 july 2016
parameter symbol min/ max min t ck lpddr2 unit 800 lpddr2 sdram core parameters *12 read latency rl min 3 6 tck(avg) write latency wl min 1 3 tck(avg) active to active command period t rc min t ras +t rpab (with all - bank precharge) t ras +t rppb (with per - bank precharge) ns cke min. pulse width during self - refresh (low pulse width during self - refresh) t ckesr min 3 15 ns self refresh exit to next valid command delay t xsr min 2 t rfcab +10 ns exit power down to next valid command delay t xp min 2 7.5 ns lpddr2 - s4 cas to cas delay t ccd min 2 2 tck(avg) internal read to precharge command delay t rtp min 2 7.5 ns ras to cas delay t rcd min 3 18 ns row precharge time (single bank) t rppb min 3 1 8 ns row precharge time (all banks) t rppb 4 - bank min 3 1 8 ns row precharge time (all banks) t rppb 8 - bank min 3 21 ns row active time t ras min 3 42 ns max - 70 ns write recovery time t wr min 3 15 ns internal write to read command delay t wtr min 2 7.5 ns active bank a to active bank b t rrd min 2 10 ns four bank activate window t faw min 8 50 ns minimum deep power down time t dpd min 500 us AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 115/129 - rev.1.0 july 2016
parameter symbol min/ max min t ck lpddr2 unit 800 lpddr2 temperature de - rating tdqsck de - rating t dqsck (derated) max 6000 ps core timings temperature de - rating for sdram t rcd (derated) min t rcd + 1.875 ns t rc (derated) min t rc + 1.875 ns t ras (derated) min t ras + 1.875 ns t rp (derated) min t rp + 1.875 ns t rrd (derated) min t rrd + 1.875 ns note 1 input set-up/hold time for signal(ca0 ~ 9, cs#) note 2 cke input setup time is measured from cke reaching high/low voltage level to ck/ck# crossing. note 3 cke input hold time is measured from ck/ck# crossing to cke reaching high/low voltage level . note 4 frequency values are for reference only. clock cycle time (tck) shall be used to determine device capabilities. note 5 to guarantee device operation before the lpddr2 device is configured a number of ac boot timing parameters are defined in the table 51 . boot parameter symbols have the letter b appended, e.g., tck during boot is t ck b . note 6 frequency values are for reference only. clock cycle time (tck or tckb) shall be used to determine device capabilities. note 7 the sdram will set some mode register default values upon receiving a reset (mrw) command as specified in 3. 3 . note 8 the output skew parameters are measured with ron default settings into the reference load. note 9 the min tck column applies only when tck is greater than 6ns for lpddr2-sx. in this case, both min tck values and analog timings (ns) shall be satisfied. note 10 all ac timings assume an input slew rate of 1v/ns. note 11 read, write, and input setup and hold values are referenced to vref. figure 1 1.1 hsul_12 driver output reference load for timing and slew rate the parameters tlz(dqs), tlz(dq), thz(dqs), and thz(dq) are defined as single-ended. the timing parameters trpre and trpst are determined from the differential signal dqs-dqs#. note 12 for low- to -high and high- to -low transitions, the timing reference will be at the point when the signal crosses vtt. thz and tl z transitions occur in the same access time (with respect to clock) as valid data transitions. these parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for trpst, thz(dqs) and thz(dq) ), or begins driving (for trpre, tlz(dqs), tlz(dq) ). figure 11.1 shows a method to calculate the point when device is no longer driving thz(dqs) and thz(dq), or begins driving tlz(dqs), tlz(dq) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. note 13 measured from the start driving of dqs - dqs# to the start driving the first rising strobe edge. note 14 measured from the from start driving the last falling strobe edge to the stop driving dqs - dqs#. note 15 tdqsckds is the absolute value of the difference between any two tdqsck measurements (within a byte lane) within a contiguous sequence of bursts within a 160ns rolling window. tdqsckds is not tested and is guaranteed by design. temperature drift in the system is < 10c/s. values do not include clock jitter. note 16 tdqsckdm is the absolute value of the difference between any two tdqsck measurements (within a byte lane) within a 1.6us rolling window. tdqsckdm is not tested and is guaranteed by design. temperature drift in the system is < 10c/s. values do not include clock jitter. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 116/129 - rev.1.0 july 2016
note 17 tdqsckdl is the absolute value of the difference between any two tdqsck measurements (within a byte lane) within a 32ms rolling window. tdqsckdl is not tested and is guaranteed by design. temperature drift in the system is < 10c/s. values do not include clock jitter. note 18 tfaw is only applied in devices with 8 banks. 11.5 ca and cs# setup, hold and derating for all input signals (ca and cs#) the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base) and tih(base) value (see table 52 ) to the tis and tih derating value (see table 53 ) respectively. example: tis (total setup time) = tis(base) + tis. setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate fo r derating value (see figure figure 11 .2 ). if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see figure 1 1.4 ). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rat e between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc to vref(dc) region, use nominal slew rate for derating value (see figure 1 1.3 ). if the ac tual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value (see figure 1 1.5 ). for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac (see table 53 ). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in table 53 , the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization table 52 ca and cs# setup and hold base-values for 1v/ns unit [ps] lpddr2 reference 800 tis(base) 70 v ih/l(ac) = vref(dc) +/ - 220mv tih(base) 160 v ih/l(ac) = vref(dc) +/ - 130mv note 1 ac/dc referenced for 1v/ns ca and cs# slew rate and 2v/ns differential ck-ck# slew rate. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 117/129 - rev.1.0 july 2016
table 53 derating values lpddr2 tis/tih - ac/dc based ac220 tis ih derating in [ps] ac/dc based ac220 threshold - > vih(ac)=vref(dc)+220mv, vil(ac)=vref(dc) - 220mv dc130 threshold - > vih(dc)=vref(dc)+130mv, vil(dc)=vref(dc) - 130mv ck , ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih ca, cs# slew rate v/ns 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - - 3 - 5 - 3 - 5 13 11 29 27 45 43 - - - - 0.8 - - - - - 8 - 13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 - 6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 - 3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 - 4 20 16 36 48 0.4 - - - - - - - - - - - - - 7 2 17 34 note 1 cell contents shaded in red are defined as not supported. table 55 required time t vac above vih(ac) {below vil(ac)} for valid transition slew rate [v/ns] t vac @ 220mv [ps] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 - < 0.5 150 - AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 118/129 - rev.1.0 july 2016
figure 11.2 illustration of nominal slew rate and t vac for setup time t is for ca and cs# with respect to clock. AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 119/129 - rev.1.0 july 2016
figure 1 1.3 illustration of nominal slew rate for hold time t ih for ca and cs# with respect to clock AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 120/129 - rev.1.0 july 2016
figure 1 1.4 illustration of tangent line for setup time t is for ca and cs # with respect to clock AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 121/129 - rev.1.0 july 2016
figure 1 1.5 illustration of tangent line for for hold time t ih for ca and cs # with respect to clock AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 122/129 - rev.1.0 july 2016
11.6 data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 55 ) to the tds and tdh (see table 56 ) derating value respectively. example: tds (total setup time) = tds(base) + tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max(see figure 11.6) . if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see figure 11.8 ). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc) (see figure 1 1.7 ). if the actual signal is always later than the nominal sl ew rate line between shaded dc level to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the act ual signal from the dc level to vref(dc) level is used for derating value (see figure 1 1.9 ). for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac (see table 57 ). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. table 56 data setup and hold base-values unit [ps] lpddr2 reference 800 tds(base) 50 v ih/l(ac) = vref(dc) +/- 220mv tdh(base) 140 v ih/l(ac) = vref(dc) +/- 130mv note 1 ac/dc referenced for 1v/ns dq, dm slew rate and 2v/ns differential dqs-dqs# slew rate. ! ! ! ! AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 123/129 - rev.1.0 july 2016
table 57 derating values lpddr2 tds/tdh - ac/dc based ac220 tds, dh derating in [ps] ac/dc based ac220 threshold - > vih(ac)=vref(dc)+220mv, vil(ac)=vref(dc) - 220mv dc130 threshold - > vih(dc)=vref(dc)+130mv, vil(dc)=vref(dc) - 130mv dqs , dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq,dm slew rate v/ns 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - - 0.8 - - - - -8 - 13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 -3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 -4 20 16 36 48 0.4 - - - - - - - - - - - - -7 2 17 34 note 1 cell contents shaded in red are defined as not supported. table 59 required time t vac above vih(ac) {below vil(ac)} for valid transition slew rate [v/ns] t vac @ 220mv [ps] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 - < 0.5 150 - AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 124/129 - rev.1.0 july 2016
figure 1 1.6 illustration of nominal slew rate and t vac for setup time t ds for dq with respect to strobe AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 125/129 - rev.1.0 july 2016
figure 1 1.7 illustration of nominal slew rate for hold time t dh for dq with respect to strobe AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 126/129 - rev.1.0 july 2016
figure 1 1.8 illustration of tangent line for setup time t ds for dq with respect to strobe AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 127/129 - rev.1.0 july 2016
figure 1 1.9 illustration of tangent line for for hold time t dh for dq with respect to strobe AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 128/129 - rev.1.0 july 2016
part numbering system as4c 64m16m d2 25 b c n dram 64m16=64mx16 md2=mobile ddr2 25=400mhz b = fbga c=commerial (-30 c~+85 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-610-6800 fax: 650-620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. as4c 32m32m d2 25 b c n dram 32m32= 32mx32 m d2=mobile ddr2 25=400mhz b = fbga c = commerial (-3 0 c~+85 c) indicates pb and halogen free AS4C64M16MD2-25BCN as4c32m32md2-25bcn confidential - 129/129 - rev.1.0 july 2016

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