? semiconductor components industries, llc, 2016 october, 2016 ? rev. 0 1 publication order number: niv2161/d niv2161, nis2161 esd protection with automotive short-to- battery/ground protection low capacitance esd protection w/ short? to?battery and short?to?ground protection for automotive high speed data lines the nis/niv2161 is designed to protect high speed data lines from esd as well as short to vehicle battery situations. the ultra?low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines while the low r ds(on) fet limits distortion on the signal lines. the flow?through style package allows for easy pcb layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as usb and lvds protocols. features ? low capacitance (0.40 pf typical, i/o to gnd) ? protection for the following standards: iec 61000?4?2 (level 4) & iso 10605 ? integrated mosfets for short?to?battery and short?to?ground protection ? niv prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? automotive high speed signal pairs ? usb 2.0/3.0 ? lvds ? apix 2/3 absolute maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j(max) ?55 to +150 c storage temperature range tstg ?55 to +150 c drain?to?source v oltage v dss 30 v gate?to?source v oltage v gs 10 v lead temperature soldering t sld 260 c iec 61000?4?2 contact (esd) iec 61000?4?2 air (esd) esd esd 8 15 kv kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. wdfn10 case 511ca marking diagram www. onsemi.com pin configuration and schematics v2 = specific device code m = date code = pb?free package v2 m (note: microdot may be in either location) 123 5 4 (top view) 10 9 8 6 7 device package shipping ? ordering information niv2161mttag wdfn10 (pb?free) 3000 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. NIS2161MTTAG wdfn10 (pb?free) 3000 / tape & ree l pin 1 and pin 10 ? source 1 pin 5 and pin 6 ? source 2 pin 3 ? 5v pin 3 ? 5v pin 3 ? 5v pin 3 ? 5v pin 8 ? gnd pin 7 ? d ? pin 9 ? d + pin 2 ? d+ host pin 4 ? d?host
niv2161, nis2161 www. onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 5 16 v breakdown v oltage v br i t = 1 ma, i/o pin to gnd 16.5 v reverse leakage current i r v rwm = 5 v, i/o pin to gnd 1.0 a clamping v oltage v c i pp = 1 a, i/o pin to gnd (8/20 s pulse) 29 v clamping voltage (note 1) v c iec61000?4?2, 8 kv contact see figure 1 clamping voltage tlp (note 2) see figures 4 & 5 v c i pp = 8 a i pp = 16 a 39 66 v v junction capacitance match c j v r = 0 v, f = 1 mhz between i/o 1 to gnd and i/o 2 to gnd 1.0 % junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd (pin 7 to gnd, pin 9 to gnd) 0.40 pf drain?to?source breakdown v oltage v br(dss) v gs = 0 v, i d = 100 a 30 v drain?to?source breakdown v oltage temperature coef ficient v br(dss) / t j reference to 25 c, i d = 100 a 27 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 30 v 1.0 a gate?to?source leakage current i gss v ds = 0 v, v gs = 5 v 1.0 a gate threshold voltage (note 3) v gs(th) v ds = v gs , i d = 100 a 0.1 1.0 1.5 v gate threshold voltage t emperature coefficient v gs(th) / t j reference to 25 c, i d = 100 a ?2.5 mv/ c drain?to?source on resistance r ds(on) v gs = 4.5 v, i d = 125 ma 1.4 7.0 v gs = 2.5 v, i d = 125 ma 2.3 7.5 forward t ransconductance g fs v ds = 3.0 v, i d = 125 ma 80 ms switching turn?on delay time (note 4) t d(on) v gs = 4.5 v, v ds = 24 v i d = 125 ma, r g = 10 v 9 ns switching turn?on rise time (note 4) t r 41 ns switching turn?of f delay time (note 4) t d(off) 96 ns switching turn?of f fall time (note 4) t f 72 ns drain?to?source forward diode v oltage v sd v gs = 0 v, i s = 125 ma 0.79 0.9 v 3 db bandwidth f bw r l = 50 5 ghz product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. for test procedure see figures 3 and 4 and application note and8307/d. 2. ansi/esd stm5.5.1 electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. 3. pulse test: pulse width 300 s, duty cycle 2% 4. switching characteristics are independent of operating junction temperatures.
niv2161, nis2161 www. onsemi.com 3 figure 1. iec61000?4?2 8kv contact esd clamping voltage iec61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 2. iec61000?4?2 spec figure 3. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8307/d ? characterization of esd clamping performance. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
niv2161, nis2161 www. onsemi.com 4 figure 4. positive tlp i?v curve figure 5. negative tlp i?v curve note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. v iec is the equivalent voltage stress level calculated at the secondary peak of the iec 61000?4?2 waveform at t = 30 ns with 2 a/kv. see tlp description below for more information. transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 6. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 7 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. for more information on tlp measurements and how to interpret them please refer to and9007/d. figure 6. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 7. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms
niv2161, nis2161 www. onsemi.com 5 typical mosfet performance curves t j = 150 c 0 0.9 4.0 0.5 v ds , drain?to?source voltage (v) i d, drain current (a) 0.7 0.2 0 figure 8. on?region characteristics 0 2.0 4.0 figure 9. transfer characteristics v gs , gate?t o?source voltage (v) 1.0 8.0 figure 10. on?resistance vs. gate?to?source voltage v gs, gate voltage (v) r ds(on), drain?to?source resist ance ( ) i d, drain current (a) figure 11. on?resistance vs. drain current and gate voltage ?50 0 ?25 25 1.2 0.7 0.6 50 150 figure 12. on?resistance variation with temperature t j , junction temperature ( c) 2.0 t j = ?55 c 75 i d = 125 ma v gs = 4.5 v r ds(on), drain?to?source resistance (normalized) t j = 25 c r ds(on), drain?to?source resist ance ( ) 1.3 v gs = 2.5 v v gs = 4.5 v 1.5 3.5 0.1 25 figure 13. drain?to?source leakage current vs. voltage v ds , drain?to?source vol tage (v) 15 i dss , leakage (na) t j = 150 c t j = 125 c 10 100 v ds = 5 v 20 2.0 v 0.5 1.8 v 3.0 3 0 1.2 1.0 v gs = 10 v 10 125 100 0 5.0 10 5 3.0 1.5 1.5 5.0 4.5 t j = 25 c i d = 125 ma i d, drain current (a) 1.9 1000 2.4 v 3.5 1.0 1.0 8.0 0.1 0 0.7 0.5 10 4.0 1. 2 0.8 1.4 0.9 1.6 1.1 1.8 0.8 0.6 0.1 0.3 0.9 0.6 0.1 0 0.4 1.2 0.5 3.0 0.4 1.1 1.0 2.0 2.5 3.5 4.5 2.2 v 2.8 v 2.6 v 3.0 v 3.5 v 4.0 v 5.0 v 4.5 v 2.5 4. 5 0.2 0.3 0.5 0.7 0.8 1.0 1.1 2.5 4.0 2.0 3.0 4.0 6.0 7.0 9.0 0.2 0.3 0.4 0.6 0.8 0.9 1.0 1.1 2.0 3.0 5.0 6.0 7.0 9.0 t j = 125 c t j = ?55 c t j = 25 c t j = 125 c t j = 25 c t j = ?55 c 1.0 1.5 1.7 t j = 85 c 1
niv2161, nis2161 www. onsemi.com 6 application information today?s connected cars are using multiple high speed signal pair interfaces for various applications such as infotainment, connectivity and adas. the electrical hazards likely to be encountered in these automotive high speed signal interfaces include damaging esd and transient events which occur during manufacturing and assembly, by vehicle occupants or other electrical circuits in the vehicle. the major documents discussing esd and transient events as far as road vehicles are concerned are iso 10605 (road vehicles ? test methods for electrical disturbances from electrostatic discharge) which describes esd test methods and iso 7637 (road vehicles ? electrical disturbances from conduction and coupling) for effects caused by other electronics in the vehicle. is0 10605 is based on iec 61000?4?2 industry standard, which specifies the various levels of esd signal characteristics, but also includes additional vehicle?specific requirements. further, oem specific test requirements are usually also imposed. in addition, these high speed signal pairs require protection from short?to?battery (which goes up to 16 vdc) and short?to?ground faults. a suitable protection solution must satisfy well known constraints, such as low capacitive loading of the signal lines to minimize signal attenuation, and also respond quickly to sur ges and transients with low clamping voltage. in addition, small package sizes help to minimize demand for board?space while providing the ability to route the trace signals with minimal bending to maintain signal integrity. the niv2161 provides a solution to these high speed signal interface protections from esd as well as short?to?battery and short?to?ground situations. the esd?protection is designed to meet the iec61000?4?2 level 4 with a low i/o?to?ground capacitance of 0.65 pf typical. capacitances are closely matched to preserve signal integrity. low dynamic resistance allows very low clamping voltages, and the breakdown voltage of 16.5 v allows the device to survive a short?to?battery condition, which ranges from 9 v to 16 v. the series fets are designed with very low on?state resistance (r ds(on) ), and feature an internal layout that allows flow?through design to maintain high?speed signal integrity. the threshold voltage of 1.0 v allows operation at low gate?drive voltages consistent with usb, lvds and other low level signals. 5v 5v niv2161 d+ d? usb transceiver * *r s optional * pcb layout guidelines it is not necessary to route both pins 1?10 (and 5?6) together with a top metal trace as both source 1 and both source 2 pins are internally connected respectively. also, steps must be taken for proper placement and signal trace routing of the esd protection device in order to ensure the maximum esd survivability and signal integrity for the application. such steps are listed below. ? place the esd protection device as close as possible to the i/o connector to reduce the esd path to ground and improve the protection performance. ? make sure to use differential design methodology and impedance matching of all high speed signal traces. ? use curved traces when possible to avoid unwanted reflections. ? keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ? place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk.
niv2161, nis2161 www. onsemi.com 7 modes of operation there are three distinct modes of operation of the niv2161: normal (steady state), short?to?battery event, and short?to?ground event. the below describes each of these in more detail. normal operation (steady state) in normal operation, the mosfets operate in linear mode, with all source and drain voltages nearly equal, passing the signal levels effectively from the usb transceiver. to ensure successful link communication, the applied gate voltage must be greater than the maximum signal level from the data line plus the maximum threshold voltage of the mosfet device. due to the niv2161?s low threshold voltage of 1.5 v, both 3.3 and 5 v gate drives are suitable to provide headroom for most communication protocols. an optional addition to the application may be a pull?up resistor from the mosfet sources to the gate. when properly specified for the application (generally > 15 k is appropriate), the resistor will be transparent in normal operation and will not impede link communication. while the gate is de?powered and the link is inactive, this pull?up resistor (regardless of value) discharges the gate and completely isolates the data link from the line drivers, preventing any stimulus from damaging the data line drivers at this point. depending on link speed and signal levels, too low of a resistor value (generally 5 k or less) produces a stronger pull?up effect that can distort the link, and must be considered in the design process. short?to?battery (stb) event while the niv2161 and data channel are off, one pair of mosfet body diodes passively protects the usb transceiver ?s ports. while the data channel is on during a stb event, the niv2161 actively uses the internal mosfets to clamp in a manner akin to level?shifting as the mosfet operates in the saturation region. the source node will increase to a threshold voltage minus a very small working voltage below the gate potential thus allowing current to flow into the data port, limited by the port impedance. in this way, the niv2161 protects the data port by both limiting the termination current as well as voltage clamping the data port itself. short?to?ground (stg) event during an active stg event, niv2161 protection function is achieved by the shared?source mosfet configuration as well as passively using the bidirectional esd diode configuration. during this event, the data line output is shorted to the battery ground or the local ground for the signal controller (and any onboard power regulator) is disconnected from the battery ground. the niv2161?s bidirectional esd diodes block any reverse current path to the data line output by a reverse?connected esd diode, while not compromising esd protection functionality. during a passive stg event, the internal regulator?s current sources (of the usb transceiver or any onboard discrete component) are generally weak enough that there is no danger of power?related damage to the terminations.
niv2161, nis2161 www. onsemi.com 8 package dimensions wdfn10 3.5x2, 0.675p case 511ca issue a ???? ???? ???? dim min max millimeters a a1 0.00 0.05 a3 b 0.35 0.45 d 3.50 bsc e 2.00 bsc e 0.675 bsc notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters . 3. dimensions b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 0.20 ref b l pin 1 1 6 5 d e b a c 0.10 c 0.10 2x 2x 10 e 8x 6x note 3 a 13x c a1 (a3) seating plane c 0.05 c 0.05 0.70 0.80 l 0.75 0.85 reference top view side view bottom view 0.33 1.03 2.30 0.675 dimensions: millimeters mounting footprint 3x 1 recommended detail a b a c c m 0.10 m 0.05 l4 l1 --- 0.15 detail b 10x 0.61 package outline l1 detail a l alternate terminal construction ??? ?? b1 0.20 0.30 l4 0.15 ref b1 4x note 3 b a c c m 0.10 m 0.05 0.48 6x pitch l2 1.15 1.25 l3 0.45 0.55 l2 l3 1.40 0.70 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates , and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or dea th associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semicon ductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 niv2161/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative ?
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