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simplifying system integration tm 73s802 4c demo board user manual november 11 , 2009 rev. 1. 3 um_ 802 4 c_0 61 downloaded from: http:///
73s8024c demo board user manual um_8024c_061 2 rev. 1.3 ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corpor ation. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, ot her than expressly contained in the companys warranty detailed in the teridian semiconductor corp oration standard terms and conditions. the company assumes no responsibility for any errors which may appear in th is document, reserves the right to change devices or specifications detailed herein at any ti me without notice and does not make any commitment to update the information contained herein. accord ingly, the reader is cautioned to verify that this document is current by comparing it to th e latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridia n.com downloaded from: http:///
u m_8024c_061 73s8024c demo board user manual rev. 1.3 3 table of contents 1 introduction ................................................................................................................................... 5 1.1 package contents .................................................................................................................... 5 1.2 s afety and esd notes ............................................................................................................. 5 2 basic connections ........................................................................................................................ 6 3 hardware description .................................................................................................................... 7 3.1 demo board connectors, jumpers and test points ................................................................ . 7 3.2 recommended operating conditions and absolute maximum ratings ..................................... 9 3. 3 73s8024c pin description ....................................................................................................... 9 3.4 73s8024c pinout .................................................................................................................. 11 4 design considerations ................................................................................................................ 12 4.1 general layout rules ............................................................................................................ 12 4.2 optimization for compliance with emv and nds .................................................................... 12 5 73s8024c demo board schematics, pcb layouts and bill of materials .................................. 13 5.1 sch ematic .............................................................................................................................. 13 5.2 bill of materials ...................................................................................................................... 14 5.3 pcb layouts .......................................................................................................................... 15 6 ordering information ................................................................................................................... 18 7 related documentation ............................................................................................................... 18 8 contact information ..................................................................................................................... 18 revision history .................................................................................................................................. 19 downloaded from: http:///
73s8024c demo board user manual um_8024c_061 4 rev. 1.3 figure s figure 1: 73s8024c de mo board ............................................................................................................ 5 figure 2: 73s8024c demo board basic connections .............................................................................. 6 figure 3: 73s8024c demo board connectors, jumpers and test points ................................................. 8 figure 4: 73s8024c so28 pinout (top view) ........................................................................................ 11 figure 5: 73s8024c demo board electrical schematic .......................................................................... 13 figure 6: 73s8024c demo board top view ........................................................................................... 15 figure 7: 73s8024c demo board bottom view ...................................................................................... 15 figur e 8: 73s8024c demo board top signal layer ............................................................................... 16 figure 9: 73s8024c demo board middle layer 1, ground plane ........................................................... 16 figure 10: 73s8024c middle layer 2, supply plane .............................................................................. 17 figure 11: 73s8024c demo board bottom signal layer ........................................................................ 17 table s table 1: 73s8024c demo board connector, jumper and test points ...................................................... 7 table 2: recommended operating conditions ......................................................................................... 9 table 3: absolute maximum ra tings ........................................................................................................ 9 table 4: 73s8024c card interface pins ................................................................................................... 9 table 5: 73s8024c miscellaneous pins ................................................................................................ . 10 table 6: 73s8024c power and ground pins .......................................................................................... 10 table 7: 72s8024c microcontroller interface pins .................................................................................. 10 table 8: 73s8024c demo board bill of materials ................................................................................... 14 table 9: order numbers and packaging marks ...................................................................................... 18 downloaded from: http:///
u m_8024c_061 73s8024c demo board user manual rev. 1.3 5 1 introduction the 73s802 4 c demo board is a platform for evaluating the t eridian 73s802 4 c s mart c ard i nterface device . the board incorporates the 73s802 4 c integrated circuit and has been designed to operate either as a standalone platform (to be used in conjunction with an external microcontroller) or as a daughter card to be used in conjunction with the 73s1121f evaluation platform. the board has been designed to comply with the emv 2000 s pecification , version 4.0 . 73s802 4 c demo boards can easily be modified to comply with nds specifications by replacing a few external compo nents that are highlighted in this document. figure 1 : 73s8024c demo board 1.1 package contents th e 73 s 8024c demo board k it includes: ? a 73s8024c demo b oard ? the following documents on cd : ? 73s8024c data sheet ? 73s8024c demo board u ser manual (this document) ? application note 1.2 safety and esd notes extreme caution should be taken when handling the 73s8024 c demo board after connection to live voltages! the 73 s 8024c demo board is esd sensitive! esd precautions should be taken when h andling this board ! downloaded from: http:///
73s8024c demo board user manual um_8024c_061 6 rev. 1.3 2 basic connections the basic connections to the demo board are described below and shown in figure 2. 1. connect p ower s upply: apply 3.3 v to pin 10 of j4. 2. control signals to the device can be connected through j 2 and j4 (see figure 2 and the e lectrical s ch ematic , figure 5 ). 3. to set the clock frequency with an external clock source : ? set jp1 to the sclk setting . ? apply clock source to pin 1 of j2 . ? ap ply 3.3v (1) or gnd (0) to clkdiv1 and clkdiv2 pins to set the desired clock rate as follows : ? clkdiv1 = clkdiv2 = 0 clock frequency = sclk/8 ? clkdiv1 = 0, clkdiv2 =1 clock frequency = sclk/4 ? clkdiv1 = 1, clkdiv2 =0 c lock frequency = sclk ? clkdiv1 = clkdiv 2 = 1 clock frequency = sclk/2 4. to set the clock frequency using crystal y1 : ? the c rystal included on the demo board is 12 mhz . ? set jp1 to xtal position . ? apply 3.3v (1) or gnd (0) to clkdiv1 and clkdiv2 pins to set the desired clock rate as follows: ? clkd iv1 = clkdiv2 = 0 clock frequency = 1.5 mhz ? clkdiv1 = 0, clkdiv2 =1 clock frequency = 3 mhz ? clkdiv1 = 1, clkdiv2 =0 clock frequency = 12 mhz ? clkdiv1 = clkdiv2 = 1 clock frequency = 6 mhz figure 2 : 73s 8024c demo board basic co nnections 1 2 ckdiv2 ckdiv1 rstin cmdvcc gnd vdd pwrdn5v/ # v gnd sclk off i/ouc aux1ucaux2uc external clock source. jp1 must be in position sclk when using an external clock. otherwise, pin sclk can be left open. v pc power supply: configure jp2 to 3.3v v dd power supply: +2.7v to +3.6v (3.3v typ.) / 50ma note: clkstop and clklev can be left nc if unused. 5v/ # v too, for 5v cards only. downloaded from: http:///
u m_8024c_061 73s8024c demo board user manual rev. 1.3 7 3 hardware description 3.1 demo board connectors, jumpers and test points table 1 describes the 73s 8024c demo board connectors, jumpers and test points. the item # in t able 1 refer s to figure 3. table 1 : 73s8024c demo board connector, jumper and test points item # schematic/ silkscreen reference name function connectors : 1 j2 5v board supply / auxiliary i nterface 73s8024c auxiliary interface (i/ouc, aux1uc, aux2uc), external clock (sclk) and interrupt ( off ) pins. the external clock (sclk) can be left open when jp1 is in position xtal. the 5v power supply is unused and must be left open and jp2 must be inserted in po sition 3.3v. 9 j4 3.3v board power / digital control signals 3.3v board power supply and the 73s 8024c host control signals rstin, cmdvcc , 5v/ #v , pwrdw n, clkdiv2 and clkdiv1. 16 j5 smart card connector smart card connector. when inserting a card (credit card size format), contacts must face up. 11 j6 smart card connector sim/sam smart card format connector. j6 is wired in parallel to the smart card connector j5 (underneath the pcb). no sim/sam should be inserted when using the credit - card size connecto r j5. jumpers: 3 jp1 clock selection jumper to select between a crystal or an external clock as the frequency reference to the device. the default setting is for a crystal. 17 jp2 vpc select jumper to select the value of the power supply for the smart card dc - dc converter (73s 8024c input vpc). to support both card voltages, jp2 must be set to position 3.3v. the default setting is 3.3v. 2 jp3 vdd select jumpe r to select the digital voltage which supplies the 73s8024c . must be set for 3.3v. 8 jp4 C not used. 15 14 jp5 jp6 card polarity detect select the setting of jp5 and jp6 depends on the type of smart card connector used (nominally open or closed) and which 73s8024c card presence switch input is used. the switch is nominally open for the 73s 802 4c demo board. the jumpers can be set to: 1. use of pres (default): jp5 set to pres; jp6 set to vdd. 2. use of pres : jp5 set to preb; jp6 set to gnd. downloaded from: http:///
73s8024c demo board user manual um_8024c_061 8 rev. 1.3 item # schematic/ silkscreen reference name function test points: 10 tp1 pin 17 (vddf_adj) vdd voltage fault adjustment. the pin to the left is connected to the vddf_adj pin of the 73s 8024c and the pin to the right is gnd. when either a resistor r3, or a resistor network r1 and r3 is populated on the board, it adjusts the vdd fault level that internally triggers a card deactivation sequence. by default, the resistors r1 and r3 are not connected. this provides a vdd fault level of 2.3v typical (internally set to the 73s 8024c ). refer to the 73s 8024c data s heet for further information about vdd fault level and determination of the resistor values. 20 tp2 factory test factory test pin. do not connect. 7 12 6 13 5 4 tp 3 tp 4 tp 5 tp 6 tp7 tp8 vcc i/o rst c8 clk c4 2- pin test points for each respective smart card signal. the pin label name is the respective signal (i.e. vcc, clk) and the 2nd pin is gnd. figure 3 : 73s 8024c demo board connectors, jumpers and test points downloaded from: http:///
u m_8024c_061 73s8024c demo board user manual rev. 1.3 9 3.2 recommended operating conditions and absolute maximum ratings table 2 lists the recommended operating conditions and table 3 lists the absolute maximum ratings. operation outside these rating limits may cause permanent damage to the device. table 2 : recommended operating conditions parameter rating supply voltage v dd 2.7 to 3.6 vdc supply voltage v pc 2.7 to 3.6 vdc ambient operating temperature - 40 c to +85 c input voltage for digital inputs 0 v to v dd + 0.3 v table 3 : absolute maximum ratings parameter rating supply voltage v dd - 0.5 to 4.0 vdc supply voltage v pc - 0.5 to 4.0 vdc input voltage for digital inputs - 0.3 to (vdd+0.5) vdc storage temperature - 60 c to 150 c pin voltage - 0.3 to (vdd+0.5) vdc pin current 100 ma esd tolerance C card interface pins +/ - 6 kv esd tolerance C other pins +/ - 2 kv esd testing on card pins is hbm condition, 3 pulses, each polarity referenced to gr ound. 3.3 73s8024c pin description table 4 : 73s 8024c card interface pins name pin # description i/o 11 card i/o: data signal to/from card. includes a pull - up resistor to v cc. aux1 13 aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 12 aux2: auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 14 card reset: provides reset (rst) signal to card. clk 15 card clock: provides clock signal (clk) to card. the rate of this clock is determined by crystal oscillator frequency or external clock input and clkdiv selections. pres 10 card presence switch: active high indicates ca rd is present. should be tie d to gnd when not used, but it includes a high - impedance pull - down resistor. pres 9 card presence switch: active low indicates card is present. should be tied to v dd when not used, but it i ncludes a high - impedance pull - up res istor. vcc 17 card power supply: lo gically controlled by sequencer output of ldo regulator. requires an external filter capacitor to the card gnd. gnd 14 card ground . downloaded from: http:///
73s8024c demo board user manual um_8024c_061 10 rev. 1.3 table 5 : 73s 8024c miscellaneous pins name pin # description xtalin 24 crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. xtalout 25 crystal oscillator output: connected to crystal. left open if xtalin is being used as external clock input. vddf_adj 18 v dd faul t threshold adjustment input: this pin can be used to adjust the v ddf values (controls deactivation of the card) . must be left open if unused. nc 5,7 non - connected pin. table 6 : 73s 8024c power and ground pins name pin # descript ion vdd 21 system interface supply voltage and supply voltage for internal circuitry. vpc 6 dc - dc converter power supply source. gnd 4 dc - dc converter ground. gnd 22 digital ground. lin 5 external inductor. connect external inductor from pin 2 to vpc. keep the inductor close to pin 2. table 7 : 72s 8024c microcontroller interface pins name pin # description cmdvcc 19 command vcc (negative assertion): logic low on this pin causes the ldo regulator to ramp the v cc supply to th e card and initiates a card activation sequence, if a card is present. 5v/ #v 3 5 volt / 3 volt card selection: logic one selects 5 volts for v cc and card interface, logic low selects 3 volt operation. when the part is to be used with a single card voltage, this pin should be tied to either gnd or v dd . however, it includes a high impedance pull - up resistor to default this pin high (selection of 5v card) when not connected. pwrdn 8 power down control input. active h igh. when the power down mode is set h igh, all internal analog functions are disabled to place the 73s 8024c in its lowest power consumption mode. the power down mode is only allowed out of a card session (i.e. when cmdvcc = 1) clkdiv1 clkdiv2 1 2 sets the divide ratio from the xtal oscillat or (or external clock input) to the card clock. these pins include pull - down resistors. clkdiv1 clkdiv2 clock rate 0 0 xtalin/8 0 1 xtalin/4 1 1 xtalin/2 1 0 xtalin off 23 interrupt signal to the processor. active l ow - m ulti - function indicating fault conditions and/or card presence. open drain output configuration; includes an internal 22 k pull - up to v dd. rstin 20 reset input: this signal is the reset command to the card. i/ouc 26 system controller data i/o to/from the card. includes a pul l- up resistor to v dd. aux1uc 27 system controller auxiliary data i/o to/from the card. includes a pull - up resistor to v dd. aux2uc 28 system controller auxiliary data i/o to/from the card. includes a pull - up resistor to v dd. downloaded from: http:///
u m_8024c_061 73s8024c demo board user manual rev. 1.3 11 3.4 73s8024c pinout clkdiv 1 clkdiv 2 5v/ # v gnd vpc pr es pres i/o aux 2 aux 1 gnd aux 2 uc aux 1 uc i/ ouc xtalin xtalout o ff vdd rstin c m d vc c vcc rst clk nc lin pwrdn vddf _ adj gnd 73 s 8024 c 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 19 20 28 27 26 25 24 23 22 21 figure 4 : 73s 8024c so28 pinout (top view) downloaded from: http:///
73s8024c demo board user manual um_8024c_061 12 rev. 1.3 4 design considerations 4.1 general layout rules ? route the auxiliary signals away from card interface signals . ? keep the clk signal as short as possible and with few bends in the trace. keep the route of the clk trace to one layer (avoid vias to other plane). keep the clk trace away from other traces , especially rst and vcc. filtering of the clk trace is allowed for noise purpose. up to 30 pf to ground is allowed at the clk pin of the smart card connector. in addition, the zero ohm series resistor, r7, can be replaced for additional filtering (no more than 100 ). ? keep the vcc trace as short as possible. make the trace a minimum of 0.5 mm thick. in addition, keep the vcc away from other traces , especially rst and clk. ? keep the trace from l1 to pin 5 of the ic as short as possible. ? keep the rst trace away from the vcc and clk traces. up to 30 pf to ground is allowed for filtering . ? keep the 0.1 f capacitor close to the vdd pin of the device and directly take the other end to ground . ? keep the 0.1 f capacitor close to the vpc pin of the device and directly take the other end to ground . ? keep the 3.3 f (1.0 f for nds) capacitor close to the vcc pin of the smart card connector and directly take other end to ground . 4.2 optimization for compliance with emv and nds the default configuration of the d emo board contains a 27 pf capacitor (c12) from the clk pin of the smart connector to ground and a 27 pf capacitor (c13) from the rst pin of the smart connector to ground. these capacitors serve as filters for the clk and rst signals in the case of long traces or test equip ment perturbations. the capacitor on clk reduces ringing on the trace, reduces coupling t o other traces and slows down the edge of the clk signal. the capacitor on rst helps the perturbation specification in a noisy environment. the filter capacitors ca n be useful in the emv test environment and have no effect on nds testing . c12 and c13 are represented on both the schematic and the bom. these capacitors are optional filter capacitors on the smart card lines clk and rst, respectively for each card inte rface. these cap acitors may be adjusted (value not to exceed 30 pf) or removed to optimize performance in each specific application (pcb, card clock frequency, compliance with applicable standards etc). the default vcc capacitor of 3.3 f is required to meet the dynamic vcc (smart card supply) transient current requirement as specified in the emv2000 version 4.0 specification. for compliance with nds, a smaller capacitor of 1 f is required to meet the activation discharge time specification. downloaded from: http:///
um_8024c_061 73s8024c demo board user manual rev. 1.3 13 5 73 s 8024c d emo board schematic s, pcb layouts and bill of materials 5.1 schematic usr3 clk gnd jp6 12 3 pgnd 5v c4 22pf j4 tsm_110_01_l_sv 12 3 4 5 6 7 8 9 10 sc4 3.3v r8ru tp6 12 vdd usr5 c4 vpc r10 ru resistors not populated + c10 10uf 3.3v gnd c11 0.1uf connectors are positioned to allow multiple 8024c boards (stacking) to a 73s1121f evaluation board. also used for connecting external signals when used as a stand alone board. jp4 header lock 3 12 3 clkdiv1 gnd usr2 + c1 10uf jp2 must be set to 3.3v card detection switches are normally open card detectpolarity select i/o vdd r11 rd sio l1 10uf r20 r5 r7 0 r12 rd c8 gnd 5.0v tp7 12 jp2 12 3 r13 rd usr1 3.3v c2 0.1uf r6 offb r4 0 c8 0.1uf c1, c2, c8, c9 and l1 must be placed within 5mm of the u1 pins and connected by thick track (wider than 0.5mm) 5v s_c8 resistors not populated u1 73s8024c 1 2 3 4 5 6 7 12 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 28 27 25 24 26 clkdiv1 clkdiv2 5v3v gnd_4 lin vpc nc a u x2 pwrdn pres pres i/o a u x1 gnd_14 clk rst vcc vddf_adj cmdvcc rstin vdd gnd off aux2uc aux1uc xtalout xta l i n i/ouc jp3 must be set to 3.3v j5 smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 sio tp2 12 clkdiv2 jp3 12 3 3.3v j2 tsm_110_01_l_sv 12 3 4 5 6 7 8 9 10 + c3 10uf 5.0v tp8 12 sc8 5v3vb 3.3v tp4 12 pin18 signal names refer to 73s1121f evaluation board. gnd nc usr6 jp5 12 3 vdd c5 22pf 5v xtalinselect gnd pwrdn usr4 j1 ssm_110_l_sv 12 3 4 5 6 7 8 9 10 sclk r9ru tp1 12 sclk vddselect signal names refer to 73s1121f evaluation board. vdd cmdvccb tp5 12 xtal tp3 to tp8 to be placed very close to the pads of j5 r3 j6 sim/sam connector 1 2 3 4 5 6 7 8 c1 c2 c3 c5 c6 c7 sw1 sw2 sclk +5v tp3 12 rstin l1 must be placed close to pin 5 vpcselect int2 presb s_c4 +5v jp1 12 3 gnd pres j3 ssm_110_l_sv 12 3 4 5 6 7 8 9 10 vcc c9 0.47uf +3.3v vdd c13 27pf r1 rst y1 12.000mhz 1 4 c12 27pf 5.0v usr7 usr0 figure 5 : 73 s 8024c demo board electrical schematic downloaded from: http:///
73s8024c demo board user manual um_8024c_061 14 rev. 1.3 5.2 bill of materials table 8 provides the bill of materials for the 73s 8024c demo board schematic provided in figure 5. table 8 : 73s 8024c demo board bill of materials item quantity reference part pcb footprint digikey p art n umber part n umber manufacturer 1 3 c1,c3,c10 10 f 805 pcc2225ct - nd ecj - 2fb0j106m panasonic 2 2 c2,c8 0.1 f 603 pcc1762ct - nd ecj - 1vb1c104k panasonic 3 2 c4,c5 22 pf 603 pcc220acvct - nd ecj - 1vc1h220j panasonic 4 1 c11 3.3 f 805 pcc1925ct - nd ecj - 2yb0j335k panasonic 5 2 c12, c13 27 pf 402 pcc270cqct - nd ecj - 0ec1h270j panasonic 6 1 l1 10 h x slf6025 tdk 7 5 jp1,jp2,jp3,jp5, jp6 header 3 3pins, 2.54 mm pi tch s1011 - 36 - nd pzc36saan sullins 8 1 jp4 header lock 3 3pins, 2.54 mm pi tch wm2701 - nd 22 - 11 - 2032 molex 9 2 j1,j3 ssm_110_l_sv ssm_110_l_sv x ssm_110_l_sv samtec 10 2 j2,j4 tsm_110_01_l_sv tsm_110_01_l_sv x tsm_110_01_l_s v samtec 11 1 j5 smart card connector itt_ccm02 - 2504 ccm02- 2504 - nd ccm02- 2504 ittcannon 12 1 j6 sim/sam connector itt_ccm03 - 3754 ccm03 - 3754ct - nd ccm03 - 3754 ittcannon 13 3 r2,r4,r7 0 603 p0.0gct - nd e rj - 3gey0r00v panasonic 14 2 r5,r6 x 603 x x 15 4 r1,r8,r9,r10 ru 603 x x 16 4 r3,r11,r12,r13 rd 603 x x 17 8 tp1,tp2,tp3,tp4, tp5,tp6,tp7,tp8 tp2 2x1_header s1011 - 36 - nd pzc36saan sullins 18 1 u1 73s8024c 28sop x 73s8024c t eridian semiconductor 19 1 y1 12.000 mhz hc - 49us x190 - nd ecs - 120 - 20 - 4dn ecs 20 2 c4,c5 22 pf 603 pcc220acvct - nd ecj - 1vc1h220j panasonic 1 ru and rd are not populated on the board. they can be implemented to adjust the features of the smart card reader. downloaded from: http:///
um_8024c_061 73s8024c demo board user manual rev. 1.3 15 5.3 pcb layout s figure 6 : 73 s 8024c demo board top view figure 7 : 73 s 8024c demo board bottom view downloaded from: http:///
73s8024c demo board user manual um_8024c_061 16 rev. 1.3 figure 8 : 73 s 8024c demo board top signal layer figure 9 : 73 s 8024c demo b oard middle layer 1, ground plane downloaded from: http:///
um_8024c_061 73s8024c demo board user manual rev. 1.3 17 figure 10 : 73s 8024c middle layer 2, supply plane figure 11 : 73s 8024c demo board bottom signal layer downloaded from: http:///
73s8024c demo board user manual um_8024c_061 18 rev. 1.3 6 ordering information table 9 lists th e order number used to identify the 73 s 8024c demo board. table 9 : order numbers and packaging marks part description order number 73s8024c 28 - pin so demo board 73s8024c - db 7 related documentation the following 73 s 8024c documents are available from teridian semiconductor corporation: 73 s 8024c data sheet 73s8024c demo board user manual (this document) teridian 73s8024c versus philips tda8024t application note 8 contact information for more information about teridian semiconductor pro ducts or to che ck the availability of the 73 s 8024c , contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr .support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
um_8024c_061 73s8024c demo board user manual rev. 1.3 19 revision history revision date description 1.0 6/8 /200 4 first publication . 1.1 8/2 /2 004 minor corrections . 1.2 8/23/2005 added new logo. 1.3 11/11 /2009 added section 1.1, package contents. added section 1.2, safety and esd notes. added section 6, ordering information. added section 7, related documentation. added section 8, contact information. miscellaneous editorial changes. downloaded from: http:///

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