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spt7835 10-bit , 5 msps, 75 mw a/d conver ter technical d a t a june 27, 2001 fea tures ? monolithic 5 msps con v er ter 75 mw po w er dissipation o n-chip tr ac k-and-hold s ingle +5 v po w er supply ttl/cmos outputs 5 pf input capacitance l o w cost t r i-state output b uff ers h igh esd protection: 3,500 v minim u m selectab le +3 v or +5 v logic i/o applica tions all high-speed applications where lo w po w e r dissipation is required video imaging medical imaging ir imaging scanners digital communications general description the spt7835 is a 10-bit monolithic , lo w-cost, ultr alo w- po w e r analog-to-digital con v e r t er capab le of minim um w ord rates of 5 msps . the on-chip trac k-and-hold func- tion assures v e r y good dynamic perf or mance without the need f or e x ter nal components . the input dr iv e require- ments are minimiz ed due to the spt7835? s lo w input capacitance of only 5 pf . p o w er dissipation is e x tremely lo w at only 75 mw typical at 5 msps with a po wer supply of +5.0 v . the digital out- puts are +3 v or +5 v , and are user selectable . the spt7835 is pin-compatib le with an entire f amily of 10-bit, cmos con v e r ters (spt7835/40/50/55/60/61), which sim- plifies upg r ades . the spt7835 has incor por ated propr i- etar y circuit design* and cmos processing technologies to achie v e its adv anced perf o r m ance . inputs and outputs are ttl/cmos-compatib le to interf ace with ttl/cmos logic systems . output data f o r mat is str aight binar y . the spt7835 is a v ailab le in a 28-lead soic pac kage o v er the industr ial temperature r ange , and a 32-lead small (7 mm square) tqfp pac kage o v er the commercial temper ature r ange . *p atent pending block dia gram

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2 6/27/01 spt7835 absolute maximum ratings (beyond which damage may occur) 1 25 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. electrical specifications t a =t min to t max , av dd =dv dd =ov dd =+5.0 v, v in =0 to 4 v, ? clk =10 mhz, ? s =5 msps, v rhs =4.0 v, v rls =0.0 v, unless otherwise specified. test test spt7835 parameters conditions level min typ max units resolution 10 bits dc accuracy integral linearity error (ile) vi 1.0 lsb differential linearity error (dle) vi 0.5 lsb no missing codes vi guaranteed analog input input voltage range vi v rls v rhs v input resistance iv 50 k ? input capacitance v 5.0 pf input bandwidth (small signal) v 100 mhz offset v 2.0 lsb gain error v 2.0 lsb reference input resistance vi 400 500 600 ? bandwidth v 100 150 mhz voltage range v rls iv 0 2.0 v v rhs iv 3.0 av dd v v rhs ? v rls v 1.0 4.0 5.0 v ? (v rhf ? v rhs )v90mv ? (v rls ? v rlf )v75mv reference settling time v rhs v 15 clock cycles v rls v 20 clock cycles conversion characteristics maximum conversion rate vi 5 mhz minimum conversion rate iv 2 mhz pipeline delay (latency) iv 12 clock cycles aperture delay time v 5 ns aperture jitter time v 10 ps (p-p) dynamic performance effective number of bits (enob) ? in = 1 mhz vi 9.2 bits signal-to-noise ratio (snr) (without harmonics) ? in = 1 mhz vi 54 59 db supply voltages av dd ...................................................................... +6 v dv dd ..................................................................... +6 v input voltages analog input .............................. ? 0.5 v to av dd +0.5 v v ref .............................................................. 0 to av dd clk input ............................................................... v dd av dd ? dv dd .................................................. 100 mv agnd ? dgnd .............................................. 100 mv output digital outputs ................................................... 10 ma temperature operating temperature ............................ ? 40 to 85 c junction temperature ........................................ 175 c lead temperature, (soldering 10 seconds) ....... 300 c storage temperature ............................ ? 65 to +150 c
3 6/27/01 spt7835 test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. level test procedure i 100% production tested at the specified temperature. ii 100% production tested at t a = +25 c, and sample tested at the specified temperatures. iii qa sample tested only at the specified temperatures. iv parameter is guaranteed (but not tested) by design and characteri- zation data. v parameter is a typical value for information purposes only. vi 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. electrical specifications t a =t min to t max , av dd =dv dd =ov dd =+5.0 v, v in =0 to 4 v, ? clk =10 mhz, ? s =5 msps, v rhs =4.0 v, v rls =0.0 v, unless otherwise specified. test test spt7835 parameters conditions level min typ max units dynamic performance total harmonic distortion (thd) ? in = 1 mhz vi 59 63 db signal-to-noise and distortion (sinad) ? in = 1 mhz vi 52 57 db spurious free dynamic range v 63 db digital inputs logic 1 voltage vi 2.0 v logic 0 voltage vi 0.8 v maximum input current low vi ? 10 +10 a maximum input current high vi ? 10 +10 a input capacitance v 5 pf digital outputs logic 1 voltage i oh = 0.5 ma vi 3.5 v logic 0 voltage i ol = 1.6 ma vi 0.4 v t rise 15 pf load v 10 ns t fall 15 pf load v 10 ns output enable to data output delay 20 pf load, t a = +25 cv 10 ns 50 pf load over temp. v 22 ns power supply requirements voltages ov dd iv 3.0 5.0 v dv dd iv 4.75 5.0 5.25 v av dd iv 4.75 5.0 5.25 v currents ai dd vi 9 12 ma di dd vi 6 10 ma power dissipation ? in = 1 mhz vi 75 110 mw
4 6/27/01 spt7835 aperture delay aperture delay represents the point in time, relative to the rising edge of the clock input, that the analog input is sampled. aperture jitter the variations in aperture delay for successive samples. differential gain (dg) a signal consisting of a sine wave superimposed on vari- ous dc levels is applied to the input. differential gain is the maximum variation in the sampled sine wave amplitudes at these dc levels. differential phase (dp) a signal consisting of a sine wave superimposed on vari- ous dc levels is applied to the input. differential phase is the maximum variation in the sampled sine wave phases at these dc levels. effective number of bits (enob) sinad = 6.02n + 1.76, where n is equal to the effective number of bits. integral linearity error (ile) linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from ? fs through +fs. the deviation is measured from the edge of each particular code to the true straight line. output delay time between the clock ? s triggering edge and output data valid. overvoltage recovery time the time required for the adc to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. signal-to-noise ratio (snr) the ratio of the fundamental sinusoid power to the total noise power. harmonics are excluded. signal-to-noise and distortion (sinad) the ratio of the fundamental sinusoid power to the total noise and distortion power. total harmonic distortion (thd) the ratio of the total power of the first 9 harmonics to the power of the measured sinusoidal signal. spurious free dynamic range (sfdr) the ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal. input bandwidth small signal (50 mv) bandwidth (3 db) of analog input stage. differential linearity error (dle) error in the width of each code from its theoretical value. (theoretical = v fs /2 n ) n = sinad ? 1.76 6.02 specification definitions
5 6/27/01 spt7835 figure 1a ? timing diagram 1 figure 1b ? timing diagram 2 table i ? timing parameters description parameters min typ max units conversion time t c 2*t clk ns clock period t clk 100 ns clock high duty cycle t ch 40 50 60 % clock low duty cycle t cl 40 50 60 % clock to output delay (15 pf load) t od 15 20 25 ns dav pulse width t dav t clk ns clock to dav t s 16 21 26 ns 3 *&,5'*
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7 6/27/01 spt7835 typical interf a ce circuit v e r y f e w e x ter nal components are required to achie v e the stated de vice perf or mance . figure 2 sho ws the typical in- terf ace requirements when using the spt7835 in nor mal circuit operation. the f o llo wing sections pro vide descr ip- tions of the major functions and outline cr itical perf or- mance cr iter ia to consider f or achie ving the optimal de vice perf or mance . po wer supplies and gr ounding ply v oltages on the spt7835 be der iv ed from a single ana- log supply as sho wn in figure 2. a separ ate digital supply using this po w er supply configuration to pre v ent a possib le latch-up condition on po w e r u p . opera ting description the gener al architecture f or the cmos adc is sho wn in the b loc k diagram. the design contains eight identical successiv e appro ximation adc sections, all oper ating in parallel, a 16-phase cloc k gener ator , an 11-bit 8:1 digital output m ultiple x e r , correction logic , and a v oltage ref er- ence gener ator that pro vides common ref erence le v els f o r each adc section. the high sample r ate is achie v ed b y using m ultiple sar adc sections in par allel, each of which samples the input signal in sequence . each adc uses 16 cloc k cycles to complete a con v ersion. the cloc k cycles are allocated as sho wn in tab le ii. & & '*
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8 6/27/01 spt7835 table ii ? clock cycles clock operation 1 reference zero sampling 2 auto-zero comparison 3 auto-calibrate comparison 4 input sample 5-15 11-bit sar conversion 16 data transfer the 16-phase clock, which is derived from the input clock, synchronizes these events. the timing signals for adjacent adc sections are shifted by two clock cycles so that the analog input is sampled on every other cycle of the input clock by exactly one adc section. after 16 clock periods, the timing cycle repeats. the sample rate for the configu- ration is one-half of the clock rate; e.g., for a 10 mhz clock rate, the input sample rate is 5 mhz. the latency from analog input sample to the corresponding digital output is 12 clock cycles. since only eight comparators are used, a huge power savings is realized. the auto-zero operation is done using a closed loop system that uses multiple samples of the comparators ? response to a reference zero. the auto-calibrate operation, which calibrates the gain of the msb reference and the lsb reference, is also done with a closed loop system. multiple samples of the gain error are integrated to produce a calibration volt- age for each adc section. capacitive displacement currents, which can induce sampling error, are minimized since only one compara- tor samples the input during a clock cycle. the total input capacitance is very low since sections of the converter that are not sampling the signal are iso- lated from the input by transmission gates. voltage reference the spt7835 requires the use of a single external voltage reference for driving the high side of the reference ladder. it must be within the range of 3 v to 5 v. the lower side of the ladder is typically tied to agnd (0.0 v), but can be run up to 2.0 v with a second reference. the analog input volt- age range will track the total voltage difference measured between the ladder sense lines, v rhs and v rls . force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. by using the configuration shown in figure 3, offset and gain errors of less than 2 lsb can be obtained. in cases where wider variations in offset and gain can be tolerated, v ref can be tied directly to v rhf , and agnd can be tied directly to v rlf as shown in figure 4. decouple force and sense lines to agnd with a .01 f capacitor (chip cap preferred) to minimize high-frequency noise in- jection. if this simplified configuration is used, the following considerations should be taken into account. the reference ladder circuit shown in figure 4 is a simpli- fied representation of the actual reference ladder with force and sense taps shown. due to the actual internal structure of the ladder, the voltage drop from v rhf to v rhs is not equivalent to the voltage drop from v rlf to v rls . figure 3 ? ladder force/sense circuit 5* & & '* b 7 "" : > +d+c b 7 figure 4 ? reference ladder # # 94+ /<:0 "" : > +d+c & /5* 0 +d+ & /+d+$20 /b4d.0 b3d+ " % $2 .+
9 6/27/01 spt7835 typically, the top side voltage drop for v rhf to v rhs will equal: v rhf ? v rhs = 2.25 % of (v rhf ? v rlf ) (typical), and the bottom side voltage drop for v rls to v rlf will equal: v rls ? v rlf = 1.9 % of (v rhf ? v rlf ) (typical). figure 4 shows an example of expected voltage drops for a specific case. v ref of 4.0 v is applied to v rhf , and v rlf is tied to agnd. a 90 mv drop is seen at v rhs (= 3.91 v), and a 75 mv increase is seen at v rls (= 0.075 v). analog input v in is the analog input. the input voltage range is from v rls to v rhs (typically 4.0 v) and will scale proportionally with respect to the voltage reference. (see voltage refer- ence section.) the drive requirements for the analog inputs are very minimal when compared to most other converters due to the spt7835 ? s extremely low input capacitance of only 5 pf and very high input resistance of 50 k ? . the analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. upon powerup, the spt7835 begins its calibration algo- rithm. in order to achieve the calibration accuracy re- quired, the offset and gain adjustment step size is a frac- tion of a 10-bit lsb. since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. this results in a minimum calibration time upon powerup of 1 msec for a 5 mhz sample rate. once calibrated, the spt7835 remains calibrated over time and temperature. since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the spt7835 to remain in calibration. input protection all i/o pads are protected with an on-chip protection circuit shown in figure 6. this circuit provides esd robust- ness to 3.5 kv and prevents latch-up under severe dis- charge conditions without degrading analog transition times. figure 5 ? recommended input protection circuit 3$ #
%% b 7 9 #9?" g !2$#;- " figure 6 ? on-chip protection circuit " ! #+ #+ calibration the spt7835 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. gain and off- set errors are continually adjusted to 10-bit accuracy during device operation. this process is completely trans- parent to the user. power supply sequencing considerations all logic inputs should be held low until power to the device has settled to the specific tolerances. avoid power decou- pling networks with large time constants that could delay v dd power to the device. clock input the spt7835 is driven from a single-ended ttl-input clock. because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. the device ? s sample rate is 1/2 of the input clock frequency. (see figure 1a timing diagram.)
10 6/27/01 spt7835 digital outputs the digital outputs (d0 ? d10) are driven by a separate supply (ov dd ) ranging from +3 v to +5 v. this feature makes it possible to drive the spt7835 ? s ttl/cmos- compatible outputs with the user ? s logic system supply. the format of the output data (d0 ? d9) is straight binary. (see table iii.) the outputs are latched on the rising edge of clk. these outputs can be switched into a tri-state mode by bringing en high. table iii ? output data information analog input overrange output code d10 d9 ? d0 +f.s. + 1/2 lsb 1 1 1 1 1 1 1 1 1 1 1 +f.s. ? 1/2 lsb 0 1 1 1 1 1 1 1 1 1 ? +1/2 f.s. 0 ?? ???? ???? +1/2 lsb 0 0 0 0 0 0 0 0 0 0 ? 0.0 v 0 0 0 0 0 0 0 0 0 0 0 ( ? indicates the flickering bit between logic 0 and 1.) overrange output the overrange output (d10) is an indication that the analog input signal has exceeded the positive full- scale input voltage by 1 lsb. when this condition occurs, d10 will switch to logic 1. all other data outputs (d0 to d9) will remain at logic 1 as long as d10 remains at logic 1. this feature makes it possible to include the spt7835 in higher resolution systems. evaluation board the eb7835 evaluation board is available to aid designers in demonstrating the full performance of the spt7835. this board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction of the digital data. an application note describing the operation of this board, as well as information on the testing of the spt7835, is also available. contact the factory for price and availability.
11 6/27/01 spt7835 package outlines 28-lead soic 32-lead tqfp inches millimeters symbol min max min max a 0.346 0.362 8.80 9.20 b 0.272 0.280 6.90 7.10 c 0.346 0.362 8.80 9.20 d 0.272 0.280 6.90 7.10 e 0.031 typ 0.80 bsc f 0.012 0.016 0.30 0.40 g 0.053 0.057 1.35 1.45 h 0.002 0.006 0.05 0.15 i 0.037 0.041 0.95 1.05 j 0.007 0.17 k0 7 0 7 l 0.020 0.030 0.50 0.75 inches millimeters symbol min max min max a 0.699 0.709 17.75 18.01 b 0.005 0.011 0.13 0.28 c 0.050 typ 1.27 typ d 0.018 typ 0.46 typ e 0.0077 0.0083 0.20 0.21 f 0.090 0.096 2.29 2.44 g 0.031 0.039 0.79 0.99 h 0.396 0.416 10.06 10.57 i 0.286 0.292 7.26 7.42
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12 6/27/01 spt7835 ordering informa tion part number temperature range package type spt7835sis ? 40 to +85 c 28l soic SPT7835SCT 0 to +70 c 32l tqfp pin functions name function a g n d analog ground v rhf ref erence high f orce v rhs ref erence high sense v rls ref erence lo w sense v rlf ref erence lo w f orce v cal calibr ation ref erence v in analog input av dd analog v dd dv dd digital v dd dgnd digital ground clk input cloc k ? clk = fs (ttl) en output enab l e d0 ? 9 t r i-state data output, (d0=lsb) d10 t r i-state output ov err ange d a v data v alid output ov dd digital output supply ognd d i gital output ground n / c no connect pin assignments 5* *
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