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the allegro ? a1101-a1104 and a1106 hall-effect switches are next generation replacements for the popular allegro 312x and 314x lines of unipolar switches. the a110x family, produced with bicmos technology, consists of devices that feature fast power-on time and low-noise operation. device programming is performed after packaging, to ensure increased switchpoint accuracy by eliminating offsets that can be induced by package stress. unique hall element geometries and low- offset amplifiers help to minimize noise and to reduce the residual offset voltage normally caused by device overmolding, temperature excursions, and thermal stress. the a1101-a1104 and a1106 hall-effect switches include the following on a single silicon chip: voltage regulator, hall- voltage generator, small-signal amplifier, schmitt trigger, and nmos output transistor. the integrated voltage regulator permits operation from 3.8 to 24 v. the extensive on-board protection circuitry makes possible a 30 v absolute maximum voltage rating for superior protection in automotive and industrial motor commutation applications, without adding external components. all devices in the family are identical except for magnetic switchpoint levels. the small geometries of the bicmos process allow these devices to be provided in ultrasmall packages. the package styles available provide magnetically optimized solutions for most applications. package lh is an sot23w, a miniature low- profile surface-mount package, while package ua is a three-lead ultramini sip for through-hole mounting. each package is lead (pb) free, with 100% matte-tin-plated leadframes. a1101-ds, rev. 16 ? aec-q100 automotive qualified ? continuous-time operation fast power-on time low noise ? stable operation over full operating temperature range ? reverse battery protection ? solid-state reliability ? factory-programmed at end-of-line for optimum performance ? robust emc performance ? high esd rating ? regulator stability without a bypass capacitor continuous-time switch family packages: functional block diagram not to scale a1101, a1102, a1103, a1104, and a1106 a m p r e g u l a t o r g n d v c c v o u t o f f s e t gain t r i m c o n t r o l t o a l l s u b c i r c u i t s lh: a1101, a1102, a1103, a1104, and a1106 ua: a1101, a1102, a1103, and a1104 ua: a1106 features and benefits description 3-pin sip (suffix ua) 3-pin sot23w (suffix lh)
2 part number packing * mounting ambient, t a b rp (min) b op (max) a1101elhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 85oc 10 175 a1101elhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1101eua-t bulk, 500 pieces/bag 3-pin sip through hole a1101llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 150oc a1101llhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount A1101LUA-T bulk, 500 pieces/bag 3-pin sip through hole a1102elhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 85oc 60 245 a1102elhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1102eua-t bulk, 500 pieces/bag 3-pin sip through hole a1102llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 150oc a1102llhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1102lua-t bulk, 500 pieces/bag 3-pin sip through hole a1103elhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 85oc 150 355 a1103elhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1103llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 150oc a1103llhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1103lua-t bulk, 500 pieces/bag 3-pin sip through hole a1104eua-t bulk, 500 pieces/bag 3-pin sip through hole C40oc to 85oc 25 450 a1104llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 150oc a1104llhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1104lua-t bulk, 500 pieces/bag 3-pin sip through hole a1106eua-t bulk, 500 pieces/bag 3-pin sip through hole C40oc to 85oc 160 430 a1106llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount C40oc to 150oc a1106llhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1106lua-t bulk, 500 pieces/bag 3-pin sip through hole *contact allegro for additional packing options. selection guide absolute maximum ratings characteristic symbol notes rating units supply voltage v cc 30 v reverse supply voltage v rcc C30 v output off voltage v out 30 v reverse output voltage v rout C0.5 v output current i outsink 25 ma magnetic flux density b unlimited g operating ambient temperature t a range e C40 to 85 oc range l C40 to 150 oc maximum junction temperature t j (max) 165 oc storage temperature t stg C65 to 170 oc specifications continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 characteristic symbol test conditions min. typ. max. units supply voltage 1 v cc operating, t j < 165c 3.8 C 24 v output leakage current i outoff v out = 24 v, b < b rp C C 10 a output on voltage v out(sat) i out = 20 ma, b > b op C 215 400 mv power-on time 2 t po slew rate (dv cc /dt) < 2.5 v/s, b > b op + 5 g or b < b rp C 5 g C C 4 s output rise time 3 t r v cc = 12 v, r load = 820 ?, c s = 12 pf C C 400 ns output fall time 3 t f v cc = 12 v, r load = 820 ?, c s = 12 pf C C 400 ns supply current i ccon b > b op C 4.1 7.5 ma i ccoff b < b rp C 3.8 7.5 ma reverse battery current i rcc v rcc = C30 v C C C10 ma supply zener clamp voltage v z i cc = 10.5 ma; t a = 25c 32 C C v supply zener current 4 i z v z = 32 v; t a = 25c C C 10.5 ma 1 maximum voltage must be adjusted for power dissipation and junction temperature, see power derating section. 2 for v cc slew rates greater than 250 v/s, and t a = 150c, the power-on time can reach its maximum value. 3 c s =oscilloscope probe capacitance. 4 maximum current limit is equal to the maximum i cc(max) + 3 ma. device qualification program contact allegro for information. emc (electromagnetic compatability) requirements contact allegro for information. 1 3 2 gnd vout vcc package ua, 3-pin sip package lh 1 2 3 gnd vout vcc terminal list number name description package lh package ua 1 1 vcc connects power supply to chip 2 3 vout output from circuit 3 2 gnd ground electrical operating characteristics over full operating voltage and ambient temperature ranges, unless otherwise noted continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 characteristic symbol test conditions min. typ. max. units operate point b op a1101 t a = 25c 50 100 160 g operating temperature range 30 100 175 g a1102 t a = 25c 130 180 230 g operating temperature range 115 180 245 g a1103 t a = 25c 220 280 340 g operating temperature range 205 280 355 g a1104 t a = 25c 70 C 350 g operating temperature range 35 C 450 g a1106 t a = 25c 280 340 400 g operating temperature range 260 340 430 g release point b rp a1101 t a = 25c 10 45 130 g operating temperature range 10 45 145 g a1102 t a = 25c 75 125 175 g operating temperature range 60 125 190 g a1103 t a = 25c 165 225 285 g operating temperature range 150 225 300 g a1104 t a = 25c 50 C 330 g operating temperature range 25 C 430 g a1106 t a = 25c 180 240 300 g operating temperature range 160 240 330 g hysteresis b hys a1101 t a = 25c 20 55 80 g operating temperature range 20 55 80 g a1102 t a = 25c 30 55 80 g operating temperature range 30 55 80 g a1103 t a = 25c 30 55 80 g operating temperature range 30 55 80 g a1104 t a = 25c 20 55 C g operating temperature range 20 55 C g a1106 t a = 25c 70 105 140 g operating temperature range 70 105 140 g 1 magnetic fux density, b, is indicated as a negative value for north-polarity magnetic felds, and as a positive value for south-polarity magnetic felds. this so-called alge - braic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the feld is indicated by the absolute value of b, and the sign indicates the polarity of the feld (for example, a C100 g feld and a 100 g feld have equivalent strength, but opposite polarity). magnetic operating characteristics 1: over full operating voltage and ambient temperature ranges, un - less otherwise noted continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 characteristic symbol test conditions value units package thermal resistance r ja package lh, 1-layer pcb with copper limited to solder pads 228 oc/w package lh, 2-layer pcb with 0.463 in. 2 of copper area each side connected by thermal vias 110 oc/w package ua, 1-layer pcb with copper limited to solder pads 165 oc/w 6 7 8 9 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 20 40 60 80 100 120 140 160 180 temperature (oc) maximum allowable v cc (v) t j(max) = 165oc; i cc = i cc(max) power derating curve (r ja = 228 oc/w) package lh, 1-layer pcb (r ja = 110 oc/w) package lh, 2-layer pcb (r ja = 165 oc/w) package ua, 1-layer pcb v cc(min) v cc(max) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (mw) power dissipation versus ambient temperature (r ja = 165 oc/w) package ua, 1-layer pcb (r ja = 228 oc/w) package lh, 1-layer pcb (r ja = 110 oc/w) package lh, 2-layer pcb thermal characteristics: may require derating at maximum conditions; see application information continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 characteristic data (a1101/02/03/04/06) t a (c) supply current (on) versus ambient t emperature v cc (v) i ccon (ma) 24 3. 8 (a1101/02/03/04/06) t a (c) supply current (off) versus ambient t emperature v cc (v) i ccoff (ma) 24 3. 8 (a1101/02/03/04/06) t a (c) output v oltage (on) versus ambient t emperature v cc (v) v out(sa t) (mv) 24 3. 8 (a1101/02/03/04/06) supply current (on) versus supply v oltage t a ( c) i ccon (ma) v cc (v) ?4 0 25 15 0 (a1101/02/03/04/06) supply current (off) versus supply v oltage t a ( c) i ccoff (ma) v cc (v) ?4 0 25 15 0 (a1101/02/03/04/06) output v oltage (on) versus supply v oltage t a ( c) v out(sa t) (mv) v cc (v) ?4 0 25 15 0 0 1. 0 2. 0 3. 0 4. 0 5. 0 7. 0 6. 0 8. 0 0 1. 0 2. 0 3. 0 4. 0 5. 0 7. 0 6. 0 8. 0 0 1. 0 2. 0 3. 0 4. 0 5. 0 7. 0 6. 0 8. 0 0 1. 0 2. 0 3. 0 4. 0 5. 0 7. 0 6. 0 8. 0 ?5 00 50 10 01 50 05 10 15 20 25 ?5 00 50 10 01 50 05 10 15 20 25 ?5 00 50 10 01 50 05 10 15 20 25 0 50 10 0 15 0 20 0 25 0 30 0 35 0 40 0 0 50 10 0 15 0 20 0 25 0 30 0 35 0 40 0 continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 functional description operation the output of these devices switches low (turns on) when a magnetic field (south polarity) perpendicular to the hall element exceeds the operate point threshold, b op . after turn-on, the output is capable of sinking 25 ma and the output voltage is v out(sat) . when the magnetic field is reduced below the release point, b rp , the device output goes high (turns off). the difference in the magnetic operate and release points is the hysteresis, b hys , of the device. this built-in hysteresis allows clean switching of the output, even in the presence of external mechanical vibration and electrical noise. powering-on the device in the hysteresis region, less than b op and higher than b rp , allows an indeterminate output state. the correct state is attained after the first excursion beyond b op or b rp . continuous-time benefits c ontinuous-time devices, such as the a110x family, offer the fast - est available power-on settling time and frequency response. due to offsets generated during the ic packaging process, continuous- time devices typically require programming after packaging to tighten magnetic parameter distributions. in contrast, chopper- stabilized switches employ an offset cancellation technique on the chip that eliminates these offsets without the need for after- packaging programming. the tradeoff is a longer settling time and reduced frequency response as a result of the chopper-stabiliza - tion offset cancellation algorithm. the choice between continuous-time and chopper-stabilized designs is solely determined by the application. battery manage - ment is an example where continuous-time is often required. in these applications, v cc is chopped with a very small duty cycle in order to conserve power (refer to figure 2). the duty cycle is controlled by the power-on time, t po , of the device. because continuous-time devices have the shorter power-on time, they are the clear choice for such applications. for more information on the chopper stabilization technique, refer to technical paper stp 97-10, monolithic magnetic hall sensing using dynamic quadrature offset cancellation and technical paper stp 99-1, chopper-stabilized amplifiers with a track-and-hold signal demodulator . figure 1: switching behavior of unipolar switches on the horizontal axis, the b+ direction indicates increasing south polarity magnetic field strength, and the bC direction indicates decreasing south polarity field strength (including the case of increasing north polarity). this behavior can be exhibited when using a circuit such as that shown in panel b. b o p b r p b h y s v c c v o u t v o u t ( s a t ) s w i t c h t o l o w s w i t c h t o h i g h b + b ? v + 0 0 (a) (b) vcc v s output gnd vout r l a110x continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 additional applications information extensive applications information for hall-effect devices is available in: ? hall-effect ic applications guide , application note 27701 ? hall-effect devices: guidelines for designing subassemblies using hall-effect devices , application note 27703.1 ? soldering methods for allegros products C smt and through- hole , application note 26009 all are provided in allegro electronic data book , ams-702, and the allegro web site, www.allegromicro.com. figure 2: continuous-time application, b < b rp this figure illustrates the use of a quick cycle for chopping v cc in order to conserve battery power. position 1, power is applied to the device. position 2, the output assumes the correct state at a time prior to the maximum power-on time, t po(max) . the case shown is where the correct output state is high . position 3, t po(max) has elapsed. the device output is valid. position 4, after the output is valid, a control unit reads the output. position 5, power is removed from the device. v cc v out output sample d 1 5 4 2 t t t po(max) 3 continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 power derating power derating the device must be operated below the maximum junction temperature of the device, t j(max) . under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli - cation. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems web site.) the package thermal resistance, r ja , is a figure of merit sum - marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity, k, of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case, r jc , is relatively small component of r ja . ambient air temperature, t a , and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) t = p d r ja (2) t j = t a + t (3) for example, given common conditions such as: t a = 25c, v cc = 12 v, i cc = 4 ma, and r ja = 140 c/w, then: p d = v cc i cc = 12 v 4 ma = 48 mw t = p d r ja = 48 mw 140 c/w = 7c t j = t a + t = 25c + 7c = 32c a worst-case estimate, p d(max) , represents the maximum allow - able power level (v cc(max) , i cc(max) ), without exceeding t j(max) , at a selected r ja and t a . example : reliability for v cc at t a = 150c, package ua, using minimum-k pcb. observe the worst-case ratings for the device, specifically: r ja = 165c/w, t j(max) = 165c, v cc(max) = 24 v, and i cc(max) = 7.5 ma. calculate the maximum allowable power level, p d(max) . first, invert equation 3: t max = t j(max) C t a = 165 c C 150 c = 15 c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: p d(max) = t max r ja = 15c 165 c/w = 91 mw finally, invert equation 1 with respect to voltage: v cc(est) = p d(max) i cc(max) = 91 mw 7.5 ma = 12.1 v the result indicates that, at t a , the application and device can dis - vlsdwhdhtdwhdprqwvrikhdwdwrowdjhv9 cc(est) . compare v cc(est) to v cc(max) . if v cc(est) 9 cc(max) , then reli - able operation between v cc(est) and v cc(max) requires enhanced r ja . if v cc(est) 9 cc(max) , then operation between v cc(est) and v cc(max) is reliable under these conditions. continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 figure 3: package lh, 3-pin (sot-23w) a b c d c for reference only ?n ot for t ooling use (reference dwg-2840) dimensions in millimeters ?n ot to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits show n reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances active area depth, 0.28 mm hall elements, not to scal e =t emperature code (letter) t standard branding reference vi ew nnt branding scale and appearance at supplier discretio n seating plane gauge plane pcb layout reference vi ew 0.55 ref 0.25 bsc 0.95 bsc 0.95 1.00 0.70 2.40 2 1 b a branded face 2.90 +0.10 ?0.2 0 4 4 8x 10 ref 0.180 +0.020 ?0.053 0.05 +0.10 ?0.05 0.25 mi n 1.91 +0.19 ?0.0 6 2.98 +0.12 ?0.0 8 1.00 0.13 0.40 0.10 d d d 1.49 0.96 3 = last three digits of device part number n nnn = last three digits of device part number n a1 101, a1 102, a1 103, a1 104, and a1 106 a1 101, a1 102, a1 103, a1 104, and a1 106 customer package drawing continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 for reference only ? not for t ooling use (reference dwg-9049 ) dimensions in millimeters ? not to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits show n 23 1 1.27 nom 2.16 max 0.51 ref 0.79 ref b a b c a d e d e e 2.04 1.44 e branding scale and appearance at supplier discretion hall element, not to scale mold ejector pin indent branded face 4.09 +0.08 ?0.05 0.41 +0.03 ?0.06 3.02 +0.08 ?0.05 0.43 +0.05 ?0.07 15.75 0.25 dambar removal protrusion (6x ) gate and tie bar burr area active area depth, 0.50 mm ref nnt standard branding reference v iew = supplier emblem = last three digits of device part numbe r =t emperature code n 45 c 45 2 x 10 1.52 0.05 1 t figure 4: package ua, 3-pin sip (a1101, a1102, a1103, and a1104) continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 figure 5: package ua, 3-pin sip (a1106) for reference only ? not for t ooling use (reference dwg-9013 ) dimensions in millimeters ? not to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits show n 23 1 1.27 nom 1.02 max 0.79 ref b a b c a d e d e e 2.04 1.44 e branding scale and appearance at supplier discretion hall element, not to scale mold ejector pin indent branded face 4.09 +0.08 ?0.05 0.41 +0.03 ?0.06 3.02 +0.08 ?0.05 0.43 +0.05 ?0.07 14.99 0.25 dambar removal protrusion (6x ) gate and tie bar burr area active area depth, 0.50 mm ref nnn standard branding reference v iew = supplier emblem = last three digits of device part numbe r n 45 c 45 2 x 10 1.52 0.05 1 continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision 14 may 29, 2012 add a1106 ua package drawing 15 january 1, 2015 added the lx option to selection guide 16 september 30, 2015 corrected lh package active area depth value and lh package branding; added aec-q100 qualification under features and benefits copyright ?2015, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. continuous-time switch family a1101, a1102, a1103, a1104, and a1106 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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