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? semiconductor components industries, llc, 2017 december, 2017 ? rev. 1 1 publication order number: ncp4306/d ncp4306 secondary side synchronous rectification driver for high efficiency smps topologies the ncp4306 is high performance driver tailored to control a synchronous rectification mosfet in switch mode power supplies. thanks to its high performance drivers and versatility, it can be used in various topologies such as dcm or ccm flyback, quasi resonant flyback, forward and half bridge resonant llc. the combination of externally or fixed adjustable minimum off - time and on - time blanking periods helps to fight the ringing induced by the pcb layout and other parasitic elements. a reliable and noise less operation of the sr system is insured due to the self synchronization feature . the ncp4306 also utilizes kelvin connection of the driver to the mosfet to achieve high efficiency operation at full load and utilizes a light load detection architecture to achieve high efficiency at light load. the precise turn ? off threshold, extremely low turn ? off delay time and high sink current capability of the driver allow the maximum synchronous rectification mosfet conduction time and enables maximum smps efficiency. the high accuracy driver and 5 v gate clamp enables the use of gan mosfets. features ? self ? contained control of synchronous rectifier in ccm, dcm and qr for flyback or llc applications ? precise true secondary zero current detection ? typically 15 ns turn off delay from current sense input to driver ? rugged current sense pin (up to 200 v) ? ultrafast turn ? off trigger interface / disable input (10.5 ns) ? adjustable or fixed minimum on ? time ? adjustable or fixed minimum off - time with ringing detection ? improved robust self synchronization capability ? 7 a / 2 a peak current sink / source drive capability ? operating voltage range up to v cc = 35 v ? automatic light ? load disable mode ? gan transistor driving capability ? low startup and disable current consumption ? maximum operation frequency up to 1 mhz ? tsop6 and soic - 8 packages ? this is a pb ? free device www. onsemi.com soic ? 8 nb case 751 ? 07 marking diagrams typical applications ? notebook adapters ? high power density ac / dc power supplies (cell phone chargers) ? lcd tvs ? all smps with high efficiency requirements tsop ? 6 case 318g ? 02 1 8 xxxxx = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package xxxxx alywx 1 8 ic (pb ? free) xxxayw 1 (note: microdot may be in either location) 1 soic ? 8 nb tsop ? 6 ic (pb ? free) see detailed ordering and shipping information on page 2 of this data sheet. ordering information
ncp4306 www. onsemi.com 2 ordering information table table 1. available devices device package package marking packing shipping ? NCP4306AAAZZZADR2G soic8 6aaazzza soic ? 8 (pb ? free) 2500 / tape and reel ncp4306aadzzzadr2g 6aadzzza ncp4306aahzzzadr2g 6aahzzza ncp4306dadzzdasnt1g tsop6 6ac tsop ? 6 (pb ? free) 3000 / tape and reel ncp4306dahzzaasnt1g 6ad ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011 / d. see the on semiconductor device nomenclature document ( tnd310 / d ) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com . figure 1. typical application example ? llc converter with optional lld and trigger utilization +v bulk llc stage control m1 m2 n1 c1 ok1 n3 n2 tr1 r1 c3 +v out rtn d1 r2 c4 m4 m3 c2 ncp4306 vcc min_toff min_ton lld drv gnd cs trig vcc min_toff min_ton lld drv gnd cs trig ncp4306 r min_toff r min_ton r lld r min_toff r min_ton r lld
ncp4306 www. onsemi.com 3 figure 2. typical application example ? dcm, ccm or qr flyback converter with optional lld and disabled trig v bulk flyback control circuitry m1 c1 ok1 r1 d3 c2 tr1 r3 m2 gnd c4 d5 ncp4306 r min_toff r lld r2 drv cs fb v cc c3 d4 c5 min_toff min_ton lld +v out v bulk flyback control circuitry m1 c1 ok1 r1 d3 c2 tr1 r3 m2 gnd c4 d5 ncp4306 r min_ton r lld r2 drv cs fb v cc c3 d4 c5 vcc drv gnd cs trig +v out figure 3. typical application example ? dcm, ccm or qr flyback converter with ncp4306 in tsop6 (v cxxxxxx) v bulk c1 r1 d3 c2 tr1 flyback control circuitry m1 drv cs fb vcc c3 ok1 m2 d4 r3 c4 gnd c5 d5 ncp4306 r min_toff r lld +v out vcc min_toff lld gnd cs drv
ncp4306 www. onsemi.com 4 figure 4. typical application example ? primary side flyback converter and ncp4306 in tsop6 v bulk c1 r1 d3 c2 tr1 c6 m2 r5 c8 gnd +v out c7 r3 r4 c5 c4 r3 zcd c3 d4 vcc drv m1 r2 cs comp vcc min_toff gnd cs drv min_ton ncp4306 r min_toff r min_ton primary side flyback controller pin function description table 2. pin function description tsop6 bxxxxxx tsop6 cxxxxxx tsop6 dxxxxxx tsop6 exxxxxx tsop6 fxxxxxx tsop6 gxxxxxx soic8 axxxxxx pin name description 6 6 6 6 6 6 1 vcc supply voltage pin ? 5 5 5 ? 2 min_toff adjust the minimum off time period by connecting resistor to ground 5 ? 4 ? 5 ? 3 min_ton adjust the minimum on time period by connecting resistor to ground 4 4 ? ? ? 4 4 lld this input modulates the driver clamp level and / or turns the driv- er off during light load conditions ? ? ? 4 4 5 5 trig / dis ultrafast turn ? off input that can be used to turn off the sr mosfet in ccm applications in order to improve efficiency. activates disable mode if pulled ? up for more than 100 s 3 3 3 3 3 3 6 cs current sense pin detects if the current flows through the sr mosfet and / or its body diode 2 2 2 2 2 2 7 gnd ground connection for the sr mosfet driver and v cc decoupling capacitor. ground connection for minimum t on and t off adjust resistors, lld and trigger inputs gnd pin should be wired directly to the sr mosfet source terminal / soldering point using kelvin connection 1 1 1 1 1 1 8 drv driver output for the sr mosfet
ncp4306 www. onsemi.com 5 figure 5. internal circuit architecture ? ncp4306 minimum on time generator min_ton cs detection cs min_toff trig/dis drv vcc gnd v cc managment uvlo driver v dd lld disable detection elapsed en minimum off time generator reset elapsed control logic en disable disable detection disable disable trig dv/dt exception time generator en elapsed 10 a v trig drv out ext_adj int_adj ext_adj int_adj int_adj cs_on cs_off cs_reset
ncp4306 www. onsemi.com 6 absolute maximum ratings table 3. absolute maximum ratings rating symbol value unit supply voltage v cc ? 0.3 to 37.0 v trig / dis, min_ton, min_toff, lld input voltage (note 3) v trig / dis , v min_ton , v min_toff , v lld ? 0.3 to v cc v driver output voltage v drv ? 0.3 to 17.0 v current sense input voltage v cs ? 4 to 200 v current sense dynamic input voltage (t pw = 200 ns) v cs_dyn ? 10 to 200 v min_ton, min_toff, lld, trig input current i min_ton , i min_toff , i lld , i trig ? 10 to 10 ma drv pin current (t pw = 10 s) i drv_dyn ? 3 to 12 a vcc pin current (t pw = 10 s) i vcc_dyn 3 a junction to air thermal resistance, 1 oz 1 in2 copper area, soic8 r j ? a_soic8 200 c / w junction to air thermal resistance, 1 oz 1 in2 copper area tsop6 r j ? a_tsop6 250 c / w maximum junction temperature t jmax 150 c storage temperature t stg ? 60 to 150 c esd capability, human body model (except pin cs) (note 1) esd hbm 2000 v esd capability, human body model pin cs esd hbm 600 v esd capability, machine model (note 1) esd mm 200 v esd capability, charged device model (note 1) esd cdm class c1 - stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: except pin cs: human body model 2000 v per jedec standard jesd22 ? a114e. all pins: machine model method 200 v per jedec standard jesd22 ? a115 ? a charged machine model per jedec standard jesd22 ? c101f 2. this device meets latchup tests defined by jedec standard jesd78d. 3. if voltage higher than 22 v is connected to pin, pin input current increases. internal esd clamp contains 24 v zener diode wi th 3 k in series. it is recommended to add serial resistance in case of higher input voltage to limit input pin current. table 4. recommended operating condition parameter symbol min max unit maximum operating voltage v cc 35 v operating junction temperature t j ? 40 125 c
ncp4306 www. onsemi.com 7 electrical characteristics table 5. electrical characteristics ? 40 oc t j 125 oc; v cc = 12 v; c drv = 0 nf; r min_ton = r min_toff = 10 k or internally set values; v lld = 3.0 v or lld internally disabled; v trig / dis = 0 v; v cs = 4 v, unless otherwise noted. typical values are at t j = +25 oc parameter test conditions symbol min typ max unit supply section vcc uvlo v cc rising v ccon 3.7 4.0 4.2 v v cc falling v ccoff 3.2 3.5 3.7 vcc uvlo hysteresis v cchys 0.5 v start ? up delay v cc rising from 0 to v ccon + 1 v @ tr = 10 s t start_del 50 80 s current consumption, t min_ton = t min_toff = 1 s, t lld = 130 s c drv = 0 nf, f cs = 100 khz xaxxxxx i cc 1.8 2.5 ma xbxxxxx 1.7 2.4 c drv = 1 nf, f cs = 100 khz xaxxxxx 2.8 4.0 xbxxxxx 2.1 3.4 c drv = 10 nf, f cs = 100 khz xaxxxxx 12 15 xbxxxxx 6.7 9.0 current consumption i cc 1.4 2.2 ma current consumption below uvlo v cc = v ccoff ? 0.1 v i cc_uvlo 35 60 a current consumption in disable mode t > t lld , v lld = 0.55 v i cc_dis 60 100 a v trig / dis = 5 v; v lld = 0.55 v 60 100 t > t lld , lld set internally 37 80 v trig / dis = 5 v, lld set internally 37 80 driver output output voltage rise ? time c drv = 10 nf, 10 % to 90 % v drvmax , v cs = 4 to ? 1 v t r 60 100 ns output voltage fall ? time c drv = 10 nf, 90 % to 10 % v drvmax , v cs = ? 1 to 4 v t f 25 45 ns driver source resistance r drv_source 2 driver sink resistance r drv_sink 0.5 output peak source current i drv_source 2 a output peak sink current i drv_sink 7 a maximum driver pulse length t drv_on_max 4 ms maximum driver output voltage v cc = 35 v, c drv > 1 nf, (ver. xaxxxxx) v drvmax 9 10 11 v v cc = 35 v, c drv > 1 nf, (ver. xbxxxxx) 4.5 5.0 5.5 minimum driver output voltage v cc = v ccoff + 200 mv, (ver. xaxxxxxx) v drvmin 3.4 3.7 3.9 v v cc = v ccoff + 200 mv, (ver. xbxxxxxx) 3.4 3.7 3.9 cs input total propagation delay from cs to drv output on v cs goes down from 4 to ? 1 v, t f_cs <= 5 ns t pd_on 30 60 ns total propagation delay from cs to drv output off v cs goes up from ? 1 to 4 v, t r_cs <= 5 ns t pd_off 13 23 ns turn on cs threshold voltage v th_cs_on ? 120 ? 75 ? 40 mv turn off cs threshold voltage guaranteed by design v th_cs_off ? 1 0 mv turn off timer reset threshold volt- age v th_cs_reset 0.4 0.5 0.6 v cs leakage current v cs = 200 v i cs_leakage 500 na dv / dt detector high threshold v cs_dvdt_h 3.0 v
ncp4306 www. onsemi.com 8 table 5. electrical characteristics (continued) ? 40 oc t j 125 oc; v cc = 12 v; c drv = 0 nf; r min_ton = r min_toff = 10 k or internally set values; v lld = 3.0 v or lld internally disabled; v trig / dis = 0 v; v cs = 4 v, unless otherwise noted. typical values are at t j = +25 oc parameter unit max typ min symbol test conditions cs input dv / dt detector low threshold v cs_dvdt_l 0.5 v dv / dt detector threshold (note 4) ver. xxdxxxx t dv / dt 13 25 37 ns trigger disable input minimum trigger pulse duration v trig / dis = 5 v; shorter pulses may not be proceeded t trig_pw_min 10 ns trigger threshold voltage v trig_th 1.6 2.0 2.2 v trigger to drv propagation delay v trig / dis goes from 0 to 5 v, t r_trig / dis <= 5 ns t pd_trig 10.0 16.5 ns trigger blank time after drv turn ? on event v cs drops below v th_cs_on t trig_blank 30 55 80 ns delay to disable mode v trig / dis goes from 0 to 5 v t dis_tim 75 100 125 s disable recovery timer v trig / dis goes down from 5 to 0 v; t min_toff = 130 ns t dis_rec 1.5 3.0 s minimum pulse duration to disable mode end v trig / dis = 0 v; shorter pulses may not be proceeded t dis_end 200 ns pull down current v trig / dis = 5 v i trig / dis 7 11 15 a maximum transition time v trig / dis goes from 1 to 3 v or from 3 to 1 v t trig_tran 10 s minimum t on and t off adjust minimum t on time r min_ton = 0 (ver. xxxzxxx) t on_min 55 ns minimum t off time r min_toff = 0 (ver. xxxxzxx) t off_min 70 ns minimum t on time r min_ton = 10 k (ver. xxxzxxx) t on_min 0.90 1.00 1.10 s minimum t off time r min_toff = 10 k (ver. xxxxzxx) t off_min 0.90 1.00 1.10 s minimum t on time r min_ton = 50 k (ver. xxxzxxx) t on_min 4.50 5.00 5.50 s minimum t off time r min_toff = 50 k (ver. xxxxzxx) t off_min 4.40 4.90 5.40 s internal minimum t on time t on_min = 130 ns, (ver. xxxaxxx) t on_min ? 20% t on_min +20% ns t on_min = 220, 310, 400 ns (ver. xxx[b ? d]xxx) t on_min ? 15% t on_min +15% ns t on_min = 500, 600, 800, 1000, 1200, 1400, 1700, 2000 ns (ver. xxx[e ? l]xxx) t on_min ? 10% t on_min +10% ns internal minimum t off time t off_min = 0.9, 1.0, 1.1, 1.2, 1.4, 1.6, 1.8, 2.0, 2.2, 2.4, 2.6, 2.9, 3.2, 3.5, 3.9 s (ver. xxxx[a ? o]xx) t off_min ? 10% t off_mi n +10% s lld adjust lld pull up current (ver. xxxxxzx) i lld ? 21 ? 20 ? 19 a lld time selection ic disabled v lld 0.3 v t lld = 68 s 0.40 0.51 0.63 t lld = 130 s 0.75 0.89 1.03 t lld = 280 s 1.15 1.32 1.50 t lld = 540 s 1.68 1.82 1.97 t lld = 1075 s 2.20 2.50 2.70 lld function disabled 3.10 lld main time v lld = 0.51 v or ver. xxxxxax t lld 53 68 83 s v lld = 0.89 v or ver. xxxxxbx 100 130 160 v lld = 1.32 v or ver. xxxxxcx 220 280 340 v lld = 1.82 v or ver. xxxxxdx 420 540 660 v lld = 2.45 v or ver. xxxxxex 840 1075 1310
ncp4306 www. onsemi.com 9 table 5. electrical characteristics (continued) ? 40 oc t j 125 oc; v cc = 12 v; c drv = 0 nf; r min_ton = r min_toff = 10 k or internally set values; v lld = 3.0 v or lld internally disabled; v trig / dis = 0 v; v cs = 4 v, unless otherwise noted. typical values are at t j = +25 oc parameter unit max typ min symbol test conditions lld adjust lld reduced time disable mode activated t lld_red 0.5 t lld s lld blanking time t lld_blk 0.25 t lld s disable recovery time t min_toff = 130 ns t lld_dis_rec 1.5 3.0 s exception timer exception time (ver. xxhxxxx) t exc 4 t min_ton s exception timer ratio accuracy ratio exc ? 15 +15 % 4. test signal: v cs [v] 4.0 1.5 ? 1.0 t [ns] t dv/dt v cs_dvdt_h v cs_dvdt_l figure 6. test signal
ncp4306 www. onsemi.com 10 typical characteristics 3,3 3,4 3,5 3,6 3,7 3,8 3,9 4,0 4,1 4,2 ? 40 ? 20 0 20 40 60 80 100 120 v cc on v cc off figure 7. v ccon and v ccoff levels t j [ c] v cc [v] 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 0 5 10 15 20 25 30 35 t j = 125 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 0 5 10 15 20 25 30 35 t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c figure 8. current consumption v cs = 4 v v cc [v] i cc [ma] figure 9. current consumption, f cs = 100 khz, c drv = 1 nf, ver. xaxxxxx figure 10. current consumption, f cs = 100 khz, ver. xaxxxxx v cc [v] i cc [ma] 0 2 4 6 8 10 12 14 ? 40 ? 200 20406080100120 c drv = 0 nf c drv = 1 nf c drv = 10 nf i cc [ma] t j [ c] 0,0 0,5 1,0 1,5 2,0 2,5 0 5 10 15 20 25 30 35 figure 11. current consumption, f cs = 100 khz, ver. xbxxxxx 0 1 2 3 4 5 6 7 8 9 10 ? 40 ? 20 0 20 40 60 80 100 120 figure 12. current consumption, f cs = 100 khz, c drv = 1 nf, ver. xbxxxx i cc [ma] t j [ c] i cc [ma] v cc [v] t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c c drv = 0 nf c drv = 1 nf c drv = 10 nf
ncp4306 www. onsemi.com 11 0 10 20 30 40 50 60 ? 40 ? 20 0 20 40 60 80 100 120 20 30 40 50 60 70 80 90 100 ? 40 ? 20 0 20 40 60 80 100 120 figure 13. current consumption below uvlo, v cc = v ccoff ? 0.1 v t j [ c] i cc_uvlo [ a] i cc_dis [ a] t j [ c] figure 14. current consumption in disable mode v cs = 4 v, t > t lld 20 30 40 50 60 70 80 90 100 ? 40 ? 200 20406080100120 0 20 40 60 80 100 120 0 5 10 15 20 25 30 35 figure 15. current consumption in disable mode, v trig/dis = 5 v figure 16. current consumption in disable mode, v cs = 4 v, t > t lld 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 ? 1,0 ? 0,9 ? 0,8 ? 0,7 ? 0,6 ? 0,5 ? 0,4 ? 0,3 ? 0,2 ? 0,1 0,0 ? 1 ? 0,8 ? 0,6 ? 0,4 ? 0,2 0 0,2 0,4 0,6 0,8 1 figure 17. current consumption in disable mode, v trig/dis = 5 v figure 18. cs input current i cc_dis [ a] i cc_dis [ a] i cc_dis [ a] i cs [ma] t j [ c] v cc [v] v cs [v] v cc [v] t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c
ncp4306 www. onsemi.com 12 figure 19. supply current vs. cs voltage ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 40 ? 20 0 20 40 60 80 100 120 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 2,2 ? 1,0 ? 0,8 ? 0,6 ? 0,4 ? 0,2 0,0 0,2 0,4 0,6 0,8 1,0 figure 20. cs turn ? on threshold i cc [ma] v cs [v] v th_cs_on [mv] t j [ c] ? 2,0 ? 1,5 ? 1,0 ? 0,5 0,0 0,5 1,0 ? 40 ? 200 20406080100120 0,40 0,45 0,50 0,55 0,60 ? 40 ? 20 0 20 40 60 80 100 120 0 100 200 300 400 500 ? 40 ? 20 0 20 40 60 80 100 120 10 15 20 25 30 35 40 45 50 55 60 ? 40 ? 20 0 20 40 60 80 100 120 figure 21. cs turn ? off threshold figure 22. cs reset threshold figure 23. cs input leakage v cs = 200 v figure 24. propagation delay from cs to drv output on t j [ c] t j [ c] t j [ c] t j [ c] v th_cs_off [mv] v th_cs_reset [v] i cs_leakage [na] t pd_on [ns] t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c
ncp4306 www. onsemi.com 13 figure 25. propagation delay from cs to drv output off 4 6 8 10 12 14 16 18 20 22 24 ? 40 ? 200 20406080100120 figure 26. trigger pin threshold 1,0 1,2 1,4 1,6 1,8 2,0 2,2 0 5 10 15 20 25 30 35 t j [ c] t pd_off [ns] v cc [v] v trig_th [v] 1,7 1,8 1,9 2,0 2,1 2,2 2,3 ? 40 ? 20 0 20 40 60 80 100 120 7 8 9 10 11 12 13 14 15 ? 40 ? 20 0 20 40 60 80 100 120 figure 27. trigger pin threshold figure 28. trigger pin pull down current 3 5 7 9 11 13 15 17 ? 40 ? 20 0 20 40 60 80 100 120 t j [ c] t j [ c] t j [ c] figure 29. propagation delay from trig to drv output off figure 30. delay to disable mode, v trig/dis = 5 v v trig_th [v] i trig/dis [ a] t pd_trig [ns] 80 85 90 95 100 105 110 115 120 ? 40 ? 20 0 20 40 60 80 100 120 t dis_tim [ s] t j [ c] t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c
ncp4306 www. onsemi.com 14 figure 31. minimum on time r min_ton = 10 k 0,90 0,92 0,94 0,96 0,98 1,00 1,02 1,04 1,06 1,08 1,10 ? 40 ? 20 0 20 40 60 80 100 120 4,5 4,6 4,7 4,8 4,9 5,0 5,1 5,2 5,3 5,4 5,5 ? 40 ? 20 0 20 40 60 80 100 120 figure 32. minimum on time r min_ton = 50 k 0,90 0,92 0,94 0,96 0,98 1,00 1,02 1,04 1,06 1,08 1,10 ? 40 ? 20 0 20 40 60 80 100 120 4,4 4,5 4,6 4,7 4,8 4,9 5,0 5,1 5,2 5,3 5,4 ? 40 ? 20 0 20 40 60 80 100 120 figure 33. minimum on time r min_toff = 10 k figure 34. minimum on time r min_toff = 50 k ? 25,0 ? 20,0 ? 15,0 ? 10,0 ? 5,0 0,0 0 5 10 15 20 25 30 35 figure 35. lld current, v lld = 3.0 v figure 36. lld current, v lld = 2.5 v t j [ c] t min_ton [ s] t min_toff [ s] i lld [ a] t j [ c] t min_ton [ s] t j [ c] t j [ c] v cc [v] t min_toff [ s] t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c ? 22,0 ? 21,5 ? 21,0 ? 20,5 ? 20,0 ? 19,5 ? 19,0 ? 18,5 ? 18,0 0 5 10 15 20 25 30 35 i lld [ a] v cc [v] t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c
ncp4306 www. onsemi.com 15 figure 37. lld current figure 38. lld time, v lld = 1.82 v (or internal option) 440 460 480 500 520 540 560 580 600 620 640 ? 40 ? 200 20406080100120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ? 15.0 ? 16.0 ? 17.0 ? 18.0 ? 19.0 ? 20.0 ? 21.0 ? 22.0 ? 23.0 ? 24.0 ? 25.0 v lld [v] i lld [ a] t j [ c] t lld [ s] 9,0 9,2 9,4 9,6 9,8 10,0 10,2 10,4 ? 40 ? 20 0 20 40 60 80 100 120 v cc = 12 v, c drv = 0 nf v cc = 12 v, c drv = 1 nf v cc = 12 v, c drv = 10 nf v cc = 35 v, c drv = 0 nf v cc = 35 v, c drv = 1 nf v cc = 35 v, c drv = 10 nf 4,3 4,5 4,7 4,9 5,1 5,3 5,5 ? 40 ? 20 0 20 40 60 80 100 120 v drv [v] t j [ c] t j [ c] v drv [v] 13 18 23 28 33 38 ? 40 ? 20 0 20 40 60 80 100 120 figure 39. driver output voltage, ver. xaxxxxx figure 40. driver output voltage, ver. xbxxxxx 3,4 3,6 3,8 4,0 4,2 4,4 4,6 ? 40 ? 20 0 20 40 60 80 100 120 figure 41. dv/dt detector time threshold, ver. xxdxxxx figure 42. exception timer ratio to t min_ton , ver. xxhxxxx t j [ c] t j [ c] t dv/dt [ns] ratio exc [ ? ] t j = 125 c t j = 105 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ? 20 c t j = ? 40 c v cc = 12 v, c drv = 0 nf v cc = 12 v, c drv = 1 nf v cc = 12 v, c drv = 10 nf v cc = 35 v, c drv = 0 nf v cc = 35 v, c drv = 1 nf v cc = 35 v, c drv = 10 nf
ncp4306 www. onsemi.com 16 general description the ncp4306 is designed to operate either as a standalone ic or as a companion ic to a primary side controller to help achieve efficient synchronous rectification in switch mode power supplies. this controller features a high current gate driver along with high ? speed logic circuitry to provide appropriately timed drive signals to a synchronous rectification mosfet. with its novel architecture, the ncp4306 has enough versatility to keep the synchronous rectification system efficient under any operating mode. the ncp4306 works from an available voltage with range from 4.0 / 3.5 v to 35 v (typical). the wide v cc range allows direct connection to the smps output voltage of most adapters such as notebooks, cell phone chargers and lcd tv adapters. precise turn ? off threshold of the current sense comparator together with an accurate offset current source allows the user to adjust for any required turn ? off current threshold of the sr mosfet switch using a single resistor. compared to other sr controllers that provide turn ? off thresholds in the range of ? 10 mv to ? 5 mv, the ncp4306 offers a turn ? off threshold of 0 mv. when using a low r ds_on sr (1 m ? ) mosfet our competition, with a ? 10 mv turn off, will turn off with 10 a still flowing through the sr fet, while our 0 mv turn off turns off the fet at 0 a; significantly reducing the turn ? off current threshold and improving efficiency. many of the competitor parts maintain a drain source voltage across the mosfet causing the sr mosfet to operate in the linear region to reduce turn ? off time. thanks to the 6 a sink current of the ncp4306 significantly reduces turn off time allowing for a minimal drain source voltage to be utilized and efficiency maximized. to overcome false triggering issues after turn ? on and turn ? off events, the ncp4306 provides adjustable minimum on ? time and off ? time blanking periods. blanking times can be set internally during production or adjusted independently of ic vcc using external resistors connected to gnd (internal or external option depends on ic variant). if needed, externally set blanking periods can be modulated using additional components. an extremely fast turn ? off comparator, implemented on the current sense pin, allows for ncp4306 implementation in ccm applications without any additional components or external triggering. an ultrafast trigger input offers the possibility to further increase efficiency of synchronous rectification systems operated in ccm mode (for example, ccm flyback or forward). the time delay from trigger input to driver turn off event is t pd_trig . additionally, the trigger input can be used to disable the ic and activate a low consumption standby mode. this feature can be used to decrease standby consumption of an smps. if the trigger input is not wanted than the trigger pin can be tied to gnd. an output driver features capability to keep sr transistor turned ? off even when there is no supply voltage for the ncp4306. sr transistor drain voltage goes up and down during smps operation and this is transferred through drain gate capacitance to gate and may open transistor. the ncp4306 keeps drv pin pulled low even without any supply voltage and thanks to this the risk of turned ? on sr transistor before enough v cc is applied to the ncp4306 is eliminated. finally, the ncp4306 features a light load detection function that can be set internally or externally at lld pin by resistor connected to ground. this function detects light load or no load conditions and during them between conduction phases it decreases current consumption. this helps to improve smps efficiency. if lld function is not needed pin can be left open.
ncp4306 www. onsemi.com 17 supply section supply voltage should be connected to vcc pin. minimum voltage for proper operation is 4.0 / 3.5 v typically and maximum level is 35 v. decoupling capacitor between vcc and gnd pin is needed for proper operation and its recommended value is 1 f. if ic is supplied from smps output voltage, few ohm resistor is recommended between smps output voltage and vcc pin. resistor task is to divide decoupling cap from output to avoid closing hf currents through ncp4306 decoupling cap, because these currents may causes drops at gnd connection that affects sr transistor sensing and incorrect sr transistor turn ? off. sr transistor is usually used in low side configuration (placed in return path), but it may be also used in high side configuration (placed in positive line). it is not possible to use smps v out for sr supply in high side configuration so it is needed to p rovide supply differently. one possibility is to use auxiliary winding as shown in figure 43 . voltage from auxiliary winding is rectified, filtered and use as supply voltage. figure 43. high side configuration supplied from auxiliary winding c1 gnd +v out d5 ok1 r3 m2 m1 r1 cs fb v cc d1 drv d2 c3 c1 r2 c2 d3 c5 c4 r6 d4 tr1 r7 r8 r9 ncp4306 flyback control circuitry if auxiliary winding is not acceptable, transformer forward voltage can be used as supply source (figure 44). forward voltage is regulated by simple voltage regulator to fit ncp4306 vcc restriction. penalty for this solution is slightly lower efficiency. figure 44. high side configuration supplied from transformer forward voltage v bulk +v out c1 r2 c2 fb cs drv d2 c3 d1 d3 m1 r1 r3 ok1 d6 gnd c6 m2 d4 d5 r6 r7 c4 c5 r8 r9 flyback controll ncp4306
ncp4306 www. onsemi.com 18 auxiliary winding or forward voltage can be used as supply source also for low side configuration if v out is not high enough (figure 45). do not focus just on sr controller uvlo, but also on sr transistor characteristics. some transistors may be not turned ? on enough even at 5 v so in these case sr controller supply voltage should be increased. figure 45. low side configuration supplied from transformer forward voltage for low v out smps c6 r2 r5 c5 c4 r4 zcd r3 c1 r1 c2 d3 d4 c3 v cc drv m1 cs comp v bulk d4 r6 r7 m2 d5 r8 c7 c8 +v out < 5v gnd c9 ncp4306 primary side flyback controller current sense input figure 46 shows the internal connection of the cs circuitry on the current sense input. when the voltage on the secondary winding of the smps reverses, the body diode of m1 starts to conduct current and the voltage of m1?s drain drops approximately to ? 1 v. once the voltage on the cs pin is lower than v th_cs_on threshold, m1 is turned ? on. because of parasitic impedances, significant ringing can occur in the application. to overcome false sudden turn ? off due to mentioned ringing, the minimum conduction time of the sr mosfet is activated. minimum conduction time can be adjusted using the r min_ton resistor or can be chosen from internal fixed values. figure 46. current sensing circuitry functionality sr mosfet + v out m1 to internal logic cs_reset high dv / dt cs_off cs_on v th_cs_reset dv / dt detector v th_cs_on +
ncp4306 www. onsemi.com 19 the sr mosfet is turned ? off as soon as the voltage on the cs pin is higher than v th_cs_off (typically ? 0 .5 mv). for the same ringing reason, a minimum off ? time timer is asserted once the v cs goes above v th_cs_reset . the minimum off ? time can be externally adjusted using r min_toff resistor or can be chosen from internally fixed values (depends on version) . the minimum off ? time generator can be re ? triggered by min_toff reset comparator if some spurious ringing occurs on the cs input after sr mosfet turn ? off event. this feature significantly simplifies sr system implementation in flyback converters. in an llc converter the sr mosfet m1 channel conducts while secondary side current is decreasing (refer to figure 47) . therefore the turn ? off current depends on mosfet r dson . the ? 0 .5 mv threshold provides an optimum switching period usage while keeping enough time margin for the gate turn ? off. to ensure proper switching, the min_t off timer is reset, when the v ds of the mosfet rings and falls down past the v th_cs_reset . the minimum off ? time needs to expire before another drive pulse can be initiated. minimum off ? time timer is started again when v ds rises above v th_cs_reset . figure 47. cs input comparators thresholds and blanking periods timing in llc v ds = v cs i sec v th_cs_reset v th_cs_off v drv min on ? time min off ? time v th_cs_on turn on delay turn off delay t min_ton t min_toff min t off timer was stopped here because of v cs ncp4306 www. onsemi.com 20 figure 48. cs input comparators thresholds and blanking periods timing in flyback v th_cs_reset v th_cs_off v drv min on ? time min off ? time v th_cs_on turn on delay turn off delay min t off timer was stopped here because of v cs ncp4306 www. onsemi.com 21 figure 49. sr system connection including mosfet and layout parasitic inductances in a) llc and b) flyback application v l_layout v l_drain v rds_on v l_source v l_layout i sec v ds l layout to v cc l source r ds_on l drain mosfet equivalent circuit ncp4306 100 nf 1 f decoupling capacitors v l_layout v l_drain v rds_on v l_source v l_layout i sec v ds l layout l source r ds_on l drain mosfet equivalent circuit ncp4306 decoupling capacitors l layout to v cc v l_layout v l_drain v rds_on v l_source v l_layout i sec v ds l layout l source r ds_on l drain mosfet equivalent circuit ncp4306 decoupling capacitors l layout 1 f 100 nf a) b)
ncp4306 www. onsemi.com 22 figure 50. waveforms from sr system implemented in a) llc and b) flyback application and using mosfet in to220 package with long leads ? sr mosfet channel conduction time is reduced a) b) note that the ef ficiency impact caused by the error voltage due to the parasitic inductance increases with lower mosfets r ds_on and / or higher operating frequency. it is thus beneficial to minimize sr mosfet package leads length in order to maximize application ef ficiency. the optimum solution for applications with high secondary current i / t and high operating frequency is to use lead ? less sr mosfet i.e. sr mosfet in smt package. the parasitic inductance of a smt package is negligible causing insignificant cs turn ? off threshold shift and thus minimum impact to efficiency (refer to figure 51). figure 51. waveforms from sr system implemented in a) llc b) flyback application and using mosfet in smt package with minimized parasitic inductance ? sr mosfet channel conduction time is optimized a) b)
ncp4306 www. onsemi.com 23 it can be deduced from the above paragraphs on the induced error voltage and parameter tables that turn ? off threshold precision is quite critical. if we consider a sr mosfet with r ds_on of 1 m , the 1 mv error voltage on the cs pin results in a 1 a turn ? off current threshold difference; thus the pcb layout is very critical when implementing the sr system. note that the cs turn ? off comparator is referred to the gnd pin. any parasitic impedance (resistive or inductive ? even on the magnitude of m and nh values) can cause a high error voltage that is then evaluated by the cs comparator. ideally the cs turn?off comparator should detect voltage that is caused by secondary current directly on the sr mosfet channel resistance. in reality there will be small parasitic impedance on the cs path due to the bonding wires, leads and soldering. to assure the best efficiency results, a kelvin connection of the sr controller to the power circuitry should be implemented. the gnd pin should be connected to the sr mosfet source soldering point and current sense pin should be connected to the sr mosfet drain soldering point ? refer to figure 49. using a kelvin connection will avoid any impact of pcb layout parasitic elements on the sr controller functionality; sr mosfet parasitic elements will still play a role in attaining an error voltage. figure 52 and figure 53 show examples of sr system layouts using mosfets in d2pak and so8fl packages. figure 52. recommended layout when using sr mosfet in d2pak package figure 53. recommended layout when using sr mosfet in smt package so8 fl trigger / disable input the ncp4306 features an ultrafast trigger input that exhibits a maximum of t pd_trig delay from its activation to the start of sr mosfet turn ? off of process. this input can be used in applications operated in deep continues conduction mode (ccm) to further increase ef ficiency and / or to activate disable mode of the sr driver in which the consumption of the ncp4306 is reduced to maximum of i cc_dis . ncp4306 is capable to turn ? off the sr mosfet reliably in ccm applications just based on cs pin information only, without using the trigger input. however, natural delay of the zcd comparator and drv turn ? off delay increase overlap between primary and secondary mosfets switching (also known as cross conduction). if one wants to achieve absolutely maximum efficiency with deep ccm applications, then the trigger signal coming from the primary side should be applied to the trigger pin. it is good to set trigger pulse in way there is just short overlap between primary and secondary switches. short overlap is usually advantageous than leaving end of conduction phase on body diode. reason is body diode has usually longer recovery time and resulting overlap time (simultaneously conduction primary and secondary side switches) is longer. there are several possibilities for transferring the trigger signal from the primary to the secondary side ? refer to figure 68 and figure 69 . the trigger signal is blanked for t trig_blank after the drv turn ? on process has begun. the blanking technique is used to increase trigger input noise immunity against the parasitic ringing that is present during the turn on process due to the smps layout. the trigger input is supersedes the cs input except trigger blanking period . trig / dis signal turns the sr mosfet off or prohibits its turn ? on when the trig / dis pin is pulled above v trig_th . the sr controller enters disable mode when the trigger pin is pulled ? up for more than t dis_tim . in disable mode the ic consumption is significantly reduced. to recover from disable mode and enter normal operation, the trig / dis pin has to be pulled low at least for t dis_end .
ncp4306 www. onsemi.com 24 v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset t1 t2 t3 t4 t5 t6 t7 t8 t9 t figure 54. t rigger input functionality waveforms using the trigger to turn ? off and block the drv signal figure 54 shows basic trig / dis input functionality. at t1 the trig / dis pin is pulled low to enter into normal operation. at t2 the cs pin is dropped below the v th_cs_on , signaling to the ncp4306 to start to turn the sr mosfet on. at t3 the ncp4306 begins to drive the mosfet. at t4, the sr mosfet is conducting and the trig / dis pin is pulled high. this high signal on the trig / dis pin almost immediately turns off the drive to the sr mosfet, turning off the mosfet. the drv is not turned ? on in other case (t6) because the trigger pin is high in the time when cs pin signal crosses turn ? on threshold. this figure clearly shows that the drv can be asserted only on falling edge of the cs pin signal in case the trigger input is at low level (t2). figure 55. trigger input functionality waveforms ? trigger blanking v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset t1 t2 t3 t trig / dis blank min on ? time t trigblank in figure 55 above, at time t1 the cs pin falls below the v th_cs_on while the trigger is low setting in motion the drv signal that appears at t2. at time t2 the drv signal and trigger blanking clock begin. trig / dis signal goes high shortly after time t2. due to the trigger blanking clock (t trig_blank ) the trigger?s high signal does not affect the drv signal until the t trig_blank timer has expired. at time t3 the trig / dis signal is reevaluated and the drv
ncp4306 www. onsemi.com 25 signal is turned off. the trig / dis input is blanked for t trig_blank after drv set signal to avoid undesirable behavior during sr mosfet turn ? on event. the blanking time in combination with high threshold voltage (v trig_th ) prevent triggering on ringing and spikes that are present on the trig / dis input pin during the sr mosfet turn ? on process. controller?s response to the narrow pulse on the trig / dis pin is depicted in figure 55 ? this short trigger pulse enables to turn the drv on for t trig_blank . note that this case is valid only if device not entered disable mode before. figure 56. trigger input functionality waveforms ? trigger blanking acts like a filter v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset trig / dis blank min on ? time v trig_blank t1 t2 t3 t4 t5 t6 t0 t figure 56 above shows almost the same situation as in figure 55 with one main exception; the trig / dis signal was not high after trigger blanking timer expired so the drv signal remains high. the advantage of the trigger blanking time during drv turn ? on is evident from figure 56 since it acts like a filter on the trig / dis pin. rising edge of the drv signal may cause spikes on the trigger input. if it wasn?t for the trig / dis blanking these spikes, in combination with ultra ? fast performance of the trigger logic, could turn the sr mosfet off in an inappropriate time. figure 57. trigger input functionality waveforms ? trigger over ride, cs turn off and min on ? time v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min on ? time t1 t2 t3 t4 t5 t6 t0 t t7 t8
ncp4306 www. onsemi.com 26 figure 57 depicts all possible driver turn ? off events in details when correct v cc is applied. controller driver is disabled based on trig / dis input signal in time t2; the trig / dis input overrides the minimum on ? time period. driver is turned ? off according to the cs (v ds ) signal (t5 marker) and when minimum on ? time period elapsed already. trig / dis signal needs to be low during this event. if the cs (v ds ) voltage reaches v th_cs_off threshold before minimum on ? time period ends (t7) and the trig / dis pin is low the drv is turned ? off on the falling edge of the minimum on ? time period (t8 time marker in figure 57). this demonstrates the fact that the trigger over rides the minimum on ? time. minimum on ? time has higher priority than the cs signal. in figure 58 the trig / dis input is low the whole time and the drv pulses are purely a function of the cs signal and the minimum on ? time. the first drv pulse terminated based on the cs signal and another two drv pulses are prolonged till the minimum on ? time period end despite the cs signal crosses the v th_cs_off threshold earlier. if a minimum on ? time is too long the situation that occurs after time marker t6 figure 58 can occur, is not correct and should be avoided. the minimum t on period should be selected shorter to overcome situation that the sr mosfet is turned ? on for too long time. the secondary current then changes direction and energy flows back to the transformer that result in reduced application efficiency and also in excessive ringing on the primary and secondary mosfets. figure 58. minimum on ? time priority v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min on ? time t1 t2 t3 t4 t5 t6 t0 t t7 t8 t9 figure 59 shows ic behavior in case the trigger signal features two pulses during one cycle of the v ds (cs) signal. the trig / dis goes low enables the drv just before time t1 and drv turns ? on because the v ds voltage drops under v th_cs_on threshold voltage. the trig / dis signal disables driver at time t2. the trig / dis drops down to low level in time t3, but ic waits for complete minimum off ? time. minimum off ? time execution is blocked until cs pin voltage goes above v th_cs_reset threshold. next cycle starts in time t6. the trig / dis goes low and enables the drv before v ds drops below v th_cs_on threshold voltage thus the drv turns ? on in time t6. the trig / dis signal rises up to high level at time t7, consequently drv turns ? off and ic waits for high cs voltage to start minimum off ? time execution.
ncp4306 www. onsemi.com 27 figure 59. trig / dis input functionality waveforms ? two pulses at one cycle v ds =v cs v th_cs_reset v th_cs_off v th_cs_on v trig/dis v drv min off ? time min on ? time t1 t2 t3 t4 t5 t6 t0 t t7 t8 t9 t10 figure 60. trigger input functionality waveforms ? disable mode activation power consumption v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min on ? time t1 t2 t3 t4 t0 t t dis_tim in figure 60 above, at t2 the cs pin rises to v th_cs_off and the sr mosfet is turned ? off. at t3 the trig / dis signal is held high for more than t dis_tim . ncp4306 enters disable mode after t dis_tim . driver output is disabled in disable mode. the drv stays low (disabled) during transition to disable mode. figure 61 shows disable mode transition 2nd case ? i.e. when trigger rising edge comes during the trigger blank period. figure 62 shows entering into disable mode and back to normal sequences .
ncp4306 www. onsemi.com 28 figure 61. trigger input functionality waveforms ? disable mode clock initiation v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min on ? time t1 t2 t3 t0 t power consumption t trigblank t dis_tim figure 62. trigger input functionality waveforms ? disable and normal modes v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min off ? time t1 t2 t3 t0 t power consumption t dis_tim t dis_rec disable mode t4
ncp4306 www. onsemi.com 29 figure 63 and figure 64 shows exit from disable mode in detail. ncp4306 requires time up to t dis_rec to recover all internal circuitry to normal operation mode when recovering from disable mode. the driver is then enabled after complete t min_toff period when cs (v ds ) voltage is over v th_cs_reset threshold. driver turns ? on in the next cycle on cs (v ds ) falling edge signal only (t5 ? figure 63). the drv stays low during recovery time period. trig / dis input has to be low at least for t dis_end time to end disable mode and start with recovery. trigger can go back high after t dis_end without recovery interruption. figure 63. trigger input functionality waveforms ? exit from disable mode before the falling edge of the cs signal v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min on ? time t1 t2 t3 t0 t power consumption t4 t5 t6 t7 t8 disable mode normal mode time rec waits for complete t min_toff note: rec time = recovery time
ncp4306 www. onsemi.com 30 figure 64. trigger input functionality waveforms disable mode normal mode time rec waits for complete t min_toff t dis_end v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min off ? time t1 t2 t0 power consumption t3 t5 t4 t note: rec time = recovery time figure 65. trigger input functionality waveforms disable mode normal mode recovery t min_toff v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min off ? time t1 t2 t0 t power consumption t3 t5 t4 t t dis_rec t6 t7 t8 waits for complete t min_toff
ncp4306 www. onsemi.com 31 figure 65 shows detail ic behavior after disable mode is ended. the trigger pin voltage goes low at t1 and after t dis_rec ic leaves disable mode (t2). t ime interval between t2 and t3 is too short for complete minimum off ? time so normal mode doesn?t start. v ds voltage goes high again at time t4 and this event starts new minimum off ? time timer execution. next v ds falling edge below v th_cs_on level activates driver. figure 66. trigger input functionality waveforms v ds = v cs v th_cs_on v trig / dis v drv v th_cs_off v th_cs_reset min off ? time t1 t2 t0 power consumption t3 t5 t4 t t6 t7 t8 disable mode normal mode recovery waits for complete t min_toff t min_toff t dis_rec different situation of leaving from disable mode is shown at figure 66. minimum off ? time execution starts at time t2, but before time elapses v ds voltage falls to negative voltage. this interrupts minimum off ? time execution and the ic waits to another time when v ds voltage is positive and then is again started the minimum off ? time timer. the ic returns into normal mode after whole minimum off ? time elapses. figure 67. ncp4306 operation after start ? up event v ds = v cs v th_cs_on v ccon v cc v th_cs_off v th_cs_reset min on ? time t min_ton v drv min off ? time t min_toff t min_toff not complete t min_toff ? ic is not activated complete t min_toff ? activates ic t min_toff ? is stopped due to v ds drops below v th_cs_reset t1 t t14 t3 t2 t4 t5 t7 t6 t8 t9 t10 t11 t13 t12
ncp4306 www. onsemi.com 32 start ? up event waveforms are shown at figure 67. a start ? up event is very similar to an exit from disable mode event. the ic waits for a complete minimum off ? time event (cs pin voltage is higher than v th_cs_reset ) until drive pulses can continue. figure 67 shows how the minimum off ? time timer is reset when cs voltage is oscillating through v th_cs_reset level. the ncp4306 starts operation at time t1 (time t1 can be seen as a wake ? up event from the disable mode through trig / dis or lld pin). internal logic waits for one complete minimum off ? time period to expire before the ncp4306 can activate the driver after a start ? up or wake ? up event. the minimum off ? time timer starts to run at time t1, because v cs is higher than v th_cs_reset . the timer is then reset, before its set minimum off ? time period expires, at time t2 thanks to cs voltage lower than v th_cs_reset threshold. the aforementioned reset situation can be seen again at time t3, t4, t5 and t6. a complete minimum off ? time period elapses between times t7 and t8 allowing the ic to activate a driver output after time t8. optional primary triggering techniques for ccm flyback application are shown in figure 68 and figure 69 . ncp4306 can operate properly without triggering in ccm, but use of triggering can reduce the commutation losses and the sr mosfet drain voltage spike, which results in improved efficiency in ccm. figure 68. optional primary triggering in deep ccm application using auxiliary winding v bulk v cc c1 r3 d2 c3 tr1 d3 c2 d1 drv cs fb r2 r1 m1 m2 r4 c6 c4 d4 gnd r5 r6 r7 ok1 c5 d5 r7 ncp4306 + v out flyback control circuitry the application shown in figure 68 is simplest and the most cost effective solution for primary sr triggering. this method uses auxiliary winding made of triple insulated wire placed close to the primary winding section. this auxiliary winding provides information about primary turn ? on event to the sr controller before the secondary winding reverses. this is possible thanks to the leakage between primary and secondary windings that creates natural delay in energy transfer. this technique provides approximately 0.5% efficiency improvement when the application is operated in deep ccm and a transformer that has a leakage of 1% of primary inductance is used.
ncp4306 www. onsemi.com 33 figure 69. optional primary triggering in deep ccm application using trigger transformer v bulk v cc c1 r2 d2 c4 tr1 d3 c3 d1 drv cs fb r3 r1 m1 m2 r4 c7 c6 d4 gnd r5 r6 r7 ok1 c5 d5 r8 ncp4306 + v out flyback control circuitry tr2 application from figure 69 uses an ultra ? small trigger transformer to transfer primary turn ? on information directly from the primary controller driver pin to the sr controller trigger input. because the trigger input is rising edge sensitive, it is not necessary to transmit the entire primary driver pulse to the secondary. the coupling capacitor c5 is used to allow the trigger transformer?s core to reset and also to prepare a needle pulse (a pulse with width shorter than 100 ns) to be transmitted to the ncp4306 trig / dis input. the advantage of needle trigger pulse usage is that the required volt ? second product of the pulse transformer is very low and that allows the designer to use very small and cheap magnetic. the trigger transformer can even be prepared on a small toroidal ferrite core with outer diameter of 4 mm and four turns for primary and secondary windings to assure l primary = l secondary > 10 h. proper safety insulation between primary and secondary sides can be easily assured by using triple insulated wire for one or , better, both windings. this primary triggering technique provides approximately 0.5% efficiency improvement when the application is operated in deep ccm and transformer with leakage of 1% of primary inductance is used. it is also possible to use capacitive coupling (use additional capacitor with safety insulation) between the primary and secondary to transmit the trigger signal. we do not recommend this technique as the parasitic capacitive currents between primary and secondary may affect the trigger signal and thus overall system functionality.
ncp4306 www. onsemi.com 34 minimum t on and t off adjustment the ncp4306 offers fixed or an adjustable minimum on ? time and off ? time blanking periods (depends on ic version) that ease the implementation of a synchronous rectification system in any smps topology. these timers avoid false triggering on the cs input after the mosfet is turned on or off. fixed versions are defined internally and can?t be modified later or changed during operation. the adjustment of minimum t on and t off periods are done based on an internal timing capacitance and external resistors connected to the gnd pin ? refer to figure 70 for a better understanding. figure 70. internal connection of the min_ton generator (the min_toff works in the same way) v dd v ref t min_ton i r_min_ton c t i r_min_ton r min_ton min_ton gnd to internal logic ncp4306 discharge switch current through the min_ton adjust resistor can be calculated as: i r_min_ton v ref r min_ton (eq. 1) if the internal current mirror creates the same current through r min_ton as used the internal timing capacitor (ct) charging, then the minimum on ? time duration can be calculated using this equation. t min_on v t v ref i r_min_ton c t v ref v ref r min_ton c t r min_ton (eq. 2) the internal capacitor size would be too large if i r_min_ton was used. the internal current mirror uses a proportional current, given by the internal current mirror ratio. note that the internal timing comparator delay affects the accuracy of equations 7 and 8 when min_ton or min_toff times are selected near to their minimum possible values. please refer to figure 71 and figure 72 for measured minimum on and off time charts. figure 71. min_ton adjust characteristic figure 72. min_toff adjust characteristic 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 4,5 5,0 0 5 10 15 20 25 30 35 40 45 50 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 4,5 5,0 0 5 10 15 20 25 30 35 40 45 50 t min_ton [ s] r min_ton [k ] t min_toff [ s] r min_toff [k ]
ncp4306 www. onsemi.com 35 the absolute minimum t on duration is internally clamped to 55 ns and minimum t off duration to 70 ns in order to prevent any potential issues with the minimum t on and / or t off input being shorted to gnd. the ncp4306 features dedicated anti ? ringing protection system that is implemented with a minimum t off blank generator. the minimum off ? time one ? shoot generator is restarted in the case when the cs pin voltage crosses v th_cs_reset threshold and min_toff period is active. the total off ? time blanking period is prolonged due to the ringing in the application (refer to figure 47). some applications may require adaptive minimum on and off time blanking periods. it is possible to modulate blanking periods by using an external npn transistor ? refer to figure 73. the modulation signal can be derived based on the load current, feedback regulator voltage or other application parameter. figure 73. possible connection for min_ton and min_toff modulation v dd v ref t min_ton i r_min_ton r min_ton_2 min_ton modulation input gnd to internal logic ncp4306 discharge switch r min_ton i r_min_ton min_ton modulation current dv / dt detection ? flyback feature the ncp4306 includes optional feature for flyback type converters, which operates with shorter primary on ? time than ringing period after demagnetization phase during medium / high loads. these applications are for example usb ? pd or quick charge adapters. difficulty with this situation is that minimum off ? time doesn?t elapse before primary side switch is turned on and off again so sr controller doesn?t turn on sr mosfet. whole secondary side current flows through body diode that makes power loss. figure 74 shows situation without dv / dt detection. here can be seen that without detection next conduction cycle may be not taken through activated sr transistor. reason is not elapsed minimum off ? time blanking interval.
ncp4306 www. onsemi.com 36 figure 74. situation without dv / dt detection feature v th_cs_reset v th_cs_off v drv min off ? time v th_cs_on min on ? time primary on ? time is very short (shorter than ringing period) for low v out t min_toff has to be set to longer time length of ringing period t min_toff turn ? off delay turn ? on delay t min_ton t min_toff t min_toff driver is not turned ? on because t min_toff doesn?t elapse t min_toff timer is stopped here because of v cs< v th_cs_reset v ds = v cs i sec figure 75 shows how system with activated dv / dt detection behaves. min_toff blanking interval is also reset during voltage drops at cs pin, but if high negative dv / dt occurs at cs pin, min_toff interval is shorted and sr controller is ready to detect cs voltage lower than v cs_th_on and turn sr transistor on. negative dv / dt at cs pin after primary switch is turned off is high in compare to slope that comes during ringing after demagnetization. thanks to this we can safely detect end of primary on ? time from ringing. figure 75. situation with enabled dv / dt detection v th_cs_reset v th_cs_off min off ? time v th_cs_on min on ? time turn ? on delay turn ? off delay negative dv / dt detector at cs pin v drv t min_toff t min_toff t min_toff cs voltage drops below v th_cs_on but at time when min t off doesn?t elapse and just low dv / dt is detected so drv is not activated t min_toff timer is stopped here because of v cs < v th_cs_reset t min_toff timer doesn?t elapse but high dv / dt is detected so drv is enable t min_toff has to be set to longer time than length of ringing period v ds = v cs i sec t min_ton exception timer ? llc feature exception timer is special feature for llc type smps. it is mainly targeted to operation under light / medium load, where secondary side smps current shape is not sine, but it contains part of capacitive peak optionally with no current part followed by distorted sine. examples of current shape is shown in figure 76 . this figure shows different current shapes at different loading. lower loading makes shape more distorted from ideal sine.
ncp4306 www. onsemi.com 37 figure 76. current shapes in llc examples t i sec problematic shapes may cause prematurely sr transistor turn ? off, because cs voltage may get to zero or to positive voltage (due to low current or high di / dt and parasitic inductance). sensed voltage drop can be seen in figure 77. this sit uation is valid for sr mosfet with r dson = 1 m and with package (smt) parasitic inductance l pacpar = 0.5 nh. there can be seen that sr transistor should be turned off in time between 0.4 to 1.5 s, because cs voltage is above v th_cs_off threshold. turn ? off process can be masked by min_ton blanking interval, but in this case is needed to set it at least to 1.5 s that can make issue during very light load where current flows just short time and long min_ton may cause reverse current from output capacitors back to transformer and may change soft switching condition to hard switching at primary side. -10 -8 -6 -4 -2 2 0 0123456 v ds [mv] 7 0,00 0,50 1,00 1,50 2,00 3,00 2,50 0123456 isec[a] 7 drop just at r dson drop at r dson and parasitic inductance v th_cs_off figure 77. sensed voltage drop at sr transistor in llc during light / medium load t[ s] t[ s] to early sr transistor turn ? off is not issue just from efficiency point of view, but also from system stability point of view. when load is decreased, feedback loop asks primary side for lower power that changes secondary side current shape and sr driver can be turned off shortly after min_toff elapses. this causes lower efficiency transfer to secondary side and output voltage starts to decrease. feedback loop asks for more power, secondary current shape changes and sr driver starts to conduct whole period again that improves energy transfer efficiency and output voltage starts to increase. this has to be again regulated by feedback loop and everything starts from begin and make smps oscillations that can be accompany with audible noise.
ncp4306 www. onsemi.com 38 figure 78. llc system oscillation due to short sr transistor conduction i sec v ds1 v drv1 min_ton bodydiode conducts v ds2 v drv2 min_ton bodydiode conducts bodydiode conducts bodydiode conducts cs voltage goes above 0 v after min_ton = sr is turned off regulation loop increases transferred power because thanks to low sr conduction angle lot of power is lose at body diode regulation loop decreases transferred power because thanks to sr it is too much voltage at the output operation of new feature is shown in figure 79. current shape makes drop at sr transistor with 1 m and 0.5 nh shown as v ds that is sensed at cs pin and on and off comparators decide about sr operation based on this voltage. driver is turned on and exception timer is started when v cs drops below v cs_th_on . during minimum on ? time blanking interval off comparator is not active. cs pin voltage is above v th_cs_off after minimum on ? time elapses so driver is turned ? off and because exception timer doesn?t elapse, min_ton blanking interval is started. during this time on comparator output is blanked. reason is to avoid quick driver turning on and off that would just increase consumption. when min_ton blanking interval elapses cs voltage is again below v th_cs_on and exception timer is not elapsed, driver can be turned on again simultaneously with minimum on ? time interval. driver is turned off again almost at the end of conduction phase, but this is correct turn off. min ? ton blanking interval doesn?t start, because exception timer elapsed before so sr controller waits for v cs > v cs_th_reset to start minimum off time blanking timer. exception timer length is given as multiple of minimum on time interval. it should be not set to longer time than t exc 1 3 f swmax (eq. 3) where f swmax is maximum llc switching frequency.
ncp4306 www. onsemi.com 39 figure 79. exception timer operation body diode drop (not in scale) driver can be turned on again up to this point v ds = v cs v th_cs_off v th_cs_on min on ? time i sec v th_cs_reset min off ? time drv min on ? time_2 exception timer 0.25 a 2.7 a light load detection light load detection feature is feature which task is to decrease sr controller consumption during time when sr transistor switching is not needed. this is usually during no load and light load condition when static sr controller consumption starts to play role. goal is to disable controller during no switching time to eliminate static consumption and turn ? on sr transistor as soon as possible when switching comes. internal simplified block diagram is shown in figure 80. main parts of this system are comparator at cs input that informs about cs voltage lower than zero (body diode or sr transistor conducting), lld timer with set able nominal time and possibility to reduce it to one half and finally d flip flop with disable signal output. nominal time can be set by resistor at lld pin connected to ground or internally during production. recommended resistor values are shown in table 6. in case of very noisy system, capacitor in parallel to lld resistor may be used. capacitor value impacts start ? up time, because capacitor has to be charged above disable threshold by internal lld current source. figure 80. lld internal block diagram v cslld cs reset elapsed lld timer set max to t lld set max to t lld / 2 tim > 1 / 4 t lld s r q disable
ncp4306 www. onsemi.com 40 table 6. pin function description lld setting t lld [ s] ic disabled 70 130 280 540 1075 lld disabled r lld [k ] <12 27 43 68 91 120 >470* *floating pin allowed, small cap for noise robustness improvement recommended logic function is also described by bubble diagram in figure 81. lld timer is running every time when cs pin voltage is positive (body diode and or transistor not conducting). if conduction doesn?t come sooner than lld timer elapses, disable flag is set (ic is sent into low consumption mode), lld timer length is changed to t lld / 2 (this adds some hysteresis in system and helps keeping overall system stable) and timer is also reset. sr controller waits for falling edge at cs pin (begin of new conduction cycle). when cs goes negative, disable mode is deactivated and ic starts to wake up (takes t lld_dis_rec , system wake up is controlled same as exit from disable mode by trig / dis pin). end of conduction phase (cs voltage goes positive) starts lld timer. if next conduction phase comes shortly after first (pulses in skip burst) so shortly than t lld / 4 just lld timer is reset. lld timer length is set back to t lld only when new conduction phase comes after previous in time between t lld / 4 to t lld / 2. this situation happens when load is slowly increased and skip bursts come more often. figure 81. lld operation bubble diagram reset tim disable = 0 lld_cmp & tim cnt < t lld lld_cmp start reset tim disable = 0 t tim = t lld disable = 1 t tim = 1 / 2 t lld reset tim lld tim is running 1 / 4 example of lld operation with flyback convertor can be seen in figure 82. smps works under heavy load from point 0 to 1 where switching pulses comes regularly at high frequency that resets lld timer soon after begin of counting. load is significantly decreased to light load at point 1 so primary controller turns to skip mode. lld timer elapses during skip so controller enters disable mode with very low consumption and change lld timer maximum to t lld / 2. switching pulse in skip comes at time 3, this resets lld timer and starts ic wake ? up. controller is waked up fully before point 4 and turns ? on sr transistor. there is again no switching from 4 to 6 and thanks to it , lld timer elapses at point 5 and controller enters disable mode again. disable mode is ended at time 6, because new cycle comes. sr controller wakes ? up and next pulse in skip burst is conducted via sr transistor. time between 7 and 8 is delay between skip burst. time is still less than t lld / 4, lld timer interval is not changed. pulse at time 8 is fully conducted via sr transistor, because controller was not in disable mode before pulse came. no switching period between 9 and 11 is longer than t lld / 2 that changes lld timer setting to t lld . this is because shorter delay between skip burst means higher load. pulses are transferred via sr transistor at time 11 and 12, because disable mode was not activated. load is being decreased again between time 12 to 15 so at time 15 sr controller enters disable mode and lld timer time is reduced again to t lld / 2. second pulse in skip burst is again transferred via turned on sr transistor. disable mode is activated after t lld / 2 at time 18. load is sharply changed at time 19 that means lld timer is reset each pulse and timers time is kept at t lld / 2. load is removed at time 20 and disable is activated at time 21. suitable lld timer setting for flyback type of smps is 540 or 1075 s (for special type 280 s).
ncp4306 www. onsemi.com 41 figure 82. lld operation with flyback smps v ds = v cs drv dis i cc lld tim t lld t1 t2 t4 t1 t2 t1 t2 t4 01 4 2 3 56 7 89101112 1314 15 1617 1819 20 21 22 t2 example of lld operation with llc convertor can be seen in figure 83. smps works under heavy load from point 0 to 3. both lld timers are reset each cycle before lld timer reaches t lld / 4 and disable mode is not activated. smps load decreases at point 3 and goes into skip. lld timers elapse during no switching time and change lld timer time to t lld / 2. when skip burst comes at time 6 channel 2 starts to wake up, channel 1 starts to wake up at time 7. both channels are ready to conduct via sr transistor at time 8 respectively 9. skip burst ends at time 12, lld timers elapse at time 13 and 14 (reached t lld / 2) and sr controllers enter disable mode. controllers wake up at time 15 and 16 same as was in time 6 and 7. smps goes into skip in time 21, but load is connected soon and smps starts to operate under higher load from time 22. lld timers reach time higher than t lld / 4 but lower than t lld / 2 so lld timers maximum is set to t lld . lld timer setting for llc may be set to lower times. figure 83. lld operation with llc smps v ds1 = v cs1 drv1 lld tim1 01 4 2 3 56 7 8 9 1011 12 13 14 15 1617 19 202122 v ds2 = v cs2 drv2 dis1 dis2 lld tim2 t lld1 t lld1 23 24 25 26 27 28 t1 t2 t4
ncp4306 www. onsemi.com 42 operation flow followed bubble diagram at figure 84 shows overall operation flow. black bubbles are fundamental parts of system. states for dv / dt feature are colored by blue color and states for llc feature (exception timer) are in red. llc and dv / dt features are never activated both at same time. operation starts in bubble start where system comes when vcc is higher than uvlo level and / or disable mode is activated (by lld or trig / dis pin) . figure 84. overall operation bubble diagram power dissipation calculation it is important to consider the power dissipation in the mosfet driver of a sr system. if no external gate resistor is used and the internal gate resistance of the mosfet is very low, nearly all energy losses related to gate charge are dissipated in the driver. thus it is necessary to check the sr driver power losses in the target application to avoid over temperature and to optimize efficiency. in sr systems the body diode of the sr mosfet starts conducting before sr mosfet is turned ? on, because there is some delay from v th_cs_on detect to turn ? on the driver. on the other hand , the sr mosfet turn off process always starts before the drain to source voltage rises up significantly. therefore, the mosfet switch always operates under zero voltage switching (zvs) conditions when in a synchronous rectification system. the following steps show how to approximately calculate the power dissipation and die temperature of the ncp4306 controller. note that real results can vary due to the effects of the pcb layout on the thermal resistance. step 1 ? mosfet gate to source capacitance: during zvs operation the gate to drain capacitance does not have a miller effect like in hard switching systems because the drain to source voltage does not change (or its change is negligible). figure 85. typical mosfet capacitances dependency on vds and vgs voltages
ncp4306 www. onsemi.com 43 c iss c gs c gd (eq. 4) c rss c gd (eq. 5) c oss c ds c gd (eq. 6) therefore, the input capacitance of a mosfet operating in zvs mode is given by the parallel combination of the gate to source and gate to drain capacitances (i.e. c iss capacitance for given gate to source voltage). the total gate charge , q g_total , of most mosfets on the market is defined for hard switching conditions. in order to accurately calculate the driving losses in a sr system, it is necessary to determine the gate charge of the mosfet for operation specifically in a zvs system. some manufacturers define this parameter as q g_zvs . unfortunately , most datasheets do not provide this data. if the c iss (or q g_zvs ) parameter is not available then it will need to be measured. please note that the input capacitance is not linear (as shown figure 85) and it needs to be characterized for a given gate voltage clamp level. step 2 ? gate drive losses calculation: gate drive losses are affected by the gate driver clamp voltage. gate driver clamp voltage selection depends on the type of mosfet used (threshold voltage versus channel resistance). the total power losses (driving loses and conduction losses) should be considered when selecting the gate driver clamp voltage. most of today?s mosfets for sr systems feature low r ds_on for 5 v v gs voltage. the ncp4306 offers both a 5 v gate clamp and a 10 v gate clamp for those mosfet that require higher gate to source voltage . the total driving loss can be calculated using the selected gate driver clamp voltage and the input capacitance of the mosfet: p drv_total v cc v clamp c g_zvs f sw (eq. 7) where: v cc is the ncp4306 supply voltage v clamp is the driver clamp voltage c g_zvs is the gate to source capacitance of the mosfet in zvs mode f sw is the switching frequency of the target application the total driving power loss won?t only be dissipated in the ic , but also in external resistances like the external gate resistor (if used) and the mosfet internal gate resistance (figure 86). because ncp4306 features a clamped driver, it?s high side portion can be modeled as a regular driver switch with equivalent resistance and a series voltage source. the low side driver switch resistance does not drop immediately at turn ? off, thus it is necessary to use an equivalent value (r drv_sin_eqk ) for calculations. this method simplifies power losses calculations and still provides acceptable accuracy. internal driver power dissipation can then be calculated using equation 10: figure 86. equivalent schematic of gate drive circuitry v cc v cc ? v clamp ? + drv gnd r drv_sink_eq r drv_source_eq r g_ext sr mosfet r g_int c g_zvs
ncp4306 www. onsemi.com 44 p drv_ic 1 2 c g_zvs v clamp 2 f sw r drv_sink_eq r drv_sink_eq r g_ext r g_int c g_zvs v clamp f sw (v cc v clamp ) (eq. 8) 1 2 c g_zvs v clamp 2 f sw r drv_source_eq r drv_source_eq r g_ext r g_int (eq. 9) where: r drv_sink_eq is the ncp4306 driver low side switch equivalent resistance (1.6 ) r drv_source_eq is the ncp4306 driver high side switch equivalent resistance (7 ) r g_ext is the external gate resistor (if used) r g_int is the internal gate resistance of the mosfet step 3 ? ic consumption calculation: in this step , power dissipation related to the internal ic consumption is calculated. this power loss is given by the i cc current and the ic supply voltage. the i cc current depends on switching frequency and also on the selected min t on and t off periods because there is current flowing out from the min_ton and min_toff pins. the most accurate method for calculating these losses is to measure the i cc current when c load = 0 nf and the ic is switching at the target frequency with given min_t on and min_t off adjust resistors. ic consumption losses can be calculated as: p cc v cc i cc (eq. 10) step 4 ? ic die temperature arise calculation: the die temperature can be calculated now that the total internal power losses have been determined (driver losses plus internal ic consumption losses). the so8 package thermal resistance is specified in the maximum ratings table for a 35 m thin copper layer with no extra copper plates on any pin (i.e. just 0.5 mm trace to each pin with standard soldering points are used). the die temperature is calculated as: t die (p drv_ic p cc) r j a t a (eq. 11) where: p drv_ic is the ic driver internal power dissipation p cc is the ic control internal power dissipation r j ? a is the thermal resistance from junction to ambient t a is the ambient temperature
ncp4306 www. onsemi.com 45 opn coding table ncp4306 opn is built from prefix of ncp4306 and postfix that consist of seven letters. meaning of these letters are shown in table 7. table 7. opn coding table ncp4306xxxxxxx postfix index parameter postfix parameter 1 pinout a min_ton, min_toff, lld, trig / dis ? 8 pins b min_ton, lld c min_toff, lld d min_ton, min_toff e min_toff, trig / dis f min_ton, trig / dis g trig / dis, lld h none 2 drv a drv clmp = 10 v b drv clmp = 5 v 3 dv / dt + exception a none d flyback (dv / dt) ? 100 v / s h llc exception ? multiplier 4 4 min_ton a 130 ns b 220 ns c 310 ns d 400 ns e 500 ns f 600 ns g 800 ns h 1000 ns i 1200 ns j 1400 ns k 1700 ns l 2000 ns z external 5 min_toff a 0.9 s b 1.0 s c 1.1 s d 1.2 s e 1.4 s f 1.6 s g 1.8 s h 2.0 s i 2.2 s j 2.4 s k 2.6 s l 2.9 s m 3.2 s n 3.5 s o 3.9 s z external
ncp4306 www. onsemi.com 46 table 7. opn coding table (continued) ncp4306xxxxxxx postfix index parameter postfix parameter 6 lld a 68 s b 130 s c 280 s d 540 s e 1075 s f disabled z external 7 reserved a ?
ncp4306 www. onsemi.com 47 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm / d. soldering footprint*
ncp4306 www. onsemi.com 48 package dimensions ? 6 case 318g ? 02 issue v 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm / d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 10 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m
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