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16 bit microcontroller tlcs-900/l1 series TMP91FW60FG tmp91fw60dfg revision 1.9 toshiba corporation
the information contained herein is subject to change without notice. toshiba is continually working to improve the qual ity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fa il due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizi ng toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that to shiba products are used w ithin specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. the toshiba products listed in this document are in tended for usage in general electronics applications (computer, personal equipment, office equipment, m easuring equipment, indust rial robotics, domestic appliances, etc.). these toshiba products are neither intended nor wa rranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instru ments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by to shiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. please contact your sales representative for product- by-product details in this document regarding rohs compatibility. please use these products in this docum ent in compliance with all applicable laws and regulations that regulate the inclusion or use of co ntrolled substances. toshib a assumes no liability for damage or losses occurring as a result of nonc ompliance with applicable laws and regulations. ? 2007 toshiba corporation all rights reserved revision history date revision 2006/2/28 0.1 tentative 2006/3/06 0.2 flash section is corrected. 2006/3/13 0.3 correction of a clerical error. 2006/8/04 1.4 p99 figure 5-3 is corrected. p99 figure 5-4 is deleted. p272 the value is added to t.b.d of specification section. p126 figure 7-1 p132-133 tmrb mode register ta1out of tb3m od and tb4mod is corrected. ta1out -> ta3out, ta5out p226 table 14-6 is corrected p178 9.3.3.14 the description is corrected. 2006/10/31 1.5 scout: system clock output ffph -> fsys dc spec vih/vi l is corrected. table 2-8 sample warm-up times after clearance of stop mode is corrected. table 4-2 i/o port setting list is corrected. port 3, 4, 7 control register/fun ction register contrast table is corrected. 1.1 features interrupts is corrected 9.3.2 i2cbus mode control register note1:set the date revision 2007/2/16 1.6 1.1 features program patch logic 2.3.4 prescaler clock co ntroller is corrected. 16.table of sfr's 2.1 reset 10 system clocks 16us -> 1us 18. points to note and restriction 2007/4/16 1.7 15.2 dc electrical characteristics power down voltage min 4.5v -> 2.0v 14.6.10 addresses of program example are corrected 2007/8/27 1.8 dmar register (89h) is corrected by rwm prohibition. 18.2 points of note j. releasing the halt mode by requesting an interruption is deleted. 2.3.2 note3 is added 8.2.1 sio plescaler is correct ed, and table 8-2 is corrected 8.3 note2 and note3 are added 18.2 points of note j.clocks for serial channels (sio) is added 2007/10/15 1.9 7.3 sfr 16. table of sfr's tb0ffcr, tb1ffcr, tb2ffcr, tb3ffcr and tb4ffcr register is corrected. page 1 2007-10-15 20070701-en ? the information contained herein is subject to change without notice. ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba semiconductor reliabi lity handbook? etc. ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or re liability or a malfunctionor failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and /or sale are prohibited under any appl icable laws and regulations. ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patents or other rights of toshiba or the third parties. ? please contact your sales representative for product-by-product details in this document regarding rohs compatibility. please use these products in this document in compliance wi th all applicable laws and regulations that regulate the inclusion or use of controll ed sub- stances. toshiba assumes no liabili ty for damage or losses occurring as a result of noncompliance with applicable laws and regu lations. this product uses the super flash ? technology under the licence of silicon storage technology, inc. super flash ? is registered trademark of silicon storage technology, inc. tmp91fw60 cmos 16 bit microcontroller TMP91FW60FG/dfg 1.1 features ? high-speed 16-bit cpu (900/l1 cpu) - instruction mnemonics are upward-compatible with tlcs-900,900/h,900/l - 16 mbytes of linear address space - general-purpose registers and register banks - 16-bit multiplication and division instructions; bit transfer and arithmetic instructions - micro dma: 4 channels (800ns/2 bytes at 20mhz) ? minimum instruction execution time:200ns (at 20mhz) ? built-in memory - rom:128k bytes (flash rom) - ram:8k bytes ? external memory expansion - expandable up to 16 mbytes (shared program/data area) - can simultaneously support 8/16-bit width external data bus dynamic data bus syzing ? 8-bit timers: 6 channels ? 16-bit timers: 5 channels ? general-purpose serial interface: 5 channels - uart/synchronous mode: 3 channels -i 2 c bus mode: 2 channels ? 10-bit ad converter (built-in sample hold circuit): 16 channels ? special timer for clock product no. rom (flash rom) ram package TMP91FW60FG 128k bytes 8k bytes lqfp100-p-1414-0.50f tmp91fw60dfg qfp100-p-1420-0.65a page 2 2007-10-15 tmp91fw60 ? watchdog timer ? program patch logic: 6 banks ? chip select/wait controller: 4 channels ? interrupts: 57 interrupts - 9 cpu interrupts: software interrupt instruction and illegal instruction - 36 internal interrupts: 7 priority levels are selectable - 12 external interrupts: 7 priority levels are select able (among 1 interrupts are selectable edge mode) ? input/output ports: 83 pins ? standby function: three halt modes: idle2 (programmable), idle1 and stop ? clock controller - clock gear function: select a high-frequency clock fc/1 to fc/16 - oscillator for clock (fs = 32.768 khz) ? operating voltage flash read operation > vcc=4.5 v - 5.5 v (fc max = 20mhz) flash write/erase operation > vcc=4.75 v - 5.25 v (fc max = 20mhz) ? package - lqfp100-p-1414-0.50f (TMP91FW60FG) - qfp100-p-1420-0.65a (tmp91fw60dfg) page 3 2007-10-15 tmp91fw60 1.2 pin assignment diagram figure 1-1 pin assignment(TMP91FW60FG) vrefh TMP91FW60FG lqfp100 topview 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 avss p70/ta0in p71/ta1out p72/ta3out p73/ta4in p74/ta5out p75/int0 p80/tb0in0/int5 p81/tb0in1/int6 avcc p82/tb0out0 p83/tb0out1 p84/tb1in0/int7 p85/tb1in1/int8 p86/tb1out0 p87/tb1out1 p90/txd0 p91/rxd0 p92/sclk0/cts0 p93/txd1 p95/sclk1/cts1 dvcc p30/tb3in0/int3/sda0 pz3/r/w pz2/hwr pz1/wr pz0/rd p27/a7/a23 p26/a6/a22 p25/a5/a21 p24/a4/a20 p23/a3/a19 p22/a2/a18 dvcc nmi dvss p21/a1/a17 p20/a0/a16 p17/ad15/a15 p16/ad14/a14 p15/ad13/a13 p14/ad12/a12 p13/ad11/a11 p12/ad10/a10 p11/ad9/a9 p10/ad8/a8 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 p44/ale p43/cs3/sclk2/cts2 p42/cs2/rxd2 p41/cs1/txd2 p40/cs0/scout pa3/tb2out1 pa2/tb2out0 pa1/tb2in1/int2 pa0/tb2in0/int1 emu1 boot/emu0 p97/xt2 p96/xt1 reset am1 x1 dvss x2 p60/an8 p65/an13 p57/an7 p61/an9 p62/an10 p63/an11 p64/an12 p55/an5 p66/an14 p67/an15 p53/an3 p52/an2 p51/an1 p50/an0 dvss dvcc pb3/tb4out1 pb2/tb4out0 pb1/tb4in1/int10/scl1 pb0/tb4in0/int9/sda1 p33/tb3out1 p32/wait/tb3out0 am0 p31/tb3in1/int4/scl0 p56/an6 p94/rxd1 p54/an4 page 4 2007-10-15 tmp91fw60 figure 1-2 pin a ssignment(tmp91fw60dfg) tmp91fw60dfg qfp100 topview 35 40 45 55 60 65 70 75 pb0/tb4in0/int9/sda1 p66/an14 p67/an15 vrefh avss avcc p70/ta0in p71/ta1out p72/ta3out p73/ta4in p74/ta5out p75/int0 p80/tb0in0/int5 p81/tb0in1/int6 p82/tb0out0 p83/tb0out1 p84/tb1in0/int7 p85/tb1in1/int8 p86/tb1out0 p87/tb1out1 p90/txd0 p91/rxd0 p92/sclk0/cts0 p93/txd1 p94/rxd1 p95/sclk1/cts1 am0 dvcc x2 dvss x1 am1 reset p96/xt1 p97/xt2 emu0/boot emu1 pa0/tb2in0/int1 pa1/tb2in1/int2 pa2/tb2out0 pa3/tb2out1 p40/cs0/scout p41/cs1/txd2 p42/cs2/rxd2 p43/cs3/sclk2/cts2 p44/ale p00/ad0 p01/ad1 p02/ad2 p03/ad3 p04/ad4 p05/ad5 p06/ad6 p07/ad7 p10/ad8/a8 p11/ad9/a9 p12/ad10/a10 p13/ad11/a11 p14/ad12/a12 p15/ad13/a13 p16/ad14/a14 p17/ad15/a15 p20/a0/a16 p21/a1/a17 dvss nmi dvcc p22/a2/a18 p23/a3/a19 p24/a4/a20 p25/a5/a21 p26/a6/a22 p27/a7/a23 pz0/rd pz1/wr pz2/hwr pz3/r/w p30/tb3in0/int3/sda0 p31/tb3in1/int4/scl0 p32/wait/tb3out0 p33/tb3out1 pb1/tb4in1/int10/scl1 pb2/tb4out0 pb3/tb4out1 dvcc dvss p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 p60/an8 p61/an9 p62/an10 p63/an11 p64/an12 p65/an13 1 10 5 15 20 25 30 50 80 85 90 95 100 page 5 2007-10-15 tmp91fw60 1.3 block diagram figure 1-3 block diagram page 6 2007-10-15 tmp91fw60 1.4 pin names and functions table 1-1 pin names and functions(1/3) pin name pin number input / output functions p00-p07 ad0-ad7 8 io io port 0: i/o port that allows i/o to be selected at the bit level address data (lower): 0 to 7 address/data bus p10-p17 ad8-ad15 a8-a15 8 io io o port1: i/o port that allows i/o to be selected at the bit level address data (upper): 8 to 15 of address/data bus address: 8 to 15 of address bus p20-p27 a0-a7 a16-a23 8 io o o port 2: i/o port that allows i/o to be selected at the bit level address: 0 to 7 of address bus address: 16 to 23 of address bus pz0 rd 1 o o port z0: output port read:strobe signal for reading external memory pz1 wr 1 o o port z1: output port write: strobe signal for writing data to pins ad0 to ad7 pz2 hwr 1 io o port z2: i/o port (with pull-up resistor) high write: strobe signal for writing data to pins ad8 to ad15 pz3 r/w 1 io o port z3: i/o port (with pull-up resistor) read/write: 1 represents read or dummy cycle; 0 represents write cycle. p30 tb3in0 int3 sda0 1 io i i io port 30: i/o port 16-bit timer 3 input 0:timer b3 count/capture trigger input 0 interrupt request pin 3: interrupt request pin with programmable rising edge / falling edge. serial bus interface data 0 in i2c bus mode. p31 tb3in1 int4 scl0 1 io i i io port 31: i/o port 16-bit timer 3 input 1:timer b3 count/capture trigger input 1 interrupt request pin 4: interrupt request on rising edge serial bus interface clock 0 in i2c bus mode. p32 wait tb3out0 1 io i o port 32: i/o port wait: pin used to request cpu bus wait ((1 n) wait mode) 16-bit timer 3 output 0: timer b3 output 0 p33 tb3out1 1 io o port 33: i/o port 16-bit timer 3 output 1: timer b3 output 1 p40 cs0 scout 1 io o o port 40: i/o port (with pull-up resistor) chip select 0: outputs 0 when address is within specified address area system clock output: outputs f sys or fs clock. p41 cs1 txd2 1 io o o port 41: i/o port (with pull-up resistor) chip select 1: outputs 0 when address is within specified address area serial send data 2 p42 cs2 rxd2 1 io o i port 42: i/o port (with pull-up resistor) chip select 2: outputs 0 when address is within specified address area serial receive data 2 p43 cs3 sclk2 cts2 1 io o io i port 43: i/o port (with pull-up resistor) chip select 3: outputs 0 when address is within specified address area serial clock i/o 2 serial data send enable 2 (clear to send) p44 ale 1 io o port 44: i/o port (with pull-up resistor) address latch enable p50-57 an0-an7 8 io i port 5: i/o port analog input: pin used to input to ad converter page 7 2007-10-15 tmp91fw60 p60-67 an8-an15 8 io i port 6: i/o port analog input: pin used to input to ad converter p70 ta0in 1 io i port 70: i/o port 8-bit timer 0 input: timer a0 input p71 ta1out 1 io o port 71: i/o port 8-bit timer 1 output:timer a1 output p72 ta3out 1 io o port 72: i/o port 8-bit timer 3 output:timer a3 output p73 ta4in 1 io i port 73: i/o port 8-bit timer 4 input: timer a4 input p74 ta5out 1 io o port 74: i/o port 8-bit timer 5 output:timer a5 output p75 int0 1 io i port 75: i/o port interrupt request pin 0: interrupt request pin with programmable level / rising edge / falling edge. p80 tb0in0 int5 1 io i i port 80: i/o port 16-bit timer 0 input 0:timer b0 count/capture trigger input 0 interrupt request pin 5: interrupt request pin with programmable rising edge / falling edge. p81 tb0in1 int6 1 io i i port 81: i/o port 16-bit timer 0 input 1:timer b0 count/capture trigger input 1 interrupt request pin 6: interrupt request on rising edge p82 tb0out0 1 io o port 82: i/o port 16-bit timer 0 output 0: timer b0 output 0 p83 tb0out1 1 io o port 83: i/o port 16-bit timer 0 output 1: timer b0 output 1 p84 tb1in0 int7 1 io i i port 84: i/o port 16-bit timer 1 input 0:timer b1 count/capture trigger input 0 interrupt request pin 7: interrupt request pin with programmable rising edge / falling edge. p85 tb1in1 int8 1 io i i port 85: i/o port 16-bit timer 1 input 1:timer b1 count/capture trigger input 1 interrupt request pin 8: interrupt request on rising edge p86 tb1out0 1 io o port 86: i/o port 16-bit timer 1 output 0: timer b1 output 0 p87 tb1out1 1 io o port 87: i/o port 16-bit timer 1 output 1: timer b1 output 1 p90 txd0 1 io o port 90: i/o port serial send data 0 p91 rxd0 1 io i port 91: i/o port serial receive data 0 p92 sclk0 cts0 1 io io i port 92: i/o port serial clock i/o 0 serial data send enable 0 (clear to send) p93 txd1 1 io o port 93: i/o port serial send data 1 p94 rxd1 1 io i port 94: i/o port serial receive data 1 table 1-1 pin names and functions(2/3) pin name pin number input / output functions page 8 2007-10-15 tmp91fw60 note: all pins that have built-in pull-up resistors (other than the reset pin) can be disconnected from the built-in pull-up resistor by software. p95 sclk1 cts1 1 io io i port 95: i/o port serial clock i/o 1 serial data send enable 1 (clear to send) p96 xt1 1 io i port 96: i/o port low-frequency oscillator connection pin p97 xt2 1 io o port 97: i/o port low-frequency oscillator connection pin pa0 tb2in0 int1 1 io i i port a0: i/o port 16-bit timer 2 input 0:timer b2 count/capture trigger input 0 interrupt request pin 1: interrupt request pin with programmable rising edge / falling edge. pa1 tb2in1 int2 1 io i i port a1: i/o port 16-bit timer 2 input 1:timer b2 count/capture trigger input 1 interrupt request pin 2: interrupt request on rising edge pa2 tb2out0 1 io o port a2: i/o port 16-bit timer 2 output 0: timer b2 output 0 pa3 tb2out1 1 io o port a3: i/o port 16-bit timer 2 output 1: timer b2 output 1 pb0 tb4in0 int9 sda1 1 io i i io port b0: i/o port 16-bit timer 4 input 0:timer b4 count/capture trigger input 0 interrupt request pin 9: interrupt request pin with programmable rising edge / falling edge. serial bus interface data 1 in i2c bus mode. pb1 tb4in1 int10 scl1 1 io i i io port b1: i/o port 16-bit timer 4 input 1:timer b4 count/capture trigger input 1 interrupt request pin 10: interrupt request on rising edge serial bus interface clock 1 in i2c bus mode. pb2 tb4out0 1 io o port b2: i/o port 16-bit timer 4 output 0: timer b4 output 0 pb3 tb4out1 1 io o port b3: i/o port 16-bit timer 4 output 1: timer b4 output 1 nmi 1i non-maskable interrupt request pin: interrupt request pin with programmable falling edge or both edge. am0-1 2 i operation mode:fixed to am1 "1", am0 "1". emu0-1 2 o set to open pins reset 1 i reset: initializes tmp91fw60. (with pull-up resistor) vrefh 1 i pin for reference voltage input to ad converter avcc 1 power supply pin for ad converter avss 1 gnd pin for ad converter (0 v) x1/x2 2 io high frequency oscillator connection pins dvcc 3 power supply pins (all dvcc pins should be connected with the power supply pin.) dvss 3 gnd pins (0 v) (all dvss pins should be connected with the gnd (0v) pin.) table 1-1 pin names and functions(3/3) pin name pin number input / output functions page 9 2007-10-15 tmp91fw60 2. cpu the tmp91fw60 incorporates a high-performance 16-bit cpu (the 900/l1-cpu). for cpu operation, see the "tlcs-900/l1 cpu". the following describe the unique function of the cpu us ed in the tmp91fw60; thes e functions are not covered in the tlcs-900/l1 cpu section. 2.1 reset when resetting the tmp91fw60 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-fre quency oscillator has stabilized. then hold the reset input to low level at least for 10 system clocks (1us at 20 mhz). thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then hold the reset input to low level at least for 10 system clocks. it means that the system clock mode f sys is set to fc/2. when the reset is accept, the cpu: 1. sets as follows the prog ram counter (pc) in accordance with the reset vector stored at address ffff00h to ffff02h: - pc (7:0) <- value at ffff00h address - pc (15:8) <- value at ffff01h address - pc (23:16) <- value at ffff02h address 2. sets the stack pointer (xsp) to 100h. 3. sets bits page 10 2007-10-15 tmp91fw60 figure 2-1 tmp91fw60 reset timing chart data-out f fph a16~a23 ale ad0~ad15 ad0~ad15 (p20 to p27 input mode) (p40 to p43 input mode) (pz3 input mode) |