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slg 7nt4192 greenpak 3 ? power g ood g enerato r l ogic silego technology, inc. preliminary rev 0. 11 slg 7 nt4192 _ds_r0 11 revised may 2 7 , 201 3 slg 7nt4192 _gp_r00 2 general description silego slg 7nt4192 is a low power and small form device. the soc is housed in a 2mm x 3 mm t q fn package which is optimal for using with small devices. features ? low power consumption ? pb - free / rohs compliant ? halogen - free ? t qfn - 20 package output summary ? 9 outputs C open drain pin configuration 1 2 3 4 vdd bc_acok_dsw dpwrok bc_acok_ec_in 5 6 sus_vr_pwrgd v1 7 pwrbtn_n 11 8 9 10 20 19 18 pch_pwrok vccst_pwrgd pwrbtn_dsw_n v2 ddr_vccio_pwrgd all_sys_pwrgd tqfn - 20 top view 12 13 14 15 16 17 gnd sys_pwrok v3 pwrbtn_ec_in vbat_mon rsmrst_pwrgd_n v3.3a_dsw_pwrgd slg7nt4192
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 2 2 block diagram
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 3 3 p in configuration pin # pin name type pin description 1 vdd pwr supply voltage 2 bc_acok_dsw input digital in without schmitt trigg er 3 dpwrok output open drain 4 bc_acok_ec_in output open drain 5 sus_vr_pwrgd input digital in without schmitt trigger 6 v1 input analog input 7 pwrbtn_n input digital in without schmitt trigger 8 vccst_pwrgd output open drain 9 pwrbtn_dsw_n output open drain 10 v2 input analog input 11 gnd gnd ground 12 sys_pwrok output open drain 13 v3 input analog input 14 pwrbtn_ec_in output open drain 15 vbat_mon input analog input 16 rsmrst_pwrgd_n output open drain 17 v3.3a_dsw_pwrgd input digital in without schmitt trigger 18 all_sys_pwrgd output open drain 19 ddr_vccio_pwrgd input digital in without schmitt trigger 20 pch_pwrok output open drain ordering information part number package type slg 7nt4192 v v=t q fn - 20 slg 7nt4192 v tr t q fn - 20 C tape and reel (3k units)
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 4 4 absolute maximum conditions parameter min. max. unit v high to gnd - 0.3 7 v voltage at input pins - 0.3 7 v current at input pin - 1.0 1.0 ma storage temperature range - 65 150 c junction temperature -- 150 c electrical characteristics (@ 25c, unless otherwise stated) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3. 135 3.3 3. 465 v t a operating temperature - 40 25 85 c i q quiescent cur rent static inputs and outputs -- 85 -- a v ih high - level input voltage logic input 1. 8 -- -- -- v il low - level input voltage logic input -- -- 1. 3 v i ih high - level input current logic input pins; v in =3.3v - 1.0 -- 1.0 a i il low - level input current logic input pins; v in =0v - 1.0 -- 1.0 a v ol low - level output voltage open drain, i ol = 3 ma, 1x driver -- 0.080 0 .1 5 v i ol low - level output current open drain, v ol = 0.4 v, 1x driver 7.3 12 -- ma v o maximal voltage applied to any pin in high - impedance state -- -- vdd v v acmp0 analog comp arator reference voltage including acmp0 voltage reference t.b.d. 950 t.b.d. mv v acmp1 analog comparator reference voltage including acmp1 voltage reference t.b.d. 950 t.b.d. mv v acmp2 analog comparator reference voltage including acmp2 voltage reference t.b.d. 950 t.b.d. mv v acmp 3 analog comparator reference voltage including acmp 3 voltage reference t.b.d. 950 t.b.d. mv v hyst analog comparator hysteresis voltage acmp0, acmp1, acmp2 , acmp 3 t.b.d. 50 t.b.d. mv v offset analog comparator offset voltage ac mp0, acmp1, acmp2 , acmp 3 -- 5 -- mv t dly0 delay0 time t.b.d. 2.5 t.b.d. ms
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 5 5 t dly1 delay1 time t.b.d. 2.5 t.b.d. ms t dly4 delay4 time t.b.d. 2 t.b.d. ms t dly5 delay5 time t.b.d. 10 t.b.d. ms t su start up time -- t.b.d. -- ms
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 6 6 slg 7nt4192 function ality waveforms inputs: d0 C pin # 1 5 ( v bat_mon ) d1 C pin # 1 7 ( v3.3a_dsw_pwrgd ) d2 C pin # 7 ( pwrbtn_n ) d3 C pin # 6 ( v1 ) d4 C pin # 1 0 ( v2 ) d5 C pin # 1 3 ( v 3 ) d6 C pin # 2 ( bc_acok_dsw ) outputs: d 7 C pin # 3 ( dpwrok ) w ith external 5k ? pull - up resistor d 8 C pin # 16 ( rsmrst_pwrgd_n ) with external 5k ? pull - up resistor d 9 C pin # 1 4 ( pwrbtn_ec_in ) with external 5k ? pull - up resistor d1 0 C pin # 9 ( pwrbtn_dsw_n ) with external 5k ? pull - up resistor d1 1 C pin # 8 ( vccst_pwrgd ) with external 5k ? pull - up resistor d1 2 C pin # 18 ( a ll_sys_pwrgd ) with external 5k ? pull - up resistor d1 3 C pin # 12 ( sys_pwrok ) with external 5k ? pull - up resistor d1 4 C pin #20 (pch_pwrok) with external 5k ? pull - up resistor d15 C pin #4 (bc_acok_ec_in) with external 5k ? pull - up resistor 1. c hip f unctionality (pin 5 (sus_vr_pwrgd) , pin 19 (ddr_vccio_pwrgd) are always high)
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 7 7 package top marking datasheet revision programming code number part code revision date 0. 11 0 2 0 5 / 2 7 /201 3
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 8 8 package drawing and dimensions 20 lead t q fn package jedec mo - 2 20 , variation wcee
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 9 9 tape and reel specification package type # of pins nominal package size (mm) max units reel & hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch t q fn 20l 2 x3 mm 0.4p green 20 2x3x0.75 3000 3000 178/60 42 168 42 168 8 4 carrier tape drawing and dimensions package type pocket btm length (mm) pocket btm width (mm) pocket depth (mm) index hole pitch (mm) pocket pitch (mm) index hole diameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) tape width (mm) a0 b0 k0 p0 p1 d0 e f w tqfn 20l 2x3mm 0.4p green 2.25 3.3 1.1 4 4 1.55 1.75 3.5 8 refer to eia - 481 specifications recommended reflow soldering profile please see ipc/jedec j - std - 020: latest revision for reflow pr ofile based on package volume of 4.50 mm 3 (nominal). more information can be found at www.jedec.org .
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 10 10 datasheet revision history date version change 05 / 2 0 /201 3 0. 1 new design 05/2 7 /2013 0. 11 updated design
slg 7nt4192 power g ood g enerato r l ogic slg 7nt4192 _ds_r0 11 preliminary page 11 11 silego w ebsite & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customer s. for more information regarding silego green products, please visit: http://greenpak.silego.com/ http://greenpak2.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ products are also available for purchase directly from silego at the sileg o online store at http://store.silego.com/ . silego technical support datasheets and errata, application notes and example designs, user guides, and hardware support docu ments and the latest software releases are av ailable at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions and support please send email requests to greenpak@silego.com users of silego products can receive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for suppo rt. local sales offices are also available to help customers. more information regarding your local representative is availa ble at the silego website or send a request to info@silego.com contact silego directly silego can be contac ted directly via e - mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminars and events, listings of worldwide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. silego technology does not assume any liability arising out of such applications or use s of its products. silego technology reserves the right to improve product design, functions and reliability without notice.

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