vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect g52360-0, rev 2.0 page 1 02/09/01 ? vitesse semiconductor corporation ? 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com features applications general description the vsc7961 is a single-supply limiting amplifier with loss of signal (los) detect for sonet/sdh and fibre channel applications up to 3.125gb/s. the vsc7961 provides a constant output signal swing for a wide range of input voltages and has positive emitter-coupled logic (pecl). the vsc7959 provides the same func- tionality as the vsc7961 with current-mode logic (cml) outputs. key features of the vsc7961 are its rms power detectors for programmable los detection, optional output squelch, adjustable output levels, excellent jitter performance, and fast edge rates. the vsc7961 is available in die form or in a tssop-16 package. block diagram ? 3.3v or 5v power supply typical supply current of 32ma positive emitter-coupled logic (pecl) outputs optional output squelch loss of signal detect output offset correction rise/fall times faster than 100ps packages: tssop-16, bare die vsc7961 100 ? in+ in- rms power detect and control lowpass filter 10pf offset correction 8k ? output control 8k ? v cc v cc los squelch level out+ out- los cz1 cz2 th sonet/sdh at 622mb/s, 1.244gb/s, 2.488gb/s, and 3.125gb/s full-speed fibre channel (1.062gb/s) small form factor (sff) receivers atm optical receivers
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect page 2 g52360-0, rev 2.0 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com electrical characteristics table 1: dc specifications note: (1) see figure 4 for supply current measurement setup. table 2: dc specifications notes: (1) deterministic jitter measured peak-to-peak with k28.5 pattern. (2) random jitter measured with minimum input. symbol parameter min typ max units conditions v cc power supply voltage 3.135 5.5 v i cc power supply current (1) 59 ma v cc = 3.3v 62 ma v cc = 5v i ee power supply current (1) 31 ma v cc = 3.3v 35 m v cc = 5v i ccsq power supply current when squelched (1) 58 ma v cc = 3.3v 62 ma v cc = 5v i eesq power supply current when squelched (1) 20 ma v cc = 3.3v 23 ma v cc = 5v i sq squelch input current 0 400 a pssr power supply rejection ratio 20 db f < 2mhz symbol parameter min typ max units conditions data rate 3.125 gb/s v in input voltage range 10 1200 mv peak-to-peak j d deterministic jitter 25 ps see note 1 j r random jitter 8 ps see note 2, rms t r, t f rise and fall times 55 100 ps 20% to 80% v n input referred noise 230 v rms, in+ to in- r diff differential input resistance 100 ? in+ to in- f l low frequency cutoff 2mhzc z open 2khzc z = 0.1f v sq output signal when squelched 20 mv output ac-coupled v oh pecl output high voltage -1025 -850 mv -850 mv squelched v ol pecl output low voltage -1810 -1620 mv -1620 mv squelched z o output resistance 100 ? single-ended
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect g52360-0, rev 2.0 page 3 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com table 3: loss of signal specifications table 4: loss of signal truth table absolute maximum ratings (1) power supply voltage (v cc )............................................................................................................. -0.5v to +6v maximum junction temperature range ............................................................................................. ............tbd storage temperature range (t s )................................................................................................. -55 c to +150 c note: (1) caution: stresses listed under ?absolute maximum ratings? may be applied to devices one at a time without caus- ing permanent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods may affect device reliability. recommended operating conditions positive voltage rail (v cc ).................................................................................................................. 3.3v or 5v junction temperature range (t j )................................................................................................ -40 c to +100 c ambient temperature range (t a )................................................................................................. -40 c to +85 c symbol parameter min typ max units conditions h los los hystersis 3.1 3.3 5.5 db h los = 20 log (v thd /v tha ) i los los assert/deassert time 0.22 0.25 0.28 s v tha los assert threshold 8.2 mv r th = 2.5k ? 12.8 19.8 21.8 mv r th = 7k ? 57.2 mv r th = 20k ? v thd los deassert threshold 11.4 mv r th = 2.5k ? 26.2 29.0 31.6 mv r th = 7k ? 75.2 mv r th = 20k ? v losh los output high voltage 3.3 v i los = ? 30a v losl los output low voltage 0.168 v i los = +1.2a squelch los output high low off low high on high low on low low on
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect page 4 g52360-0, rev 2.0 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com package pin descriptions figure 1: pin diagram table 5: pin identifications pin name pin no. description cz1 1 offset correction loop capacitor. place capacitor between this pin and cz2 to alter time constant of offset correction loop. see detailed description section. cz2 2 offset correction loop capacitor. place capacitor between this pin and cz1 to alter time constant of offset correction loop. see detailed description section. gnd 3 supply ground in+ 4 noninverted input signal in- 5 inverted input signal gnd 6 supply ground nc 7 this pin may be either connected to ground of left unconnected. this pin does not effet the performance of the device. th 8 loss of signal (los) threshold. connect a resistor from this pin to ground to set the input signal level at which los outputs will be asserted. see application information section. los 9 inverted loss of signal output. los is high for input signals above the threshold programmed by th. see detailed description section. los 10 noninverted loss of signal output. los is low for input signals above the threshold programmed by th. see detailed description section. vcc 11 power supply out- 12 inverted data output out+ 13 noninverted data output vcc 14 power supply squelch 15 squelch input. squelch is disabled if this pin is unconnected or set low. when squelch is high, out+ and out- are forced to static levels. see detailed description section. nc 16 no connection 1 2 3 4 5 6 7 8 cz1 cz2 gnd in+ in- gnd nc th nc squelch vcc out+ out- vcc los los 16 15 14 13 12 11 10 9 vsc7961 top view tssop-16 package
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect g52360-0, rev 2.0 page 5 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com bare die descriptions figure 2: pad assignments vsc7961 die size: 1597 m x 1597 m (0.06287" x 0.06287") pad pitch: 180 m (0.00709") pad passivation opening: 95 m x 95 m (0.00374" x 0.00374") pad 16 nc 1597 m (0.06287") 1597 m (0.06287") pad 2 caz2 pad 3 gnda pad 4 lainp pad 5 lainm pad 6 gnda pad 7 nc pad 15 sq pad 14 vcca pad 13 laop pad 12 laom pad 11 vcca pad 10 los pad 9 los pad 8 th pad1 caz1 the back side of the die may either be left floating or connected ot ground.
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect page 6 g52360-0, rev 2.0 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com table 6: pad coordinates pad name pin name pad/pin number coordinates (m) description x y cz1 cz1 1 270.525 1359.05 offset correction loop capacitor. place capacitor between this pin and cz2 to alter time constant of offset correction loop. see detailed description section. cz2 cz2 2 80.95 1170.525 offset correction loop capacitor. place capacitor between this pin and cz1 to alter time constant of offset correction loop. see detailed description section. gnda gnd 3 80.95 990.525 supply ground lainp in+ 4 80.95 810.525 noninverted input signal lainm in- 5 80.95 630.525 inverted input signal gnda gnd 6 80.95 450.525 supply ground nc nc 7 80.95 270.525 this pin may be either connected to ground of left unconnected. this pin does not effet the performance of the device. th th 8 270.525 80.95 loss of signal (los) threshold. connect a resistor from this pin to ground to set the input signal level at which los outputs will be asserted. see application information section. los los 9 1169.475 80.95 inverted loss of signal output. los is high for input signals above the threshold programmed by th. see detailed description section. los los 10 1359.05 270.525 noninverted loss of signal output. los is low for input signals above the threshold programmed by th. see detailed description section. vcca vcc 11 1359.05 450.525 power supply loam out- 12 1359.05 630.525 inverted data output laop out+ 13 1359.05 810.525 noninverted data output vcca vcc 14 1359.05 990.525 power supply sq squelch 15 1359.05 1170.525 squelch input. squelch is disabled if this pin is unconnected or set low. when squelch is high, out+ and out- are forced to static levels. see detailed description section. nc ?? /16 1169.475 1359.05 no connection
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect g52360-0, rev 2.0 page 7 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com detailed description the vsc7961 is a high-speed limiting amplifier with loss of signal (los) detect. the device is designed to operate with a 3.3v or 5v supply in sdh/sonet and fibre channel applications up to 3.125gb/s. the vsc7961 has positive emitter-coupled logic (pecl) outputs. the vsc7959 provides the same functionality as the vsc7961 with current-mode logic (cml) outputs. the key features of the vsc7961 are loss-of-signal (los) detect, output offset correction, output squelch, low power supply current, and fast rise and fall times. the inputs of the device provide 100 ? input impedance between in+ and in- and are intended to be dc- coupled. the pecl output circuits should be terminated through 50 ? to v cc - 2v. loss of signal (los) detect this feature utilizes an rms power detector with programmable los indicator to provide two outputs, los and los . the input th is used to set the threshold at which the loss of signal detector outputs, los and los, change state. see loss of signal specifications (table 3) for setting the resistor value between th and ground. the loss-of-signal truth table (table 4) clarifies how los and squelch interact. optional squelch squelch is disabled when squelch is not connected or is set to ttl low level. when squelch is set to ttl high level and los is asserted, the data outputs, out+ and out- are forced to static levels. if los is not asserted, the outputs will not be squelched. offset correction this feature is provided to ensure that the offsets in the amplifier coupled with its gain do not cause the out- put buffer to give a false output. because of the high gain of the amplifier, offset correction using a low-fre- quency feedback loop reduces input offset. if no component is placed between pins cz1 and cz2, the low frequency cut-off is 2mhz. if a 0.1 f capacitor is placed between cz1 and cz2, the low frequency cut-off is lowered to about 2khz. for fibre channel and gigabit ethernet applications, leave pins cz1 and cz2 open. for atm/sonet and other scrambled non-return-to-zero (nrz) applications, place a 0.1 f capacitor between cz1 and cz2. this maintains a one-decade separation between the lowest input frequency and the low fre- quency cut-off. the low frequency cut-off of the offset correction loop is given by the following equation: f oc = 43 / [2 * 35k (c z + 100pf)] = 196* 10 -6 / (c z + 100pf) = 196* 10 -6 / (0.1 f + 100pf) = 1.96khz
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect page 8 g52360-0, rev 2.0 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com output level control the level pin adjusts the output levels to 20ma when grounded and to 16ma when left unconnected. figure 3: supply current measurement applications information wire bonding for best performance, gold ball-bonding techniques are recommended. to minimize inductance, keep wire bond lengths short. pcb layout guidelines use high frequency pcb layout techniques with solid ground planes to minimize crosstalk and emi. keep high speed traces as short as possible for signal integrity. short input and output traces will provide best perfor- mance. i mod v cc i cc vsc7961 i out 100 ? 100 ? supply current (i cc and i ee ) a 100 ? 100 ? v ee a i ee
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect g52360-0, rev 2.0 page 9 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com package information 1. all dimensioning and tolerancing per asme. y14.5-1994 2. controlling dimension: millimeter 3. this outline conforms to jedec publication 95 registration ms-026 tssop-16
vitesse semiconductor corporation advance product information vsc7961 3.125gb/s pecl limiting amplifier with los detect page 10 g52360-0, rev 2.0 02/09/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com ordering information the order number for this product is formed by a combination of the device type and package type. notice vitesse semiconductor corporation ( ? vitesse ? ) provides this document for informational purposes only. this document contains pre-production information about vitesse products in their concept, development and/or testing phase. all information in this document, includ ing descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. n othing contained in this document shall be construed as extending any warranty or promise, express or implied, that any vitesse product will be availabl e as described or will be suitable for or will accomplish any particular task. vitesse products are not intended for use in life support appliances, devices or systems. use of a vitesse product in such appl ications without writ- ten consent is prohibited. vsc7961 xx device type package 3.125gb/s pecl limiting amplifier yd: tssop-16 w: dice waffle pack with los detect
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