View NB4L16MMNEVB_8981216.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2016 august, 2016 ? rev. 4 1 publication order number: nb4l16m/d nb4l16m 2.5v/3.3v, 5 gb/s multi level clock/data input to cml driver/receiver/buffer/ translator with internal termination description the nb4l16m is a differential driver/receiver/buffer/translator which can accept lvpecl, lvds, cml, hstl, lvcmos/lvttl and produce 400 mv cml output. the device is capable of receiving, buffering, and translating a clock or data signal that is as small as 75 mv operating up to 3.5 ghz or 5.0 gb/s, respectively. as such, it is ideal for sonet, gige, fiber channel and backplane applications (see table 6 and figures 20, 21 22, and 23). differential inputs incorporate internal 50 termination resistors and accept l vpecl (positive ecl), l vttl/l vcmos, cml, hstl or lvds. the differential 16 ma cml output provides matching internal 50 termination, and 400 mv output swing when externally receiver terminated, 50 to v cc (see figure 19). these features provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external components. the v bb , an internally generated voltage supply, is available to this device only. for single-ended input configuration, the unused complementary differential input is connected to v bb as a switching reference voltage. the v bb reference output can be used also to re-bias capacitor coupled differential or single-ended output signals. for the capacitor coupled input signals, v bb should be connected to the v td pin and bypassed to ground with a 0.01 f capacitor. when not used v bb should be left open. this device is housed in a 3x3 mm 16 pin qfn package. application notes, models, and support documentation are available at www.onsemi.com . features ? maximum input clock frequency up to 3.5 ghz ? maximum input data rate up to 5.0 gb/s ? < 0.7 ps maximum clock rms jitter ? < 10 ps maximum data dependent jitter at 2.5 gb/s ? 220 ps typical propagation delay ? 60 ps typical rise and fall times ? cml output with operating range: ? v cc = 2.375 v to 3.6 v with v ee = 0 v ? cml output level (400 mv peak-to-peak output), differential output only ? 50 internal input and output termination resistors ? functionally compatible with existing 2.5 v / 3.3 v lvel, lvep, ep, and sg devices ? these devices are pb-free, halogen free and are rohs compliant a = assembly location l = wafer lot y = year w = work week = pb-free package marking diagram* qfn ? 16 mn suffix case 485g ? 01 www.onsemi.com 16 nb4l 16m alyw 1 (note: microdot may be in either location) 1 ordering information device package shipping ? mb4l16mmng qfn ? 16 (pb-free) 123 units/tube mb4l16mmnr2g qfn ? 16 (pb-free) 3000/tape & reel ?for information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d . *for additional marking information, refer to application note and8002/d .
nb4l16m www.onsemi.com 2 v cc nc v ee v ee v cc v bb v ee v ee v cc q q v cc v td d d v td 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb4l16m exposed pad (ep) q q figure 1. functional block diagram v td d d 50 v td 50 r1 r2 r1 r2 v ee v cc figure 2. pin configuration (top view) table 1. pin description pin name i/o description 1 v td ? internal 50 termination pin. see table 4 (note 1). 2 d lvpecl, cml, hstl, lvcmos, lvds, lvttl input inverted differential input. internal 36.5 k to v cc and 73 k to v ee (note 1). 3 d lvpecl, cml, hstl, lvcmos, lvds, lvttl input non-inverted differential input. internal 73 k to v cc and 36.5 k to v ee (note 1). 4 v td ? internal 50 termination pin. see table 4. (note 1) 15 v bb ? internally generated reference voltage supply. 6 nc no connect pin. the no connect (nc) pin is electrically connected to the die and must be left open. 10 q cml output non-inverted differential output. typically receiver terminated with 50 resistor to v cc . 11 q cml output inverted differential output. typically receiver terminated with 50 resistor to v cc . 7, 8, 13, 14 v ee ? negative supply voltage 5, 9, 12, 16 v cc ? positive supply voltage ? ep ? exposed pad (ep). ep on the package bottom is thermally connected to the die for improved heat transfer out of the package. the pad is not electrically connected to the die, but is recommended to be soldered to v ee on the pc board. 1. in the differential configuration when the input termination pins (v td , v td ) are connected to a common termination voltage and if no signal is applied on d/d input then the device will be susceptible to self-oscillation.
nb4l16m www.onsemi.com 3 table 2. attributes characteristics value input default state resistors r1 r2 37.5 k 73 k esd protection human body model machine model charged device model > 2 kv > 200 v > 1 kv moisture sensitivity (note 1) pb-free pkg qfn ? 16 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 157 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d . table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 6 v v ee negative power supply v cc = 0 v ? 6 v v i positive input negative input v ee = 0 v v cc = 0 v v i = v cc v i = v ee 6 ? 6 v v inpp differential input voltage |d ? d | |v cc ? v ee | v i in input current through r t (50 resistor) static surge 45 80 ma i out output current continuous surge 25 50 ma i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction-to-ambient) (note 1) 0 lfpm 500 lfpm qfn ? 16 42 35 c/w jc thermal resistance (junction-to-case) 1s2p (note 1) qfn ? 16 4 c/w t sol wave solder (pb-free) 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. jedec standard multilayer board ? 1s2p (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb4l16m www.onsemi.com 4 table 4. dc characteristics, clock inputs, cml outputs (v cc = 2.375 v to 3.8 v, v ee = 0 v, t a = ? 40 c to +85 c) symbol characteristic min typ max unit i cc power supply current (inputs and outputs open) 30 45 55 ma v oh output high voltage (note 1) v cc ? 40 v cc ? 10 v cc mv v ol output low voltage (note 1) v cc ? 500 v cc ? 400 v cc ? 300 mv differential input driven single-ended (figures 15 and 17) v th input threshold reference voltage range (note 3) 1050 v cc ? 150 mv v ih single-ended input high voltage v th + 150 v cc mv v il single-ended input low voltage v ee v th ? 150 mv v bb internally generated reference voltage supply (loaded with ? 100 a) v cc ? 1500 v cc ? 1400 v cc ? 1300 mv differential inputs driven differentially (figures 16 and 18) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage v ee v cc ? 150 mv v cmr input common mode range (differential configuration) 950 v cc ? 75 mv v id differential input voltage (v ihd ? v ild ) 150 v cc ? v ee mv i ih input high current (vtd/vtd open) d d 0 0 100 50 150 100 a i il input low current (vtd/vtd open) d d ? 100 ? 150 ? 50 ? 100 0 0 a r tin internal input termination resistor 40 50 60 r tout internal output termination resistor 40 50 60 r te m p coef internal i/o termination resistor temperature coefficient 16 m / c note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. cml outputs require 50 receiver termination resistors to v cc for proper operation. see figure 14. 2. input and output parameters vary 1:1 with v cc . 3. v th is applied to the complementary input when operating in single-ended mode. 4. v cmr min varies 1:1 with v ee , v cmrmax varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb4l16m www.onsemi.com 5 table 5. ac characteristics (v cc = 2.375 v to 3.8 v, v ee = 0 v; (note 1)) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@v inppmin ) (figures 3 and 4) f in 3.5 ghz f in 4.5 ghz 280 150 400 300 280 150 400 300 280 150 400 300 mv f data maximum operating data rate 3.5 5.0 3.5 5.0 3.5 5.0 gb/s t plh , t phl propagation delay to output differential @ 0.5 ghz (figure 6) 175 215 265 175 220 265 175 225 265 ps t skew duty cycle skew (note 2) device-to-device skew (note 6) 2.0 6.0 10 90 2.0 6.0 10 90 2.0 6.0 10 90 ps t jitter rms random clock jitter (note 4) f in 4.5 ghz peak-to-peak data dependent jitter (note 5) f data = 2.5 gb/s f data = 3.5 gb/s f data = 5.0 gb/s 0.2 1.5 2.0 9.0 0.7 10 12 25 0.2 1.5 2.0 9.0 0.7 10 12 25 0.2 1.5 2.0 9.0 0.7 10 12 25 ps v inpp input voltage swing/sensitivity (differential configuration) (note 3) 75 v cc ? v ee 75 v cc ? v ee 75 v cc ? v ee mv t r t f output rise/fall times @ 0.5 ghz (figure 5) (20% ? 80%) 60 90 60 90 60 90 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. measured by forcing v inpp (min) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20% ? 80%). see figure 12 and 14. 2. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @ 0.5 ghz. 3. v inpp (max) cannot exceed v cc ? v ee . input voltage swing is a single-ended measurement operating in differential mode. see figure 11. 4. additive rms jitter with 50% duty cycle input clock signal. 5. additive peak-to-peak data dependent jitter with nrz input data signal, prbs 2 23 ? 1 and k28.7 pattern. see figures 7, 8, 9, 10, 11 and 12. 6. device-to-device skew is measured between outputs under identical transition @ 0.5 ghz.
nb4l16m www.onsemi.com 6 typical operating characteristics figure 3. output voltage amplitude (v outpp ) vs. input clock frequency (f in ) and temperature at 3.3 v power supply 0 50 100 150 200 250 300 350 400 450 2 2.5 3 3.5 4 4.5 5 5.5 0 output voltage amplitude (mv) ? 40 c input clock frequency (ghz) +85 c +25 c 0 50 100 150 200 250 300 350 400 450 2 2.5 3 3.5 4 4.5 5 5.5 0 output voltage amplitude (mv) input clock frequency (ghz) ? 40 c +25 c +85 c figure 4. output voltage amplitude (v outpp ) vs input clock frequency (f in ) and temperature at 2.5 v power supply 30 40 50 60 70 80 90 ? 40 25 85 v cc = 3.3 v v cc = 2.5 v time (ps) temperature ( c) figure 5. rise/fall time vs temperature and power supply 175 185 195 205 215 225 235 245 255 265 ? 40 25 85 time (ps) temperature ( c) figure 6. propagation delay vs temperature and power supply v cc = 3.3 v v cc = 2.5 v
nb4l16m www.onsemi.com 7 figure 7. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 (v inpp = 75 mv; input signal ddj = 12 ps) figure 8. typical output waveform at 3.2 gb/s with prbs 2 ^23 ? 1 (v inpp = 75 mv; input signal ddj = 12 ps) voltage (50 mv/div) time (80 ps/div) voltage (50 mv/div) time (60 ps/div) device ddj = 1.5 ps device ddj = 2 ps figure 9. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv; input signal ddj = 12 ps) voltage (64 mv/div) time (72 ps/div) figure 10. typical output waveform at 3.2 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv; input signal ddj = 12 ps) voltage (64 mv/div) time (60 ps/div) device ddj = 1.5 ps device ddj = 2 ps figure 11. typical output waveform at 5 gb/s with prbs 223 ? 1 (vinpp = 400 mv; input signal ddj = 13 ps) figure 12. typical output waveform at 6.125 gb/s with prbs 223 ? 1 (vinpp = 400 mv; input signal ddj = 15 ps) voltage (64 mv/div) time (43 ps/div) voltage (64 mv/div) time (36 ps/div) device ddj = 9 ps device ddj = 14 ps
nb4l16m www.onsemi.com 8 figure 13. ac reference measurement d d q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q) figure 14. typical termination for output driver and device evaluation driver device receiver device qd q d z o = 50 z o = 50 50 50 v cc d v th d v th figure 15. differential input driven single-ended d d figure 16. differential inputs driven differentially v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th v ihdmax v ildmax v ihdmin v ildmin v ihdtyp v ildtyp note: v ee v in v cc ; v ih > v il v cmr v cc v cmmax v cmmax gnd figure 17. v th diagram figure 18. v cmr diagram v id = v ihd ? v ild
nb4l16m www.onsemi.com 9 q q v cc v ee 16 ma 50 50 figure 19. cml output structure table 6. interfacing options interfacing options connections cml connect v td and v td to v cc lvds connect v td and v td together ac-coupled bias v td and v td inputs within common mode range (v cmr ) rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos an external voltage (v thr ) should be applied to the unused complementary differential input. nominal v thr is 1.5 v for lvttl and v cc /2 for lvcmos inputs. this voltage must be within the v thr specification.
nb4l16m www.onsemi.com 10 application information all nb4l16m inputs can accept lvpecl, cml, lvttl, lvcmos and lvds signal levels. the limitations for dif ferential input signal (lvds, pecl, or cml) are minimum input swing of 75 mv and the maximum input swing of 2500 mv . within these conditions, the input voltage can range from v cc to 1.2 v. examples interfaces are illustrated below in a 50 environment (z = 50 ). 50 v cc d d 50 v cc v td v ee v cc q 50 50 v ee figure 20. cml to cml interface z q z figure 21. pecl to cml receiver interface 50 z z v cc v cc pecl driver d d 50 v ee v bias v td v ee r t r t v ee v cc r t 5.0 v 290 3.3 v 150 2.5 v 80 recommended r t values 50 50 v cc v td v bias v td
nb4l16m www.onsemi.com 11 50 z z v cc v cc lvds driver 50 v ee v ee d d v td v td figure 22. lvds to cml receiver interface figure 23. lvcmos/lvttl to cml receiver interface 50 z v cc v cc lvttl/ lvcmos driver d d 50 v ee no connect v td v cc v td no connect v ref v ref lvcmos lvttl 1.5 v recommended v ref values v cc v ee 2
nb4l16m www.onsemi.com 12 package dimensions ??? ??? ??? ? 16 3x3, 0.5p case 485g ? 01 issue f 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x l1 detail a l alternate terminal constructions ?? *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d . recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.03 0.05 a3 0.20 ref b 0.18 0.24 0.30 d 3.00 bsc d2 1.65 1.75 1.85 e 3.00 bsc e2 1.65 1.75 1.85 e 0.50 bsc k 0.18 typ l 0.30 0.40 0.50 l1 0.00 0.08 0.15 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nb4l16m/d eclinps is a registered trademark of semiconductor components industries, llc (scillc) or its subsidiaries in the united state s and/or other countries. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NB4L16MMNEVB

	To Download NB4L16MMNEVB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .