View APW7252_8987494.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. high efficiency power supply for small size display features general description two outputs: -+ 5v (APW7252a) -+ 5.2v (APW7252b) wide input voltage from 2.5v to 5.5v >82% efficiency with 12ma load between outp and outn fully integrated mosfets for synchronous rectification integrated compensation and feedback circuits i 2 c adjustable output voltages 1ua shutdown supply current programmable active discharge wlcsp1.92x1.28-15 package lead free green devices available (rohs compliant) the APW7252 is boost architecture ic and the major pro- viding to positive and negative voltage output driven. the APW7252 is synchronize boost ic and also synchronize charge pump output driven. the APW7252 has simply circuit application, only providing input supply ? boutput supply ? bpositive voltage and negative voltage capacitor. that ?| s advantage cost, cheap and simple scheme. the APW7252 is available in wlcsp 1.92x1.28-15 ball packages. applications smart phone portable device simplified application circuit cfly1 vin sw 2.5v~5.5v input 4.7m f 2.2 m h pgnd cfly2 outn 4.7 m f reg 2.2 m f 4.7 m f 4v~6v output 4.7 m f outp APW7252 enn enp scl sda i 2 c control enable/ disable -4v~-6v output agnd
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 2 ordering and marking information note: anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs and compatible with both snpb and lead-free soldiering operations. anpec lead-free products meet or exceed the leadfree requirements of ipc/jedec j std-020c for msl classification at lead-free peak reflow temperature. pin configuration APW7252 package code ha : wlcsp 1.92x1.28-15 operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device assembly material handling code temperature range package code APW7252a ha : w52a x x - date code APW7252b ha : x - date code w52b x a b c 1 2 3 d e cfly1 reg vin pgnd outp reg sda agnd sw cfly2 enn pgnd outn scl enp (top view)
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 3 absolute maximum ratings (note 1) note1: absolute maximum ratings are those values beyond which the life of a device may be impaired. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics symbol parameter typical value unit q ja junction-to-ambient resistance in free air (note 2) 76.5 o c/w q jc junction-to-case (top) resistance in free air 0.2 o c/w symbol parameter rating unit v reg , v cfly1 v outp reg, cfly1, outp to gnd voltage -0.3 ~ 7 v v outn, v cfly2 outn to gnd voltage +0.3 ~ -7 v v vin , v scl , v sda, v enn , v enp vin, scl, sda/fault, enn, enp to gnd voltage -0.3 ~ 7 v v sw sw to gnd voltage -0.3 ~ v reg +0.3 v human body model 2 kv charged device model 500 v latch up 100 ma t j maximum junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr maximum lead soldering temperature(10 seconds) 260 o c note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. symbol parameter range unit v vin vin to gnd voltage 2.5 ~ 5.5 v v sda, v enn , v enp vin, scl, sda, enn, enp to gnd voltage 0 ~ 5.5 v i out output current between outp and outn 0~40 ma t a ambient temperature -40 ~ 85 o c t j junction temperature -40 ~ 125 o c recommended operating conditions (note 3) note 3: refer to the typical application circuit.
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 4 electrical characteristics APW7252 symbol parameter test conditions min typ max unit supply current i vin vin supply current v enp =v enn =3.7v C 540 - m a i vin_sd vin supply current in shutdown v enp =v enn =0v C 1 3 m a under-voltage lockout v uvlo_r vin uvlo rising threshold voltage v vin rising, t a = -40 ~ 85 o c (note4) 2.3 2.4 2.5 v v uvlo_f vin uvlo falling threshold voltage v vin rising, t a = -40 ~ 85 o c (note4) 2.1 2.2 2.3 v v uvlo_hys vin uvlo threshold hyeteresis C 0.2 C v boost regulator v reg reg output voltage register vreg_set = 0x00, no load - 4 - v reg programmable range 4 - 6.2 v reg output voltage accuracy -3 - 3 % i bst_ilim boost nfet current limit v vin = 3.7 v, l=2.2uh, t a = 25 c 0.6 - - a r on_bst_l boost low side switch on-resistance t a =25 , i=100ma, - 300 - m r on_bst_h boost high side switch on-resistance t a =25 , i=100ma, - 500 - m i lxp_leak sw leakage current v sw =6v, v enp =v enn =0v - - 10 m a d max sw maximum duty - 91 - % f sw_bst boost switching frequency 1.35 1.8 2.25 mhz t ss_bst boost soft start time t a =25 , c vbst =10 m f - 600 - m s negative regulator (outn) v outn outn output voltage register voutn_set=0x00, no load - -4 - v outn programmable range -4 - -6 v outn output voltage accuracy -1 - 1 % f sw_outn charge pump switching frequency - 900 - khz load regulation i out =40ma - 15 - %/a i cfly1_lea k cfly1 pin leakage current v cfly1 =6v, v enn =0v - - 10 m a i cfly2_lea k cfly2 pin leakage current v cfly2 =-6v, v enn =0v -10 - - m a r on_cfly1 cfly1 to gnd on resistance i=100ma - 0.35 - r on_cfly2 cfly2 to gnd on resistance i=-100ma, pmosfet - 0.75 - v vin = 3.7v, enn = enp = v vin , v outp = 5.2v, v outn = -5.2 v, t a = -40 o c to 85 o c; typical values are at t a = 25 o c, unless otherwise noted.
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 5 electrical characteristics (cont.) APW7252 symbol parameter test conditions min typ max unit r on_reg_ cfly1 reg to cfly1 on resistance i=100ma - 0.65 - r on_outn _cfly2 outn to cfly2 on resistance i=-100ma - 0.55 - r dis_outn outn discharge resistance v outn =-1v - 100 - t ss_outn outn softstart time t a =25 - 0.6 - ms i out (vp to vn)=0ma-40ma-0 ma, tr=100ns, tf=400ns - - 3.5 % load transient v outn peak-to-peak voltage v vin =3.7v, v reg =5.4v, v outp =5.2v, v outn =-5.2v, c vreg =4.7uf, c outp =4.7uf, c outn =4.7uf, l=2.2uh, c fly =2.2uf, t a =25 i out (vp to vn)=12ma-40ma- 12ma, tr=100ns, tf=400ns - - 3.5 % no load - - 0.85 %/v i out (vp to vn)=5ma - - 1.25 %/v line transient v outn peak-to-peak voltage v vin =2.8v to 4.5v to 2.8v, tr=tf=24us, v reg =5.4v, v outp =5.2v, v outn =-5.2v, c vreg =4.7uf, c outp =4.7uf, c outn =4.7uf, l=2.2uh, c fly =2.2uf, t a =25 i out (vp to vn)=35ma - - 2.5 %/v positive regulator (outp) v outp outp output voltage register voutp_set=0x00, no load - 4 - v outp programmable range 4 - 6 v outp output voltage accuracy -1 - 1 % v drp_out p outp dropout voltage v load_outp =100ma - - 150 mv load regulation i out =80ma - 3.4 - %/a r dis_outp outp discharge resistance v outp =1v - 100 - t ss_outp outp softstart time t a =25 - 0.6 - ms i out (vp to vn)=0ma-40ma-0ma, tr=100ns, tf=400ns - - 2 % load transient v outp peak-to-peak voltage v vin =3.7v, v reg =5.4v, v outp =5.2v, v outn =-5.2v, c vreg =4.7uf, c outp =4.7uf, c outn =4.7uf, l=2.2uh, c fly =2.2uf, t a =25 i out (vp to vn)=12ma-40ma-12m a, tr=100ns, tf=400ns - - 2 % v vin = 3.7v, enn = enp = v vin , v outp = 5.2v, v outn = -5.2 v, t a = -40 o c to 85 o c; typical values are at t a = 25 o c, unless otherwise noted.
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 6 electrical characteristics (cont.) APW7252 symbol parameter test conditions min typ max unit no load - - 0.85 %/v i out =5ma - - 1 %/v line transient v outp peak-to-peak voltage v vin =2.8v to 4.5v to 2.8v, tr=tf=24us, v reg =5.4v, v outp =5.2v, v outn =-5.2v, c vreg =4.7uf, c outp =4.7uf, c outn =4.7uf, l=2.2uh, c fly =2.2uf, t a =25 i out =35ma - - 1.3 %/v thermal shutdown - 160 - thermal shutdown hysteresis - 10 - reg under-voltage threshold - 0.5*v reg - v outp under-voltage threshold - 0.5*v outp - v outn under-voltage threshold - 0.5*v out n - v logic/digital v il logic input low voltage enn, enp ,scl, sda - - 0.54 v v ih logic input high voltage enn, enp ,scl, sda 1.1 - - v input logic high threshold 0.8 - 1 v input logic high threshold hysteresis 200 mv internal pull-down resistance enn, enp - 200 - k i 2 c scl clock frequency - - 400 khz smbus control smbdat and smbclk logic high logic 1.1 - - v low logic - - 0.54 v smbdat and smbclk leakage current - 0.01 1 ua f smb smbus operating frequency 10 - 100 khz t buf bus free time between stop and start condition 4.7 - - us t _hd_sta hold time after start condition after this period, the first clock is generated 4 - - us t _sd_sta repeated start condition setup time 4.7 - - us t _sd_sto stop condition setup time 4 - - us t _hd_dat data hold time 300 - - ns t _su_dat data setup time 250 - - ns t _timeout detect clock low timeout 25 - 35 ms t _low clock low period 4.7 - - us t _high clock high period 4 - 50 us t _low_sex t slave device cumulative clock low extend time_slave - - 25 ms t _low_me xt master device cumulative clock low extend time_master - - 10 ms t f_smb fall time of smb dat/clk - - 300 ns t r_smb rise time of smb dat/clk - - 1000 ns t _smb_por power on reset of smb time in which a device must be operation after power on reset - 3 500 ms v vin = 3.7v, enn = enp = v vin , voutp = 5.4v, v outn = -5.4 v, t a = -40 o c to 85 o c; typical values are at t a = 25 o c, unless otherwise noted.
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 7 pin description pin no. name function a1 enn vn enable input. note, this pin has 200k (typ.) pull-down to agnd. a2 outn negative charge pump output. connect a 4.7 m f capacitor to ground. connecting two 4.7 m f capacitors to ground will lower the negative charge pump output voltage ripple. a3 cfly2 charge pump negative connection. place a capacitor between cfly1 and cfly2 to generate the outn voltage. b1 enp reg and outp enable input. note, this pin has 200k (typ.) pull-down to agnd. b2 scl serial clock connection for i 2 c interface. b3, e1 pgnd power ground. c1 vin input supply. connect a 4.7 m f to ground. c2 sda serial data connection for i 2 c interface. c3 cfly1 charge pump positive connection. place a capacitor between cfly1 and cfly2 to create the outn voltage. d1 sw switch node for boost converter. connect an inductor between the vin and sw pins for boost converter operation. d2 agnd analog ground. d3,e2 reg boost converter output. the boost converter output supplies the power to the negative charge pump and ldo. connect a 4.7 m f capacitor to ground. e3 outp ldo output. connect a 4.7 m f capacitor to ground.
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 8 block diagram and typical application circuit cfly1 vin sw 2.5v~5.5v input boost pwm controller c1 l1 c2 pgnd cfly2 regulated charge pump outn 0.5 xv ref reg v reg current limit comparator gm dac oscillator i 2 c interface scl sda enp enn uv gm v ref v ref dac outp dac c3 4.7 m f c4 c5 i 2 c bus -4v~-6v 4v~6v 0.5xv ref uv pgnd agnd ldo regulator v outp v outn 1.2v 4.7 m f 2.2 m h 4.7 m f 2.2 m f 4.7 m f
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 9 power on/off sequence vin enp enn v reg 0.6ms v outp v outn uvlo_r power on-enn rising after v reg softstart finished 0.6ms 0.6ms 0.6ms outp discharge uvlo_f outn discharge discharge active or non-active determined by disn bit discharge active or non-active determined by disp bit
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 10 power on/off sequence (cont.) vin enp enn v reg 0.6ms v outp v outn uvlo_r power on-enn rising before v reg softstart finished 0.6ms 0.6ms 0.6ms outp discharge uvlo_f outn discharge discharge active or non-active determined by disn bit discharge active or non- active determined by disp bit
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 11 power on/off sequence (cont.) vin enp enn v reg 0.6ms v outp v outn uvlo_r power off-enn falling before enp falling 0.6ms 0.6ms 0.6ms outp discharge uvlo_f outn discharge discharge active or non-active determined by disn bit discharge active or non-active determined by disn bit
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 12 i 2 c control b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 1 1 0 r/w read=1 write=0 7-bit hard coded device address: t buf t hd;sta t low t r t hd;dat t f t high t su;dat t su;sto v ih v il v ih v il smbclk smbdat s p s p start stop t low:mext t low:mext t low:mext clk ack clk ack smbclk smbdat t su;sta write 1 byte (command byte is sent after the address and detemines which register receives the data that follows the command byte.) read 1 byte (command byte is sent after the address and detemines which register is accessed. after a start, the device address is sent again and lsb is set to logic 1. data defined by command byte then is sent by APW7252.) s 0 1 1 0 1 command byte 0 1 1 w r / a data byte a p slave address a register address register data slave address s 0 1 1 0 1 command byte 0 1 1 w r / a data byte 1 p slave address a register address register data 1 s w r / 1 a a timing diagram figure 1: smbus common ac specification figure 2: timing diagram of smbus timeout
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 13 register map slave address : 0111110 address bit name default value description resolution range r/w 00h [4:0 ] voutp_se t 0x0 voutp voltage adjustment 100mv 4v ~ 6v r/w 01h [4:0 ] voutn_s et 0x0 voutn voltage adjustment 100mv -4v ~ -6v r/w 02h [4:0 ] vreg_set 0x0 vreg voltage adjustment 100mv 4v ~ 6.2v r/w 03h [1:0 ] discharge control 0x03 voutp/voutn discharge resistance enable/disable - - r/w 04h [4:0 ] vendor id 0x00 vendor id code - - r table 1: register map
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 14 register definition data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved reserved reserved voutp_set[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w bit name bit definition voutp_set[4:0] voutp voltage adjustment: 00000: 4v 01011: 5.1v 00001: 4.1v 01100: 5.2v (default:7252b) 00010: 4.2v 01101: 5.3v 00011: 4.3v 01110: 5.4v 00100: 4.4v 01111: 5.5v 00101: 4.5v 10000: 5.6v 00110: 4.6v 10001: 5.7v 00111: 4.7v 10010: 5.8v 01000: 4.8v 10011: 5.9v 01001: 4.9v 10100: 6.0v 01010: 5.0v (default:7252a) 10101~11111: 6.0v register 00:voutp_set
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 15 register definition (cont.) data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved reserved reserved voutn_set[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w bit name bit definition voutn_set[4:0] voutn voltage adjustment: 00000: -4v 01011: -5.1v 00001: -4.1v 01100: -5.2v (default:7252b) 00010: -4.2v 01101: -5.3v 00011: -4.3v 01110: -5.4v 00100: -4.4v 01111: -5.5v 00101: -4.5v 10000: -5.6v 00110: -4.6v 10001: -5.7v 00111: -4.7v 10010: -5.8v 01000: -4.8v 10011: -5.9v 01001: -4.9v 10100: -6.0v 01010: -5.0v (default:7252a) 10101~11111: -6.0v register 01:voutn_set
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 16 register definition (cont.) data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved reserved reserved vreg_set[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w bit name bit definition vreg_set[4:0] vreg voltage adjustment: 00000: 4v 01100: 5.2v (default:7252a) 00001: 4.1v 01101: 5.3v 00010: 4.2v 01110: 5.4v (default:7252b) 00011: 4.3v 01111: 5.5v 00100: 4.4v 10000: 5.6v 00101: 4.5v 10001: 5.7v 00110: 4.6v 10010: 5.8v 00111: 4.7v 10011: 5.9v 01000: 4.8v 10100: 6.0v 01001: 4.9v 10101: 6.1v 01010: 5.0v 10110: 6.2v 01011: 5.1v 10111~11111: 6.2v register 02:vreg_set
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 17 register definition (cont.) data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved reserved reserved reserved reserved reserved disp disn read/write r/w r/w r/w r/w r/w r/w r/w r/w bit name bit definition disn voutn discharge resistance enable/disable: 0: disable voutn discharge resistance 1: enable voutn discharge resistance disp voutp discharge resistance enable/disable: 0: disable voutp discharge resistance 1: enable voutp discharge resistance (note: if enn and enp are goes low then discharge function was always turn on.) register 03: discharge_control data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved reserved reserved vendor id code [4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w bit name bit definition vendor id code [4:0] vendor id code: 00101: default register 04: vendor id
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 18 function description under-voltage lockout an under-voltage lockout function prevents the device from operating if the input voltage on vin is lower than approxi- mately 2.4v. the device automatically enters the shut- down mode if the voltage on vin drops below approxi- mately 2.2v. this under-voltage lockout function is imple- mented in order to prevent the malfunctioning of the converter. soft-start the APW7252 has a built-in digital soft-start to control the rise rate of the output voltage and limit the input current surge during start-up. during soft-start, the reference voltage, output from a dac, raises up step by step to control the output voltage to rise gently. frequency modulation mode (pfm) the APW7252 s boost converter and negative charge pump will automatically enter in pfm mode operation to reduce the dominant switching losses. these controls get low quiescent current, help to maintain high efficiency over the complete load range. over-temperature protection (otp) the over-temperature circuit limits the junction tempera- ture of the APW7252. when the junction temperature ex- ceeds 160 o c, a thermal sensor turns off the both power mosfet s, allowing the devices to cool. the thermal sen- sor allows the converters to start a soft-start process and regulate the output voltage again after the junction tem- perature cools by 10 o c. the otp designed with a 10 o c hysteresis lowers the average junction temperature (t j ) during continuous thermal overload conditions, increas- ing the life time of the device. under voltage protection (uvp) the under-voltage protection circuit monitors the outputs to protect the device against short-circuit or heavy load conditions. when one of the output voltages is falls be- low the uvp threshold (50% of vref), a fault signal is generated and the device turns off all outputs. the device is then latched off and will initials a soft-start process until re-cycle enp and enn or vin. over current protection (ocp) the APW7252 monitors the output current of the boost converter, flowing through the n-channel power mosfet, and limits the ic from damages during overload, short- circuit and over-voltage conditions. enable and shutdown driving enp and enn to ground turns off the vp and vn voltage respectively. when both enn and enp is in logic low state, the boost converter is also enters shutdown mode and vin quiescent supply current reduces to less than 3 m a. discharge resistance enable/disable APW7252 discharge resistance function always turn on condition are enn and enp were setting low when input voltage is high than por. secondly, the input voltage is low than por then that s always turn on no matter enn and enp were setting high or low states. the indepen- dent discharge function of v outp and v outn can be by disp bit and disn bit. if the v outp and v outn were normal opera- tion then discharge resistance function was disabling.
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 19 function description input voltage capacitor selection the APW7252 is boost architecture application of power ic. the major boost architecture is providing to positive and negative voltage output driving capable. the ceramic capacitors are recommended for input capacitor applications. low esr will effectively reduce the input voltage ripple caused by switching operation. the 4.7uf capacitors are sufficient for most applications. the input capacitor selection was suggestion x5r or x7r type. output voltage (boost converter) capacitor selection for the boost converter output voltage capacitor suggests choose low esr filter ceramic capacitor. a minimum ce- ramic of 4.7uf or high than value capacitor has advan- tages response for load transient and ripple. the output capacitor selection was suggestion x5r or x7r type. output voltage (positive) capacitor selection the positive voltage is ldo architecture. the input ca- pacitor use low esr ceramic capacitor, a minimum of 4. 7uf or more than 4.7uf capacitor. the output capacitor selection was suggestion x5r or x7r type. layout suggestion the fig.3 is layout suggestion. a few notes can be let APW7252 has high performance. please refer as below notes for your modify pcb layout. 1. input, output, flying, positive and negative capacitors can be closed to the ic terminal as far as possible. 2. reg pin have 2 pins must to connected together. 3. the sw pin node trace is short as far as possible. 4. the ground path keeps to the one plane area. 5. pgnd must be shorted together with agnd on the same ground plane. figure.3 layout suggestion output voltage (negative) capacitor selection the negative voltage is charge pump architecture. the input capacitor use low esr ceramic capacitor, a mini- mum of 4.7uf or more than 4.7uf capacitor. the output capacitor selection was suggestion x5r or x7r type. this capacitor chooses to will impact the negative output volt- age accuracy and load regulation. flying capacitor selection the negative voltage is charge pump architecture, its must need to connect an external capacitor. the flying capacitor suggestion use 2.2uf ceramic capacitor. the flying capacitor selection was suggestion x5r or x7r type. (top view) cfly1 reg vin pgnd outp reg sda agnd sw cfly2 enn pgnd outn scl enp :via :top path :bottom path :ground path
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 20 package information wlcsp1.28x1.92-15 pin 1 e d aaa a1 a2 a nx c seating plane s y m b o l min. max. 0.62 0.12 0.20 0.30 1.92 1.98 0.20 a a1 b d e e millimeters a2 0.35 0.42 0.40 bsc wlcsp1.28*1.92-15 0.016 bsc min. max. inches 0.024 0.005 0.014 0.017 0.008 0.012 0.076 0.078 0.008 1.28 1.34 0.050 0.053 aaa 0.05 0.002 2 e e b
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 21 carrier tape & reel dimensions a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d application a h t1 c d d w e1 f 178.0 2.00 50 min. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 8.0 0.30 1.75 0.10 3.5 0.05 p0 p1 p2 d0 d1 t a0 b0 k0 wlcsp(1.9x2.1) 4.0 0.10 4.0 0.10 2.0 0.05 1.5+0.10 -0.00 0.5 min. 0.25 0.02 1.55 0.05 2.05 0.05 0.70 0.05 (mm) devices per unit package type unit quantity wlcsp(1.28x1.92) tape & reel 3000
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 22 classification profile taping direction information wlcsp1.28x1.92-15 user direction of feed
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 23 classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ tj=125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma reliability test program
copyright ? anpec electronics corp. rev. a.1 - dec., 2016 APW7252 www.anpec.com.tw 24 customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838

▲Up To Search▲

Price & Availability of APW7252

	To Download APW7252 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .