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cyw43362 single-chip ieee 802.11? b/g/n mac/baseband/radio cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document no. 002-14779 rev. *h revised march 30, 2017 the cypress cyw43362 single-chip device provides the highest leve l of integration for interent of things applications and handh eld wireless systems, featuring in tegrated ieee 802.11? b/g and ieee 802.11n. it in cludes a 2.4 ghz wlan cmos power amplifier (pa) that meets the output power requiremen ts of most handheld systems. an optional external low-noise amplifier (lna) and exte r- nal pa are also supported. along with the integrated power amplifier, the cyw43362 also in cludes integrated transmit and receive baluns, further reducing the overall solution cost. host interface options include sdio v2 .0 that can operate in 4b or 1b modes. utilizing advanced design techniques and process technology to reduce active and idle power, the cyw43362 is designed to address the needs of highly mobile devices that require minima l power consumption and compact size. it includes a power manage- ment unit that simplifies the system power topology and allows for operation di rectly from a rechargeable mobile platform batte ry while maximizing battery life. features single-band 2.4 ghz ieee 802.11 b/g/n integrated wlan cmos power amplifier with internal power detector and closed-loop power control internal fractional-n pll enables the use of a wide range of reference clock frequencies supports ieee 802.15.2 exte rnal 3-wire and 4-wire coexistence schemes to opt imize bandwidth utilization with other co-located wireless technologies such as bluetooth, zigbee, or bt smart. also supports seci coexistence interface. supports sdio v2.0 (50 mhz, 4-bit and 1-bit) integrated arm cortex?-m3 cpu with on-chip mem- ory enables running ieee 802.11 firmware that can be field-upgraded with future features. supports wmm ? , wmm-ps, and wi-fi voice personal (upgradable to voice enterprise in the future) security: ? hardware wapi acceleration engine ? aes and tkip in hardware for faster data encryp- tion and ieee 802.1 1i compatibility ? wpa?- and wpa2?- (personal) support for pow- erful encryption and authentication programmable dynamic power management supports battery voltage range from 2.3v to 4.8v sup- plies with internal switching regulator 1 kbit one-time programmable (otp) memory for storing board parameters 69-bump wlbga (4.52 mm x 2.92 mm, 0.4 mm pitch) figure 1. cyw43362 system block diagram t/r ? switch vio vbatt 2.4 ? ghz ? wlan ? tx 2.4 ? ghz ? wlan ? rx cyw43362 wlan ? host ? i/f wl_rst_n sdio cbf coexistence ? interface system ? clock sleep ? clock
document no. 002-14779 rev. *h page 2 of 51 cyw43362 introduction this document provides engineering design in formation for the cyw43362, a single chip with an integrated 2.4 ghz rf transceiver , mac, and baseband processor that fully supports the i eee 802.11? b/g/n standards. the information provided is intended for hardware design engin eers who will be incorporating the cyw43362 into their designs. cypress part numbering scheme cypress is converting the acquired iot part numbers from broadcom to the cypress part numbering sch eme. due to this conversion, there is no change in form, fit, or function as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. table 1. mapping table for part number between broadcom and cypress iot resources cypress provides a wealth of data at http://www.cypress.co m/internet-things-iot to help you to select the right iot device for your design, and quickly and effectively integrate the device into y our design. cypress provides cust omer access to a wide range of infor- mation, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates. customers can acquire technical documentation and so ftware from the cypress s upport community website ( http://com- munity.cypress.com/ ). broadcom part number cypress part number BCM43362 cyw43362 BCM43362kubg cyw43362kubg
document no. 002-14779 rev. *h page 3 of 51 cyw43362 contents 1. overview ............................................................ 4 1.1 overview ............................................................. 4 1.2 standards compliance ........................................ 5 2. power supplies and power management ....... 6 2.1 wlan power management ................................. 6 2.2 power supply topology ..... .............. ........... ........ 6 2.3 voltage regulators .......... .................................... 7 2.4 pmu sequencing ................................................ 7 2.5 low-power shutdown ......................................... 8 2.6 cbuck regulator features ................................ 8 3. frequency references ..................................... 9 3.1 crystal interface and clock generation .............. 9 3.2 tcxo .................................................................. 9 3.3 external 32.768 khz low-power oscillator ....... 11 4. wlan system interfaces ............................... 12 4.1 sdio v2.0 .......................................................... 12 4.1.1 sdio pin descriptions ........................... 12 4.2 external coexistence interface ........................ 13 5. wireless lan mac and phy.......................... 15 5.1 mac features ................................................... 15 5.1.1 mac description ..... ............................... 15 5.1.1.1.psm ............................................... 16 5.1.1.2.wep .............................................. 16 5.1.1.3.txe ................................................ 16 5.1.1.4.rxe ............................................... 16 5.1.1.5.ifs ................................................. 17 5.1.1.6.tsf ................................................ 17 5.1.1.7.nav ............................................... 17 5.1.1.8.mac-phy interface ....................... 17 5.2 phy description ................................................ 17 5.2.1 phy features ........................................ 17 6. wlan radio subsystem ................................ 20 6.1 receive path ..................................................... 20 6.2 transmit path .................................................... 20 6.3 calibration ......................................................... 20 7. cpu and global functions ............. ................ 21 7.1 wlan cpu and memory s ubsystem .... ........... 21 7.2 one-time programmable memory .................... 21 7.3 gpio interface .................................................. 21 7.4 jtag interface ................................................. 21 7.5 uart interface ................................................ 21 8. wlan software architecture......................... 22 8.1 host software architecture ................................22 8.2 device software architecture .............................22 8.2.1 remote downloader ...............................22 8.3 wireless configuration ut ility ............ ............ .....23 9. pinout and signal descriptions..................... 23 9.1 signal assignments ............................................23 9.2 wlan gpio signals and strapping options .....31 10. dc characteristics.......................................... 32 10.1 absolute maximum rating s ...............................32 10.2 environmental ratings .......................................32 10.3 electrostatic discharge specifications ...............32 10.4 recommended operating conditions and dc characteristics .............................................33 11. wlan rf specifications................................ 34 11.1 2.4 ghz band general rf specifications ..........34 11.2 wlan 2.4 ghz receiver performance specifications .....................................................34 11.3 wlan 2.4 ghz transmitter performance specifications .....................................................37 11.4 general spurious emissions specifications .......38 12. internal regulator electrical specifications. 39 12.1 core buck regulator ...... .............. .............. ........39 12.2 3.3v ldo (ldo3p3) ..........................................41 12.3 cldo .................................................................41 12.4 lnldo1 .............................................................42 13. system power consumption ......................... 43 14. interface timing and ac characteristics ..... 44 14.1 sdio default mode timing ................................44 14.2 sdio high-speed mode timing .........................45 14.3 jtag timing ......................................................46 15. package information ...................................... 47 15.1 package thermal characteristics ......................47 15.1.1 junction temperature estimation and psi versus theta jc ..................................47 16. mechanical information.. ................................ 48 17. ordering information...................................... 49 18. references ...................................................... 49 document history page ................................................. 50 sales, solutions, and legal information ...................... 51
document no. 002-14779 rev. *h page 4 of 51 cyw43362 1. overview 1.1 overview the cypress cyw43362 provides the highest le vel of integration for a internet of thi ngs applications and handheld wireless syst em, with integrated ieee 80 2.11 b/g/n. it provides a small form-f actor solution with minima l external components to drive down cost f or mass volumes and allows for flexibility in size, form, and functi on. the cyw43362 is designed to address the needs of highly mo bile devices that require minimal power consumption and reliable operation. figure 2 shows the interconnect of all the major physical blocks in the cyw43 362 and their associated ex ternal interfaces, which are described in greater detail in the following sections. figure 2. cyw43362 block diagram backplane ram (240 kb) rom (448 kb) pmu ctrl lpo swreg ldo sleep clk 2.4 ghz pa (int) gpio uart jtag jtag arm processor sdiod mac single-stream 802.11n phy radio 802.11b/g/n gpio uart jtag otp wdog timer bt coex ext lna/rf switch control power supply sdio por wl_rst_n xtal osc dedicated crystal or tcxo always on buffer tcxo signal shared with bt/fm/gps chip
document no. 002-14779 rev. *h page 5 of 51 cyw43362 1.2 standards compliance the cyw43362 supports the following standards: ieee 802.11n 802.11b 802.11g 802.11d 802.11h 802.11i 802.11j the cyw43362 will support the following future drafts/standards: 802.11w?secure management frames 802.11 extensions: ? wmm? ? 802.11i mac enhancements ? 802.11r fast roaming support (between aps) ? 802.11k radio resource measurement security: ? wep ? wapi ? wpa? personal ? wpa2? personal ? aes (hardware accelerator) ? tkip (hw accelerator) ? ckip (sw support) qos protocols: ? wmm ? wwm-ps (u-apsd) ? wwm-sa proprietary protocols: ? wfaec coexistence interfaces: ? supports ieee 802.15.2 external three-wi re coexistence scheme to support additional wireless technologies, such as bluetooth, zigbee, or bt smart.
document no. 002-14779 rev. *h page 6 of 51 cyw43362 2. power supplies and power management 2.1 wlan power management the cyw43362 has been designed with the strin gent power consumption requirements of po rtable devices in mind. all areas of the chip design are optimized to minimize power consumption. silic on processes and cell libraries were chosen to reduce leakage cur - rent and supply voltages. additionally, the cyw43362 integrated ram is a low-leakage memory wit h dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additionally, the cyw43362 includes an advanced wlan power management unit (pmu) sequencer . the pmu sequencer provides significant power savings by putting the cyw43362 into various pow er management states appropriate to the current environment and activities that are being performed. th e power management unit enables and disables internal regulators, switches, and othe r blocks based on a computation of the requir ed resources and a table that describes the relationship between resources and the t ime needed to enable and disable them. power-up sequences are fully programmable. configurable, free-running counters, which run on the 32.768 khz low-power oscillator (lpo) sleep clock in t he pmu sequencer, are used to turn individual regulators and power switches on and off. clock speeds are dynamically changed, or gat ed off, as appropriate for the current mode. slower clock spee ds are used wherever possible. the cyw43362 power states are described as follows: active mode?all components in the cyw43 362 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode (pwm or burst) based on the load current. clock speeds are dynam ically adjusted by the pmu sequencer. sleep mode?the radio, afe, plls, and t he crystal oscillator are powered down. the rest of the cyw43362 remains pow- ered up in an idle state. all main clocks are shut down. the 32.768-khz lpo sleep clock is available only for the pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in sleep mode, the primary power consumed is due to leakage current. power-down modes?the cyw43362 has a full power-down mode and a low-power shutdown mode. a full power-down occurs when there is no vio voltag e, and wl_rst_n and ext_smprs_req ar e low. a low-power shutdown occurs when vio is present, and wl_rst_n and ext_smprs_req are low. in low-power shutdown, only the band gap and ldo3p3 are on. both power-down modes are exited when t he host asserts either wl_rst_n or ext_smps_req high. external mode?in this mode, the following are true: ? the assertion of ext_smps_req turns only the core buck (cbuck) regulator on. ? the wlan is in reset (wl_rst_n = low). ? the state of ldo3p3 and the ban d gap are dependent on vbat and vio. 2.2 power supply topology the cyw43362 contains a power management unit (pmu), a buck-mode switching regulator, and three low noise ldos. these integrated regulators simplify power supply design in wlan embed ded designs. all regulator input s and outputs are brought out t o pins on the cyw43362, providing system designer s with the flexibility to choose which of the cyw43362 integrated regulators to use. one option is to supply the pmu from a single, variable power supply, vbat, which can range from 2.3v to 4.8v. using this option, all of the required voltages are pr ovided by cyw43362 regulators except for a low current rail, vio, which must be prov ided by the host to power the i/o signal buffers when the chip is out of reset. alternately, if specific rails such as 3.3v, 1.8v, and 1.2v already exist in the system, appropriate regulators in the cyw43362 can be bypassed, thereby reducing the cost and boar d space associated with external regulator components such as inductors and large capacitors. the cbuck and cldo get powered whenever the reset signal is dea sserted. the cbuck regulator can be turned on by asserting ext_smps_req high. asserting ext_pwm_r eq high will set cbuck to pwm mode . driving ext_pwm_req low will put cbuck in burst mode. optionally, lnldo may also be powered. all regulators are powered down only when the reset signal is asserted.
document no. 002-14779 rev. *h page 7 of 51 cyw43362 figure 3. power topology 2.3 voltage regulators all cyw43362 regulator output voltages are pmu programmable and have the following nominal c apabilities. the currents listed below indicate regulator capabilities. see system power consumption on page 43 for the actual expected loads. core buck switching regulator (cbuck): 2.3?4.8v input, nominal 1.5v ou tput (up to 500 ma). ldo3p3: 2.3?4.8v input, nominal 3.3v output (up to 40 ma) cldo (for the core): 1.45?2.0v input, nominal 1.2v output (up to 150 ma) low-noise lnldo1: 1.45?2.0v input, nom inal 1.2v output (up to 150 ma) see internal regulator electrical specifications on page 39 for full regulator specifications. 2.4 pmu sequencing the wlan pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and th e time needed to enable and disable them. resource requests come from several sources: clock re quests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource request timers. the pmu sequencer maps clock requests in to a set of resources required to produce the r equested clocks. each resource is in one of four states: enabled, disabled, tr ansition_on, and transition_off. each resource has a timer that co ntains 0 when the resource is enabled or disabled and a nonzero value in the transition states. the timer is loaded with the resource's time_on or time_off value when the pmu determines that the resour ce must be enabled or disabled. that timer decrements on each lpo sleep clock. when it reaches 0, the state changes from trans ition_off to disabled or transition_on to enabled. if the time_ on value is 0, the resource can go immediately from disabled to en abled. similarly, a time_off value of 0 indicates that the resou rce can cyw43362 ln ? ldo1 section ? sensitive ? to ? power ? supply ? noise loads ? not ? sensitive to ? power ? supply ? noise ? cldo vbat ? 2.3v ? to ? 4.8v wl_rst_n 1.4v ? to ? 1.8v 1.2v 2.5v ? to ? 3.4v ? 1.2v cyw43362 cyw43362 internal ? wlan ? power amplifiers (30 ? ma) optional (250 ? ma) external ? device ? (bt/fm/gps/other) vio notes: 1 . ? ldo3p3 ? is ? always ? enabled ? when ? vio ? is ? present ? in ? order ? to ? provide ? bias ? for ? vddio_rf ? and ? the ? external ? rf ? switch. 2. ? areas ? in ? dark ? gray ? are ? internal ? to ? the ? BCM43362. ? 3. ? vddio ? and ? vddio_sd ? can ? be ? powered ? from ? separate ? supplies ? if ? sdio ? signaling ? needs ? to ? be ? at ? a ? different ? level ? than ? vddio. ?? this ? diagram ? shows ? the ? more ? common ? case ? where ? vddio ? and ? vddio_sd ? are ? powered ? from ? the ? same ? supply. ext_pwm_req ext_smps_req vddio_rf wl ? otp ? (3.3v) wl ? radio ? ?part ? a rf ? pll wrf ? afe wrf ? xo wrf ? clpo/ext. ? lpo wrf ? lna/rx, ? bg, ? rcal wrftx wrf ? radio ? ?bb ? pll wrf ? otp wl ? digital, ? including ? memory wrf ? vco ? and ? logen vddio internal ? lnldo ldo3p3 1 core ? buck ? regulator ? vddio_sd
document no. 002-14779 rev. *h page 8 of 51 cyw43362 go immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transitio n or the timer load-decrement sequence. during each clock cycle, t he pmu sequencer performs the following actions: 1. computes the required resource set based on requests and the resource dependency table. 2. decrements all timers whose values are nonzero. if a timer r eaches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. 3. compares the request with the current resource status and determines which resources must be enabled or disabled. 4. initiates a disable sequence for each resource that is enabl ed, no longer being requested, and has no powered-up dependents. 5. initiates an enable sequence for each res ource that is disabled, is being reques ted, and has all of its dependencies enabled. 2.5 low-power shutdown the cyw43362 provides a low-power shutdown feature that allows the device to be tu rned off while the host, and any other device in the system, remain operational. when wlan is not needed, the wlan core can be put in reset by asserting wl_rst_n (logic low). vddio_rf and vddio remain powered while vio and vbat ar e both present, allowing the cy w43362 to be effectively off while keeping the i/o pins powered. during a low-power shut-dow n state, provided vio continues to be supplied to the cyw43362, most outputs are tristated and most inputs are disabled. input voltages must remain within the limits defined for normal operat ion. this is done to prevent current paths or create loading on any digital signals in the system, enabling the cyw43362 to be a ful ly inte- grated embedded device that takes full adv antage of the lowest power-saving modes. two signals on the cyw43362, the system clock input (oscin) a nd sleep clock input (ext_sleep_clk), are designed to be high- impedance inputs that do not load down the driving signal even if the cyw43362 does not have vddio power applied to it. when the cyw43362 is powered on from this state, it is the same as a normal power-up, and the device does not contain any informatio n about its state from bef ore it was powered down. 2.6 cbuck regulator features the cbuck regulator has several features that help make the cy w43362 ideal for mobile devices. first, the regulator uses 3.2 mhz as its pwm switching frequency for buck regulation. this high frequency allows th e use of small passive components for the switcher's external circui t, thereby saving pcb space in the design. in addi tion, the cbuck regulator has three modes of operat ion: pwm mode for low-ripple output and for fast transient response and extended load ranges, burst mode for lower currents, and low power burst mode for higher efficiency when the load current is very low (low power burst mode is not available for external devices). the cbuck supports external smps request to allow flexibility of supplying 1.8v to cyw43362, bcm2076, and other external devices when ext_smps_req is asserted high. it also supports lo w ripple pwm mode (7 mvpp typical) for noise-sensitive appli- cations when ext_pwm_req is asserted high. a 100 s wait/set tling time from the assertion of ext_pwm_req high before increasing the load current allows the intern al integrator precharging to complete. th is is not a requirement, but is preferred . ta b l e 2 lists the mode the cbuck operates in (b urst or pwm), based on various external control signals and internal cbuck mode register settings. table 2. cbuck operating mode selection wl_rst_l ext_smps_req ext_pwm_req internal cbuck mode required cbuck mode 00xxoff 010xburst 011xpwm 1 0 x burst burst 10xpwmpwm 110burstburst 110pwmpwm 111xpwm
document no. 002-14779 rev. *h page 9 of 51 cyw43362 for detailed cbuck perform ance specifications, see core buck regulator on page 39 . 3. frequency references an external crystal is used for generatin g all radio frequencies and normal operation clocking. as an alternative, an external fre- quency reference driven by a temperature-compensated crystal o scillator (tcxo) signal may be used. no software settings are required to differentiate between the two. in addition, a low- power oscillator (lpo) is provided for lower power mode timing. 3.1 crystal interface and clock generation the cyw43362 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscil- lator, including all external components, is shown in figure 4 . consult the reference schemati cs for the latest configuration. figure 4. recommended oscillator configuration the cyw43362 uses a fractional-n synthesize r to generate the radio frequencies, clocks , and data/packet timing. this enables it to operate using numerous frequency references. this may either be an external source such as a tcxo or a crystal interfaced direc tly to the cyw43362. the default frequency reference setting is a 26 mhz crystal or tcxo. the signal requirements and characteristics for the crysta l interface are shown in table 3 on page 10 . note: although the fractional-n synthesizer can support many refe rence frequencies, frequencies other than the default require support to be added in the driver, plus additional ext ensive system testing. contact cypress for further details. 3.2 tcxo as an alternative to a crystal, an external precision tcxo ca n be used as the frequency referenc e, provided that it meets the p hase noise requirements listed in table 3 on page 10 . when the clock is provided by an exte rnal tcxo, there are two possible connec- tion methods, as shown in figure 5 and figure 6 : 1. if the tcxo is dedicated to driving the cyw43362, it should be connected to the osc_in pin through an external 1000 pf coupling capacitor, as shown in figure 5 . the internal clock buffer connected to this pin will be turned off when the cyw43362 goes into sleep mode. when the clock buffer turns on and of f, there will be a small impedance variation up to 15%. power must be supplied to the wrf_xtal_vdd1p2 pin. 2. an alternative is to dc-couple the tcxo to the wrf_tcxo_in pin, as shown in figure 6 . use this method when the same tcxo is shared with other devices and a change in the input impedance is not acceptable be cause it may cause a frequency shift that cannot be tolerated by the other device sharing the tcxo. this pin is connected to a clock buffer powered from wrf_tcxo_vdd3p3. if the power supply to th is buffer is always on (even in sleep mode), the clock buffer is always on, thereby ensuring a constant input impedance in all states of the device. the maximum current drawn from wrf_tcxo_vdd3p3 is approximately 500 a. 12 ? ?27 ? pf 12 ? ?27 ? pf oscout oscin c c r note : ? resistor ? value ? determined ? by ? crystal ? drive ? level. ? see ? reference ? schematics ? for ? details.
document no. 002-14779 rev. *h page 10 of 51 cyw43362 figure 5. recommended circuit to use with an external dedicated tcxo figure 6. recommended circuit to use with an external shared tcxo table 3. crystal oscillator and external clock requirements and performance parameter conditions/notes crystal external frequency reference min typ max min typ max units frequency ? between 12 mhz and 52 mhz a crystal load capacitance ? ? 12 ? pf esr ? ? ? 60 ? input impedance (oscin) b resistive 30k 100k ? ? capacitive ??7.5 pf input impedance (wrf_tcxo_in) resistive 30k 100k ? ? capacitive ??4 pf oscin input voltage ac-coupled analog signal 400 ? 1200 mv p-p oscin input low level dc-coupled digital signal 0?0.2 v oscin input high level dc-coupled digital signal 1.0 ? 1.36 v wrf_tcxo_in input voltage dc-coupled analog signal c 400 ? tcxo_ vdd d mv p-p frequency tolerance initial + over temperature ? ?20 ? 20 ?20 ? 20 ppm tcxo nc 1000 ? pf oscin oscout wrf_tcxo_in wrf_tcxo_vdd3p3 tcxo nc wrf_tcxo_in oscout oscin to ? other ? devices wrf_tcxo_vdd3p3 connect ? to ? a ? supply ? (1.7v ? to ? 3.3v) ? that ? is ? powered ? up ? or ? down ? with ? the ? external ? tcxo ? clock.
document no. 002-14779 rev. *h page 11 of 51 cyw43362 3.3 external 32.768 khz low-power oscillator the cyw43362 uses a secondary low-frequency sleep clock for low-po wer mode timing. either the internal low-precision lpo or an external 32.768 khz precision oscillator is required. the internal lpo frequency range is approximately 33 khz 30% over proce ss, voltage, and temperature, which is adequate for some applications . however, one trade-off caused by this wide lpo tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing bea- cons. whenever possible, the preferred approach is to use a precisio n external 32.768 khz clock that meets the requirements listed in ta b l e 4 . note: the cyw43362 will auto-detect the lpo clock. if it senses a clock on the ext_sleep_clk pin, it will use that clock. if it doesn't sense a clock, it will use its own internal lpo. to use the internal lpo: tie ext_sleep_ clk to ground. do not leave this pin fl oating. to use an external lpo: con- nect the external 32.768 kh z clock to ext_sleep_clk. duty cycle 26 mhz clock 40 50 60 % phase noise e, f (ieee 802.11 b/g) 26 mhz clock at 1 khz offset ? ? ?119 dbc/hz 26 mhz clock at 10 khz offset ? ? ?129 dbc/hz 26 mhz clock at 100 khz offset ? ? ?134 dbc/hz 26 mhz clock at 1 mhz offset ? ? ?139 dbc/hz phase noise e, f (ieee 802.11n, 2.4 ghz) 26 mhz clock at 1 khz offset ? ? ?124 dbc/hz 26 mhz clock at 10 khz offset ? ? ?134 dbc/hz 26 mhz clock at 100 khz offset ? ? ?139 dbc/hz 26 mhz clock at 1 mhz offset ? ? ?144 dbc/hz a. the frequency step size is approximat ely 80 hz. the cyw43362 does not auto-detect the reference clock frequency; the frequenc y is specified in the software/nvram file. b. the internal clock buffer connected to this pin will be turned off when the cyw43362 goes into sleep mode. when the clock buf fer turns on and off, there will be a small impedance variation up to 15%. c. this input has an internal dc blocking capacitor, so do not include an external dc blocking capacitor. d. the maximum allowable voltage swing for the wrf_tcxo_in input is equal to the wrf_tcx0_vdd3p3 supply voltage range, which is 1.7v to 3.3v. e. for a clock reference other than 26 mhz, 20 log10(f/26) db should be added to the limits, where f = the reference clock fre quency in mhz. f. if the selected clock has a flat phase-noise response above 100 kh z, then it is acceptable to subtract 1 db from all 1 khz, 10 khz, and 100 khz values shown, and ignore the 1 mhz requirement. table 3. crystal oscillator and external clock requirements and performance (cont.) parameter conditions/notes crystal external frequency reference min typ max min typ max units
document no. 002-14779 rev. *h page 12 of 51 cyw43362 4. wlan system interfaces 4.1 sdio v2.0 the cyw43362 wlan section supports sdio version 2.0. for both 1- bit (25 mbps), 4-bit modes (100 mbps), and high speed 4-bit (50 mhz clocks?200 mbps). it has the ability to map the interrupt signal on a gpio pin. this out-of-band interrupt signal notif ies the host when the wlan device want s to turn on the sdio interface. the ability to force control of the gated clocks from within the wlan chip is also provided. sdio mode is enabled using the strapping option pins. see table 9 on page 31 for details. three functions are supported: function 0 standard sdio function (max blocksize/bytecount = 32b) function 1 backplane function to access the internal system on chip (soc) address spac e (max blocksiz e/bytecount = 64b) function 2 wlan function for efficient wlan packet tr ansfer through dma (max blocksize/bytecount = 512b) 4.1.1 sdio pin descriptions table 4. external 32.768 khz lo w-power oscillator specifications symbol parameter condition/notes specification units minimum typical maximum fr frequency ? ? 32768 ? hz ? f/fr frequency tolerance at 25c ?30 ? +30 ppm ?20c document no. 002-14779 rev. *h page 13 of 51 cyw43362 figure 7. signal connections to sdio host (sd 4-bit mode) figure 8. signal connections to sdio host (sd 1-bit mode) 4.2 external coexistence interface to manage wireless medium sharing for optimal performance, an ex ternal coexistence interface is provided that enables signaling between the cyw43362 and one or two external collocated wireless devic es such as bluetooth and/or wimax. note that three of the external coexistence interface pins are multiplexed with gpios. by default, the pins are bt_coex pins. through software they ca n be changed to gpios. the fourth bt_coex signal is also multip lexed with a gpio, but this one is a gpio by default and can be changed via software to be btcx_freq. see pinout and signal descriptions on page 23 for more details. the signals in table 6 can be enabled by software. table 6. coexistence signals signal description btcx_status coexistence signal indicating bluetooth priority status and tx/rx direction. btcx_rf_active coexistence signal i ndicating that bluetooth is active. btcx_freq indicates that the coexisting bluetooth is about to transmit on a restricted channel. btcx_txconf coexistence output giving bluetooth permission to transmit. sd ? host cyw43362 cmd dat[3:0] clk sd ? host cyw43362 cmd clk data irq
document no. 002-14779 rev. *h page 14 of 51 cyw43362 figure 9. 4-wire coexistence wiring cyw43362 coexisting device btcx_rf_active btcx_freq btcx_txconf btcx_status rf_active priority ? 2 txconf status coex_in coex_out_0 coex_out_1 c_gpio_1 * ? note: the ? pull \ down ? is ? only ? required ? if ? the ? coexisting ? device ? has ? the ? potential ? to ? float ? the ? signal. r* r* r* r
document no. 002-14779 rev. *h page 15 of 51 cyw43362 5. wireless lan mac and phy 5.1 mac features the cyw43362 wlan mac supports features specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the salient features are listed below: transmission and reception of aggregated mpdus (a-mpdu) support for power management schemes, including wmm pow er-save, power-save multipoll (psmp) and multiphase psmp operation. support for immediate ack and block-ack policies interframe space timing support, including rifs support for rts/cts and cts-to-self fram e sequences for protecting frame exchanges back-off counters in hardware for supporting multiple priorities as specified in the wmm specification timing synchronization function (tsf), network allocation ve ctor (nav) maintenance, and ta rget beacon transmission time (tbtt) generation in hardware hardware off-load for aes-ccmp, legacy wpa tkip, lega cy wep ciphers, wapi, and support for key management support for coexistence with blue tooth and other external radios programmable independent basic service set (ibss) or infrastructure basic service set functionality statistics counters for mib support 5.1.1 mac description the cyw43362 wlan mac is designed to support high throughput oper ation with low-power consumptio n. it does so without com- promising on bluetooth coexistence policies, thereby enabling optimal performance over both networks. in addition, several powe r- saving modes that have been implemented allow the mac to consum e very little power while maintaining network-wide timing syn- chronization. the architecture diagram of the mac is shown in figure 10 on page 15 . figure 10. wlan mac architecture the following sections provide an overview of the important modules in the mac. embedded ? cpu ? interface host ? registers, ? dma ? engines tx \ fifo 32 ? kb wep wep, ? tkip, ? aes txe tx ? a \ mpdu rxe pmq psm shared ? memory 6 ? kb psm ucode memory ext \ ihr ifs backoff, ? btcx tsf nav ihr ? bus shm ? bus mac \ phy ? interface rx \ fifo 10 ? kb rx ? a \ mpdu
document no. 002-14779 rev. *h page 16 of 51 cyw43362 5.1.1.1 psm the programmable state machine (psm) is a microcoded engine that provides most of the low-level control to the hardware to impl e- ment the ieee 802.11 specification. it is a microcontroller that is highly optimized for flow control operations, which are pred ominant in implementations of communica tion protocols. the instruction set and fundam ental operations are simple and general, which allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microc ode memory. it uses the shared memory to obtain operands for instructions, as a dat a store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratchpad memory (similar to a register bank) to stor e frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines by programming inte rnal hardware registers (ihr). these ihrs are collocated with the hardware functions they control and are accessed by the psm via the ihr bus. the psm fetches instructions from the micr ocode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations, the operands are obtained from shared memory, scratchpad, ihrs, or instruction literals , and the results are written into the shared memory, scratchpad, or ihrs. there are two basic branch instructions: cond itional branches and alu based branches. to better support the many decision point s in the ieee 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condi - tion signals are available to the psm without polling th e ihrs), or on the resu lts of alu operations. 5.1.1.2 wep the wired equivalent privacy (wep) engine encapsulates all the ha rdware accelerators to perform the encryption and decryption, as well as mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, wpa2 aes-ccmp. based on the frame type and association in formation, the psm determines the appropriat e cipher algorithm to be used. it supplie s the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify t he mic on receive frames. wapi is also supported. 5.1.1.3 txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with wep module to encrypt frames and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fi fos. the mac supports multiple logical queues to support traffi c streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to sched - ule a queue from which the next frame is tr ansmitted. once the frame is scheduled, the txe hardware transmits the frame based o n a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapi d assembly of mpdus into an a-mpdu for transmission. the hard- ware module aggregates the encrypted mpdus by ad ding appropriate headers and pad delimiters as needed. 5.1.1.4 rxe the receive engine (rxe) constitutes the rece ive data path of the mac. it interfaces with the dma en gine to drain the received frames from the rxfifo. it transfers byte s across the mac-phy interface and interfac es with the wep module to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteri a such as receiver address, b ssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the hea ders of the container s, and disaggregate them into component mpdus.
document no. 002-14779 rev. *h page 17 of 51 cyw43362 5.1.1.5 ifs the ifs module contains the timers required to determine interfra me space timing including rifs timing. it also contains multip le back-off engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these tim- ers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or per - form transmit frame-bursting (rifs or sifs separated, as within a txop). the back-off engines (for each access category) monitor channel ac tivity, in each slot duration, to determine whether to contin ue or pause the back-off counters. when the back-off counters reach 0, the txe gets noti fied, so that it may commence frame transmis- sion. in the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based o n pol- icies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power- saving mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initi alized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires, the mac is restored to its functional state. the psm upd ates the tsf timer based on th e sleep duration, ensuring that the tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. 5.1.1.6 tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also ma intains the target beacon transm is- sion time (tbtt). the tsf timer hardware, under the control of the psm, is ca pable of adopting timestamps received from beacon and probe response frames in order to ma intain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and d own- link transmission times used in psmp. 5.1.1.7 nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the durati on field of mac frames. this ensures that the mac complies with the protection me chanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs modu le, which uses it as a virtual carrier-sense indication. 5.1.1.8 mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from /to the phy. in addition, there is a program - ming interface, which can be controlled either by the host or the psm to co nfigure and control the phy. 5.2 phy description the cyw43362 wlan digital phy is designed to comply wi th ieee 802.11b/g/n sing le stream to provide wireless lan connectivity supporting data rates from 1 mbps to 72 mbps fo r low-power, high-performance handheld applications. the phy has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairmen ts. it incorporates efficient implementations of the filters, fft and viterbi decoder al gorithms. efficient algorithms have been de signed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisi tion and tracking, channel estimation and tracking. the phy receiver also contains a robust 11b demodulator. the phy carrier sense has been tuned to provide high throughput for ieee 802. 11g/11b hybrid networks with bluetooth coexistence.
document no. 002-14779 rev. *h page 18 of 51 cyw43362 5.2.1 phy features supports ieee 802.11b, 11g, 11n single-stream standards. supports optional greenfield mode in tx and rx. supports optional stbc receive of two space-time stream. supports ieee 802.11h/d for worldwide operation. algorithms achieving low power, enhanced sensitivity, range, and reliability algorithms to maximize throughput perf ormance in presence of bluetooth automatic gain control scheme for blocking and non blocking application scenario for cellular applications. closed loop transmit power control supports per packet rx antenna diversity. designed to meet fcc and other regulatory requirements. figure 11. wlan phy block diagram the phy is capable of fully calibrating the rf front-end to ex tract the highest performance. on power-up, the phy performs a fu ll calibration suite to correct for iq mismat ch and local oscillator leakage. the phy also performs periodic calibration to compen sate for any temperature related drift, thus maintaining high-performa nce over time. a closed loop transmit control algorithm mainta ins the output power to required level with capability control tx power on a per packet basis. one of the key feature of the phy is two sp ace-time stream receive capability. the st bc scheme can obtain diversity gains by us ing multiple transmit antennas in ap (access point) in a fading channel environment, wit hout increasing the complexity at the sta. details of the stbc receive are shown in the block diagram in figure 12 on page 19 . filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi ? decoder tx ? fsm pa ? comp modulation ? and ? coding modulate/ spread frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex
document no. 002-14779 rev. *h page 19 of 51 cyw43362 figure 12. stbc receive block diagram in stbc mode, symbols are processed in pairs. equalized output symbols are linearly combined and decoded. channel estimation is refined on every pair of symbols using th e received symbols and reconstructed symbols. equalizer demod ? combine demapper viterbi channel ? h symbol memory weighted ? averaging estimate channel transmitter fft ? of ? 2 ? symbols descramble ? and ? deframe h old h upd h new
document no. 002-14779 rev. *h page 20 of 51 cyw43362 6. wlan radio subsystem the cyw43362 includes an integrated wlan rf transceiver that has been optimized for use in 2.4 ghz wireless lan systems. it is designed to provide low power, low cost, and robust communicat ions for applications operatin g in the globally available 2.4 ghz unlicensed ism band. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. impro ve- ments to the radio design include shared tx/rx bas eband filters and high immunity to supply noise. figure 13. radio functional block diagram 6.1 receive path the cyw43362 has a wide dynamic range, direct conversion receiv er. it employs high order on-chip channel filtering to ensure re li- able operation in the noisy 2.4 ghz ism band. 6.2 transmit path baseband data is modulated and upconverted to the 2.4 ghz ism band. a linear on-chip power amplifier is included, which is capa - ble of delivering high output powers while meeting ieee 802.11b/g/n specif ications without the need for an external pa. this pa can be powered directly from vbat, thereby el iminating the need for a separate paldo. closed-loop output power control is completel y integrated. 6.3 calibration the cyw43362 features dynamic on-chip ca libration, eliminating process variatio n across components. this enables the cyw43362 to be used in high-volume applications, because calib ration routines are not required during manufacturing testing. these calibration routines are performed periodically in the course of normal radio operation. examples of this automatic calib ration are baseband filter calibration for optimum transmit and receive performance and loft calibration for leakage reduction. in add ition, i/q calibration, r calibration, and vco calibration are performed on-chip. shared ? lpf wl ? logen wl ? pll wlan ? bb voltage ? regulators lpo/ext ? lpo/rcal wl ? adc i wl ? tx ? g \ mixer wl ? dac i wl ? lna1 wl ? lna2 wl ? dac q wl ? adc q wl ? grx wl ? gtx wl ? pa wl ? pad mux mux i q i q wl ? rx ? g \ mixer
document no. 002-14779 rev. *h page 21 of 51 cyw43362 7. cpu and global functions 7.1 wlan cpu and memory subsystem the cyw43362 includes an integrated arm cortex?-m3 processor with internal ram and rom. the arm cortex-m3 processor is a low-power processor that features low ga te count, low interrupt latency, and low- cost debugging. it is intended for deeply em bed- ded applications that require fast interr upt response features. the processor implem ents the arm? architecture v7-m with suppor t for thumb?-2 instruction set. arm cortex-m3 del ivers 30% more performance gain over arm7tdmi. at 0.19 w/mhz, the cortex-m3 is the most power efficient gener al purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. arm cortex-m3 uses multiple technologies to reduce cost throu gh improved memory utilization, reduced pin overhead, and reduced silicon area. arm cortex-m3 supports independent buses for co de and data access (icode/dcode and system buses). arm cor- tex-m3 supports extensive debug features incl uding real time trace of program execution. on-chip memory for the cpu includes 240 kb sram and 448 kb rom. 7.2 one-time programmable memory various hardware configuration parameters ma y be stored in an internal 1024-bit one-time programmable (otp) memory, which is read by system software after device rese t. in addition, customer-specific parameters, including the system vendor id and the m ac address, can be stored, depending on the specific board design. the initial state of all bits in an unprogr ammed otp device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with t he cypress wlan manufacturing tes t tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but onl y bits which are still in the 0 state can be altered during each programming cycle. prior to otp programming, all values should be verified using th e appropriate editable nvram.txt file, which is provided with t he ref- erence board design package. documentation on the otp development process is availa ble on the cypress customer support por- tal. 7.3 gpio interface five general purpose i/o (gpio) pins are available on the cyw43362 that can be used to connect to various external devices. gpios are tristated by default. subsequently, they can be programme d to be either input or output pins via the gpio control reg ister. they can also be programmed to have in ternal pull-up or pull-down resistors. gpio_0 is initially used as a str apping option to select between sdio. gpios 3, 4, and 5 are multiplexed with the bl uetooth coexistence in terface. by default, these pins are bt_coex pins. software c an reprogram these pins to behave as gpios. gpio_1 is a gpio by default, but can be reprogrammed by software to become the btcx_freq signal. 7.4 jtag interface the cyw43362 supports the ieee 1149.1 jtag boundary scan standard for performing device package and pcb assembly testing during manufacturing. in addition, the jtag interface allows cy press to assist customers by us ing proprietary debug and charact er- ization test tools during board bring-up. t herefore, it is highly recommended to provid e access to the jtag pins by means of te st points or a header on all pcb designs. 7.5 uart interface one uart interface can be enabled by software as an alternate f unction on the jtag pins. uart_rx is available on the jtag_tdi pin, and uart_tx is available on the jtag_tdo pin. the uart is primarily for debugging during development. by ad ding an external rs-232 transceiver, this uart enables the cyw43362 to operate as rs-232 dat a termination equipment (dte) for exchanging a nd managing data with other serial devices. it is compatible with the industry standard 16550 uart, and it provides a fifo size of 64 8 in each direction.
document no. 002-14779 rev. *h page 22 of 51 cyw43362 8. wlan software architecture 8.1 host software architecture the host driver (dhd) provides a transparent connection betwe en the host operating system and the cyw43362 media (for exam- ple, wlan) by presenting a network driver interface to the host operating system and communicating with the cyw43362 over an interface-specific bus (sdio) to: forward transmit and receive frames between the host network stack and the cyw43362 device, and pass control requests from the host to the cyw4336 2 device, returning the cyw43362 device responses the driver communicates with the cyw43362 over the bus using a control channel and a data channel to pass control messages and data messages. the actual message format is based on the bdc protocol. 8.2 device software architecture the wireless device, protocol, and bus drivers are run on the embedded arm ? processor using a cypres s-defined operating system called hndrte, which transfers data over a propriety cypress format over the sdio interface between the host and device (bdc/ lmac). the data portion of the format cons ists of ieee 802.11 frames wrapped in a cy press encapsulation. the host side architec- ture provides all missing functionality between a network device and the cypress device interface. the host can also be customi zed to provide functionality between the cypress device interface and a full network device interface. this transfer requires a message-oriented (framed) interconnect between the host and dev ice. the sdio bus is an addressed bus? each host-initiated bus operation contains an explicit device target address?and does not natively support a higher-level data frame concept. cypress has implemented a hardwar e/software message encapsulation schem e that ignores the bus operation code address and prefixes each frame with a 4- byte length tag for framing. the device pres ents a packet-level interface over which d ata, control, and asynchronous event (fro m the device) packets are supported. the data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver. if the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet received from the device medium follows the same path in the reverse direction. if the pa ckets are control packets, the proto- col header is decoded by the protocol driv er. if the packets are wireless ioctl packets , the ioctl api of the wireless driver i s called to configure the wireless device. the microcode running in the d11 core processes all time-critical tasks. 8.2.1 remote downloader when the cyw43362 powers up, the dhd initializes and downloads the firmware to run in the device. figure 14. wlan software architecture sdio bdc/lmac ? protocol wireless ? device ? driver d11 ? core dhd ? host ? driver
document no. 002-14779 rev. *h page 23 of 51 cyw43362 8.3 wireless configuration utility the device driver that supports the cypre ss ieee 802.11 family of wireless solutions pr ovides an input/output control (ioctl) i nterface for making advanced configuration settings. the ioctl interface makes it possible to make settings that are normally not possibl e when using just the native oper ating system-specific i eee 802.11 configura- tion mechanisms. the utility uses ioctls to query or se t a number of different driver/chip operating properties. 9. pinout and si gnal descriptions 9.1 signal assignments figure 15 shows the 69-ball wlbga ball map. table 7 on page 24 shows the wlbga signal descriptions. figure 15. 69-ball wlbga ball map ab c defghjkl 1 wrf_rfin wrf_rfout #n/a wrf_pa_vdd rf_sw_ctrl_0 rf_sw_ctrl_1 vddio_rf vout_3p3 sr_vddbat1 sr_vddbat1 sr_vlx 1 2 #n/a wrf_pa_gnd #n/a wrf_pa_gnd wrf_padrv_gnd rf_sw_ctrl_3 rf_sw_ctrl_2 vdd sr_vddbat2 pmu_avss sr_pvss 2 3 wrf_lna_vdd1p2 #n/a #n/a wrf_padrv_vdd vss vss vss vdd ext_smps_req vout_lnldo1 vdd_ldo 3 4 wrf_lna_gnd wrf_ana_vdd1p2 wrf_gpio_out wrf_ana_gnd gpio_0 vss vss vddio wl_rst_n ext_pwm_req vout_cldo 4 5 wrf_vco_ldo_in_vdd1p8 #n/a wrf_vco_ldo_out_vdd1p2 wrf_res_ext gpio_1 / btcx_freq sdio_data_2 jtag_tdo btcx_txconf/ gpio_3 ext_sleep_clk vddio_sd sdio_data_1 5 6 wrf_vco_gnd #n/a wrf_xtal_gnd oscout wrf_afe_gnd xtal_pu jtag_tms jtag_tdi btcx_status/ gpio_4 sdio_data_3 sdio_data_0 6 7 wrf_tcxo_in wrf_tcxo_vdd3p3 wrf_xtal_vdd1p2 os cin #n/a wrf_afe_vdd1p2 jtag_trst_l jtag_tck btcx_rf_active/ gpio_5 sdio_cmd sdio_clk 7 ab c defghjkl
document no. 002-14779 rev. *h page 24 of 51 cyw43362 table 7. wlbga signal descriptions ball # signal name type description wlan rf interface a1 wrf_rfin i wlan ieee 802.11n rx input (50 ? ) b1 wrf_rfout o wlan ieee 802.11n internal power amplifier output (50 ? ) d5 wrf_res_ext i connect to external 15 k ? resistor (1%) to ground rf control lines (io supply = vddio_rf) e1 rf_sw_ctrl0 o rf switch control line. default at this pin is high. f1 rf_sw_ctrl1 o rf switch control line. default at this pin is low. g2 rf_sw_ctrl2 o rf switch control line. default at this pin is low. f2 rf_sw_ctrl3 o rf switch control line. default at this pin is low. note: 1. use only rf_sw_ctrl1 and rf_sw_ctrl2 unless diversity is required, in which case rf_sw_ctrl0 and rf_sw_ctrl3 can also be used to select the antenna for a pair of spdt switches. 2. for a transfer switch, use only rf_sw_ctrl1 and rf_sw_ct rl2 with the main antenna to rx when rf_sw_ctrl1 is high. 3. for a diamond-type switch, do the following: rf_sw_ctrl0 must select wlan tx, aux antenna. rf_sw_ctrl1 must select wlan rx, main antenna. rf_sw_ctrl2 must select wlan tx, main antenna. rf_sw_ctrl2 must select wlan rx, aux antenna. 4. for cases where a shared antenna is used for wlan and bl uetooth, rf_sw_cntrl_0 defaults to high when the cyw43362 is in reset. use a switch topology in which the bluetooth rf path is connected to the antenna when this signal is high. this allows bluetooth access to the antenna when wlan is in reset. 5. the following is a list of the internal pull-up/pull-down resistor strengths for the rf switch control lines when the cyw4336 2 is in reset: minimum typical maximum ? pup @ 3.3v 39k 58k 69k ? pdn @ 3.3v 39k 58k 67k 6. the default drive st rength is 6.0 ma.
document no. 002-14779 rev. *h page 25 of 51 cyw43362 sdio interface f5 sdio_data_2 i/o sdio data line 2. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enab led, but it can be disabled via software. l6 sdio_data_0 i/o sdio data line 0. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enab led, but it can be disabled via software. l5 sdio_data_1 i/o sdio data line 1. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enab led, but it can be disabled via software. l7 sdio_clk i sdio clock. k6 sdio_data_3 i/o sdio data line 3. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enabled, but it can be disabled by software. k7 sdio_cmd i/o sdio command line. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enabled, but it can be disabled by software. sdio weak internal pull-up resistances : for 1.8v (minimum, typical, maximum): 34 k ? , 51 k ? , 86 k ? for 2.5v (minimum, typical, maximum): 21 k ? , 32 k ? , 54 k ? for 3.3v (minimum, typical, maximum): 16 k ? , 24 k ? , 37 k ? software programmable sdio drive strength options : for 1.8v: 0.5 ma, 1.0 ma, 1.5 ma, 2.0 ma, 2.5 ma (default), and 3.0 ma for 2.5v: 1.5 ma, 3.0 ma, 4.5 ma, 6.0 ma, 7.5 ma (default), and 9.0 ma for 3.3v: 2.0 ma, 4.0 ma, 6.0 ma, 8.0 ma, 10.0 ma (default), and 12.0 ma jtag interface g6 jtag_tms i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, th is pin can be left unconnected (nc) as it has an internal weak pull-up resistor. g5 jtag_tdo o for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, this pin can be left unconnected (nc). this pin is also muxed with uart_tx, which can be enabled by software. h6 jtag_tdi i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, th is pin can be left unconnected (nc) as it has an internal weak pull-up resistor. this pin is also muxed with uart_rx, which can be enabled by software. h7 jtag_tck i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, th is pin can be left unconnected (nc) as it has an internal weak pull-up resistor. g7 jtag_trst_l i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, th is pin can be left unconnected (nc) as it has an internal weak pull-up resistor. jtag drive strength: for 1.8v: 1.0 ma for 2.5v: 2.5 ma for 3.3v: 3.0 ma output slewing can be enabled or disabled by software; it is enabled by default. clocks a7 wrf_tcxo_in i reference clock input for use when sharing a tcxo with another chip, such as a bt/ fm/gps chip (see frequency references on page 9 ). this input has an internal dc blocking capacitor, so do not include an external dc blocking capacitor. connect directly to the external tcxo. this input pad is powered by the wrf_tcxo_vdd3p3 supply, which should be continually powered whenever the external tcxo is powered, even when the cyw43362 is in reset, thereby ensuring this input maintains a constant load on t he tcxo signal in all device modes. if unused, ground this pin. d6 oscout o xtal oscillator amplifier output. see frequency references on page 9 . d7 oscin i xtal oscillator amplifier inpu t. this pin can also be used as the reference clock input from a dedicated (that is, not shared) tcxo. table 7. wlbga signal descriptions (cont.) ball # signal name type description
document no. 002-14779 rev. *h page 26 of 51 cyw43362 f6 xtal_pu o external reference clock enable (clock_request) default mode (open source) : xtal_pu is driven high when the clock is requ ested and pulled low with a weak internal pull-down resistor when the clock is not requested. push-pull : always driven high or low (no pu/p d). push-pull mode is enabled by software. xtal_pu internal pull-down (pd) resistances : pd @ 1.8v (minimum, typical, maximum): 356 k ? , 558 k ? , 651 k ? pd @ 2.5v (minimum, typical, maximum): 356 k ? , 559 k ? , 652 k ? pd @ 3.3v (minimum, typical, maximum): 356 k ? , 559 k ? , 653 k ? xtal_pu drive strength : for 1.8v: 2.0 ma for 2.5v: 5.0 ma for 3.3v: 6.0 ma output slewing can be enabled or disabled by software; it is enabled by default. j5 ext_sleep_clk i input pin for optional high-precisi on 32.768 khz clock (sleep clock). table 7. wlbga signal descriptions (cont.) ball # signal name type description
document no. 002-14779 rev. *h page 27 of 51 cyw43362 gpio interface e4 gpio_0 i/o this pin is used as a strapping option to se lect sdio mode (pull low). it is strongly recommended to use gpio_0 only as a host bus interface select. this pin has a weak internal pull-down resistor. e5 gpio_1/btcx_freq i/o general-purpose interface pin. this pin is high impedance on power-up and reset. subsequently, it becomes an input or output through software control. this pin has a programmable weak pull-up/down. this gpio can be used as the out-of-band wlan_irq signal for sdio. this pin can also be programmed via software to behave as the btcx_freq coexistence signal. h5 btcx_txconf/gpio_3 ? multiplexed bt_coex/gpio pi ns. when programmed as gpios, pins are high impedance on power-up and reset. subsequ ently, they can be individually programmed to become inputs or outputs through software control. they can also be programmed to have internal pull-up or pull-down resistors. only gpio 1, 3, 4, and 5 (total 4) can be used as gpios. gpio drive strength: for 1.8v: 1.0 ma for 2.5v: 2.5 ma for 3.3v: 3.0 ma output slewing can be enabled or disabled by software; it is enabled by default. j6 btcx_status/gpio_4 ? j7 btcx_rf_active/gpio_5 ? note: the following is a list of the internal pull-up/pull-down resistor strengths for the default strapping options described in the gpio section above: minimum typical maximum ? pup @ 1.8v 40k 59k 70k ? pdn @ 1.8v 39k 58k 67k ? pup @ 2.5v 40k 58k 69k ? pdn @ 2.5v 39k 58k 67k ? pup @ 3.3v 39k 58k 69k ? pdn @ 3.3v 39k 58k 67k miscellaneous signals j4 wl_rst_n i active low wlan reset signal. includes an internal 200 k ? pull-down resistor. within 1.5 ms of wl_rst_n being driven high, the pmu changes this from pd to high-z. software can optionally enable the pull-down resistor. vih = 1.08v to 3.6v. vil < 0.4v. h5 btcx_txconf/gpio_3 o coexistence output giving bluetooth permissi on to transmit. this pin is muxed and can be changed to a gpio via software. e5 gpio_1/btcx_freq i by default, this pin behaves as a gpio. however, it can be programmed via software to behave as a coexistence signal that indi cates that the coexisting bt is about to transmit on a restricted channel. j6 btcx_status/gpio_4 i coexistence signal indicating bluetooth priority status and tx/rx direction. this pin is muxed and can be changed to a gpio via software. j7 btcx_rf_active/gpio_5 i coexistence signal indicating that bluetooth is active. this pin is muxed and can be changed to a gpio via software. note: the above bluetooth coexistence and gpio signals have keepers t hat prevent them from floating when they aren?t connected; however, when they are connected to another component, prevention from floa ting can?t be assured by the keepers. integrated voltage regulators h1 vout_3p3 o 3.3v low noise ldo output (40 ma) k3 vout_lnldo1 o 1.2v output for low noise ldo1, 150 ma j1, k1 sr_vddbat1 i battery voltage input for cbuck j2 sr_vddbat2 i battery voltage input for band gap and ldop3 table 7. wlbga signal descriptions (cont.) ball # signal name type description
document no. 002-14779 rev. *h page 28 of 51 cyw43362 j3 ext_smps_req i internal 200 k ? pull-down resistor included. vih = 1.08v to 3.6v, and vil < 0.4v. note: driving this input high sets cbuck to external mode, but it does not power down the rest of the pmu. the pmu powers down when wl_rst_n is low. note: this pin is only used if the cyw43362 switching regulator is also used to power an external device. this pin should be connected to ground for applications that do not use this feature. k4 ext_pwm_req i driving this input high forces cbuck into pwm mode. internal 200 k ? pull-down resistor included. vih = 1.08v to 3.6v, and vil < 0.4v. note: this pin is only used if the cyw43362 switching regulator is also used to power an external device. this pin should be connected to ground for applications that do not use this feature. l1 sr_vlx o core buck regulator: output to inductor l3 vdd_ldo i input supply pin for cldo and lnldo1 (also acts as the voltage feedback for cbuck). l4 vout_cldo o 1.2v output from the core ldo, 150 ma table 7. wlbga signal descriptions (cont.) ball # signal name type description
document no. 002-14779 rev. *h page 29 of 51 cyw43362 power supplies b4 wrf_ana_vdd1p2 i 1.2v analog power supply a5 wrf_vco_ldo_in_ vdd1p8 i 1.4v to 1.8v vco/ldo power supply input b7 wrf_tcxo_vdd3p3 i 1.7v to 3.3v supply for the cyw43362 tcxo driver. to maintain a constant load on the tcxo_in pin, even when power is removed from the cyw43362, connect this supply pin to a 1.7v to 3.3v supply that is present whenever the external tcxo is powered up. note that this should be a clean supply (do not use vio). if not used, this pin must be connected to ground. c7 wrf_xtal_vdd1p2 i 1.2v xtal oscillator power supply. this supply is required for all clock options: crystal, dedicated tcxo, and shared tcxo (wrf_tcxo_in). d1 wrf_pa_vdd i internal power amplifier power supply (vbat supported), high current d3 wrf_padrv_vdd i internal power amplifier driver power supply (vbat supported) f7 wrf_afe_vdd1p2 i 1.2v afe power supply h2, h3 vdd i 1.2v digital supply for the core g1 vddio_rf i rf i/o and otp supply (3.3v) h4 vddio i digital i/o supply. k5 vddio_sd i digital i/o supply for sdio interface signals. a3 wrf_lna_vdd1p2 i 1.2v analog supply to the internal lna. c5 wrf_vco_ldo_ out_vdd1p2 o vco ldo output. some designs may requir e a decoupling capacitor (nominal 0.22 f) for optimal wlan performance. cypress reco mmends that a 0201 size footprint for this capacitor be included in all designs in case the capacitor is necessary. ground d4 wrf_ana_gnd ? analog ground a6 wrf_vco_gnd ? vco ground b2, d2 wrf_pa_gnd ? internal power amplifier ground c6 wrf_xtal_gnd ? xtal ground e2 wrf_padrv_gnd ? internal power amplifier driver ground e3, f3, f4, g3, g4 vss ? ground e6 wrf_afe_gnd ? afe ground k2 pmu_avss ? pmu analog ground l2 sr_pvss ? buck regulator: power switch ground a4 wrf_lna_gnd ? internal rx lna ground no connects c4 wrf_gpio_out o no connect table 8. cyw43362 during reset and after reset or during sleep signal name/group i/o type during reset after reset (and after firmware initialization) or during sleep pull r i/o pull r i/o reset/control wl_rst_n digital pd input high z a, b input ext_smps_req digital pd input pd c input ext_pwm_req digital pd input pd c input sdio signals sdio_clk digital none high z none input table 7. wlbga signal descriptions (cont.) ball # signal name type description
document no. 002-14779 rev. *h page 30 of 51 cyw43362 sdio_cmd digital none high z pu d bidirectional sdio_data0 digital none high z pu d bidirectional sdio_data1 digital none high z pu d bidirectional sdio_data2 digital none high z pu d bidirectional sdio_data3 digital none high z pu d bidirectional clock xtal_pu (clk_req) digital pd high z pd d output (high) d, e ext_sleep_clk (external 32.768 khz clock) digital none high z none input oscin (reference clock) clk none high z none input bluetooth coexistence f btcx_txconf digital none high z configurable output btcx_freq digital none high z configurable input btcx_rf_actvive digital none high z configurable input btcx_status digital none high z configurable input table 8. cyw43362 during reset and after reset or during sleep (cont.) signal name/group i/o type during reset after reset (and after firmware initialization) or during sleep pull r i/o pull r i/o
document no. 002-14779 rev. *h page 31 of 51 cyw43362 9.2 wlan gpio signals and strapping options the pins listed in ta b l e 9 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descripti ons table. each strapping option pin has an internal pull-up (pu) or pull-down (pd) r esistor that determines the default mode. to change t he mode, connect an external pu resistor to vddio or a pd resistor to gnd, using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. rf switch control rf_sw_ctl_0 digital pu high z none output rf_sw_ctl_1 digital pd high z none output rf_sw_ctl_2 digital pd high z none output rf_sw_ctl_3 digital pd high z none output gpios g gpio_x digital none high z configurable configurable a. within 1.5 ms of wl_rst_n being driven hi gh, the pmu changes this from pd to high-z. b. software can optionally enable a weak internal pull-down resistor. c. internal pull-down resistor can be disabled via software. d. default mode (open source): xtal_pu is driven high when a cl ock is requested, and pulled low with a weak internal pull-down resistor when a clock is not requested. push-pull: always driven high or low (no pu/pd). avail able via a strapping option for the fcfbga and wlcsp packages. e. the clock is not requested during sleep mode. f. the bluetooth coexistence and gpio signals have keepers that prev ent them from floating when they aren?t connected; however, when they are connected to another component, prevention from floating can?t be assured by the keepers. table 9. gpio functions and strapping options pin name wlbga pin # default function description gpio_0 e4 0 mode_sel this pin selects the host interface mode: ? 0: sdio table 8. cyw43362 during reset and after reset or during sleep (cont.) signal name/group i/o type during reset after reset (and after firmware initialization) or during sleep pull r i/o pull r i/o
document no. 002-14779 rev. *h page 32 of 51 cyw43362 10. dc characteristics note: values in this document are design goals and are subject to change based on the results of device characterization. 10.1 absolute maximum ratings caution! the absolute maximum ratings in ta b l e 1 0 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operat ion is not guaranteed under thes e conditions. operation at abso lute maximum conditions for extended periods can advers ely affect long-term reliability of the device. 10.2 environmental ratings the environmental ratings are shown in ta b l e 11 . 10.3 electrostatic discharge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding strap s to discharge static electricity is required when handling these devices. always store unused material in its antistatic packagi ng. table 10. absolute maximum ratings rating symbol value unit dc supply for vbat vbat ?0.5 to 6.0 v dc supply for wlan power amplifier vddpa ?0.5 to 6.0 v dc supply voltage for i/o vddio, vddio_sd ?0.5 to 4.1 v dc supply voltage for rf blocks in chip vddrf ?0.5 to 1.29 v dc supply voltage for core vdd ?0.5 to 1.29 v dc supply voltage for rf i/os vddio_rf ?0.5 to 4.1 v dc input supply voltage for cldo and lnldo ? ?0.5 to 2.1 v wrf_vco_ldo_in_vdd1p8 ? ?0.5 to 2.75 v wrf_tcxo_vdd3p3 ? ?0.5 to 3.63 v wl_rst_n ? ?0.5 to 3.63 v ext_smps_req ? ?0.5 to 3.63 v ext_pwm_req ? ?0.5 to 3.63 v maximum undershoot voltage for i/o v undershoot ?0.5 v maximum overshoot voltage for i/o v overshoot vddio + 0.5 v maximum junction temperature t j 125 c table 11. environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +85c ? c operation storage temperature ?40 to +125c ? c? relative humidity less than 60 % storage less than 85 % operation table 12. esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/jesd22-a114 1250 v machine model (mm) esd_hand_mm machine model contact 50 v
document no. 002-14779 rev. *h page 33 of 51 cyw43362 10.4 recommended operating conditions and dc characteristics functional operation is not guarant eed outside the limits shown in table 13 , and operation outside these limits for extended periods can adversely affect long-term reliability of the device. cdm esd_hand_cdm charged device model contact discharge per jedec eia/jesd22-c101 175 v table 13. recommended operating conditions and dc characteristics element symbol value unit minimum typical maximum dc supply voltage for vbat vbat 2.3 ? 4.8 a a. the maximum continuous supply voltage is 4. 8v. brief spikes above this 4.8v can be to lerated. specifically, voltages as high as 5.5v for up to 10 seconds cumulative duration over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds cumulative dur ation over the lifetime of the device are allowed. v dc supply for wlan power amplifier vddpa 2.3 3.3 4.8 a v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf i/os vddio_rf 3.13 3.3 3.46 v wrf_vco_ldo_in_vdd1p8 ? 1.4 1.8 1.9 v wrf_tcxo_vdd3p3 (icc = 500 a max) b,c b. the maximum limits for tcxo_vdd3p3 noise are: 20 khz, 100 nv/sqrt(hz); 100 khz, 80 nv/sqrt(hz); 1 mhz, 50 nv/sqrt(hz); 2 mhz, 30 nv/sqrt (hz) c. conditions for icc = 500 a maximum are: ?30c, 3.3v, 52 mhz. ? 1.7 1.8 3.3 v input high voltage (wl_rst_n, ext_smps_req, ext_pwm_req) v ih 1.08 ? 3.6 v input low voltage (wl_rst_n, ext_smps_req, ext_pwm_req) v il ??0.4v input high voltage (vddio = 1.8v) d d. for non-sdio digital i/o only. v ih 1.1 ? vddio v input low voltage (vddio = 1.8v) c v il ? ? 0.7 v input high voltage (vddio = 2.5v) c v ih 1.7 ? vddio v input low voltage (vddio = 2.5v) c v il ? ? 0.8 v input high voltage (vddio = 3.3v) c v ih 2.0 ? vddio v input low voltage (vddio = 3.3v) c v il ? ? 0.8 v sdio input high voltage (vddio_sd = 1.8v) v ih 1.17 ? vddio_sd v sdio input low voltage (vddio_sd = 1.8v) v il ? ? 0.63 v sdio input high voltage (vddio_sd = 2.5v or 3.3v) v ih 2.0 ? vddio_sd v sdio input low voltage (vddio_sd = 2.5v or 3.3v) v il ? ? 0.8 v output low voltage e e. for sdio and non-sdio outputs. v ol ? ? 0.4 v output high voltage d v oh vddio ? 0.4v ? ? v input low current i il ? 0.3 ? a input high current i ih ? 0.3 ? a table 12. esd specifications pin type symbol condition esd rating unit
document no. 002-14779 rev. *h page 34 of 51 cyw43362 11. wlan rf specifications the cyw43362 includes an integrated direct conversion radio that supports the 2.4 ghz band. this section describes the rf char- acteristics of the 2.4 ghz radio. note: values in this document are design goals and may change based on device characterization results. unless otherwise stated, the specifications in this section apply when the operating c onditions are within the limits specified in table 11, ?environmental ratings,? on page 32 and table 13, ?recommended operating c onditions and dc characteristics,? on page 33 . functional operation outside these limits is not guaranteed. typical values apply for the following conditions: vbat = 3.6v ambient temperature +25c figure 16. rf port location note: all specifications are me asured at the rf port unless otherwise specified. 11.1 2.4 ghz band general rf specifications 11.2 wlan 2.4 ghz receiver performance specifications note: the specifications in ta b l e 1 5 are measured at the rf port. table 14. 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s table 15. wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz operating temperature ? ?30 25 85 c filter cyw43362 t/r ? rf ? switch (0.5 ? db ? insertion ? loss) antenna ? port rf ? port wlan ? tx wlan ? rx chip ? port
document no. 002-14779 rev. *h page 35 of 51 cyw43362 rx sensitivity (8% per for 1024 octet psdu) at wlan rf port a 1 mbps dsss ?95 ?97 ? dbm 2 mbps dsss ?92.5 ?94.5 ? dbm 5.5 mbps dsss ?90 ?92 ? dbm 11 mbps dsss ?87 ?89 ? dbm rx sensitivity (10% per for 1000 octet psdu) at wlan rf port a 6 mbps ofdm ?88 ?90 ? dbm 9 mbps ofdm ?88 ?90 ? dbm 12 mbps ofdm ?86 ?88 ? dbm 18 mbps ofdm ?84 ?86 ? dbm 24 mbps ofdm ?82 ?84 ? dbm 36 mbps ofdm ?79 ?81 ? dbm 48 mbps ofdm ?75 ?77 ? dbm 54 mbps ofdm ?73 ?75 ? dbm rx sensitivity (10% per for 4096 octet psdu) at wlan rf port a . defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates mcs7 ?70 ?72 ? dbm mcs6 ?72.5 ?74.5 ? dbm mcs5 ?74.5 ?76.5 ? dbm mcs4 ?78.5 ?80.5 ? dbm mcs3 ?82 ?84 ? dbm mcs2 ?84.5 ?86.5 ? dbm mcs1 ?86.5 ?88.5 ? dbm mcs0 ?88 ?90 ? dbm blocking level @ wlan rf port for 1db rx sensitivity degradation (without external filtering). b 698?716 mhz wcdma, lte ?28 ? ? dbm 776?787 mhz wcdma, lte ?28 ? ? dbm 824?849 mhz gsm850 ?19 c ??dbm 824?849 mhz wcdma, lte ?28 d ??dbm 880?915 mhz gsm900 ?19 ? ? dbm 880?915 mhz wcdma, lte ?28 ? ? dbm 1710?1785 mhz gsm1800 ?22 ? ? dbm 1710?1785 mhz wcdma, lte ?28 ? ? dbm 1850?1910 mhz gsm1900 ?22 ? ? dbm 1850?1910 mhz wcdma, lte ?28 ? ? dbm 1880?1920 mhz td?scdma ?33 ? ? dbm 1900?1920 mhz lte ?28 ? ? dbm 1910?1930 mhz lte ?28 ? ? dbm 1920?1980 mhz wcdma, lte ?28 ? ? dbm 1930?1990 mhz lte ?32 ? ? dbm 2010?2025 mhz td?scdma ?31 ? ? dbm 2500?2570 mhz wcdma, lte ?50 ? ? dbm 2570?2620 mhz lte ?50 ? ? dbm 3168?4752 mhz uwb ?28 ? ? dbm 3402?3620 mhz wimax ?23 ? ? dbm 6336?8976 mhz uwb ?21 ? ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6?54 mbps (10% per, 1000 octets) ?13 ? ? dbm table 15. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document no. 002-14779 rev. *h page 36 of 51 cyw43362 lpf 3-db bandwidth ? ? 9 ? 10 mhz adjacent channel rejection-dsss (difference between interfering and desired signal [25 mhz apart] at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection-ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1000 e octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db maximum receiver gain ? ? ? 90 ? db gain control step ? ? ? 3 ? db rcpi accuracy f range ?98 dbm to ?75 dbm ?3 ? 3 db range above ?75 dbm ?5 ? 5 db return loss zo = 50 across the dynamic range. 10 ? ? db a. derate by 1.5 db for ?30 c to ?10c and 55c to 85c. b. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that b and for the purpose of this test. it is not intended to indicate any specific usage of each band in any specific country. c. min value is ?23 db for chan 11. d. min value is ?36 dbm for chan 11. e. for 65 mbps, the size is 4096. f. the minimum and maximum values shown have a 95% confidence level. table 15. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document no. 002-14779 rev. *h page 37 of 51 cyw43362 11.3 wlan 2.4 ghz transmitter performance specifications note: the specifications in ta b l e 1 6 are measured at the rf port output. table 16. wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz transmitted power in cellular and fm bands at rf port (at 18.5 dbm, 90% duty cycle, 1 mbps cck). a 76?108 mhz fm rx ? ?161 ?159 dbm/hz 170?240 mhz dab ? ?161 ?159 dbm/hz 470?862 mhz dvb-h ? ?161 ?159 dbm/hz 728?746 mhz wcdma, lte ? ?161 ?159 dbm/hz 746?757 mhz wcdma, lte ? ?161 ?159 dbm/hz 869?894 mhz wcdma, lte ? ?161 ?159 dbm/hz 925?960 mhz gsm, wcdma, lte ? ?161 ?159 dbm/hz 1570?1580 mhz gps ? ?155 ?153 dbm/hz 1592?1610 mhz glonass ? ?155 ?153 dbm/hz 1805?1880 mhz gsm, wcdma, lte ? ?155 ?153 dbm/hz 1880?1920 mhz td-scdma ? ?134 ?132 dbm/hz 1850?1910 mhz wcdma, lte ? ?134 ?132 dbm/hz 1910?1930 mhz wcdma, lte ? ?134 ?132 dbm/hz 1900?1920 mhz wcdma, lte ? ?134 ?132 dbm/hz 1930?1990 mhz gsm, wcdma, lte ? ?134 ?132 dbm/hz 2010?2075 mhz td-scdma ? ?125.3 ?123.3 dbm/hz 2110?2170 mhz wcdma, lte ? ?125.3 ?123.3 dbm/hz harmonic level at rf port (at 18 dbm with 90% duty cycle, 1 mbps cck) 4.8?5.0 ghz 2nd harmonic ? ?19.5 ?12.8 dbm/ mhz 7.2?7.5 ghz 3rd harmonic ? ?37.7 ?26.7 dbm/ mhz tx power at rf port for highest power level setting at 25c, vbat = 3.6v and spectral mask and evm compliance b, c evm does not exceed ieee 802.11b (dsss/cck) ?9 db 18.5 ? ? dbm ofdm, bpsk ?8 db 18 ? ? dbm ofdm, qpsk ?13 db 18 ? ? dbm ofdm, 16-qam ?19 db 18 ? ? dbm ofdm, 64-qam (r = 3/4) ?25 db 15.5 ? ? dbm ofdm, 64-qam (r = 5/6) ?28 db 14.5 ? ? dbm tx power control dynamic range ? 9 ? ? db closed loop tx power variation at highest power level setting (at rf port) across full temperature and voltage range. applies across 5 to 21 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss zo = 50 4 6 ? db load pull variation for output power, evm, and adjacent channel power ratio (acpr) vswr = 2:1. evm degradation ? 3.5 ? db output power variation ? 2 ? db acpr-compliant power level ? 15 ? dbm vswr = 3:1. evm degradation ? 4 ? db output power variation ? 3 ? db acpr-compliant power level ? 15 ? dbm
document no. 002-14779 rev. *h page 38 of 51 cyw43362 11.4 general spurious emissions specifications a. the cellular standards listed indicate only typical usages of th at band in some countries. other standards may also be used w ithin those bands. b. derate by 1.5 db for temperatures less than ?10c or more th an 55c, or voltages less than 3.0v. derate by 3.0 db for voltages of less than 2.7v or voltages of less than 3.0v at temperatures less than ?10c or greater than 55c. c. tx power for ch 1 and ch 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance. table 17. general spurious emissions specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?44 ?41 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?68 ?65 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?54 ?51 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?88 ?85 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm note: the specifications in this table are at the rf port.
document no. 002-14779 rev. *h page 39 of 51 cyw43362 12. internal regulator electrical specifications note: values in this document are design goals and are subject to change based on the results of device characterization. functional operation is not guara nteed outside the specif ication limits provided in this section. 12.1 core buck regulator the specifications for the core buck regulator (cbuck) are provided in table 18 . table 18. core buck regulator specification notes minimum typical maximum units input supply voltage ? 2.3 ? 4.8 a volts pwm mode switching frequency ? 2.56 3.2 3.84 mhz pwm output current ? ? ? 500 ma output current limit ? ? 700 ? ma output voltage range programmable, 33.33 mv steps default = 1.8v 1.2 ? 1.833 volts output voltage dc accuracy includes load and line regulation. vbat = 2.7v to 4.8v, load 0 to 500 ma, inductor dcr < 137.5 m ? ?5 ? 5 % pwm ripple voltage, static b measure with 20 mhz bw limit. fixed load (0 to 500 ma). max ripple based on vbat < 4.3v, vout = 1.833v, fs = 3.2 mhz, 1.5 h inductor l > 0.6144 h, cap+board total-esr < 10 m ? , cout > 1.9 f ? 7 20 mvpp pwm load step transient voltage error vbat = 2.7v to 4.8v, current step = 150 to 400 ma, 1 sec rise-time based on 0402, 6.3v, x5r, and 4.7 f c ceramic capacitor. ? 100 200 mv pwm line step transient voltage error vbat step from 2.3 to 2.7v, 10 sec rise-time, fixed 500 ma load based on 0402, 6.3v, x5r, and 4.7 f b ceramic capacitor. ? 50 100 mv pwm load regulation a vbat = 2.7v to 4.8v, 10 ma to 500 ma load. inductor dcr < 137.5 m ? ? ? + 30 mv pwm line regulation a vbat = 2.7v to 4.8v, 500 ma load. inductor dcr < 137.5 m ? ? ? + 10 mv burst mode ripple voltage, static load < 30 ma. measure with 20 mhz bw limit. ? ? 80 mvpp 30 ma < load < 200 ma. measure with 20 mhz bw limit. ? ? 200 mvpp burst mode load step transient voltage error vbat = 2.7v to 4.8v, current step 10 to 200 ma, 1 sec rise-time based on 0402, 6.3v, x5r, and 4.7 f b ceramic capacitor. ? 60 120 mv burst mode line step transient voltage error vbat step from 2.3v to 2.7v, 10 sec rise-time, fixed 200 ma load based on 0402, 6.3v, x5r, and 4.7 f b ceramic capacitor. ? 50 100 mv burst mode load regulation vbat = 2.7v to 4.8v, 10 ma to 200 ma load ? 35 50 mv burst line regulation input voltage 2.7 to 4.8v, 200 ma load ? 44 70 mv peak pwm mode efficiency d 200 ma load current 30 ma load current 80 60 90 ? % % burst mode efficiency 5 ma load current 70 80 ? %
document no. 002-14779 rev. *h page 40 of 51 cyw43362 an efficiency plot for the cbuck regulator is shown in figure 17 . the plot shows typical performance for nominal process silicon, vout = 1.8v, vbat = 3.6v, and temperature = 25c. figure 17. cbuck efficiency start-up time from power down ? ? 1350 1500 s burst to pwm mode transient voltage error ensure load current < 200 ma during a mode change ? ? 160 mv external inductor see preferred inductor list ? 1.5 ? h external output capacitor ceramic, x5r, 0402, cap-esr < 4 m ? esl < 700 ph at 3.2 mhz, 20%, 6.3v ? 4.7 ? f external input capacitor for sr_vddbat1 pins, ceramic, x5r, 0603, cap-esr < 4 m ? at 3.2 mhz, 10%, 6.3v ? 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s a. the maximum continuous supply voltage is 4.8v. brief spikes above this 4.8v can be tolerated. specifically, voltages as high as 5.5v for up to 10 seconds cumulative duration over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds cumulative dur ation over the lifetime of the device are allowed. b. these are not load or line step transient tests. c. more capacitance can be used to reduc e the transient error at the output. d. vbat < 4.3v. inductor dcr < 137.5 m ? , acr < 1 ? . table 18. core buck regulator (cont.) specification notes minimum typical maximum units 0 10 20 30 40 50 60 70 80 90 100 0 0 0 1 0 0 1 0 1 1 1 . 0 load in ma power efficiency in % pwm mode burst mode
document no. 002-14779 rev. *h page 41 of 51 cyw43362 12.2 3.3v ldo (ldo3p3) 12.3 cldo table 19. 3.3v ldo (ldo3p3) specification notes minimum typical maximum units input supply voltage ? 2.3 3.6 4.8 a a. the maximum continuous supply voltage is 4.8v. brief spikes above this 4.8v can be tolerated. specifically, voltages as high as 5.5v for up to 10 seconds cumulative duration over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds cumulative dur ation over the lifetime of the device are allowed. volts output current ? ? ? 40 ma output voltage, vo step size 100 mv. default = 3.3v. 2.4 3.3 3.4 volts dropout voltage at max load ? ? 200 mv output voltage dc accuracy include line/load regulation. ?5 ? +5 % quiescent current no load ? 8 17 a line regulation vin from (vo + 0.2v) to 4.8v, maximum load ?0.2 ? +0.2 %vo/v load regulation load from 1 ma to 40 ma ? 0.02 0.05 %vo/ma leakage current power-down mode ? ? 5 a psrr vbat ?? 3.6v, vo = 2.5v, co = 1 f, max load, 100 hz to 1 mhz 20 ? ? db start-up time from the rising edge of vio as the chip powers up from a full power down (that is, band gap off) ? 1200 1400 s ldo turn-on time ldo turn-on time when rest of chip is up ? ? 100 s in-rush current during turn-on from its output capacitor in fully discharged state ? ? 135 ma external output capacitor, co ceramic, x5r, 0402, (esr: 30 m ? ?200 m ? ), 10%, 10v ? 1 ? f external input capacitor for sr_vddbat2 pin (shared with band gap) ceramic, x5r, 0603, (esr: 30 m ? ?200 m ? ), 10%, 10v ? 1 ? f table 20. cldo specification notes minimum typical maximum units input supply voltage, vin min = 1.25 + 0.2v = 1.45v. dropout voltage requirement must be met under max load. 1.45 1.5 2.0 volts output current ? ? ? 150 ma output voltage, vo programmable in 25 mv steps 1.075 1.2 1.325 volts dropout voltage at max load ? ? 200 mv output voltage dc accuracy include line/load regulation vin > vo + 0.2v ?4 ? +4 % quiescent current no-load ? 10 15 a line regulation vin from (vo + 0.2v) to 2v, max load ?0.2 ? +0.2 %vo/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 %vo/ma leakage current power-down ? ? 10 a
document no. 002-14779 rev. *h page 42 of 51 cyw43362 12.4 lnldo1 note: recommended inductor for cbuck: 1.5 h 20%. murata? lqm21pn1r5mc0 2.0 1.25 0.55 mm dcr = 0.26 ? 25%. murata lqm2mpn1r5ng0 2.0 1.60 1.00 mm dcr = 0.11 ? 25%. psrr @1 khz, vin ?? 1.5v, co = 1?2.2 f 20 40 ? db start-up time from full-chip power down a ? 1250 1400 s ldo turn-on time ldo turn-on time when rest of chip is up ? ? 180 s in-rush current during turn-on from its output capacitor in fully discharged state ? ? 150 ma external output capacitor, co (nominal values) ceramic, x5r, 0402, (esr: 30 m ? ?200 m ? ), 10%, 10v ? 2.2 ? f external input capacitor (nominal values) only use an external input cap at vdd_ldo pin if it is not supplied from cbuck output. ceramic, x5r, 0402, (esr: 30 m ? ? 200 m ? ), 10%, 10v ? 1 2.2 f a. with cbuck soft-starting concurrently. table 21. lnldo1 specification notes minimum typical maximum units input supply voltage, vin min = 1.25 + 0.2v = 1.45v dropout voltage requirement must be met under max load. 1.45 1.5 2.0 volts output current ? ? ? 150 ma output voltage, vo programmable in 25 mv steps 1.075 1.2 1.325 volts dropout voltage at max load ? ? 200 mv output voltage dc accuracy include line/load regulation vin > vo+0.2v ?4 ? +4 % quiescent current no-load ? 31 44 a line regulation vin from (vo+0.2v) to 2v, max load ?0.2 ? +0.2 %vo/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 %vo/ma leakage current power-down ? ? 10 a output noise @30 khz, 60 ma load co = 2.2 f @100 khz, 60 ma load co = 2.2 f ? ? 60 30 nv/rt hz nv/rt hz psrr @1 khz, vin ?? 1.5v, co = 2.2 f 20 50 ? db ldo turn-on time ldo turn-on time when rest of chip is up ? ? 180 s in-rush current during turn-on from its output capacitor in fully discharged state ? ? 150 ma external output capacitor, co (nominal values) ceramic, x5r, 0402, (esr: 30 m ? ?200 m ? ), 10%, 10v ? 2.2 ? f table 20. cldo specification notes minimum typical maximum units
document no. 002-14779 rev. *h page 43 of 51 cyw43362 13. system power consumption note: table 22 shows typical values. power consumption referenced to vbat @ 3. 6v, 20c, vddio = 1.8v, cbuck out = 1.5v. table 22. system power consumption wlan operational modes total (ivbat) off 1 11 a off 2 40 a idle 185 a sleep 5 200 a rx (listen) 3 52 ma rx (active) 4 59 ma power save 6, 9 1.9 ma tx cck (11 mbps at 18.5 dbm) 7, 11 320 ma tx ofdm (54 mbps at 15.5 dbm) 8, 11 270 ma tx ofdm (65 mbps at 14.5 dbm) 10, 11 260 ma note 1: wl_rst_n = low, vddio is not present note 2: wl_rst_n = low, vddio is present note 3: carrier sense (cca) when no carrier present note 4: carrier sense (cs) detect/packet rx note 5: intra-beacon sleep note 6: beacon interval = 102.4 ms, dtim = 1, beacon duration = 1 ms @1 mbps. integrated sleep + wakeup + beacon rx current over 1 dtim interval. note 7: cck power at chip port. duty cycle is 100%. includes pa contribution at 3.6v. note 8: ofdm power at chip port. duty cycle is 100%. includes pa contribution at 3.6v. note 9: in wlan power-saving mode, the following blocks are powered down: crystal oscillator, bas eband pll, afe, rf pll, radio note 10: ofdm power at chip port is 16 dbm, duty cycle is 100%, includes pa contribution at 3.6v. the above blocks are turned on in the required order with sufficie nt time for them to settle. this sequencing is done by the pm u controller that controls the settling time for each of the blocks. it also has information to determine the order in which the blocks should be turned o n. the settling times and the dependency order are programmable in the pmu controller. the default clk settling time is set to 8 ms at power-up. it can be reduced after power-up. note 11: absolute junction temperature limits maintained throug h active thermal monitoring and dynamic tx duty cycle limiting.
document no. 002-14779 rev. *h page 44 of 51 cyw43362 14. interface timing and ac characteristics note: values in this document are design goals and are subject to change based on the results of device characterization. unless otherwise stated, the specifications in this section apply when the operating c onditions are within the limits specified in table 11 on page 32 and table 13 on page 33 . functional operation outside of these limits is not guaranteed. 14.1 sdio default mode timing sdio default mode timing is shown by the combination of figure 18 and table 23 on page 44 . figure 18. sdio bus timing (default mode) table 23. sdio bus timing a parameters (default mode) parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) frequency?data transfer mode fpp 0 ? 25 mhz frequency?identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock fall time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu 5 ? ? ns input hold time tih 5 ? ? ns outputs: cmd, dat (referenced to clk) output delay time?data transfer mode todly 0 ? 14 ns t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
document no. 002-14779 rev. *h page 45 of 51 cyw43362 14.2 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 19 and table 24 . figure 19. sdio bus timing (high-speed mode) t output delay time?identification mode todly 0 ? 50 ns a. timing is based on cl ? 40 pf load on cmd and data. b. min(vih) = 0.7 vddio and max(vil) = 0.2 vddio. table 24. sdio bus timing a parameters (h igh-speed mode) a. timing is based on cl ? 40pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min(vih) = 0.7 vddio and max(vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 7 ? ? ns clock high time twh 7 ? ? ns clock rise time ttlh ? ? 3 ns clock fall time tthl ? ? 3 ns inputs: cmd, dat (referenced to clk) input setup time tisu 6 ? ? ns input hold time tih 2 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf table 23. sdio bus timing a parameters (default mode) parameter symbol minimum typical maximum unit t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% vdd t oh sdio_clk
document no. 002-14779 rev. *h page 46 of 51 cyw43362 14.3 jtag timing table 25. jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ?
document no. 002-14779 rev. *h page 47 of 51 cyw43362 15. package information 15.1 package thermal characteristics 15.1.1 junction temperature estimation and psi versus theta jc package thermal characterization parameter psi-jt ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta-j c ( ? jc ). the reason for this is ? jc assumes that all the power is dissipated through the top surface of the package case . in actual applications, some of the powe r is dissipated through the bottom and sid es of the package. ? jt takes into account power dissipated through the top, bo ttom, and sides of the package. the equation for calculat- ing the device junction tem perature is as follows: t j = t t + p ?? jt where: t j = junction temperature at steady-state condition, c t t = package case top center temperat ure at steady-state condition, c p = device power dissipation, watts ? jt = package thermal characteristics (no airflow), c/w table 26. package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate based on a 4-la yer pcb that conforms to eia/jesd51?7 (101.6 mm x 114.3 mm x 1.6 mm) and p = 1.2w continuous dissipation. characteristic value in still air ? ja (c/w) 44.88 ? jb (c/w) 1.20 ? jc (c/w) 0.20 ? jt (c/w) 0.04 ? jb (c/w) 14.21 maximum junction temperature t j (c) b b. absolute junction temperature limits maintained through acti ve thermal monitoring and dynamic tx duty cycle limiting. 125 maximum power dissipation (w) 1.2
document no. 002-14779 rev. *h page 48 of 51 cyw43362 16. mechanical information figure 20. 69-ball wlbga mechanical information
document no. 002-14779 rev. *h page 49 of 51 cyw43362 17. ordering information 18. references the references in this section may be used in conjunction with this document. part number package description operating ambient temperature BCM43362kubg 69-ball wlbga halogen-free package (4.52 mm x 2.92 mm, 0.40 pitch) single-band ieee 802.11b/g/n 2.4 ghz wlan ?30c to +85c note: add a ?t? to the end of the part number to specify ?tape and reel?. document (or item) name number source cypress items cyw43362 reference board schematics ? cypress representative
document no. 002-14779 rev. *h page 50 of 51 cyw43362 document history page document title: cyw43362 single-chi p ieee 802.11? b/g/n mac/baseband/radio document number: 002-14779 revision ecn orig. of change submission date description of change ** ? ? 07/15/2010 43362-ds100-r initial release *a ? ? 02/17/2011 43362-ds101-r updated: ? lpo clock to lpo sleep clock throughout the document. ? figure3: ?power topology,? onpage 15. ? ?tcxo? on page20. ? table2:?crystal oscil- lator and external clock requirements and performance,? on page21. ? ?external 32.768 khz low-power oscillator? on page22. ? table3:?external 32.768 khz low-power oscillator specifications,? on page22. ? table8:?wlbga signal descripti ons,? on page49. ? table9:?BCM43362 during reset and after reset or during sleep,? on page55. ? table12:?environmental ratings,? on page 59. ? table13:?esd specifications,? on page59. ? table14:?recommended operating conditions and dc charac- teristics,? on page60. ? table16:?wlan 2.4 ghz receiver performance speci- fications,? on page62. ? table17:?wlan 2.4 ghz transmitter performance specifications,? on page65. ? table18: ?general spurious emissions specifi- cations,? on page67. ? table19:?core buck regulator,? on page68. ? table20:?3.3v ldo (ldo3p3),? on p age71. ? table21:?cldo,? on page72. ? table22:?lnldo1,? on page73. *b ? ? 03/28/2011 43362-ds102-r updated: ? table11:?absolute maximum ratings,? on page62. ? table14:?recommended operating conditions and dc characteristics,? on page64. ? table19:?core buck regulator ,? on page73. ? table20:?3.3v ldo (ldo3p3),? on page76. *c ? ? 09/01/2011 43362-ds103-r updated: ? changed maximum battery voltage range from 5.5v to 4.8v. ? ?low-power shutdown? on page20. ? t able8:?wlbga signal descriptions,? on page53. ? table13:?esd specificatio ns,? on page63. ? table16:?wlan 2.4 ghz receiver performance specificat ions,? on page67. ? table17:?wlan 2.4 ghz transmitter performance specificat ions,? on page70. ? table18:?general spurious emissions specifications,? on page72. ? table19:?core buck regulator,? on page73. ? table20:?3.3v ldo (ldo3p3),? on page76. ? table23:?system power consumption,? on page79. *d ? ? 02/17/2012 43362-ds104-r updated: ? table23:?system power consumption,? on page79 deleted: ? support for short gi mode in tx and rx *e ? ? 04/07/2014 43362-ds105-r updated: ? ieee 802.15.2 su pport for zigbee and bt smart on page 1. ? coexistence interfaces for zigbee and bt smart on page 11. deleted: ? ccxv(2, 3, 4, 5) proprietary protocols on page 11. *f ? ? 02/13/2015 43362-ds106-r updated: ? removed ?preliminary? from the document type. *g 5444083 utsv 09/30/2016 migrated to cypress template format added cypress part numbering scheme *h 5675324 utsv 03/30/2017 upd ated with cypress new logo spi/gspi related sections are removed from this document.
document no. 002-14779 rev. *h revised march 30, 2017 page 51 of 51 ? cypress semiconductor corporation, 2010-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desig n, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. cyw43362 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forum | projects | video | blogs | training components technical support cypress.com/support 51

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