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mb39c502/50 3/504 high efficiency step down dc/dc controller datasheet cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 08449 rev * a revised february 12, 2016 description mb39c502 is a single output step down dc/dc controller using external fets. it achieves the high efficiency with enhanced low power mode (lpm) operation in light load. in enhanced lpm, this controller operates that the quiescent current is re duced only 30a and the switching frequency is fallen by extending on time. these operations enable to improve the efficiency in light load. internal compensation circuit with current mode architecture and internal boost switch allow reducing the bom parts and the component area. features ? high efficiency with enhanced lpm operation ? automatic transition for pfm/pwm ? enhanced lpm operation transferred by slp_n assertion ? over current alerting ? reference voltage accuracy: 1% ? output voltage range : 0.7v to 2.0v ( mb39c502) : 2.4v to 3.5v (mb39c503) : fixed 5v (mb39c504) ? vin input voltage range : 4.0v to 25v (mb39c502/c503) : 5.4v to 25v (mb39c504) ? vdd input voltage range: 4.5v to 5.5v (mb39c502/c503) ? internal 5v ldo with switchover (mb39c504) ? fixed freq uency emulated on - time control: 800khz ? current mode architecture with internal compensation circuit ? internal boost switch ? fixed 700s soft start time without load dependence ? internal discharge fet ? power good monitor ? enhanced protection functions: ovp, uvp, ilim ? thermal shutdown ? small 3mm 3mm 0.75mm qfn16 package applications ? point of load vr for note pc ? general purpose step down regulator
document number: 002 - 08449 rev * a page 2 of 46 mb39c502/503/504 contents 1. typical application ................................ ................................ ................................ ................................ 3 2. pin configuration ................................ ................................ ................................ ................................ ... 4 3. pin configuration ................................ ................................ ................................ ................................ ... 6 4. block diagram ................................ ................................ ................................ ................................ ........ 8 5. absolute maximum rating ................................ ................................ ................................ .................. 10 6. recommended operating conditions ................................ ................................ ................................ . 11 7. electrica l characteristics ................................ ................................ ................................ .................... 13 8. protections and power good function ................................ ................................ ............................... 22 8.1 description ................................ ................................ ................................ ................................ ......... 22 8.2 timing chart ................................ ................................ ................................ ................................ ...... 23 9. enhanced lpm description ................................ ................................ ................................ ................ 27 9.1 ultra low quiescent current ................................ ................................ ................................ .............. 28 9.2 extended on time ................................ ................................ ................................ ............................. 28 9.3 timing chart of enhanced lpm ................................ ................................ ................................ ......... 29 10. over current alerting de scription ................................ ................................ ................................ .. 30 11. application note ................................ ................................ ................................ .............................. 31 11.1 setting operating conditions ................................ ................................ ................................ ............. 31 11.1.1 setting output voltage ................................ ................................ ................................ ................... 31 11.1.2 setting over current limitation and over current alerting ................................ ............................ 31 11.2 selection pa rts ................................ ................................ ................................ ................................ ... 32 11.2.1 selection of smoothing inductor ................................ ................................ ................................ .... 32 11.2.2 selection of switching fet ................................ ................................ ................................ ............ 33 11.2.3 selection of fly back diode ................................ ................................ ................................ ........... 35 11.2.4 selection of boost diode ................................ ................................ ................................ ................ 35 11.2.5 selection of input capacit or ................................ ................................ ................................ ........... 36 11.2.6 selection of output capacitor ................................ ................................ ................................ ........ 37 11.2.7 selection of boost capacitor ................................ ................................ ................................ .......... 38 11.2.8 selection of vdd capacitor ................................ ................................ ................................ ........... 39 11.2.9 selection of vcc capacitor and resistor ................................ ................................ ...................... 39 11.3 layout ................................ ................................ ................................ ................................ ................ 40 12. ordering information ................................ ................................ ................................ ....................... 43 13. package dimensions ................................ ................................ ................................ ....................... 44 14. major chang es ................................ ................................ ................................ ................................ . 45
document number: 002 - 08449 rev * a page 3 of 46 mb39c502/503/504 1. typical application (mb39c502/c503) d r v h l x d r v l p g n d c s n c s p v d d v i n 4 . 0 v ~ 2 5 v v o u t v 5 b s t v c c p o w e r g o o d s l p # s l p _ n l o a d v i n a g n d v o u t s e n s e f b v o u t s e n s e c i n m h m l l r s c o u t e n e n p w r g d i l i m o c a l e r t a l e r t _ n c i n d v c c
document number: 002 - 08449 rev * a page 4 of 46 mb39c502/503/504 (mb39c504) 2. pin configuration (mb39c502/c503) e p : a g n d p w r g d ( t o p v i e w ) c s n v c c 1 3 1 4 1 5 1 6 1 2 3 4 1 2 1 1 1 0 9 8 7 6 5 d r v h v i n l x p g n d e n f b c s p s l p _ n b s t i l i m d r v l a l e r t _ n v d d 3 . 0 m m 3 . 0 m m d r v h l d o 5 v i n 5 . 4 v ~ 2 5 v v c c s l p # s l p _ n v i n a g n d v o u t s e n s e v o u t s c i n m h e n e n p w r g d v o u t v o u t l x d r v l p g n d c s n c s p v o u t b s t l o a d v o u t s e n s e m l l p o w e r g o o d i l i m c i n d v c c r s c o u t
document number: 002 - 08449 rev * a page 5 of 46 mb39c502/503/504 (mb39c504) e p : a g n d p w r g d ( t o p v i e w ) c s n v c c 1 3 1 4 1 5 1 6 1 2 3 4 1 2 1 1 1 0 9 8 7 6 5 d r v h v i n l x p g n d e n v o u t s c s p s l p _ n b s t v o u t d r v l i l i m l d o 5 3 . 0 m m 3 . 0 m m
document number: 002 - 08449 rev * a page 6 of 46 mb39c502/503/504 3. p in configuration (mb39c502/c503) pin number pin name i/o description 1 ilim(*1) i connect to vcc terminal. 2 alert_n o open drain output terminal with over current alerting. 3 vdd i power supply voltage input terminal of switching fet gate driver. 4 dr vl o low side switching fet gate driver output terminal. 5 pgnd - power ground. 6 lx - inductor and high side switching fet source connection terminal. 7 vin i power supply of switching regulator input terminal. 8 drvh o high side switching fet gate dr iver output terminal. 9 bst i boost capacitor connection terminal. 10 en i enable input of pwm controller. when turning on, apply greater than 0.65v and less than 5.5v. when turning off, apply less than 0.25v. 11 csp i current sensing positive input ter minal. 12 csn i current sensing negative input terminal. 13 fb i feedback voltage input of switching regulator. 14 slp_n i low power mode signal input terminal. transferred to low power mode by connecting to l level 15 pwrgd o open drain output term inal with power good. 16 vcc i power supply voltage input terminal of pwm controller. ep agnd - analog ground. *1: ilim terminal should be fixed to connect to vcc terminal.
document number: 002 - 08449 rev * a page 7 of 46 mb39c502/503/504 (mb39c504) pin number pin name i/o description 1 ilim(*1) i connect to vcc te rminal whenever. 2 vout i dcdc output voltage input for switchover. 3 ldo5 o 5v ldo output terminal. 4 drvl o low side switching fet gate driver output terminal. 5 pgnd - power ground. 6 lx - inductor and high side switching fet source connection term inal. 7 vin i power supply of switching regulator input terminal. 8 drvh o high side switching fet gate driver output terminal. 9 bst i boost capacitor connection terminal. 10 en i enable input of pwm controller. when turning on, apply greater than 2.5 v and less than 25v. when turning off, apply less than 0.6v. 11 csp i current sensing positive input terminal. 12 csn i current sensing negative input terminal. 13 vouts i dcdc output voltage input terminal. 14 slp_n i low power mode signal input termi nal. transferred to low power mode by connecting to l level 15 pwrgd o open drain output terminal with power good. 16 vcc i power supply voltage input terminal of pwm controller. ep agnd - analog ground. *1: ilim terminal should be fixed to connect to vcc terminal.
document number: 002 - 08449 rev * a page 8 of 46 mb39c502/503/504 4. block diagram (mb39c502/c503) u v c m p e r r o r a m p o v c m p t o n t i m e r t o n f b b u f f e r v t h c o n t r o l 1 . 1 5 x r e f 0 . 7 0 x r e f c u r r e n t s e n s e a m p a g n d e n p w r g d c m p 0 . 9 2 x r e f p w r g d l o g i c ( o p e n d r a i n ) u v p l o g i c o v p l o g i c o v p u v p d r i v e l o g i c a s t p w m p w r g d d r v h d r v l l x b s t p g n d b s t s w c o n t r o l r s q x q c s p c s n o v p u v p h i g h s i d e d r i v e r l o w s i d e d r i v e r u v l o s l p l o g i c e n b g r v r e f e n # e n b s t u v l o z c b s t u v u v l o v c c s l p _ n d h d l i b i a s c o n t r o l e n _ s l p d s b _ s l p i b i a s p g n d l x u v l o r e f r e f v c c v b i a s d i s c h g l o g i c i l i m f b r e f s s r e f v i n e n # c u r r e n t c m p c s n v d d v d d o c a l e r t ( o p e n d r a i n ) i l i m a l e r t c m p a l t a l t a l e r t _ n v i n v i n
document number: 002 - 08449 rev * a page 9 of 46 mb39c502/503/504 (mb39c504) u v c m p e r r o r a m p o v c m p t o n t i m e r t o n f b b u f f e r v t h c o n t r o l 1 . 1 5 x r e f 0 . 7 0 x r e f c u r r e n t s e n s e a m p a g n d e n p w r g d c m p 0 . 9 2 x r e f p w r g d l o g i c ( o p e n d r a i n ) u v p l o g i c o v p l o g i c o v p u v p d r i v e l o g i c a s t p w m p w r g d l x b s t p g n d b s t s w c o n t r o l r s q x q c s p c s n o v p u v p h i g h s i d e d r i v e r l o w s i d e d r i v e r u v l o e n b g r v r e f e n # e n b s t u v l o z c b s t u v u v l o v c c d h d l p g n d 1 l x u v l o r e f r e f v c c v b i a s d i s c h g l o g i c i l i m v o u t s r e f s s r e f v i n e n # l d o 5 v d d l d o 5 s w i t c h o v e r v i n v o u t d r v h d r v l i l i m c u r r e n t c m p s l p l o g i c i b i a s c o n t r o l e n _ s l p d s b _ s l p i b i a s s l p _ n v i n v i n
document number: 002 - 08449 rev * a page 10 of 46 mb39c502/503/504 5. absolute maximum rating (mb39c502/c503/c504) parameter symbol condition rating unit min max power supply voltage v vin vin inp ut voltage C 0.3 +28 v v vcc vcc input voltage C 0.3 +6.5 v v vdd vdd input voltage (mb39c502/c503) C 0.3 +6.5 v v vout vout input voltage (mb39c504) C 0.3 +6.5 v terminal voltage v bst bst bias voltage C 0.3 +34.5 v v lx lx switching voltage C 2 +28 v v fb fb input voltage (mb39c502/c503) C 0.3 v vcc +0.3 v v vouts vouts input voltage C 0.3 +6.5 v v input ilim input voltage C 0.3 v vcc +0.3 v v cs csp, csn input voltage C 0.3 +6.5 v v en en input voltage (mb39c502/c503) C 0.3 +6.5 v en input voltage (mb39c5 04) C 0.3 +28 v v slp slp_n input voltage C 0.3 +6.5 v v nod pwrgd, alert_n bias voltage C 0.3 +6.5 v difference voltage v bst - lx bst C lx difference voltage C 0.3 +6.5 v v bst - vdd bst C vdd difference voltage (mb39c502/c503) - +28 v v bst - ldo5 bst C vout, ldo5 difference voltage (mb39c504) - +28 v v gnd agnd C pgnd difference voltage C 0.3 +0.3 v v csp - csn csp C csn difference voltage C 0.3 +0.3 v output current i drv drvh, drvl dc current C 60 +60 ma i nod pwrgd - +2 ma i alert alert_n sink current (mb39c502/c503) - +2 ma power dissipation p d ta 25c - 2100(*1) mw storage temperature t stg - C 55 +125 c *1: when the ic is mounted on 10cm 10cm four - layer square epoxy board. ic is mounted on a four - layer epoxy board, which terminal bias, and the ics thermal p ad is connected to the epoxy board. warning ? semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings.
document number: 002 - 08449 rev * a page 11 of 46 mb39c502/503/504 6. recommended operating conditi ons (mb39c502/c503/c504) parameter symbol condition value unit min typ max power supply voltage v vin vin input voltage (mb39c502/c503) 4.0 - 25 v v vin vin input voltage (mb39c504) 5.4 - 25 v v vcc vcc input voltage 4.5 - 5.5 v v vdd vdd input vol tage (mb39c502) 4.5(*1) - 5.5 v v vdd vdd input voltage (mb39c503) 4.5 - 5.5 v v ldo5 vout input voltage (mb39c504) 4.5 - 5.5 v terminal voltage v bst bst bias voltage 0 - 30.5 v v lx lx switching voltage C 1 - 25 v v input fb, ilim input voltage (mb39c 502/c503) 0 - v vcc v v input ilim input voltage (mb39c504) 0 - v vcc v v cs csp, csn input voltage (mb39c502) 0 - 2.0 v v cs csp, csn input voltage (mb39c503) 0 - 3.5 v v cs csp, csn, vouts input voltage (mb39c504) 0 - 5.5 v v en en, slp_n input voltag e (mb39c502/c503) 0 - 5.5 v v en en input voltage (mb39c504) 0 - 25 v v slp slp_n input voltage (mb39c504) 0 - 5.5 v v nod pwrgd, alert_n bias voltage (mb39c502/c503) 0 - 5.5 v v nod pwrgd bias voltage (mb39c504) 0 - 5.5 v difference voltage v bst - lx b st C lx difference voltage 0 - 5.5 v v bst - vdd bst C vdd difference voltage (mb39c502/c503) - - 25 v v bst - ldo5 bst C vout, ldo5 difference voltage (mb39c504) - - 25 v v gnd agnd C pgnd difference voltage C 0.05 - 0.05 v v csp - csn csp C csn difference voltage 0 - 35 mv output current i drv drvh, drvl dc current C 45 - 45 ma i nod pwrgd, alert_n sink current - - 1 ma bst capacitor c bst connect bst to lx capacitor - 0.47 - f vcc capacitor c vcc connect vcc to agnd capacitor - 1.0 - f vdd capacitor c vdd connect v dd to pgnd capacitor (mb39c502/c503) - 4.7 - f ldo5 capacitor c ldo5 connect ldo5 to pgnd capacitor(mb39c504) - 4.7 - f operating ambient temperature t a ambient temperature C 30 - 85 c *1: this vdd minimum input voltage indicates dynamic input range be low 1ms. refer to figure (next page) about the static vdd minimum input voltage.
document number: 002 - 08449 rev * a page 12 of 46 mb39c502/503/504 warning ? the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteri stics are warranted when the device is operated within these ranges. ? always use semiconductor devices within their recommended operating condition ranges. ? operation outside these ranges may adversely affect reliability and could result in device failure. ? n o warranty is made with respect to use, conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 vdd static input voltage / v ambient temprature / degc vdd static input voltage vs. ambient temprature (bat54xv2t1g boost diode connected)
document number: 002 - 08449 rev * a page 13 of 46 mb39c502/503/504 7. electrical characteristics (mb39c5 02) vin = 7.4v, vdd, bst and en connect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. parameter symbol condition value unit min typ max reference voltage internal reference voltage v ref this voltage is compared to f eedback voltage. ta = 25c 0.693 0.700 0.707 v ta = C 10c to 85c 0.686 - 0.714 v fb input current i fb vfb = 1.0v C 0.1 - 0.1 a enable, slp_n enable condition v en enable voltage range 0.65 - 5.5 v v dsb disable voltage range 0 - 0.25 v en input cur rent i en v en = 5.0v - 0 0.1 a slp_n enable condition v slpdsb lpm disable voltage range 0.65 - 5.5 v v slpen lpm enable voltage range 0 - 0.35 v slp_n input current i slp_n v slp_n = 5.0v - 0 0.1 a supply current vdd supply current i vddpwm vdd, vcc inp ut current at pwm operating. t a = 25c - 380 760 a i vddpfm vdd, vcc input current at idle state in pfm operation. static 0a inductor current. t a = 25c - 180 360 a i vddlpm vdd, vcc input current at idle state in lpm operation. static 0a inductor curr ent. t a = 25c - 30 60 a vdd shutdown current i vddsdn vdd, vcc input current at v en = 0v - 0.1 1.0 a vin supply current i vin v vin = 25v - 10 15 a vin shutdown current i vinsdn vin input current at v en = 0v - 0.1 1.0 a under voltage lockout vcc uvlo threshold v uvlo uvlo release voltage 3.99 4.14 4.29 v v hys hysteresis 0.005 0.070 0.200 v soft start, discharge period of power on reset t por from enable on to the switching initiating. 200 - 1000 s ramp up time t ss from the switching initiating aft er enable on to the output voltage reaches 95%. 598 665 732 s discharge resistance r dischg vout = 0.2v, discharge enable. 50 100 200 discharge ends voltage v dischg v csn voltage. 0.07 0.10 0.13 v
document number: 002 - 08449 rev * a page 14 of 46 mb39c502/503/504 vin = 7.4v, vdd, bst and en connect to 5v power suppl y, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c502) parameter symbol condition value unit min typ max on timer on time t on v vin = 7.4v, v csn = 1.2v 193 210 227 ns minimum on time t minon v vin = 7.4v, v csn = 0.2v 80 120 - ns mi nimum off time t minoff - 200 400 ns currentlimitation current limitation threshold v ilimit csp C csn difference voltage at ilim connects to vcc. 19.0 24.0 29.0 mv ilim input current i ilim v ilim = 5.0v - 0 0.1 a csp, csn input current i cs v cs = 1.2v C 5.0 C 2.0 - a over and under voltage protection over voltage threshold ratio rt ov for target output voltage. at output voltage increasing. 110 115 125 % propagation delay of ov t ov - 4 10 25 s under voltage t hreshold ratio rt uv for target output voltage. at output voltage decreasing. 65 70 75 % propagation delay of uv t uv - 40 100 200 s power good monitor power good threshold ratio rt pg for target output voltage. at output voltage increasing. 86 92 98 % h ysteresis ratio rt hys - 3 5 7 % propagation delay t pg power good 20 50 200 s t pb power bad 4 10 25 s pwrgd leak current i lkpg v pwrgd = 5.5v - 0 1 a pwrgd output voltage l level v olpg i pwrgd = 1ma sink - 0.05 0.10 v thermal shut down shut down t emperature t tsdh shut down temperature. - 150(*1) - c t tsdl exited temperature from thermal shut down state. - 125(*1) - c over current alerting over current alerting threshold ratio rt alt for target current limitation. at output current increasing. 78 85 92 % propagation delay t alton on alerting assertion 20 50 200 s t altoff on alerting de - assertion 3 10 25 s alert_n leak current i lkalt v alert_n = 5.5v - 0 1 a alert_n output voltage l level v olalt i alert_n = 1ma sink - 0.05 0.10 v *1: no production tested, ensure by design.
document number: 002 - 08449 rev * a page 15 of 46 mb39c502/503/504 vin = 7.4v, vdd, bst and en conn ect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c502) parameter symbol condition value unit min typ max driver high side on resistance r hoh at 100ma current sourcing - 3(*1) - r hol at 100ma current sinkin g - 1(*1) - low side on resistance r loh at 100ma current sourcing - 4(*1) - r lol at 100ma current sinking - 0.75(*1) - high side source current i srch v drvh = 2.5v - 0.7(*1) - a high side sink current i sinkh v drvh = 2.5v - 1.1(*1) - a low side s ource current i srcl v drvl = 2.5v - 0.5(*1) - a low side sink current i sinkl v drvl = 2.5v - 1.7(*1) - a dead time t dead from drvh turn off to drvl turn on. and reverse it. 10 20 - ns boost switch boost switch on resistance r bst i bst = 10ma - 30 50 bs t leak current i lkbst v bst = 30v - 0.1 1.0 a *1: no production tested, ensure by design.
document number: 002 - 08449 rev * a page 16 of 46 mb39c502/503/504 vin = 7.4v, vdd, bst and en connect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c503) parameter symbol condition value unit min typ max reference voltage internal reference voltage v ref this voltage is compared to feedback voltage. ta = 25c 0.99 1.00 1.01 v ta = C 10c to 85c 0.98 - 1.02 v fb input current i fb vfb = 1.0v C 0.1 - 0.1 a enable, slp_n enable conditi on v en enable voltage range 0.65 - 5.5 v v dsb disable voltage range 0 - 0.25 v en input current i en v en = 5.0v - 0 0.1 a slp_n enable condition v slpdsb lpm disable voltage range 0.65 - 5.5 v v slpen lpm enable voltage range 0 - 0.35 v slp_n input cu rrent i slp_n v slp_n = 5.0v - 0 0.1 a supply current vdd supply current i vddpwm vdd, vcc input current at pwm operating. t a = 25c - 380 760 a i vddpfm vdd, vcc input current at idle state in pfm operation. static 0a inductor current. t a = 25c - 180 3 60 a i vddlpm vdd, vcc input current at idle state in lpm operation. static 0a inductor current. t a = 25c - 30 60 a vdd shutdown current i vddsdn vdd, vcc input current at v en = 0v - 0.1 1.0 a vin supply current i vin v vin = 25v - 10 15 a vin shutdo wn current i vinsdn vin input current at v en = 0v - 0.1 1.0 a under voltage lockout vcc uvlo threshold v uvlo uvlo release voltage 3.99 4.14 4.29 v v hys hysteresis 0.005 0.070 0.200 v soft start, discharge period of power on reset t por from enable on to the switching initiating. 200 - 1000 s ramp up time t ss from the switching initiating after enable on to the output voltage reaches 95%. 598 665 732 s discharge resistance r dischg vout = 0.2v, discharge enable. 50 100 200 discharge ends voltage v dischg v csn voltage. 0.07 0.10 0.13 v
document number: 002 - 08449 rev * a page 17 of 46 mb39c502/503/504 vin = 7.4v, vdd, bst and en connect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c503) parameter symbol condition value unit min typ max on timer on time t on v vin = 7. 4v, v csn = 3.3v 529 575 621 ns minimum on time t minon v vin = 7.4v, v csn = 0.2v 100 200 ns minimum off time t minoff - 90 180 ns currentlimitation current limitation threshold v ilimit csp C csn difference voltage at ilim connects to vcc. 21.0 26.0 31.0 m v ilim input current i ilim v ilim = 5.0v - 0 0.1 a csp input current i csp v csp = 3.3v - 2.0 5.0 a csn input current i csn v csp = 3.3v - 8.0 20.0 a over and under voltage protection over voltage threshold ratio rt ov for target output voltage. at outpu t voltage increasing. 110 115 125 % propagation delay of ov t ov - 4 10 25 s under voltage threshold ratio rt uv for target output voltage. at output voltage decreasing. 65 70 75 % propagation delay of uv t uv - 40 100 200 s power good monitor power go od threshold ratio rt pg for target output voltage. at output voltage increasing. 86 92 98 % hysteresis ratio rt hys - 3 5 7 % propagation delay t pg power good 20 50 200 s t pb power bad 4 10 25 s pwrgd leak current i lkpg v pwrgd = 5.5v - 0 1 a pwrgd output voltage l level v olpg i pwrgd = 1ma sink - 0.05 0.10 v thermal shut down shut down temperature t tsdh shut down temperature. - 150(*1) - c t tsdl exited temperature from thermal shut down state. - 125(*1) - c over current alerting over curren t alerting threshold ratio rt alt for target current limitation. at output current increasing. 78 85 92 % propagation delay t alton on alerting assertion 20 50 200 s t altoff on alerting de - assertion 3 10 25 s alert_n leak current i lkalt v alert_n = 5.5v - 0 1 a alert_n output voltage l level v olalt i alert_n = 1ma sink - 0.05 0.10 v *1: no production tested, ensure by design.
document number: 002 - 08449 rev * a page 18 of 46 mb39c502/503/504 vin = 7.4v, vdd, bst and en con nect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c503) parameter symbol condition value unit min typ max driver high side on resistance r hoh at 100ma current sourcing - 3(*1) - r hol at 100ma current sinki ng - 1(*1) - low side on resistance r loh at 100ma current sourcing - 4(*1) - r lol at 100ma current sinking - 0.75(*1) - high side source current i srch v drvh = 2.5v - 0.7(*1) - a high side sink current i sinkh v drvh = 2.5v - 1.1(*1) - a low side source current i srcl v drvl = 2.5v - 0.5(*1) - a low side sink current i sinkl v drvl = 2.5v - 1.7(*1) - a dead time t dead from drvh turn off to drvl turn on. and reverse it. 10 20 - ns boost switch boost switch on resistance r bst i bst = 10ma - 30 50 b st leak current i lkbst v bst = 30v - 0.1 1.0 a *1: no production tested, ensure by design.
document number: 002 - 08449 rev * a page 19 of 46 mb39c502/503/504 vin = 7.4v, vout, bst and en connect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c504) parameter symbol condition value unit min typ max reference voltage internal reference voltage v ref this voltage is compared to feedback voltage. ta = 25c 4.95 5.00 5.05 v ta = C 10c to 85c 4.90 - 5.10 v vouts input current i vouts v vouts = 5.0v 2.5 5.0 12.5 a enable, slp_n enable condition v en enable voltage range 2.5 - 25 v v dsb disable voltage range 0 - 0.6 v en input current i en v en = 5.0v - 0.5 1.2 a slp_n enable condition v slpdsb lpm disable voltage range 0.65 - 5.5 v v slpen lpm enable voltage range 0 - 0.35 v slp_n input current i slp_n v slp_n = 5.0v - 0 0.1 a supply current vout supply current i voutpwm vout, vcc input current at pwm operating. t a = 25c - 400 800 a i voutpfm vout, vcc input current at idle state in pfm operation. static 0a inductor curren t. t a = 25c - 200 400 a i voutlpm vout, vcc input current at idle state in lpm operation. static 0a inductor current. t a = 25c - 50 100 a vout shutdown current i voutsdn vout, vcc input current at v en = 0v - 0.1 1.0 a vin supply current i vin v vin = 25v - 20 30 a vin shutdown current i vinsdn vin input current at v en = 0v - 0.1 1.0 a under voltage lockout vcc uvlo threshold v uvlo uvlo release voltage 3.99 4.14 4.29 v v hys hysteresis 0.005 0.070 0.200 v soft start, discharge period of power on reset t por from enable on to the switching initiating. 300 - 1400 s ramp up time t ss from the switching initiating after enable on to the output voltage reaches 95%. 598 665 732 s discharge resistance r dischg vout = 0.2v, discharge enable. 50 100 200 discharge ends voltage v dischg v csn voltage. 0.07 0.10 0.13 v
document number: 002 - 08449 rev * a page 20 of 46 mb39c502/503/504 vin = 7.4v, vout, bst and en connect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c504) parameter symbol condition value unit min typ max on timer on time t on v vin = 7.4v, v vout = 5.0v 802 872 942 ns minimum on time t minon v vin = 7.4v, v vout = 0.2v 100 200 - ns minimum off time t minoff - - 120 240 ns currentlimitation current limitation threshold v ilimit csp C csn difference voltage at ilim connects to vcc. 21.0 26.0 31.0 mv ilim input current i ilim v ilim = 5.0v - 0 0.1 a csp input current i csp v csp = 5.0v - 2.0 5.0 a csn input current i csn v csn = 5.0v - 8.0 20.0 a over and under voltage protection over voltage threshold ratio rt ov fo r target output voltage. at output voltage increasing. 110 115 125 % propagation delay of ov t ov - 4 10 25 s under voltage threshold ratio rt uv for target output voltage. at output voltage decreasing. 65 70 75 % propagation delay of uv t uv - 40 100 200 s power good monitor power good threshold ratio rt pg for target output voltage. at output voltage increasing. 86 92 98 % hysteresis ratio rt hys - 3 5 7 % propagation delay t pg power good 20 50 200 s t pb power bad 4 10 25 s pwrgd leak current i lk pg v pwrgd = 5.5v - 0 1 a pwrgd output voltage l level v olpg i pwrgd = 1ma sink - 0.05 0.10 v thermal shut down shut down temperature t tsdh shut down temperature. - 150(*1) - c t tsdl exited temperature from thermal shut down state. - 125(*1) - c * 1: no production tested, ensure by design.
document number: 002 - 08449 rev * a page 21 of 46 mb39c502/503/504 vin = 7.4v, vout, bst and en connect to 5v power supply, pgnd, lx = 0v. t a = C 30c to +85c, unless otherwise noted. (mb39c504) parameter symbol condition value unit min typ max 5v ldo output voltage v ld o5 no switchover. vout input voltage < 4.4v 4.75 5.00 5.25 v output current i ldo5 no switchover. v vin = 5.4v 25 - - ma output short current i ldo5s no switchover. v ldo5 = 0v - 80 125 ma switchover voltage v swovr vout voltage rising. 4.35 4.50 4.60 v v h ys hysteresis voltage. 0.08 0.10 0.12 v startup time t sldo5 ldo5 voltage reaches to 4.2v. c ldo5 , c vcc = 1.0f 100 150 400 s driver high side on resistance r hoh at 100ma current sourcing - 3(*1) - r hol at 100ma current sinking - 1(*1) - low side on resistance r loh at 100ma current sourcing - 4(*1) - r lol at 100ma current sinking - 0.75(*1) - high side source current i srch v drvh = 2.5v - 0.7(*1) - a high side sink current i sinkh v drvh = 2.5v - 1.1(*1) - a low side source current i srcl v drv l = 2.5v - 0.5(*1) - a low side sink current i sinkl v drvl = 2.5v - 1.7(*1) - a dead time t dead from drvh turn off to drvl turn on. and reverse it. 10 20 - ns boost switch boost switch on resistance r bst i bst = 10ma - 30 50 bst leak current i lkbst v b st = 30v - 0.1 1.0 a *1: no production tested, ensure by design.
document number: 002 - 08449 rev * a page 22 of 46 mb39c502/503/504 8. protections and power good function 8.1 description (mb39c502/c503/c504) this pwm control ic has some protection functions uvlo, ovp, uvp, ilim, and tsd for the assumed various power system f ailures. details of these protections are written as follows. under voltage lockout (uvlo) the under voltage lockout (uvlo) protects ics from malfunction and protects the system from destruction/deterioration, according to the reasons mentioned below. ? tra nsitional state when the voltage inputs to vcc (5v power supply) terminal. ? momentary decrease to prevent such a malfunction, this function detects a voltage drop of the 5v power supply, and stops ic operations. when the voltage of 5v power supply exceeds t he threshold voltage of the under voltage lockout protection circuit, the system is restored. over voltage protection (ovp) this function stops the output voltage when the output voltage has increased, and protects devices connected to the output. when th e over voltage is detected, the controller is fixed that the high side switching fet is turned off and the low side switching fet is turned on with 10s propagation delay. when the enable is reentered, this fixed state is released and beginning soft start. under voltage protection (uvp) this function stops the output voltage when the output voltage has lowered, and protects devices connected to the output. when the under voltage is detected, the controller is fixed that the high side switching fet is turne d off and the low side switching fet is turned off with 100s propagation delay. when the enable is reentered, this fixed state is released and beginning soft start. over current limitation (ilim) this function limits the output current when it has increa sed, and protects devices connected to the output. this function detects the inductor valley current with current sense resister rsense. the differential voltage of the csp - csn terminals is amplified to x20 by internal current sense amplifier, and compared to the limit voltage of 480mv fixed at internal preset condition. until the amplified voltage fall the limit voltage, the high side switching fet is held i n the off state. after the voltage has fallen below the limit voltage, the high side switching fet i s placed into the on state. this limits the lower bound of the inductor current and also restricts the over current. as a result, it becomes operation that the output voltage droops. thermal shutdown (tsd) this function prevents the pwm control ic from a t hermal destruction. if the junction temperature reaches +150c, the high side and low side switching fet are turned off. then the discharge operation is carried out to discharge the output capacitor (the discharge operation continues until the state of the thermal shutdown released). if the junction temperature drops to +125c, the soft start is automatically reactivated. power good (pwrgd) power good flag is hoisted at pwrgd terminal (open drain) to hi - z level with 50s propagation delay, when the output voltage becomes larger than 92% of the output setting voltage. it is related by the ovp protection written above. when the output voltage becomes lower than power good threshold level, the pwrgd terminal is changed to l level with 10s propagation delay .
document number: 002 - 08449 rev * a page 23 of 46 mb39c502/503/504 state table of protection function (mb39c502/c503/c504) protection function high side fet low side fet output state remarks under voltage lockout (uvlo) off off off after releasing uvlo, the system is an automatic restoration with soft start. over v oltage protection (ovp) off on latch off latch stall. it returns the system by enable reentry. under voltage protection (uvp) off off latch off latch stall. it returns the system by enable reentry. over current limitation (ilim) switching switching ? the output voltage is drooped with current limitation. thermal shutdown (tsd) off off off after releasing tsd, the system is an automatic restoration with soft start. 8.2 timing chart (mb39c502/c503/c504) under voltage lockout protection (uvlo) t i m e d r v l v o u t e n v c c t u r n o n u v l o d r v h p g o o d t o v c c p o w e r o n r e s e t 2 0 0 u s C 1 0 0 0 u s p o w e r g o o d p o w e r g o o d 5 0 u s p r o p a g a t i o n d e l a y p o w e r o n r e s e t 2 4 0 u s v o u t 9 2 % o f s e t t i n g v o l t a g e 5 v
document number: 002 - 08449 rev * a page 24 of 46 mb39c502/503/504 over voltage protection (ovp) t i m e d r v l v o u t e n v c c u v l o d r v h p g o o d t o v c c p o w e r g o o d p o w e r g o o d o v p t u r n o f f p o w e r o n r e s e t 1 0 u s p r o p a g a t i o n d e l a y 5 0 u s p r o p a g a t i o n d e l a y v o u t 9 2 % o f s e t t i n g v o l t a g e t u r n o n p o w e r o n r e s e t 2 0 0 u s C 1 0 0 0 u s 5 v
document number: 002 - 08449 rev * a page 25 of 46 mb39c502/503/504 under voltage protection (uvp) t i m e d r v l v o u t e n v c c u v l o d r v h p g o o d t o v c c p o w e r g o o d p o w e r g o o d u v p t u r n o f f p o w e r o n r e s e t 5 0 u s p r o p a g a t i o n d e l a y 1 0 0 u s p r o p a g a t i o n d e l a y v o u t 9 2 % o f s e t t i n g v o l t a g e 1 0 u s p r o p a g a t i o n d e l a y v o u t 8 7 % o f s e t t i n g v o l t a g e t u r n o n p o w e r o n r e s e t 2 0 0 u s C 1 0 0 0 u s 5 v
document number: 002 - 08449 rev * a page 26 of 46 mb39c502/503/504 over current limitation (ilim) t i m e d r v l v o u t d r v h p g o o d t o v c c p o w e r g o o d i l i o u t 1 0 u s p r o p a g a t i o n d e l a y p o w e r b a d v o u t 8 7 % o f s e t t i n g v o l t a g e v o u t s e t t i n g v o l t a g e i l i m d e t e c t i o n l e v e l k e e p t h e o f f s t a t e o f t h e h i g h s i d e f e t u n t i l t h e d e t e c t i o n v a l u e i s g a i n e d
document number: 002 - 08449 rev * a page 27 of 46 mb39c502/503/504 thermal shutdown (tsd) 9. enhanced lpm description (mb39c502/c503/c504) this pwm controller has some features for high efficiency technology with ultra low quiescent current and extended on time on asserting slp_l signal from the system. notes ? perform transferring to enhance d lpm in the static switching state after 2ms from en turn on. the soft starting on the enabling enhanced lpm does not allow this controller. ? in enhanced lpm, maximum loading current is less than critical current of discontinuous conductive mode, in othe r words pulse skip mode. t i m e d r v l v o u t e n v c c u v l o d r v h p g o o d t o v c c p o w e r g o o d p o w e r g o o d t s d t j > 1 5 0 d e g c t j < 1 2 5 d e g c 5 0 u s p r o p a g a t i o n d e l a y p o w e r o n r e s e t v o u t 9 2 % o f s e t t i n g v o l t a g e p o w e r o n r e s e t 2 0 0 u s C 1 0 0 0 u s t u r n o n 5 v
document number: 002 - 08449 rev * a page 28 of 46 mb39c502/503/504 9.1 ultra low quiescent current (mb39c502/c503/c504) this controller has the feature of ultra low quiescent current 30ua in enhanced lpm. so that the ic power loss is effectively improved efficiency i n dcdc light load. 9.2 extended on time (mb39c502/c503/c504) this controller uses feed forward on - time architecture with the information of input and output voltage. and this controller is transferred extended on - time keeping the input and output voltage i nformation in enhanced lpm. by the on time is extended, gate drive loss is reduced by decreasing the switching frequency. 0 a 0 a i n d u c t o r c u r r e n t h i g h s i d e g a t e i n d u c t o r c u r r e n t h i g h s i d e g a t e i n n o r m a l o p e r a t i o n i n e n h a n c e d l p m o p e r a t i o n o n t i m e d e p e n d e d o n v i n a n d v o u t v o l t a g e o n t i m e d e p e n d e d o n v i n a n d v o u t v o l t a g e a n d x 1 . 4 1 f o r n o r m a l o p e r a t i o n s l p _ n e n e n h a n c e d l p m a s s e r t i o n t i m m i n g m a x i m u m l o a d i n g c u r r e n t i n e n h a n c e d l p m e n t u r n o n e n h a n c e d l p m a s s e r t i o n b r a n k 2 m s f r o m e n t u r n o n s w i t c h i n g f r e q u e n c y l o a d c u r r e n t c r i t i c a l c u r r e n t d i s c o n t i n u o u s c o n d u c t i v e m o d e ( p u l s e s k i p m o d e ) c o n t i n u o u s c o n d u c t i v e m o d e p e r m i s s i o n p r o h i b i t i o n
document number: 002 - 08449 rev * a page 29 of 46 mb39c502/503/504 9.3 timing chart of enhanced lpm (mb39c502/c503/c504) this controller is transferred to enhanced lpm synchr onized the zero crossing of inductor current, and transferred to normal operation with 100ns propagation delay avoid the switching period. 0 a n o r m a l l o w p o w e r s y n c h r o n i z e d w i t h z e r o c r o s s f l a g o f i n d u c t o r c u r r e n t 0 a n o r m a l k e e p t h e n o r m a l m o d e i l o a d s l p _ n v r m o d e i n d u c t o r c u r r e n t 0 a l o w p o w e r w a i t t h e t i m i n g b e c o m e s t o a n i d l e m o d e n o r m a l i d l e s t a t e < 1 . 2 5 u s ( < f s w _ c c m - 1 ) 0 a l o w p o w e r a n y t i m e f o r i d l e p e r i o d n o r m a l < 1 0 0 n s i d l e s t a t e i d l e s t a t e i d l e s t a t e i d l e s t a t e i l o a d s l p _ n v r m o d e i n d u c t o r c u r r e n t i d l e s t a t e i l o a d s l p _ n v r m o d e i n d u c t o r c u r r e n t i d l e s t a t e i l o a d s l p _ n v r m o d e i n d u c t o r c u r r e n t i d l e s t a t e
document number: 002 - 08449 rev * a page 30 of 46 mb39c502/503/504 10. over current alerting description (mb39c502/c503) this controller has over current alerting function. in near over current limitation range, the alert_n with nch open drain terminal is change to l level. over current alerting level is set 85% for over current limitation level. i o u t v o u t i o u t _ m a x i o u t _ l i m i t o v e r c u r r e n t a l e r t i n g r a n g e i o u t _ o c a l e r t o v e r c u r r e n t a l e r t i n g l e v e l i s s e t 8 5 % o f o v e r c u r r e n t l i m i t a t i o n l e v e l
document number: 002 - 08449 rev * a page 31 of 46 mb39c502/503/504 11. application note 11.1 setting operating conditions 11.1.1 setting output voltage the output voltage can be set by adjusting the setting output voltage resister ratio. setting output voltage is calculated by the following formula. (mb39c502) (mb39c503/c504) v out : output set ting voltage (v) r1, r2 : feedback resistor () the total resistor value ( r1+r2 ) of the setting output resistor should be selected up to 300k. when the output voltage setting value is higher than 1.2v, select resistance that the current of 300a or more flows into feedback res istor. 11.1.2 setting over current limitation and over current alerting the over current limitation value can be set by adjusting the current sense resistor. calculate the resister value by the following formula. (mb39c502) (mb39c503/c50 4) r sense : over current limitation value setting resister () i limit : over current limitation value (a) i l : inductor ripple current peak to peak value (a) v out : output voltage (v) l : inductance (h) 7 0 2 2 1 . r r r v out ? ? ? 0 . 1 2 2 1 ? ? ? r r r v out 1 9 10 300 2 024 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? l v i i . r out l limit sense 1 9 10 300 2 025 . 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? l v i i r out l limit sense
document number: 002 - 08449 rev * a page 32 of 46 mb39c502/503/504 the over current limitation value needs to set a sufficient m argin against the maximum load current. the over current alerting value is set with over current limitation value as following formula. (mb39c503/c504) r sense : over current limitation value setting resister () i alert : over curren t alerting value (a) i l : inductor ripple current peak to peak value (a) v out : output voltage (v) l : inductance (h) 11.2 selection parts 11.2.1 selection of smoothing inductor (mb39c502/c503/c504) as a rough guide, inductance of an inductor should keep the peak to peak value of inductor ripple current below 50% of the maximum output current. the inductance fulfilling the above condition can be found by the following formula. l : inductance (h) i out_max : maximum load current lor : inductor ri pple current peak to peak value C maximum output current ratio (less than 0.5) v in : power supply voltage (v) v out : output voltage (v) f sw : switching frequency (hz) the minimum output current (critical current) in the condition that inductor current doe s not flow in reverse can be found by the following formula. i oc : critical current (a) l : inductance (h) v in : power supply voltage (v) v out : output voltage (v) f sw : switching frequency (hz) the maximum value of the current flow ing through the inductor needs to be found in order to determine whether the current flowing through the inductor is within the rated value. the maximum current flowing through the inductor can be found by the following formula. 2 85 0 2 10 300 024 0 9 l out sense alert i . l v r . i ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sw in out max _ out out in f v v i lor v v l ? ? ? ? ? sw in out in out oc f v v v l v i ? ? ? ? ? 2
document number: 002 - 08449 rev * a page 33 of 46 mb39c502/503/504 i l_m ax : maximum inductor current (a) i out_max : maximum load current (a) i l : inductor ripple current peak to peak value (a) 11.2.2 selection of switching fet (mb39c502/c503/c504) in general, mosfet should be used with a 30v absolute maximum rating. obtain the max imum value of the current flowing through the switching fet in order to determine whether the current flowing through the switching fet is within the rated value. the maximum current flowing through the switching fet can be found by the following formula. i d_max : maximum switching fet drain current (a) i out_max : maximum load current (a) i l : inductor ripple current peak to peak value (a) in addition, find the loss of the switching fet in order to determine whether the allowable loss of the switching is within the rated value. the allowable loss of the high side fet can be found by the f ollowing formula. p fet_hs : overall loss of high side fet (w) p ron_hs : conduction loss of high side fet (w) p sw_hs : switching loss of high side fet (w) the conduction loss of high side is followed as. p ron_h s : conduction loss of high side fet (w) i out_max : maximum load current (a) v in : power supply voltage (v) v out : output voltage (v) r on_hs : on resistance of high side fet () the switching loss of high side is followed as. p sw_hs : switching loss of high side fet (w) v in : power supply voltage (v) f sw : switching frequency (hz) i out_max : maximum load current (a) q sw : amount of high side fet gate switch electric charge (c) 2 l max _ out max _ l i i i ? ? 2 l max _ out max _ d i i i ? ? hs _ sw hs _ ron hs _ fet r p p ? ? hs _ on in out max _ out hs _ ron r v v i p ? ? ? 2 sw max _ out sw in hs _ sw q i f v . p ? ? ? ? ? 56 1
document number: 002 - 08449 rev * a page 34 of 46 mb39c502/503/504 mosfet has a tendency where the gate drive loss increases because lower voltage product has the bigger amount of gate electric charge (q g ). normally, we recommend a 4v drive product, however, the idle period at light load (both the high side fet and the low side fet is off period) get longer and the gate drive voltage of the high side fet may decrease, in the automatic pfm/pwm transition. the voltage drops most at no load mode. at the time, confirm that the boost voltage (voltage between bst - lx pins) is a big enough value for the gate threshold value voltage of the high side fet. if it is not enough, consider adding the boost diode, increasing the capacitor value of the capacitor or using a 2.5v (or 1.8v) drive product to the high side fet. the allowable loss of the low side fet can be found by the following formula. p fet_ls : overall loss of low side fet (w) p ron_ls : conduction loss of low side fet (w) i out_max : maximum ou tput current (a) v in : switching power supply voltage (v) v out : output voltage (v) r on_ls : on resistance of low side fet () in switching of low side fet, the transiting voltage between drain to source is generally small. the switching fet loss is omitt ed in this document as it is negligible. ls _ on in out max _ out ls _ ron ls _ fet r v v i p p ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2
document number: 002 - 08449 rev * a page 35 of 46 mb39c502/503/504 11.2.3 selection of fly back diode (mb39c502/c503/c504) this device is improved by adding the fly back diode when the conversion efficiency improvement or the suppression of the low side fet fever is desired, although those are unnecessary to execute normally. the effect is achieved in the condition where the switching frequency is high or output voltage is lower. select period for the electric current flow into fly back diode is limited to dead time period because the synchronous rectification system is adopted (as for the dead time, see electrical characteristics). each rating for the fly back diode can be calculated by the following formula. i d : forward current rating of sbd (a) i out_max : ma ximum load current (a) f sw : switching frequency (hz) t d1 , t d2 : dead times (s) i fsm : rated value of fly back diode (v) i out_max : maximum output current (a) i l : inductor ripple current peak to peak value (a) v r_fly : dc reversing voltage of fly back diode (v) v in : switching power supply voltage (v) 11.2.4 selection of boost diode (mb39c502) select a schottky barrier diode (sbd) that has a small forward voltage drop. the current to drive the gate of high - side fet flows to the sbd of the boost circuit. the average current can be found by the following formula. select a boost diode that keep the average current below the current rating. i d : forward current (a) q g_hs : total gate electric charge of high - side fet (c) f sw : switching frequency (hz) the rating of the boost diode can be found by the following formula. v r_boost : boost diode dc reverse voltage (v) v in : switching power supply voltage (v) ? ? 2 1 _ d d sw max out d t t f i i ? ? ? ? 2 _ l max out fsm i i i ? ? ? in fly r v v ? _ sw hs _ g d f q i ? ? in boost _ r v v ?
document number: 002 - 08449 rev * a page 36 of 46 mb39c502/503/504 11.2.5 selection of input capacitor (mb39c502/c503/c504) select the input capacitor whose esr is as small as possible. the ceramic capacitor is an ideal. use the tantalum capacitor and the polymer capacitor o f low esr when a mass capacitor is needed as the ceramic capacitor cannot support. the ripple voltage is generated in the power supply voltage by the switching operation. calculate the lower bound of input capacitor according to an allowable ripple voltage . calculate the ripple voltage of the power supply from the following formula. v in : power supply ripple voltage peak to peak value (v) i out_max : maximum load current (a) c in : input capacitance (f) v in : power supply voltage (v) v out : output voltage (v) f sw : switching frequency (hz) esr : series resistance component of input capacitor () i l : ripple current peak to peak value of inductor (a) capacitor has frequency characteristics, the temperature characteristics, and the volt age characteristics, etc. the effective capacitance might become extremely small depending on the use conditions. note the effective capacitance in the use conditions. calculate ratings of the input capacitor by following formula. v cin : withstand voltage of the input capacitor (v) v in : power supply voltage (v) irms : allowable ripple current of input capacitor (effective value) (a) i out_max : maximum load current (a) v in : power supply voltage (v) v out : out put voltage (v) ? ? ? ? ? ? ? ? ? ? ? ? 2 l max _ out sw in out in max _ out in i i esr f v v c i v in cin v v ? ? ? in out in out max _ out v v v v i irms ? ? ? ?
document number: 002 - 08449 rev * a page 37 of 46 mb39c502/503/504 11.2.6 selection of output capacitor since a high esr causes the output ripple voltage to increase, a low esr capacitor is needs to be used in order to reduce the output ripple voltage. generally, the ceramic capacitor is used as the output c apacitor. with the switching ripple voltage taken consideration, the minimum capacitance required can be found by the following formula. (mb39c502/c503/c504) c out : output capacitance (f) esr : series resistance element of output ca pacitor () v out : output ripple voltage (v) i l : inductor ripple current peak to peak value (a) also, it is necessary to unite a pole by the output capacitor and the output load with a zero by the internal compensation circuit, and to limit the crossov er frequency. the minimum capacitance required can be found by the following formula. (mb39c502) (mb39c503) (mb39c504) (mb39c502) (mb39c503) (mb39c504) i out_max : maximum output load current (a) v out : output voltage (v) r sense : over current limitation value setting resister () ? ? esr i v f c l out sw out ? ? ? ? 2 1 out max _ out 6 out v i 10 5 . 42 c ? ? ? ? out max _ out 6 out v i 10 0 . 49 c ? ? ? ? max _ out 6 out i 10 7 . 21 c ? ? ? ? out sense 6 out v r 1 10 59 . 0 c ? ? ? ? ? out sense 6 out v r 1 10 67 . 0 c ? ? ? ? ? sense 6 out r 1 10 27 . 0 c ? ? ? ?
document number: 002 - 08449 rev * a page 38 of 46 mb39c502/503/504 moreover, the output capacitance is also derived from the allowable amount of overshoot and under shoot. adjust the capacitance so that the overshoot/undershoot voltage should not exceed the target voltage range. 11.2.7 selection of bo ost capacitor to drive the gate of high side fet, the boost capacitor must have enough stored charge. 0.47f is assumed to be standard; however, it is necessary to adjust it when the high side fet q g is big. consider the capacitance calculated by the foll owing formula as the lowest value for the boost capacitance and select a thing anymore. (mb39c502/c503/c504) c bst : boost capacitance (f) q g_hs : amount of high side fet gate charge (c) calculate ratings of the boost capacitor by t he following formula. (mb39c502/c503) (mb39c504) v cbst : withstand voltage of the boost capacitor (v) v vdd : input voltage of vdd terminal (v) v ldo5 : input voltage of ldo5 terminal (v) hs _ g bst q c ? ? 10 vdd cbst v v ? 5 ldo cbst v v ?
document number: 002 - 08449 rev * a page 39 of 46 mb39c502/503/504 11.2.8 selection of vdd cap acitor 4.7f is assumed to be a standard, and when q g of switching fet used large, it is necessary to adjust it. to suppress the ripple voltage by the switching fet gate drive, consider the capacitance calculated by the following formula as the lowest val ue for vdd capacitor and select a thing any more. calculate ratings of the vdd terminal capacitor by the following formula. (mb39c502/c503) (mb39c504) c vdd : vdd pin capacitance (f) c ldo5 : ldo5 pin capacitan ce (f) q g : total amount of high and low side fets gate charge (c) calculate ratings of the vdd terminal capacitor by the following formula. (mb39c502/c503) (mb39c504) v cvdd : withstand voltage of the vdd ter minal capacitor (v) v vdd : input voltage of vdd terminal (v) v cldo5 : withstand voltage of the ldo5 terminal capacitor (v) v ldo5 : input voltage of ldo5 terminal (v) 11.2.9 selection of vcc capacitor and resistor (mb39c502/c503) connect 1.0f between vcc to agn d terminal. connect 10 between vcc to vdd terminal. (mb39c504) connect 1.0f between vcc to agnd terminal. connect 10 between vcc to ldo5 terminal. g vdd q c ? ? 50 g ldo q c ? ? 50 5 vdd cvdd v v ? 5 5 ldo cldo v v ?
document number: 002 - 08449 rev * a page 40 of 46 mb39c502/503/504 11.3 layout (mb39c502/c503) consider the points listed below and do the layout design. ? provide the ground pl ane as much as possible on the ic mounted face. connect bypass capacitor connected with the vcc and vdd pins, and agnd pin of the switching system parts with switching system gnd (pgnd). connect other gnd connection pins with control system gnd (agnd), and separate each gnd, and try not to pass the heavy current path through the control system gnd (agnd) as much as possible. in that case, connect control system gnd (agnd) and switching system gnd (pgnd) at the single point of gnd (pgnd) directly below ic. s witching system parts are input capacitor (c in ), switching fet, fly back diode (sbd), inductor (l) and output capacitor (c out ). ? connect the switching system parts as much as possible on the surface. avoid the connection through the through hole as much as possible. ? as for agnd pins of the switching system parts, provide the through hole at the proximal place, and connect it with gnd of internal layer. ? pay the most attention to the loop composed of input capacitor (c in ), switching fet, and fly back diode (sb d). consider parts are disposed mutually to be near for making the current loop as small as possible. ? place the bootstrap capacitor (c bst ) proximal to bst and lx pins of ic as much as possible. ? connect the line to the lx pin proximal to the drain pin of lo w - side fet. also large electric current flows momentary in this net. wire the line of width of about 0.8 mm as standard, and as short as possible. ? large electric current flows momentary in the net of drvh and drvl pins connected with the gate of switching fet. wire the line width of about 0.8 mm to be a standard, as short as possible. take special care about the line of the drvl pin, and wire the line as short as possible. ? by - pass capacitor (c vcc , c vdd ) connected with vcc, and vdd should be placed close to the pin as much as possible. also connect the gnd pin of the bypass capacitor with gnd of internal layer in the proximal through - hole. ? pull the feedback line to be connected to the fb pin of the ic separately from near the output capacitor pin, whenever po ssible. consider the line connected with fb pins to keep away from a switching system parts as much as possible because it is sensitive to the noise. also, place the output voltage setting resistor connected to this line near ic, and try to shorten the li ne to the fb pin. in addition, for the internal layer right under the component mounting place, provide the control system gnd (agnd) of few ripple and few spike noises, or provide the ground plane of the power supply as much as possible. consider that the discharge current momentary flows into the csn pin (about 10ma at 1.0v output voltage) when the dc/dc operation stops, and then sustain the width for the feedback line. there is leaked magnetic flux around the inductor or backside of place equipped with i nductor. line and parts sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with inductor).
document number: 002 - 08449 rev * a page 41 of 46 mb39c502/503/504 gnd routing example layout example of switching components e p : a g n d ( t o p v i e w ) i n n e r l a y e r : a g n d c v c c c v d d c b s t i n n e r l a y e r : p g n d p g n d s u r f a c e l a y e r c v i n c o n n e c t t h e p g n d t o t h e a g n d a t s i n g l e p o i n t d i r e c t l y u n d e r t h e i c c v i n h i g h s i d e s w i t c h i n g f e t l o w s i d e s w i t c h i n g f e t s b d ( o p t i o n a l ) i n d u c t o r o u t p u t c a p a c i t o r p g n d v i n v o u t s e n s e r e s i s t o r t o c s p t o c s n t o l x v o u t s e n s e
document number: 002 - 08449 rev * a page 42 of 46 mb39c502/503/504 (mb39c504) consider the points listed b elow and do the layout design. ? provide the ground plane as much as possible on the ic mounted face. connect bypass capacitor connected with the vcc and ldo5 pins, and agnd pin of the switching system parts with switching system gnd (pgnd). connect other g nd connection pins with control system gnd (agnd), and separate each gnd, and try not to pass the heavy current path through the control system gnd (agnd) as much as possible. in that case, connect control system gnd (agnd) and switching system gnd (pgnd) at the single point of gnd (pgnd) directly below ic. switching system parts are input capacitor (c in ), switching fet, fly back diode (sbd), inductor (l) and output capacitor (c out ). ? connect the switching system parts as much as possible on the surface. avo id the connection through the through hole as much as possible. ? as for agnd pins of the switching system parts, provide the through hole at the proximal place, and connect it with gnd of internal layer. ? pay the most attention to the loop composed of input capacitor (c in ), switching fet, and fly back diode (sbd). consider parts are disposed mutually to be near for making the current loop as small as possible. ? place the bootstrap capacitor (c bst ) proximal to bst and lx pins of ic as much as possible. ? connect the line to the lx pin proximal to the drain pin of low - side fet. also large electric current flows momentary in this net. wire the line of width of about 0.8 mm as standard, and as short as possible. ? large electric current flows momentary in the net of dr vh and drvl pins connected with the gate of switching fet. wire the line width of about 0.8 mm to be a standard, as short as possible. take special care about the line of the drvl pin, and wire the line as short as possible. ? by - pass capacitor (c vcc , c ldo5 ) connected with vcc, and ldo5 should be placed close to the pin as much as possible. also connect the gnd pin of the bypass capacitor with gnd of internal layer in the proximal through - hole. ? pull the feedback line to be connected to the fb pin of the ic se parately from near the output capacitor pin, whenever possible. consider the line connected with fb pins to keep away from a switching system parts as much as possible because it is sensitive to the noise. also, place the output voltage setting resistor c onnected to this line near ic, and try to shorten the line to the fb pin. in addition, for the internal layer right under the component mounting place, provide the control system gnd (agnd) of few ripple and few spike noises, or provide the ground plane of the power supply as much as possible. consider that the discharge current momentary flows into the csn pin (about 10ma at 1.0v output voltage) when the dc/dc operation stops, and then sustain the width for the feedback line. there is leaked magnetic flux around the inductor or backside of place equipped with inductor. line and parts sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with inductor).
document number: 002 - 08449 rev * a page 43 of 46 mb39c502/503/504 gnd routing example layout example of switching com ponents 12. ordering information table 1 2 - 1 ordering information part number package remarks mb39c502wqn - g - amere1 16 - pin plastic qfn (wn 2 016) mb39c503wqn - g - amere1 mb39c504wqn - g - amere1 e p : a g n d ( t o p v i e w ) i n n e r l a y e r : a g n d c v c c c l d o 5 c b s t i n n e r l a y e r : p g n d p g n d s u r f a c e l a y e r c v i n c o n n e c t t h e p g n d t o t h e a g n d a t s i n g l e p o i n t d i r e c t l y u n d e r t h e i c c v i n h i g h s i d e s w i t c h i n g f e t l o w s i d e s w i t c h i n g f e t s b d ( o p t i o n a l ) i n d u c t o r o u t p u t c a p a c i t o r p g n d v i n v o u t s e n s e r e s i s t o r t o c s p t o c s n t o l x v o u t s e n s e
document number: 002 - 08449 rev * a page 44 of 46 mb39c502/503/504 13. package dimensions
document number: 002 - 08449 rev * a page 45 of 46 mb39c502/503/504 14. major changes spansion publication number: mb39c502_ds405 - 00020 - 1v0 - e page section change results revision 1.0 - - initial release note: please see document history about later revised information. document history document title: mb39c502/503/504 high efficiency step down dc/dc controller datasheet document number: 00 2 - 08449 revision ecn orig. of change submission date description of change ** ? taoa 09/09 /201 4 migrated to cypress and assig ned document number 002 - 08449 . no change to document contents or format. *a 5127378 taoa 02/1 2 /2016 updated to cypress template
document number: 002 - 08449 rev * a page 46 of 46 mb39c502/503/504 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distrib utors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress.com/go/interface lighting & power control cypress.com/go/powerpsoc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress .com/go/usb wireless/rf cypress.com/go/wireless spansion products cypress.com/spansion products psoc? so lutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support cypress ? , the cypress logo, spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse tm , ornand tm , easy designsim tm , traveo tm and combinations thereof, are trademarks and registered trademarks of cypress semiconductor corp. arm and cortex are the registered trademarks of arm limited in the e u and other countri es. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semiconductor corporation, 2014 - 2016 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply a ny license under patent or other rights. cypress products are not warranted nor intended to be used for medi cal, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life - support systems where a malfu nction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress a gainst all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and s ubject to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable a greement. any reproduction, modification, translation, compilation, or representation of this source co de except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limit ed to, the implied warranties of merc hantability and fitness for a part icular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress does not assume any liability arising out of the application or use of any product or cir cuit described herein. cypress does not au thorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the in clusion of cypress product in a life - support systems application impli es that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement.

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