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ht82k94e/HT82K94A usb multimedia keyboard encoder 8-bit mcu rev. 1.50 1 october 11, 2007 general description this device is an 8-bit high performance risc architec- ture microcontroller designed for usb product applica - tions. it is particularly suitable for use in products such as keyboards and keyboard with calculator. a halt fea - ture is included to reduce power consumption. the mask version HT82K94A is fully pin and function- ally compatible with the otp version ht82k94e device. the HT82K94A is under development and will be avail - able soon. features operating voltage: f sys =6m/12mhz: 2.2v~5.5v 40 bidirectional i/o lines (max.) 8-bit programmable timer/event counter with overflow interrupt (shared with pd4, vector 08h) 16-bit programmable timer/event counter and overflow interrupts (shared with pa7, vector 0ch) crystal oscillator (6mhz or 12mhz) watchdog timer ps2 and usb modes supported usb 2.0 low speed function 4 endpoints supported (endpoint 0 included) 6144 16 program memory rom 224 8 data memory ram one internal usb interrupt (vector 04h) all i/o ports support wake-up options halt function and wake-up feature reduce power consumption 8-level subroutine nesting up to 0.33 s instruction cycle with 12mhz system clock at v dd =5v bit manipulation instruction 16-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles optional 3-battery mode 2.4v lvr/2.6v lvd ( 0.1v) by option, low battery detector with internal bit optional 2-battery mode 2.2v lvr/2.4v lvd ( 0.1v) by option, low battery detector with internal bit operating voltage from 4.0v to 5.5v (for connect usb/ps2 mode) operating voltage from 2.2v to 3.3v (for pure cal. mode) 48-pin ssop package technical document tools information faqs application note
block diagram ht82k94e/HT82K94A rev. 1.50 2 october 11, 2007

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pin assignment pin description pin name i/o rom code option description pa0~pa6 pa7/tmr1 i/o pull-high wake-up cmos/nmos/pmos bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by rom code option. the input or output mode is con- trolled by pac (pa control register). pull-high resistor options: pa0~pa7 cmos/nmos/pmos options: pa0~pa7 wake-up options: pa0~pa7 pa7 is pin-shared with tmr1 input, respectively. pb0~pb7 i/o pull-high wake-up bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options). wake-up options: pb0~pb7 pc0~pc7 i/o pull-high wake-up bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by pull-high options). wake-up options: pc0~pc7 pd0~pd3 pd4/tmr0 pd5~pd7 i/o pull-high wake-up bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by pull-high options). wake-up options: pd0~pd7 pd4 is pin-shared with tmr0 input. pe0~pe7 i/o pull-high wake-up bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by pull-high options). wake-up options: pe0~pe7 ht82k94e/HT82K94A rev. 1.50 3 october 11, 2007 * 6 * - * 4 * 5 * * * 1 * * * 1 7 1 6 1 - 1 4 1 5 1 * 1 1 1 1 1 7 6 - 4 5 1 * 5 4 - 6 7 1 * 5 4 - 6 7 1 *

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pin name i/o rom code option description vss negative power supply, ground res i schmitt trigger reset input. active low vdd positive power supply v33o o 3.3v regulator output usbd+/clk i/o usbd+ or ps2 clk i/o line usb or ps2 function is controlled by software control register usbd-/data i/o usbd- or ps2 data i/o line usb or ps2 function is controlled by software control register osc1 osc2 i o osc1, osc2 are connected to a 6mhz or 12mhz crystal/resonator (determined by software instructions) for the internal system clock. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature...............................0 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =6mhz 2.2 5.5 v f sys =12mhz 2.2 5.5 v i dd1 operating current (6mhz crystal) 5v no load, f sys =6mhz 6.5 12 ma i dd2 operating current (12mhz crystal) 5v no load, f sys =12mhz 7.5 16 ma i stb1 standby current (wdt enabled) 5v no load, system halt, usb suspend 250 a i stb2 standby current (wdt disabled) 5v no load, system halt, usb suspend 230 a i stb3 standby current (wdt enabled) 5v no load, system halt, input/output mode, set suspend2 [1eh] 15 a v il1 input low voltage for i/o ports 5v ttl level 0 0.8 v v ih1 input high voltage for i/o ports 5v ttl level 2 5v v il2 input low voltage (res ) 5v cmos level 0 0.4v dd v v ih2 input high voltage (res ) 5v cmos level 0.9v dd v dd v i ol1 i/o port sink current for pa1~pa7, pb, pc, pd 5v v ol =3.4v 10 15 20 ma i ol2 i/o port sink current for pa1~pa7, pb, pc, pd 5v v ol =0.4v 248ma i ol3 i/o port sink current for pa0 5v v ol =0.4v 7 10 13 ma ht82k94e/HT82K94A rev. 1.50 4 october 11, 2007
symbol parameter test conditions min. typ. max. unit v dd conditions i oh1 i/o port source current for pa1~pa7, pb, pc, pd 5v v oh =3.4v 2 4 8 ma i oh2 i/o port source current for pa0 5v v oh =3.4v 12 18 24 ma r ph pull-high resistance for pa, pb, pc, pd 5v 25 50 80 k v lvr low voltage reset 2-battery option 2.1 2.2 2.3 v 3-battery option 2.3 2.4 2.5 v lvd low battery detecting voltage 2-battery option 2.3 2.4 2.5 v 3-battery option 2.5 2.6 2.7 v v33o 3.3v regulator output 5v i v33o = 5ma 3.0 3.3 3.6 v a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc) 5v 6 12 mhz f timer timer i/p frequency (tmr) 5v 0 12 mhz t wdtosc watchdog oscillator 5v 15 31 70 s t wdt1 watchdog time-out period (wdt osc) 5v without wdt prescaler 4 8 16 ms t wdt2 watchdog time-out period (system clock) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 t sys power-up, watchdog time-out from normal 1024 t wdtosc t int interrupt pulse width 1 s ht82k94e/HT82K94A rev. 1.50 5 october 11, 2007
functional description ht82k94e/HT82K94A rev. 1.50 6 october 11, 2007 execution flow the system clock for the microcontroller is derived from a crystal (6 or 12mhz). the system clock is internally di - vided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme allows each instruction to be effectively executed in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call or return from subroutine, initial reset, internal interrupt, usb in - terrupt or return from interrupts, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed to the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. 1 * 1 * 1 * 8 $ ( ( 9 : ; ( ( 9 0 : 8 $ ( ( 9 / : ; ( ( 9 : 8 $ ( ( 9 / : ; ( ( 9 / : / / ! ( 2 < ( 9 ( 2 : execution flow mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000000 usb interrupt 0000000000100 timer/event counter 0 overflow 0000000001000 timer/event counter 1 overflow 0000000001100 skip program counter+2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits
ht82k94e/HT82K94A rev. 1.50 7 october 11, 2007 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 6144 16 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the usb and external inter - rupt service program. if the usb interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter 0 in - terrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in - terrupt is enabled and the stack is not full, the program begins execution at location 008h. location 00ch this location is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter - rupt is enabled and the stack is not full, the program begins execution at location 00ch. table location any location in the program memory can be used as look-up tables. there are three method to read the rom data by two table read instructions: tabrdc and tabrdl , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the three methods are shown as follows:
the instructions tabrdc [m] (the current page, one page=256words), where the table locations is defined by tblp (07h) in the current page. and the rom code option tbhp is disabled (default).
the instructions tabrdc [m] , where the table lo - cations is defined by registers tblp (07h) and tbhp (01fh). and the rom code option tbhp is enabled.
the instructions tabrdl [m] , where the table lo - cations is defined by registers tblp (07h) in the last page (1700h~17ffh). only the destination of the lower-order byte in the ta- ble is well-defined, the other bits of the table word are transferred to the lower portion of tblh , and the re- maining 1-bit words are read as 0 . the table higher-order byte register (tblh) is read only. the ta- ble pointer (tblp, tbhp) is a read/write register (07h, 1fh), which indicates the table location. before ac- cessing the table, the location must be placed in the tblp and tbhp (if the otp option tbhp is disabled, the value in tbhp has no effect). the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main rou - tine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt should be disabled prior to the table read instruction. 4 ( = ! - 8 8 > 8 8 >
? ( 2 @ ( , ( ( = ) ? ( ( ( = ( # < 0 ( = 2 ( 9 5 4 ( a " ! : # < 0 ( = 2 ( 9 5 4 ( a " ! : b ( ( ! ( % ( ( ( 8 > > 6 > * > > ) ? ( ( ( = ( - > program memory instruction table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 table location note: *12~*0: table location bits p12~p8: current program counter bits when tbhp is disabled @7~@0: table pointer bits tbhp register bit3~bit0 when tbhp is enabled
ht82k94e/HT82K94A rev. 1.50 8 october 11, 2007 it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the require - ments. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp value. otherwise, the rom code option tbhp is dis - abled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current program counter bits. stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al- lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub- sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return ad - dresses are stored). data memory ram for bank 0 the data memory is designed with 255 8 bits. the data memory is divided into two functional groups: spe - cial function registers and general purpose data mem - ory (224 8). most are read/write, but some are read only. the general purpose data memory, addressed from 20h to ffh, is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decre - ment and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0 or mp1). data memory ram for bank 1 the special function registers used in usb interface are located in ram bank 1. in order to access the bank1 register, only the indirect addressing pointer mp1 can be used and the bank register bp should be set to 1 . the mapping of ram bank 1 is as shown. & 2 ( ! (
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ht82k94e/HT82K94A rev. 1.50 9 october 11, 2007 indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] ([02h]) will access data memory pointed to by mp0 (mp1). reading location 00h (02h) itself indi - rectly will return the result 00h. writing indirectly results in no operation. the indirect addressing pointer (mp0) always point to bank0 ram addresses regardless of the value of the bank register (bp). the indirect addressing pointer (mp1) can access bank0 or bank1 ram data according to the value of bp which is set to 0 or 1 respectively. the memory pointer registers (mp0 and mp1) are 8-bit registers. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera- tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addi - tion operations related to the status register may give different results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt instruction. the pdf flag can be affected only by ex - ecuting the halt or clr wdt instruction or dur - ing a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides internal timer/event counter and usb interrupts. the interrupt control register (intc;0bh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register
ht82k94e/HT82K94A rev. 1.50 10 october 11, 2007 the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related in - terrupt is enabled, until the sp is decremented. if immedi - ate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. usb interrupts are triggered by the following usb events and the related interrupt request flag (usbf; bit 4 of the intc) will be set. the corresponding usb fifo is accessed from the pc the usb suspends signal from the pc the usb resumes signal from the pc the usb sends reset signal when the interrupt is enabled, the stack is not full and the usb interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (usbf) and emi bits will be cleared to disable other interrupts. when the pc host access the fifo of the ht82k94e/ HT82K94A, the corresponding request bit of the usr is set, and a usb interrupt is triggered. so user can easily decide which fifo is accessed. when the interrupt has been served, the corresponding bit should be cleared by firmware. when the ht82k94e/HT82K94A receives a usb suspend signal from the host pc, the suspend line (bit0 of the usc) of the ht82k94e/HT82K94A is set and a usb interrupt is also triggered. also when the ht82k94e/HT82K94A receives a re - sume signal from the host pc, the resume line (bit3 of the usc ) of ht82k94e/HT82K94A is set and a usb in - terrupt is triggered. whenever a usb reset signal is detected, the usb in - terrupt is triggered. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (; bit 5 of intc), caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be re - set and the emi bit cleared to disable further interrupts. the internal timer/even counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (;bit 6 of intc), caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and the t1f is set, a subroutine call to location 0ch will occur. the related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in- terrupt acknowledge signals are held until the reti in- struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an in- terrupt service, but ret will not. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eui controls the usb interrupt (1= enabled; 0= disabled) 2 et0i controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer/event counter 1 interrupt (1= enabled; 0= disabled) 4 usbf usb interrupt request flag (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) 6 t1f internal timer/event counter 1 request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc (0bh) register
ht82k94e/HT82K94A rev. 1.50 11 october 11, 2007 interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector usb interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch once the interrupt request flags (tf, usbf) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. interrupts of - ten occur in an unpredictable manner or need to be ser - viced immediately in some applications. if only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the call operates in the interrupt subroutine. oscillator configuration there is an oscillator circuits in the microcontroller. this oscillator is designed for system clocks. the halt mode stops the system oscillator and ignores an exter - nal signal to conserve power. a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. in stead of a crystal, a resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works within a period of approximately 31 s. the wdt oscillator can be disabled by rom code option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator), or instruction clock (sys - tem clock divided by 4), determines the rom code op - tion. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by rom code option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator, nor - mally with a period of 31 s/5v) is selected, it is first di - vided by 256 (8-stage) to get the nominal time-out period of 8ms/5v. this time-out period may vary with temperatures, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be real- ized. writing data to ws2, ws1, ws0 (bits 2, 1, 0 of the wdts) can give different time-out periods. if ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5v. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operates in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. the high nibble and bit 3 of the wdts are re - served for user s defined flags, which can only be set to 10000 (wdts.7~wdts.3). ! ( 2 < ) * 6 0 = ( + ( ! 2 - 0 = ( 6 0 0 (
+ ( 0 + 3 +
" 2 + watchdog timer ! 2 ( ! 2 2 system oscillator
ht82k94e/HT82K94A rev. 1.50 12 october 11, 2007 if the device operates in a noisy environment, using the on-chip 32khz rc oscillator (wdt osc) is strongly rec - ommended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register the wdt overflow under normal operation will initialize a chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset and only the program counter and sp are reset to zero. to clear the contents of the wdt (including the wdt prescaler), three methods are employed; external reset (a low level to res ), software instruction and a halt instruction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depending on the rom code option clr wdt times selection option .ifthe clr wdt is se- lected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in the case wherein clr wdt1 and clr wdt2 are cho- sen (i.e. clrwdt times is equal to two), these two in- structions must be executed to clear the wdt, otherwise, the wdt may reset the chip as a result of time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following: the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se - lected). the contents of the on-chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and re - counted again (if the wdt clock is from the wdt os - cillator). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on i/o ports or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . after the to and pdf flags are examined, the cause for chip reset can be determined. the pdf flag is cleared by a system power-up or exe - cuting the clr wdt instruction and is set when exe - cuting the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the oth - ers remain in their original status. the i/o ports wake-up and interrupt methods can be considered as a continuation of normal execution. each bit in the port a can be independently selected to wake-up the device by option. pb, pc and pd can also be selected to wake-up the device by option. upon awakening from an i/o port stimulus, the program will resume execution of the next instruction. if it awakens from an interrupt, two sequence may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related inter - rupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period will be in - serted after a wake-up. if the wake-up results from an in - terrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cy - cles. if the wake-up results in the next instruction execu- tion, this will be executed immediately after the dummy period is completed. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and sp, leav - ing the other circuits in their original state. some regis - ters remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 0 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged
ht82k94e/HT82K94A rev. 1.50 13 october 11, 2007 to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses when the sys - tem resets (power-up, wdt time-out or res reset) or when the system awakes from the halt state. when a system reset occurs, an sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack + ( ! + > # 2 " ! ! ( ! 0 = ( 2 reset configuration the status of the registers are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tmr0 xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 tmr1h xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- program counter 000h 000h 000h 000h 000h 000h 000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 wdts 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111 pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 reset circuit ( 0 $ ( ( ! reset timing chart
ht82k94e/HT82K94A rev. 1.50 14 october 11, 2007 register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pe 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pec 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pipe_ctrl 0000 1111 uuuu uuuu 0000 1111 0000 1111 uuuu uuuu 0000 1111 0000 1111 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pipe 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall 0000 1111 uuuu uuuu 0000 1111 0000 1111 uuuu uuuu 0000 1111 0000 1111 sies 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 misc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 endpt_en 0000 1111 uuuu uuuu 0000 1111 0000 1111 uuuu uuuu 0000 1111 0000 1111 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 usc 11xx 0000 11xx uuuu 11xx 0000 11xx 0000 uuxx uuuu uu00 0u00 uu00 0u00 usr 0000 0000 uuuu uuuu 0100 0000 0100 0000 uuuu uuuu u1uu 0000 u1uu 0000 scc 0000 0010 uuuu uuuu 0000 0010 0000 0010 uuuu uuuu 0uu0 u000 0uu0 u000 note: * stands for warm reset u stands for unchanged x stands for unknown bit no. label function 0~2, 5 unused bit, read as 0 3te to define the tmr0 active edge of timer/event counter 0 (0=active on low to high; 1=active on high to low) 4 ton to enable/disable timer 0 counting (0=disabled; 1=enabled) 6 7 tm0 tm1 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register timer/event counter two timer/event counters (tmr0, tmr1) are imple - mented in the microcontroller. the timer/event counter 0 contains an 8-bit programmable count-up counter and the clock may comes from an external source or from f sys /4. the timer/event counter 1 contains an 16-bit program - mable count-up counter and the clock may come from an external source or from the system clock divided by 4.
ht82k94e/HT82K94A rev. 1.50 15 october 11, 2007 bit no. label function 0~2, 5 unused bit, read as 0 3te to define the tmr1 active edge of timer/event counter 1 (0=active on low to high; 1=active on high to low) 4 ton to enable/disable timer 1 counting (0=disabled; 1=enabled) 6 7 tm0 tm1 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register

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# : # a ( , , % % timer/event counter 1 using the internal clock source, there is only 1 reference time-base for timer/event counter 0. the internal clock source is coming from f sys /4. the external clock input allows the user to count exter - nal events, measure time intervals or pulse widths. using the internal clock source, there is only 1 reference time-base for timer/event counter 1. the internal clock source is coming from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths. there are 2 registers related to the timer/event counter 0; tmr0 ([0dh]), tmr0c ([0eh]). two physical regis - ters are mapped to tmr0 location; writing tmr0 makes the starting value be placed in the timer/event counter 0 preload register and reading tmr0 gets the contents of the timer/event counter 0. the tmr0c is a timer/event counter control register, which defines some options. there are 3 registers related to timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). writing tmr1l will only put the written data to an internal lower-order byte buffer (8 bits) and writing tmr1h will transfer the specified data and the contents of the lower-order byte buffer to tmr1h and tmr1l preload registers, respectively. the timer/event counter 1 preload register is changed by each writing tmr1h op - erations. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr1l will read the contents of the lower-order byte buffer. the tmr1c is the timer/event counter 1 control register, which defines the operating mode, counting en - able or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external
ht82k94e/HT82K94A rev. 1.50 16 october 11, 2007 (tmr0/tmr1) pin. the timer mode functions as a nor - mal timer with the clock source coming from the f sys /4 (timer0/timer1). the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0/tmr1). the counting is based on the f sys /4 (timer0/timer1). in the event count or timer mode, once the timer/event counter 0/1 starts counting, it will count from the current contents in the timer/event counter 0/1 to ffh or ffffh. once overflow occurs, the counter is reloaded from the timer/event counter 0/1 preload register and generates the interrupt request flag (t0f/t1f; bit 5/6 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr0/tmr1 has re - ceived a transient from low to high (or high to low if the te bits is 0 ) it will start counting until the tmr0/tmr1 returns to the original level and resets the ton. the measured result will remain in the timer/event counter 0/1 even if the activated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it receives further transient pulse. note that, in this operating mode, the timer/event counter 0/1 starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter 0/1 is reloaded from the timer/event counter 0/1 preload register and issues the interrupt request just like the other two modes. to en- able the counting operation, the timer on bit (ton; bit 4 of tmr0c/tmr1c) should be set to 1. in the pulse width measurement mode, the ton will be cleared automati- cally after the measurement cycle is completed. but in the other two modes the ton can only be reset by in- structions. the overflow of the timer/event counter 0/1 is one of the wake-up sources. no matter what the oper - ation mode is, writing a 0 to et0i/et1i can disable the corresponding interrupt services. in the case of timer/event counter 0/1 off condition, writing data to the timer/event counter 0/1 preload regis - ter will also reload that data to the timer/event counter 0/1. but if the timer/event counter 0/1 is turned on, data written to it will only be kept in the timer/event counter 0/1 preload register. the timer/event counter 0/1 will still operate until overflow occurs (a timer/event counter 0/1 reloading will occur at the same time). when the timer/event counter 0/1 (reading tmr0/tmr1) is read, the clock will be blocked to avoid errors. as clock blocking may results in a counting error, this must be taken into consideration by the programmer. input/output ports there are 40 bidirectional input/output lines in the microcontroller, labeled from pa to pe, which are mapped to the data memory of [12h], [14h], [16h], [18h] and [1ah] respectively. all of these i/o ports can be used for input and output operations. for input oper - ation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instru ction mov a,[m] (m=12h, 14h, 16h, 18h or 1ah). for output op - eration, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pec) to control the input/output configura- tion. with this control register, cmos/nmos/pmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically un- der software control. to function as an input, the corre- sponding latch of the control register must write a 1 . the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possi - ble in the read-modify-write instruction. for output function, cmos is the only except port a which can be 3 4 d ( * )
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ht82k94e/HT82K94A rev. 1.50 17 october 11, 2007 optioned as cmos/nmos/pmos configurations. these control registers are mapped to locations 13h, 15h, 17h and 19h. after a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high op - tions). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h or 18h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of all the i/o ports have the capability of wak - ing up the device. there are pull-high options available for i/o lines. once the pull-high option of an i/o line is selected, the i/o line have pull-high resistor. otherwise, the pull-high resistor is absent. it should be noted that a non-pull-high i/o line operating in input mode will cause a floating state. it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. low voltage reset/detector lvr/lvd the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the bat- tery, the lvr will automatically reset the device inter- nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage i.e. a voltage in the range between 0.9v~v lvr must exist for greater than 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera - tion at 4mhz system clock. there is a low voltage detector (lvd) and a low voltage reset circuit (lvr) implemented in the microcontrollers. where lvr function can be enabled/disabled by op - tions. user can read the lvd detector status (0/1) from misc.5. the lvr has the same effect or function with the external res signal which performs a chip reset. both lvr and lvd functions will disable in the halt mode. there are two kind of lvr/lvd definition: 2-battery or 3-battery option. when 2-battery option is selected: lvr=2.2v; lvd=2.4v. otherwise, 3-battery option is selected: lvr=2.4v; lvd=2.6v. 5 . 5 . 3 . * . 3 . . 7 # 5 . 5 5 . 5 # . 7 ! ( 2 ! g g 2 ( ! # ( ( 2 low voltage reset note: *1. to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2. since low voltage has to be maintained for over 1ms in its original state, therefore there s a 1ms delay before entering the reset mode
ht82k94e/HT82K94A rev. 1.50 18 october 11, 2007 suspend wake-up and remote wake-up if there is no signal on the usb bus for over 3ms, the ht82k94e/HT82K94A will go into suspend mode. the suspend line (bit 0 of the usc) will be set to 1 and a usb interrupt is triggered to indicate that the ht82k94e/HT82K94A should jump to the suspend state to meet the 500 a usb suspend current spec. in order to meet the 500 a suspend current, the firm - ware should disable the usb clock by clearing the usbcken (bit3 of the scc) to 0 . the suspend cur - rent is 400 a. when the resume signal is sent out by the host, the ht82k94e/HT82K94A will wake-up the mcu by usb in - terrupt and the resume line (bit 3 of the usc) is set. in order to make the ht82k94e/HT82K94A function prop - erly, the firmware must set the usbcken (bit 3 of the scc) to 1 . since the resume signal will be cleared before the idle signal is sent out by the host, the sus - pend line (bit 0 of the usc) will be set to 0 . so when the mcu is detecting the suspend line (bit0 of usc), the resume line should be remembered and taken into con - sideration. after finishing the resume signal, the suspend line will go inactive and a usb interrupt is triggered. the follow - ing is the timing diagram. the device with remote wake-up function can wake-up the usb host by sending a wake-up pulse through rmwk (bit 1 of the usc). once the usb host receives a wake-up signal from the ht82k94e/HT82K94A, it will send a re - sume signal to the device. the timing is as follows: configuring the device as a ps2 device the ht82k94e/HT82K94A can be configured as a usb interface or ps2 interface device, by configuring the sps2 (bit 4 of usr) and susb (bit 5 of the usr). if sps2=1, and susb=0, the ht82k94e/HT82K94A is configured as a ps2 interface, pin usbd- is configured as a ps2 data pin and usbd+ is configured as a ps2 clk pin. user can easily read or write to the ps2 data or ps2 clk pin by accessing the corresponding bit ps2dai (bit 4 of the usc), ps2cki (bit 5 of the usc), ps2dao (bit 6 of the usc) and s2cko (bit 7 of the usc) respectively. user should make sure that in order to read the data properly, the corresponding output bit must be set to 1 . for example, if it is desired to read the ps2 data by reading ps2dai, the ps2dao should set to 1 . other- wise it is always read as 0 . if sps2=0, and susb=1, the ht82k94e/HT82K94A is configured as a usb interface. both the usbd- and usbd+ is driven by the sie of the ht82k94e/ HT82K94A. user can only write or read the usb data through the corresponding fifo. both sps2 and susb default is 0 . , ( ! ( 2 , e , ( ! ( 2 , e
+
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. ( ( , ( # usb interface there are eleven registers, including pipe_ctrl (41h in bank 1), awr (address + remote wake-up 42h in bank 1), stall (43h in bank 1), pipe (44h in bank 1), sies (45h in bank 1), misc (46h in bank 1), endpt_en (47h in bank 1), fifo0 (48h in bank 1), fifo1 (49h in bank 1), fifo2 (4ah in bank 1) and fifo3 (4bh in bank 1) used for the usb function. awr register contains current address and a remote wake up function control bit. the initial value of awr is 00h . the address value extracted from the usb command is not to be loaded into this register until the setup stage is completed. bit no. label r/w function 0 wken w remote wake-up enable/disable 7~1 ad6~ad0 w usb device address awr (42h) register
ht82k94e/HT82K94A rev. 1.50 19 october 11, 2007 stall, pipe, pipe_ctrl and endpt_en registers pipe register represents whether the endpoint corresponding is accessed by host or not. after act_en signal being sent out, mcu can check which endpoint had been accessed. this register is set only after the time when host access the corresponding endpoint. stall register shows whether the endpoint corresponding works or not. as soon as the endpoint work improperly, the bit corresponding must be set. pipe_ctrl register is used for configuring in (bit=1) or out (bit=0)pipe. the default is define in pipe. where bit0 (data0) of the pipe_ctrl register is used to setting the data toggle of any endpoint (except endpoint0) using data toggles to the value data0. once the user want the any endpoint (except endpoint0) using data toggles to the value data0. the user can output a low pulse to this bit. the low pulse period must at least 10 instruction cycle. endpt_en register is used to enable or disable the corresponding endpoint (except endpoint 0) enable endpoint (bit=1) or disable endpoint (bit=0) the bitmaps are list as follows : register name r/w register address bit7~bit4 reserved bit 3 bit 2 bit 1 bit 0 default value pipe_ctrl r/w 01000001b pipe 3 pipe 2 pipe 1 pipe 0 00001111 stall r/w 01000011b pipe 3 pipe 2 pipe 1 pipe 0 00001111 pipe r 01000100b pipe 3 pipe 2 pipe 1 pipe 0 00000000 endpt_en r/w 01000001b pipe 3 pipe 2 pipe 1 pipe 0 00001111 pipe_ctrl (41h), stall (43h), pipe (44h) and endpt_en (47h) registers the sies register is used to indicate the present signal state which the sie receives and also defines whether the sie has to change the device address automatically. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 func. nmi eot crc _err nak in out f0_err adr_set r/w r/w r r/w r r r/w r/w r/w reg_ adr 01000101b sies (45h) register func. name r/w description adr_ set r/w this bit is used to configure the sie to automatically change the device address with the value of the address+remote_wakeup register (42h). when this bit is set to 1 by f/w, the sie will update the device address with the value of the address+remote_wakeup register (42h) after the pc host has successfully read the data from the device by the in operation. the sie will clear the bit after updat - ing the device address. otherwise, when this bit is cleared to 0 , the sie will update the device address immediately after an address is written to the address+re - mote_wakeup register (42h) default 0 f0_err r/w this bit is used to indicate that some errors have occurred when accessing the fifo0. this bit is set by sie and cleared by f/w. default 0 out r/w this bit is used to indicate that an out token (except for the out zero length) has been received. the f/w clear the bit after the out data has been read. this bit will also be cleared by the sie after the next valid setup token is received. default 0 in r this bit is used to indicate that the current signal the usb is receiving from the pc host is in token. nak r this bit is used to indicate that the sie is transmitting nak signal to the host in re - sponse to the pc host in or out token.
ht82k94e/HT82K94A rev. 1.50 20 october 11, 2007 func. name r/w description crc _err r/w this bit is used to indicate there are crc error (bit=1). firmware must do something to save the device and keep it in good condition. this bit is set by sie and cleared by f/w. eot r end of transaction flag, normal status is 1. if suspend= 1 line & eot = 0 indicates that something is wrong in the usb interface. firmware in-charge must do something to save the device and keep it in good condition. nmi r/w this bit is used to control whether the usb interrupt is output to the mcu in nak re - sponse to the pc host in or out token. 1: has only usb interrupt, data is transmitted to the pc host or data is received from the pc host 0: always has usb interrupt if the usb accesses fifo0 default 0 sies function misc register combines a command and status to control desired endpoint fifo action and to show the status of the desired endpoint fifo. the misc will be cleared by usb reset signal. bit no. label r/w function 0 req r/w after setting the other status of the desired one in the misc, endpoint fifo can be requested by setting this bit to 1 . after the job has been done, this bit has to be cleared to 0 . 1 tx r/w this bit defines the direction of data transferring between mcu and endpoint fifo. when the tx is set to 1 , this means that the mcu wants to write data to the end - point fifo. after the job has been done, this bit has to be cleared to 0 before termi - nating request to represent the end of transferring. for reading action, this bit has to be cleared to 0 to represent that mcu wants to read data from the endpoint fifo and has to be set to 1 after the job is done. 2 clear r/w clear the requested endpoint fifo, even if the endpoint fifo is not ready. 4 3 selp1 selp0 r/w defines which endpoint fifo is selected, selp1,selp0: 00: endpoint fifo0 01: endpoint fifo1 10: endpoint fifo2 11: endpoint fifo3 5 scmd r/w used to show that the data in endpoint fifo is a setup command. this bit has to be cleared by firmware. that is to say, even the mcu is busy, the device will not miss any setup commands from the host. 6 ready r read only status bit, this bit is used to indicate that the desired endpoint fifo is ready to work. 7 len0 r/w used to indicate that a 0-sized packet is sent from a host to the mcu. this bit should be cleared by firmware. misc (46h) register the mcu can communicate with the endpoint fifo by setting the corresponding registers, of which address is listed in the following table. after reading the current data, next data will show after 2 s, used to check the endpoint fifo status and response to misc register, if read/write action is still going on. registers r/w bank address bit7~bit0 fifo0 r/w 1 48h data7~data0 fifo1 r/w 1 49h data7~data0 fifo2 r/w 1 4ah data7~data0 fifo3 r/w 1 4bh data7~data0
ht82k94e/HT82K94A rev. 1.50 21 october 11, 2007 there are some timing constrains and usages illustrated here. by setting the misc register, mcu can perform reading, writing and clearing actions. there are some examples shown in the following table for endpoint fifo reading, writing and clearing. actions misc setting flow and status read fifo0 sequence 00h 01h delay 2 s, check 41h read* from fifo0 register and check not ready (01h) 03h 02h write fifo1 sequence 0ah 0bh delay 2 s, check 4bh write* to fifo1 register and check not ready (0bh) 09h 08h check whether fifo0 can be read or not 00h 01h delay 2 s, check 41h (ready) or 01h (not ready) 00h check whether fifo1 can be written or not 0ah 0bh delay 2 s, check 4bh (ready) or 0bh (not ready) 0ah read 0-sized packet sequence form fifo0 00h 01h delay 2 s, check 81h read once (01h) 03h 02h write 0-sized packet sequence to fifo1 0ah 0bh delay 2 s, check 0bh 0fh 0dh 08h note: *: there are 2 s existing between 2 reading action or between 2 writing action usb/ps2 status and control register the register is used to indicate there are usb suspend, usb resume and usb reset signal in usb bus. also user can output a high pulse in rmwk bit to wake-up the pc for usb remote function. bit no. label r/w function 0 susp r read only, usb suspend indication. when this bit is set to 1 (set by sie ), it indi - cates the usb bus enters suspend mode. the usb interrupt is also triggered on any changes of this bit. 1 rmwk w usb remote wake-up command. it is set by mcu to force the usb host leaving the suspend mode. when this bit is set to 1 ,2 s delay for clearing this bit to 0 is needed to insure the rmwk command is accepted by sie. 2 urst r/w usb reset indication. this bit is set/cleared by usb sie. this bit is used to detect which bus (ps2 or usb) is attached. when the urst is set to 1 , this indicates that a usb reset has occurred (the attached bus is usb) and a usb interrupt will be ini- tialized. 3 resume r usb resume indication. when the usb leaves the suspend mode, this bit is set to 1 (set by sie). this bit will appear 20ms waiting for the mcu to detect. when the resume is set by the sie, an interrupt will be generated to wake-up the mcu. in or - der to detect the suspend state, the mcu should set the usbcken and clear susp2 (in scc register) to enable the sie detecting function. the resume will be cleared while the susp is going 0 . when the mcu is detecting the susp, the re - sume (wakes-up the mcu ) should be remembered and taken into consideration. 4 ps2dai r read only, usbd-/data input 5 ps2cki r read only, usbd+/clk input 6 ps2dao w data for driving the usbd-/data pin (default= 1 ) 7 ps2cko w data for driving the usbd+/clk pin (default= 1 ) usc (1ch) register
ht82k94e/HT82K94A rev. 1.50 22 october 11, 2007 usb endpoint interrupt status register the register is used to indicate which endpoint is accessed or has external interrupt pa4/ext is activated and to select the serial bus (ps2 or usb). the endpoint request flags (ep0if, ep1if, ep2if, ep3if and extif ) are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request flag will be set to 1 and the usb interrupt will occur (if the usb interrupt is enabled and the stack is not full). when the active endpoint request flag is served, the endpoint request flag has to be cleared to 0 . where usb _flag bit is only a bit for firmware to store the usb-mode data. this bit only clear to zero after power-on reset. bit no. label r/w function 0 ep0if r/w when this bit is set to 1 (set by the sie), it indicates the endpoint 0 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 1 ep1if r/w when this bit is set to 1 (set by the sie), it indicates the endpoint 1 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 2 ep2if r/w when this bit is set to 1 (set by the sie), it indicates the endpoint 2 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 3 ep3if r/w when set to 1 , indicated endpoint 3 interrupt event . must wait mcu to process in - terrupt event, then clear this bit by firmware. this bit must be 0, then next interrupt event will be process. default value is 0. 4 sps2 r/w the ps2 function is selected when this bit is set to 1 . (default= 0 ) 5 susb r/w the usb function is selected when this bit is set to 1 . (default= 0 ) 6 undefined, should be cleared to 0 7 usb _flag r/w this flag is used to show the mcu is in usb mode. (bit=1) this bit is r/w by fw and will be cleared to 0 after power-on reset. (default= 0 ) usr (1dh) register system clock control register this register is designed to control the system clock and make the device to meet usb 500 a suspend current spec. as well as a lvd indicator. since the device can operate at 6mhz or 12mhz in usb mode, so in order to make sie work properly, there should has a sysclk bit to indicate what system frequency is working. the usbcken bit is used to turn-off or turn-on the sie system clock to meet the usb 500 a suspend current. for normal operation, this bit must be 1. otherwise, the sie cannot detect the usb signal. ps2_flag bit is only a bit for firmware to store the ps2 mode data. this bit only clear to zero by hardware after power-on reset. suspend2 bit is used to second suspend mode.
ht82k94e/HT82K94A rev. 1.50 23 october 11, 2007 bit no. label r/w function 0, 2 undefined, should be cleared to 0 1 osc_ctrl r/w 1: high driver of oscillator circuit for low voltage 0: normal driver of oscillator circuit 3 usbcken r/w usb clock control bit. when this bit is set to 1 , it indicates that the usb clock is en - abled. otherwise, the usb clock is turned-off. (default= 0 ) 4 suspend2 r/w this bit is used to reduce power consumption in the suspend mode. in the normal mode this bit must be cleared to zero(default= 0 ). in the halt mode this bit should be set high to reduce power consumption and lvr with no function. in the usb mode this bit cannot be set high. 5 ps2_flag r/w this flag is used to show the mcu is under ps2 mode. (bit=1) this bit is r/w by fw and will be cleared to 0 after power-on reset. (default= 0 ) 6 sysclk r/w this bit is used to specify the system oscillator frequency used by the mcu. if a 6mhz crystal oscillator or resonator is used, this bit should be set to 1 . if a 12mhz crystal oscillator or resonator is used, this bit should be cleared to 0 (default). 7 lvd r/w 1: battery voltage low 0: battery voltage high scc (1eh) register table high byte pointer for current table read tbhp (address 0x1f) register bits labels read/write option functions (0x1f) 4~0 pgc4~pgc0 r/w store current table read bit12~bit8 data options the following table shows all kinds of option in the microcontroller. all of the options must be defined to ensure proper system functioning. no. option 1 chip lock bit (by bit) 2 pa0~pa7 pull-high resistor enabled or disabled (by bit) 3 pb0~pb7 pull-high resistor enabled or disabled (by nibble) 4 pc0~pc7 pull-high resistor enabled or disabled (by nibble) 5 pd0~pd7 pull-high resistor enabled or disabled (by nibble) 6 pe0~pe7 pull-high resistor enabled or disabled (by nibble) 7 lvr enable or disable 8 wdt enable or disable 9 wdt clock source: f sys /4 or wdtosc 10 clrwdt instruction(s): 1 or 2 11 pa0~pa7 output structures: cmos/nmos open-drain/pmos open-drain (by bit) 12 pa0~pa7 wake-up enabled or disabled (by bit) 13 pb0~pb7 wake-up enabled or disabled (by nibble) 14 pc0~pc7 wake-up enabled or disabled (by nibble) 15 pd0~pd7 wake-up enabled or disabled (by nibble) 16 tbhp enable or disable (default disable) 17 lvr/lvd kind: 2-battery or 3-battery
application circuits crystal or ceramic resonator for multiple i/o applications note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res high. x1 can use 6mhz or 12mhz, x1 as close osc1 & osc2 as possible. components with * are used for emc issue. components with ** are used for resonator only. ht82k94e/HT82K94A rev. 1.50 24 october 11, 2007
, / ) # , 0 ) 1 1 . 5 < , 0 , / 1 1 1 1 3 - , 3 , - 3 - 3 - . 8 * - 8 g * - 8 g g g 5 . 8 g g * - 8 g * - 8 g . 8 < 8 1 1 g . 8 8 8 . 8 < 5 g g g g g g g 3 -
instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht82k94e/HT82K94A rev. 1.50 25 october 11, 2007
mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] (5) tabrdc [m] (6) tabrdl [m] read rom code (locate by tblp and tbhp) to data memory and tblh read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) 2 (1) none none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. (5) : rom code tbhp option is enabled (6) : rom code tbhp option is disabled ht82k94e/HT82K94A rev. 1.50 26 october 11, 2007
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 27 october 11, 2007
and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack program counter+1 program counter addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 28 october 11, 2007
clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 29 october 11, 2007
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 30 october 11, 2007
halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter program counter+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 31 october 11, 2007
mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation program counter program counter+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 32 october 11, 2007
ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 33 october 11, 2007
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 34 october 11, 2007
rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 35 october 11, 2007
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 36 october 11, 2007
sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 37 october 11, 2007
sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (locate by tblp and tbhp) to tblh and data memory (rom code tbhp is enabled) description the low byte of rom code addressed by the table pointer (tblp and tbhp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory (rom code tbhp is dis - abled) description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 38 october 11, 2007
tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op- eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c ht82k94e/HT82K94A rev. 1.50 39 october 11, 2007
package information 48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 ht82k94e/HT82K94A rev. 1.50 40 october 11, 2007 * 6 5 * , 8 h & >
product tape and reel specifications reel dimensions ssop 48w symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 100 0.1 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 ht82k94e/HT82K94A rev. 1.50 41 october 11, 2007 ,
carrier tape dimensions ssop 48w symbol description dimensions in mm w carrier tape width 32 0.3 p cavity pitch 16 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 12 0.1 b0 cavity width 16.2 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 ht82k94e/HT82K94A rev. 1.50 42 october 11, 2007 + 8 ,
ht82k94e/HT82K94A rev. 1.50 43 october 11, 2007 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 0755-8616-9908, 8616-9308 fax: 0755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 028-6653-6590 fax: 028-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holtek.com copyright 2007 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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