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1 block diagram features description 16-/14-/11-bit 2.5gsps dacs the lt c ? 2000 is a family of 16-/14-/11-bit 2.5 gsps cur- rent steering dacs with exceptional spectral purity. the single (1.25 gsps mode) or dual (2.5 gsps mode) port source synchronous lvds interface supports data rates of up to 1.25 gbps using a 625 mhz ddr data clock, which can be either in quadrature or in phase with the data. an internal synchronizer automatically aligns the data with the dac sample clock. additional features such as pattern generation, lvds loopout and junction temperature sensing simplify system development and testing. a serial peripheral interface ( spi) port allows configura - tion and read back of internal registers. operating from 1.8v and 3.3 v supplies, the ltc2000 consumes 2.2 w at 2.5gsps and 1.3w at 1.25gsps. a pplications n 80dbc sfdr at 70mhz f out n >68dbc sfdr from dc to 1000mhz f out n 40ma nominal full-scale, 1v output compliant n 10ma to 60ma adjustable full-scale current range n single or dual port ddr lvds and dhstl interface n low latency (7.5 cycles for single port, 11 cycles for dual port) n >78 dbc 2-tone imd from dc to 1000mhz f out n C165dbc/hz additive phase noise at 1mhz offset for 65mhz f out n 170-lead (9mm 15mm) bga package n broadband communication systems n docsis cmts n direct rf synthesis n radar n instrumentation n automatic test equipment l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 8330633. lvds receivers ddr data flip-flops 4:1 tstp/n pd cs sck sdi sdo sv dd 50 i outp i outn fsadj refio 50 10k 2000 bd ckp/n gnd dv dd33 dv dd18 av dd33 av dd18 gain adjust clock sync clk receiver delay adjust dckop/n dckip/n dbp/n[15:0] dap/n[15:0] clk divider 2 or 4 ref spi pattern generator junction temperature 16-bit dac f out (mhz) 0 50 sfdr (dbc) 60 70 80 90 100 200 400 600 800 2000 ta01b 1000 1200 digital amplitude = 0dbfs i outfs = 40ma sfdr vs f out , f dac = 2.5gsps ltc 2000 2000f for more information www.linear.com/ltc2000
2 t a b le o f c ontents features ..................................................... 1 applications ................................................ 1 block diagram .............................................. 1 description .................................................. 1 absolute maximum ratings .............................. 3 pin configuration .......................................... 3 order information .......................................... 4 electrical characteristics ................................. 5 t iming characteristics .................................... 8 t ypical performance characteristics ................... 9 pin functions .............................................. 16 block diagram ............................................. 17 t iming diagrams ......................................... 18 operation ................................................... 18 introduction ............................................................ 18 d ual-port mode ...................................................... 19 sin gle-port mode .................................................... 19 s erial peripheral interface (spi) ............................. 22 p ower-on reset ...................................................... 22 p ower down ........................................................... 22 r eference operation ............................................... 22 s etting the full-scale current ................................. 23 d ac transfer function ............................................ 24 a nalog outputs (i outp/n ) ........................................ 24 da c sample clock (ckp/n) .................................... 25 d ivided clock output (dckop/n) ............................ 25 l vds data clock input (dckip/n) .......................... 25 l vds data input ports (dap/n, dbp/n) ................. 26 c lock synchronizer ................................................. 27 m inimizing harmonic distortion ............................. 29 m easuring lvds input timing skew ....................... 29 m easuring internal junction temperature (t j ) ....... 32 pa ttern generator ................................................... 32 spi register summary ................................... 33 applications information ................................ 34 s ample start-up sequence ..................................... 34 o utput configurations ........................................... 35 g enerating the dac sample clock .......................... 35 s ynchronizing multiple ltc2000s in dual-port mode ...................................................................... 36 s ynchronizing multiple ltc2000s in single-port mode ...................................................................... 38 p cb layout considerations .................................... 40 pin locations (l tc2000-16) ............................. 45 pin locations (l tc2000-14) ............................. 47 pin locations (l tc2000-11) ............................. 49 package description ..................................... 51 t ypical application ....................................... 52 related parts .............................................. 52 ltc 2000 2000f for more information www.linear.com/ltc2000
3 p in c on f iguration ab solute m aximum r atings av dd 33 , dv dd 33 , sv dd ................................. C0. 3 v to 4v av dd 18 , dv dd 18 ............................................ C0.3 v to 2v i outp , i outn ................. C1.2 v to min ( av dd 33 + 0.3 v, 4v) fsadj , refio ............ C 0.3 v to min ( av dd 33 + 0.3 v, 4v) dckip , dckin ............ C 0.3 v to min ( dv dd 33 + 0.3 v, 4v) dckop , dckon .......... C 0.3 v to min ( dv dd 33 + 0.3 v, 4v) dap /n, dbp /n ............ C 0.3 v to min ( dv dd 33 + 0.3 v, 4v) tstp , tstn ................ C 0.3 v to min ( av dd 33 + 0.3 v, 4v) (notes 1, 2) ltc2000-16 ltc2000-14 ltc2000-11 1 s r q p n m l k j h gnd gnd dv dd33 av dd33 gnd g f e d c b a 2 3 4 5 6 7 8 9 10 bga package 170-lead (9mm 15mm 1.54mm) top view av dd18 dv dd18 t jmax = 125c, e ja = 20c/w, e jb = 8c/w, e jctop = 9c/w, e jcbottom = 3c/w 1 s r q p n m l k j h dv dd33 av dd18 gnd gnd gnd g f e d c b a 2 3 4 5 6 7 8 9 10 bga package 170-lead (9mm 15mm 1.54mm) top view av dd33 dv dd18 t jmax = 125c, e ja = 20c/w, e jb = 8c/w, e jctop = 9c/w, e jcbottom = 3c/w 1 s r q p n m l k j h gnd gnd dv dd33 av dd18 gnd g f e d c b a 2 3 4 5 6 7 8 9 10 bga package 170-lead (9mm 15mm 1.54mm) top view av dd33 dv dd18 t jmax = 125c, e ja = 20c/w, e jb = 8c/w, e jctop = 9c/w, e jcbottom = 3c/w ckp , ckn ................... C 0.3 v to min ( av dd 18 + 0.3 v, 2v) cs , pd , sck , sdi , sdo ... C 0.3 v to min ( sv dd + 0.3 v , 4 v) operating temperature range ltc 2 000 c ................................................ 0 c to 70 c ltc 2 000 i ............................................. C 40 c to 85 c maximum junction temperature .......................... 12 5 c storage temperature range .................. C 55 c to 125 c lead temperature ( soldering , 10 sec ) ................... 26 0 c ltc 2000 2000f for more information www.linear.com/ltc2000
4 o r d er i n f ormation ltc2000 c y C16 #pbf lead free designator pbf = lead free resolution 16 = 16-bit resolution 14 = 14-bit resolution 11 = 11-bit resolution p ackage t ype 170-lead (15mm 9mm 1.54mm) bga temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) product part number part number ball finish part marking* package type msl rating temperature range ltc2000cy-16#pbf sac305 (rohs) ltc2000y-16 bga 3 0c to 70c ltc2000cy-14#pbf sac305 (rohs) ltc2000y-14 bga 3 0c to 70c ltc2000cy-11#pbf sac305 (rohs) ltc2000y-11 bga 3 0c to 70c ltc2000iy-16#pbf sac305 (rohs) ltc2000y-16 bga 3 C40c to 85c ltc2000iy-14#pbf sac305 (rohs) ltc2000y-14 bga 3 C40c to 85c ltc2000iy-11#pbf sac305 (rohs) ltc2000y-11 bga 3 C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ ltc 2000 2000f for more information www.linear.com/ltc2000
5 e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. av dd18 , dv dd18 = 1.71v to 1.89v, av dd33 , dv dd33 = 3.135v to 3.465v, sv dd = 1.71v to 3.465v, r fsadj = 500, 12.5 load from i outp/n to gnd including internal 50 termination, unless otherwise specified. symbol parameter conditions min typ max units dc performance resolution ltc2000-16 l 16 bits ltc2000-14 l 14 bits ltc2000-11 l 11 bits dnl differential nonlinearity ltc2000-16 l 0.5 2.7 lsb ltc2000-14 l 0.2 1 lsb ltc2000-11 l 0.1 0.5 lsb inl integral nonlinearity ltc2000-16 l 1 4 lsb ltc2000-14 l 0.5 2 lsb ltc2000-11 l 0.2 1 lsb offset error ltc2000-16 l 0.05 % fsr ltc2000-14 l 0.06 % fsr ltc2000-11 l 0.09 % fsr offset error drift 1 ppm/c gain error 0.5 % fsr gain error drift 5 ppm/c power supply rejection ratio full-scale; av dd33 = 3.135v to 3.465v 69 db analog output full-scale output current r fsadj = 500 40 ma output compliance range l C1 1 v output resistance i outp/n to gnd l 42 50 58 output capacitance 6 pf output bandwidth r ioutp/n = 12.5, C3db excluding sin(x)/x 2.1 ghz ac performance maximum update rate dual-port mode single-port mode l l 2.5 1.25 gsps gsps sfdr spurious free dynamic range f dac = 1.25gsps, 0dbfs f out = 50mhz, lin_dis = 0, lin_gn = 75% f out = 100mhz, lin_dis = 0, lin_gn = 75% f out = 250mhz, lin_dis = 0, lin_gn = 75% f out = 500mhz, lin_dis = 0, lin_gn = 75% 82 82 74 74 dbc dbc dbc dbc spurious free dynamic range f dac = 2.5gsps, 0dbfs f out = 100mhz, lin_dis = 0, lin_gn = 75% f out = 200mhz, lin_dis = 0, lin_gn = 75% f out = 500mhz, lin_dis = 0, lin_gn = 75% f out = 1000mhz, lin_dis = 0, lin_gn = 75% l 67 76 74 72 68 dbc dbc dbc dbc f out = 500mhz, lin_dis = 1 f out = 1000mhz, lin_dis = 1 66 62 dbc dbc imd 2-t one intermodulation distortion f out2 = f out1 + 1.25mhz f dac = 1.25gsps, C6dbfs f out = 50mhz, lin_dis = 0, lin_gn = 75% f out = 100mhz, lin_dis = 0, lin_gn = 75% f out = 250mhz, lin_dis = 0, lin_gn = 75% f out = 500mhz, lin_dis = 0, lin_gn = 75% 100 90 90 82 dbc dbc dbc dbc 2-t one intermodulation distortion f out2 = f out1 + 1.25mhz f dac = 2.5gsps, C6dbfs f out = 100mhz, lin_dis = 1 f out = 200mhz, lin_dis = 1 f out = 500mhz, lin_dis = 1 f out = 1000mhz, lin_dis = 1 87 86 84 78 dbc dbc dbc dbc f out = 500mhz, lin_dis = 0, lin_gn = 75% f out = 1000mhz, lin_dis = 0, lin_gn = 75% 80 67 dbc dbc ltc 2000 2000f for more information www.linear.com/ltc2000
6 e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. av dd18 , dv dd18 = 1.71v to 1.89v, av dd33 , dv dd33 = 3.135v to 3.465v, sv dd = 1.71v to 3.465v, r fsadj = 500, 12.5 load from i outp/n to gnd including internal 50 termination, unless otherwise specified. symbol parameter conditions min typ max units nsd noise spectral density 0dbfs single tone, f dac = 2.5gsps, i outfs = 40ma ltc2000-16, f out = 100mhz ltc2000-16, f out = 350mhz ltc2000-16, f out = 550mhz ltc2000-16, f out = 950mhz C166 C161 C158 C156 dbm/hz dbm/hz dbm/hz dbm/hz ltc2000-14, f out = 100mhz ltc2000-14, f out = 350mhz ltc2000-14, f out = 550mhz ltc2000-14, f out = 950mhz C164 C160 C158 C155 dbm/hz dbm/hz dbm/hz dbm/hz ltc2000-11, f out = 100mhz ltc2000-11, f out = 350mhz ltc2000-11, f out = 550mhz ltc2000-11, f out = 950mhz C156 C155 C154 C153 dbm/hz dbm/hz dbm/hz dbm/hz phase noise f dac = 2.5gsps, f out = 65mhz 0dbfs single tone, i outfs = 40ma 10khz offset 1mhz offset C147 C165 dbc /hz dbc/hz wcdma aclr wcdma aclr (single carrier) adjacent/alternate adjacent channel f dac = 2.5gsps, f out = 350mhz f dac = 2.5gsps, f out = 950mhz 77/79 72/75 dbc dbc latency latency (note 5) single-port mode dual-port mode, dap/n data dual-port mode, dbp/n data 7.5 10 11 cycles cycles cycles aperature delay ckp/n rising to i outp/n transition 3 ns settling time 2.2 ns reference output voltage l 1.225 1.25 1.275 v input voltage l 1.1 1.4 v reference temperature coefficient 25 ppm/c output impedance 10 k dac clock inputs (ckp, ckn) differential input voltage range l 0.3 1.8 v common-mode input voltage set internally 1 v sampling clock frequency l 50 2500 mhz input impedance 5 k lvds inputs (dckip, dckin, dap/n, dbp/n) differential input voltage range l 0.2 0.6 v common-mode voltage range l 0.4 1.8 v differential input impedance l 95 120 145 maximum data rate l 1250 mbps lvds clock frequency l 25 625 mhz ltc 2000 2000f for more information www.linear.com/ltc2000
7 e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. av dd18 , dv dd18 = 1.71v to 1.89v, av dd33 , dv dd33 = 3.135v to 3.465v, sv dd = 1.71v to 3.465v, r fsadj = 500, 12.5 load from i outp/n to gnd including internal 50 termination, unless otherwise specified. symbol parameter conditions min typ max units lvds output (dckop, dckon) differential output voltage 100 differential load, dcko_isel = 0 50 differential load, dcko_isel = 1 l l 0.24 0.24 0.36 0.36 0.48 0.48 v v common -mode output v oltage l 1.075 1.2 1.325 v internal termination resistance dcko_trm = 1 100 cmos digital inputs (cs, pd, sck, sdi) v ih digital input high voltage l 70 %v svdd v il digital input low voltage l 30 %v svdd i lk digital input leakage v in = gnd or sv dd l 10 a c in digital input capacitance 8 pf cmos digital output (sdo) v oh digital output high voltage i source = 0.2ma l 85 %v svdd v ol digital output low voltage i sink = 1.6ma l 15 %v svdd hi-z output leakage l 10 a hi-z output capacitance 8 pf power supply v vdd33 av dd33 , dv dd33 supply voltage l 3.135 3.3 3.465 v v vdd18 av dd18 , d vdd18 supply voltage l 1.71 1.8 1.89 v v svdd sv dd spi supply voltage l 1.71 3.465 v i avdd33 av dd33 supply current, av dd33 = 3.3v pd = sv dd pd = gnd l l 68 0.1 72 10 ma a i dvdd33 dv dd33 supply current, dv dd33 = 3.3v pd = sv dd pd = gnd l l 8 0.1 12 5 ma a i avdd18 av dd18 supply current, av dd18 = 1.8v f dac = 2500mhz f dac = 1250mhz f dac = 0hz, pd = sv dd f dac = 0hz, pd = gnd l l l l 720 375 23 3 790 420 27 180 ma ma ma a i dvdd18 dv dd18 supply current, dv dd18 = 1.8v f dac = 2500mhz f dac = 1250mhz f dac = 0hz, pd = sv dd f dac = 0hz, pd = gnd l l l l 350 190 10 0.1 395 215 14 240 ma ma ma a i svdd sv dd supply current (note 4), sv dd = 3.3v f sck = 0hz l 0.1 5 a total power dissipation f dac = 2500mhz f dac = 1250mhz f dac = 0hz, pd = sv dd f dac = 0hz, pd = gnd 2180 1270 310 6 mw mw mw w ltc 2000 2000f for more information www.linear.com/ltc2000
8 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. av dd18 , dv dd18 = 1.71v to 1.89v, av dd33 , dv dd33 = 3.135v to 3.465v, sv dd = 1.71v to 3.465v, r fsadj = 500, output load 50 double terminated, unless otherwise specified. t iming c haracteristics symbol parameter conditions min typ max units t 1 sdi valid to sck setup (note 3) l 4 ns t 2 sdi valid to sck hold (note 3) l 4 ns t 3 sck high time (note 3) l 9 ns t 4 sck low time (note 3) l 9 ns t 5 cs pulse width (note 3) l 10 ns t 6 sck high to cs high (note 3) l 7 ns t 7 cs low to sck high (note 3) l 7 ns t 10 cs high to sck high (note 3) l 7 ns t 13 sck low to sdo valid unloaded (note 3) l 10 ns sck frequency 50% duty cycle (note 3) l 50 mhz t 11 lvds dap/n, dbp/n to dcki setup time (note 3) dcki_q = 1 dcki_q = 0, dcki_tadj = 000 l l 200 600 ps ps t 12 lvds dap/n, dbp/n to dcki hold time (note 3) dcki_q = 1 dcki_q = 0, dcki_tadj = 000 l l 200 C200 ps ps note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: guaranteed by design and not production tested. note 4: digital inputs at 0v or sv dd . note 5: latency is the delay from a transition on dckip/n until the ckp/n transition which causes the sample on dap/n or dbp/n to appear at the dac output i outp/n , as measured in dac sample clock (ckp/n) cycles. ltc 2000 2000f for more information www.linear.com/ltc2000
9 t ypical p er f ormance c haracteristics dnl vs i outfs and temperature offset error vs temperature gain error vs temperature reference output voltage vs temperature supply current vs f dac shutdown current vs temperature ltc2000-16 integral nonlinearity (inl) ltc2000-16 differential nonlinearity (dnl) inl vs i outfs and temperature i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, unless otherwise noted. code ?32768 inl (lsb) 0 2 32768 2000 g01 ?2 ?4 ?16384 0 16384 4 code ?32768 dnl (lsb) 0 1 32768 2000 g02 ?1 ?2 ?16384 0 16384 2 temperature (c) ?50 ?6 inl (lsb) ?4 ?2 0 2 6 ?25 0 25 50 2000 g03 75 100 4 inl (pos) inl (neg) 10ma 20ma 40ma 60ma temperature (c) ?50 ?6 dnl (lsb) ?4 ?2 0 2 6 ?25 0 25 50 2000 g04 75 100 4 dnl (pos) dnl (neg) 10ma 20ma 40ma 60ma temperature (c) ?50 ?1.0 gain error (% fsr) ?0.5 0 0.5 1.0 ?25 0 25 50 2000 g06 75 100 temperature (c) ?50 1.240 v ref (v) 1.245 1.250 1.255 1.260 ?25 0 25 50 2000 g07 75 100 f dac (mhz) 0 i (ma) 300 400 500 1500 2500 2000 g08 200 100 0 500 1000 2000 600 700 800 dv dd33 av dd33 dv dd18 av dd18 temperature (c) ?50 ?0.06 offset error (%fsr) ?0.04 ?0.02 0 0.02 0.06 ?25 0 25 50 2000 g05 75 100 0.04 16 bit 14 bit 11 bit temperature (c) ?50 i (a) 15 2000 g09 5 ?5 0 50 ?25 25 75 25 35 10 0 20 30 100 dvdd18 avdd18 svdd avdd33 dvdd33 ltc 2000 2000f for more information www.linear.com/ltc2000
10 t ypical p er f ormance c haracteristics sfdr vs f out and temperature, f dac = 2.5gsps sfdr vs f out and digital amplitude (dbfs), f dac = 2.5gsps sfdr vs f out and i outfs , f dac = 2.5gsps hd2 vs f out and f dac hd3 vs f out and f dac single-tone spectrum at f out = 70mhz, f dac = 2.5gsps single-tone spectrum at f out = 990mhz, f dac = 2.5gsps sfdr vs f out and f dac i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, lin_dis = 0, lin_ gn = 75% unless otherwise noted. frequency (mhz) 20 ?90 10db/div ?80 ?60 ?50 ?40 1012 2004 2500 0 2000 g10 ?70 516 1508 ?30 ?20 ?10 rbw = 2khz, vbw = 5khz ref = 5dbm, atten = 25db sweep = 620s (1001 pts) f dac -f out image frequency (mhz) 20 ?90 10db/div ?80 ?60 ?50 ?40 1012 2004 2500 0 2000 g11 ?70 516 hd3 1508 ?30 ?20 ?10 rbw = 2khz vbw = 5khz ref = 5dbm atten = 25db sweep = 620s (1001 pts) f dac -f out image hd2 and hd3 in 2nd nyquist band f out (mhz) 0 50 sfdr (dbc) 60 70 80 90 100 200 400 600 800 2000 g12 1000 1200 2.5gsps 2.0gsps 1.6gsps 1.25gsps digital amplitude = 0dbfs f out (mhz) 0 50 sfdr (dbc) 60 70 80 90 100 200 400 600 800 2000 g13 1000 1200 90c 25c ?40c digital amplitude = 0dbfs f out (mhz) 0 50 sfdr (dbc) 60 70 80 90 100 200 400 600 800 2000 g14 1000 1200 0dbfs ?3dbfs ?6dbfs ?12dbfs ?16dbfs f out (mhz) 0 50 sfdr (dbc) 60 70 80 90 100 200 400 600 800 2000 g15 1000 1200 60ma 40ma 20ma 10ma f out (mhz) 0 50 hd2 (dbc) 60 70 80 90 100 200 400 600 800 2000 g16 1000 1200 2.5gsps 2.0gsps 1.6gsps 1.25gsps digital amplitude = 0dbfs f out (mhz) 0 50 hd3 (dbc) 60 70 80 90 100 200 400 600 800 2000 g17 1000 1200 2.5gsps 2.0gsps 1.6gsps 1.25gsps digital amplitude = 0dbfs hd2 vs f out and digital amplitude (dbfs), f dac = 2.5gsps f out (mhz) 0 50 hd2 (dbc) 60 70 80 90 100 200 400 600 800 2000 g18 1000 1200 0dbfs ?3dbfs ?6dbfs ?12dbfs ?16dbfs ltc 2000 2000f for more information www.linear.com/ltc2000
11 t ypical p er f ormance c haracteristics 2-tone imd vs f out and f dac 2-tone imd vs f out and digital amplitude, f dac = 2.5gsps sfdr vs f out and linearization setting, f dac = 2.5gsps ltc2000-16 single-tone nsd vs f out and f dac ltc2000-16 single-tone nsd vs f out and i outfs hd3 vs f out and linearization setting, f dac = 2.5gsps 2-tone imd vs f out and linearization setting, f dac = 2.5gsps hd3 vs f out and digital amplitude (dbfs), f dac = 2.5gsps 2-tone imd vs f out and f dac with default linearization i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, lin_dis = 0, lin_ gn = 75% unless otherwise noted. f out (mhz) 0 50 hd3 (dbc) 60 70 80 90 100 200 400 600 800 2000 g19 1000 1200 0dbfs ?3dbfs ?6dbfs ?12dbfs ?16dbfs f out (mhz) 0 60 imd (dbc) 70 80 90 100 110 200 400 600 800 2000 g22 1000 1200 2.5gsps 2.0gsps 1.6gsps 1.25gsps digital amplitude = ?6dbfs f2 = f1 + 1.25mhz lin_dis = 0 lin_gn = 75% f out (mhz) 0 50 hd3 (dbc) 60 70 80 90 100 200 400 600 800 2000 g25 1000 1200 lin_gn = 100% lin_gn = 75% lin_gn = 50% lin_dis = 1 digital amplitude = 0dbfs f out (mhz) 0 60 imd (dbc) 70 80 90 100 110 200 400 600 800 2000 g20 1000 1200 2.5gsps 2.0gsps 1.6gsps 1.25gsps digital amplitude = ?6dbfs f2 = f1 + 1.25mhz lin_dis = 1 f out (mhz) 0 60 imd (dbc) 70 80 90 100 110 200 400 600 800 2000 g21 1000 1200 0dbfs ?6dbfs ?12dbfs ?16dbfs f2 = f1 + 1.25mhz lin_dis = 1 f out (mhz) 0 ?170 nsd (dbm/hz) ?165 ?160 ?155 ?150 ?145 200 400 600 800 2000 g26 1000 1200 2.5gsps 1.25gsps digital amplitude = 0dbfs 40ma full-scale current 0dbm single-tone f out (mhz) 0 60 imd (dbc) 70 80 90 100 110 200 400 600 800 2000 g23 1000 1200 lin_gn = 100% lin_gn = 75% lin_gn = 50% lin_gn = 1% digital amplitude = ?6dbfs f2 = f1 + 1.25mhz f out (mhz) 0 ?170 nsd (dbm/hz) ?165 ?160 ?155 ?150 60ma 40ma 20ma ?145 200 400 600 800 2000 g27 1000 1200 digital amplitude = 0dbfs f dac = 2.5gsps 12.5 total output load f out (mhz) 0 50 sfdr (dbc) 60 70 80 90 100 200 400 600 800 2000 g24 1000 1200 lin_gn = 100% lin_gn = 75% lin_gn = 50% lin_dis = 1 digital amplitude = 0dbfs ltc 2000 2000f for more information www.linear.com/ltc2000
12 single carrier docsis mid band wideband aclr, f dac = 2.5gsps single carrier docsis mid band narrowband aclr, f dac = 2.5gsps single carrier docsis low band wideband aclr, f dac = 2.5gsps single carrier docsis low band narrowband aclr, f dac = 2.5gsps t ypical p er f ormance c haracteristics i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, lin_dis = 0, lin_ gn = 75% unless otherwise noted. frequency (mhz) 50 10db/div ?60 ?40 ?20 850 2000 g28 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 250 450 650 150 350 550 750 950 ?89.9dbm/6mhz ?87.3dbm/6mhz ?89.2dbm/6mhz ?11.2dbm/6mhz rbw = 20khz vbw = 2khz ref = ?20dbm atten = 5db sweep = 60s frequency (mhz) carrier power = ?11.16dbm, center freq = 200mhz 173 10db/div ?60 ?40 ?20 213 2000 g31 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 183 193 203 223 rbw = 30khz vbw = 3khz ref = ?20dbm atten = 5db sweep = 24s offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?100.31dbm ?96.02dbm ?96.47dbm ?96.40dbm ?96.40dbm upper ?94.84dbm ?94.67dbm ?95.48dbm ?96.29dbm ?96.57dbm frequency (mhz) 50 10db/div ?60 ?40 ?20 850 2000 g29 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 250 450 650 150 350 550 750 950 ?84.1dbm/6mhz ?11.7dbm/6mhz rbw = 20khz vbw = 2khz ref = ?20dbm atten = 5db sweep = 60s frequency (mhz) carrier power = ?11.66dbm, center freq = 550mhz 523 10db/div ?60 ?40 ?20 563 2000 g32 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 533 543 553 573 offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?95.63dbm ?93.01dbm ?94.66dbm ?95.19dbm ?94.97dbm upper ?93.62dbm ?92.97dbm ?94.51dbm ?94.87dbm ?95.15dbm rbw = 30khz vbw = 3khz ref = ?20dbm atten = 5db sweep = 24s single carrier docsis high band wideband aclr, f dac = 2.5gsps frequency (mhz) 50 10db/div ?60 ?40 ?20 850 2000 g30 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 250 450 650 150 350 550 750 950 ?89.2dbm/6mhz ?89.2dbm/6mhz rbw = 20khz vbw = 2khz ref = ?20dbm atten = 5db sweep = 60s ?89.4dbm/6mhz ?14dbm/6mhz single carrier docsis high band narrowband aclr, f dac = 2.5gsps frequency (mhz) carrier power = ?14.04dbm, center freq = 980mhz 953 10db/div ?60 ?40 ?20 993 2000 g33 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 963 973 983 1003 offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?89.47dbm ?87.24dbm ?93.04dbm ?93.52dbm ?93.33dbm upper ?89.52dbm ?87.00dbm ?92.94dbm ?92.51dbm ?92.03dbm rbw = 30khz vbw = 3khz ref = ?20dbm atten = 5db sweep = 24s ltc2000-16 ltc 2000 2000f for more information www.linear.com/ltc2000
13 32 carrier docsis mid band narrowband aclr, f dac = 2.5gsps 32 carrier docsis high band wideband aclr, f dac = 2.5gsps 32 carrier docsis high band narrowband aclr, f dac = 2.5gsps 32-carrier docsis low band wideband aclr, f dac = 2.5gsps 32-carrier docsis low band narrowband aclr, f dac = 2.5gsps 32-carrier docsis mid band wideband aclr, f dac = 2.5gsps frequency (mhz) 50 10db/div ?60 ?40 850 2000 g34 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 250 450 650 150 350 550 750 950 rbw = 20khz vbw = 2khz ref = ?30dbm atten = 5db sweep = 60s frequency (mhz) carrier power = ?28.64dbm, center freq = 386mhz 359 10db/div ?60 ?40 399 2000 g37 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 369 379 389 409 offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?39.32dbm ?29.01dbm ?28.68dbm ?28.54dbm ?28.49dbm upper ?103.86dbm ?95.18dbm ?94.68dbm ?94.97dbm ?95.08dbm rbw = 30khz vbw = 3khz ref = ?30dbm atten = 5db sweep = 24s frequency (mhz) 50 10db/div ?60 ?40 850 2000 g35 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 250 450 650 150 350 550 750 950 rbw = 20khz vbw = 2khz ref = ?30dbm atten = 5db sweep = 60s frequency (mhz) carrier power = ?28.42dbm, center freq = 500mhz 473 10db/div ?60 ?40 513 2000 g38 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 483 493 503 523 offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?102.49dbm ?94.71dbm ?94.02dbm ?94.36dbm ?93.72dbm upper ?39.23dbm ?28.92dbm ?28.69dbm ?28.71dbm ?28.74dbm rbw = 30khz vbw = 3khz ref = ?30dbm atten = 5db sweep = 24s frequency (mhz) 50 10db/div ?60 ?40 850 2000 g36 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 250 450 650 150 350 550 750 950 rbw = 20khz vbw = 2khz ref = ?30dbm atten = 5db sweep = 60s frequency (mhz) carrier power = ?29.31dbm, center freq = 800mhz 773 10db/div ?60 ?40 813 2000 g39 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 783 793 803 823 offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?98.23dbm ?90.00dbm ?89.76dbm ?89.72dbm ?89.76dbm upper ?40.42dbm ?29.56dbm ?29.20dbm ?29.25dbm ?29.55dbm rbw = 30khz vbw = 3khz ref = ?30dbm atten = 5db sweep = 24s t ypical p er f ormance c haracteristics i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, lin_dis = 0, lin_ gn = 75% unless otherwise noted. ltc2000-16 ltc 2000 2000f for more information www.linear.com/ltc2000
14 128 carrier docsis low band wideband aclr, f dac = 2.5gsps 157 carrier docsis gap channel wideband aclr, f dac = 2.5gsps 157 carrier docsis gap channel narrowband aclr, f dac = 2.5gsps 157 carrier tones with gap channel wideband aclr, f dac = 2.5gsps 157 carrier tones with gap channel narrowband aclr, f dac = 2.5gsps 128 carrier docsis low band narrowband aclr, f dac = 2.5gsps frequency (mhz) 50 10db/div ?60 ?40 850 2000 g40 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 250 450 650 150 350 550 750 950 rbw = 20khz, vbw = 2khz ref = ?30dbm, atten = 5db sweep = 60s frequency (mhz) carrier power = ?37.59dbm, center freq = 832mhz 805 10db/div ?60 ?40 845 2000 g43 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 815 825 835 855 offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?48.37dbm ?37.97dbm ?37.33dbm ?37.13dbm ?37.15dbm upper ?103.39dbm ?95.72dbm ?95.55dbm ?96.33dbm ?95.91dbm rbw = 30khz vbw = 3khz ref = ?30dbm atten = 5db sweep = 24s t ypical p er f ormance c haracteristics i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, lin_dis = 0, lin_ gn = 75% unless otherwise noted. ltc2000-16 frequency (mhz) 30 10db/div ?60 ?40 830 2000 g41 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 230 430 630 130 330 530 730 930 rbw = 20khz, vbw = 2khz ref = ?30dbm, atten = 5db sweep = 60s frequency (mhz) 30 10db/div ?60 ?40 830 2000 g42 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 230 430 630 130 330 530 730 930 rbw = 20khz, vbw = 2khz, ref = ?30dbm, atten = 5db, sweep = 60s, lin_dis = 1 frequency (mhz) gap channel power = ?96.45dbm, center freq = 508mhz 481 10db/div ?60 ?40 521 2000 g44 ?80 ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 491 501 511 531 offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz bw 750khz 5.25mhz 6mhz 6mhz 6mhz lower ?48.05dbm ?36.61dbm ?36.32dbm ?36.48dbm ?36.54dbm upper ?47.93dbm ?36.50dbm ?36.27dbm ?36.45dbm ?36.57dbm rbw = 30khz, vbw = 3khz ref = ?30dbm, atten = 5db sweep = 24s frequency (mhz) 510 ?130 10db/div ?120 ?100 ?90 ?80 ?30 ?60 515 520 2000 g45 ?110 ?50 ?40 ?70 525 rbw = 30khz, vbw = 3khz ref = ?30dbm, atten = 10db sweep = 24s, lin_dis = 1 ltc 2000 2000f for more information www.linear.com/ltc2000
15 t ypical p er f ormance c haracteristics i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, lin_dis = 0, lin_ gn = 75% unless otherwise noted. ltc2000-16 single carrier wcdma aclr vs f out , f dac = 2.5gsps ltc2000-16 single carrier wcdma aclr at 350mhz, f dac = 2.5gsps additive phase noise, f out = 65mhz, f dac = 2.5gsps ltc2000-14 differential nonlinearity (dnl) ltc2000-14 single-tone nsd vs f out and f dac ltc2000-14 integral nonlinearity (inl) f out (mhz) 0 ?90 aclr (dbc) ?80 ?70 ?60 ?50 200 400 600 800 2000 g46 1000 1200 adj channel 2nd adj channel 5th adj channel frequency (mhz) carrier power = ?17.06dbm, center freq = 350mhz 323 ?60 ?40 363 2000 g47 ?80 10db/hz ?100 ?70 ?50 ?30 ?90 ?110 ?120 ?130 333 343 353 373 offset freq 5.00mhz 10.00mhz 15.00mhz 20.00mhz 25.00mhz bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz 3.84mhz lower ?94.15dbm ?95.61dbm ?95.72dbm ?96.97dbm ?96.07dbm upper ?94.40dbm ?94.99dbm ?95.55dbm ?96.37dbm ?96.50dbm rbw = 30khz vbw = 3khz ref = ?20dbm atten = 5db sweep = 24s offset frequency (khz) ?160 phase noise (dbc/hz) ?150 ?130 ?110 ?100 0.01 1 10 1000 2000 g48 ?170 0.1 100 ?120 ?140 ?180 code ?8192 inl (lsb) 0 1 8192 2000 g49 ?1 ?2 ?4096 0 4096 2 f out (mhz) 0 ?170 nsd (dbm/hz) ?165 ?160 ?155 ?150 ?145 200 400 600 800 2000 g51 1000 1200 2.5gsps 1.25gsps digital amplitude = 0dbfs 40ma full-scale current 0dbm single tone code ?8192 dnl (lsb) 0 0.5 8192 2000 g50 ?0.5 ?1.0 ?4096 0 4096 1.0 ltc 2000 2000f for more information www.linear.com/ltc2000
16 p in functions av dd18 : 1.8 v analog supply voltage input. 1.71 v to 1.89 v. av dd33 : 3.3 v analog supply voltage input. 3.135 v to 3.465v. ckp, ckn: dac sample clock inputs. maximum clock frequency (f dac ) is 2500 mhz. clock signal should be ac coupled. cs: serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the register. when cs is taken high, sck is disabled and sdo is high impedance. dap[15:0], dan[15:0]: port a lvds data inputs. max- imum data rate is 1.25 gbps. port a is used only in dual - port mode. connect to gnd if not used. the data input format is twos complement. dbp[15:0], dbn[15:0]: port b lvds data inputs. max- imum data rate is 1.25 gbps. in single-port mode, only port b is used. in dual-port mode, the sample from port?b appears at i outp/n one cycle after the sample from port a. the data input format is twos complement. dckip, dckin : lvds data clock inputs. maximum frequency (f dcki ) is 625 mhz. in dual-port mode, f dcki = f dac /4. in single-port mode, f dcki = f dac /2 dckop, dckon: lvds data clock outputs. maximum frequency is 625 mhz. select frequency (f dac /4 or f dac /2), output current (3.5 ma or 7 ma), and termination ( none or 100) using register 0x02. dv dd18 : 1.8 v digital supply voltage input. 1.71 v to 1.89v. dv dd33 : 3.3 v digital supply voltage input. 3.135 v to 3.465v. fsadj: full-scale adjust pin. the dac full-scale current is 16 ? ( v refio /r fsadj ). connect a 500 resistor from fsadj to gnd to set the full-scale current to 40ma. gnd: ground. i outp , i outn : dac analog current outputs. differential output is nominally 40 ma. maximum update rate is 2.5gsps. the output current is evenly divided between i outp and i outn when the twos compliment dac code is set to mid-scale (all zeros). pd ( pin s1): active low power-down input. when pd is low, the ltc2000 supply current is less than 440a. to exit power-down mode switch pd high to sv dd . t ypical p er f ormance c haracteristics i outfs = 40ma, t a = 25c, av dd18 = dv dd18 = 1.8v, av dd33 = dv dd33 = 3.3v, r load = 12.5, lin_dis = 0, lin_ gn = 75% unless otherwise noted. ltc2000-11 differential nonlinearity (dnl) ltc2000-11 single-tone nsd vs f out and f dac ltc2000-11 integral nonlinearity (inl) code ?1024 inl (lsb) 0 0.5 1024 2000 g52 ?0.5 ?1.0 ?512 0 512 1.0 code ?1024 dnl (lsb) 0 0.25 1024 2000 g53 ?0.25 ?1.50 ?512 0 512 0.50 f out (mhz) 0 ?170 nsd (dbm/hz) ?165 ?160 ?155 ?150 ?145 200 400 600 800 2000 g54 1000 1200 2.5gsps 1.25gsps digital amplitude = 0dbfs 40ma full-scale current 0dbm single tone ltc 2000 2000f for more information www.linear.com/ltc2000
17 p in functions block diagram lvds receivers ddr data flip-flops 4:1 tstp/n pd cs sck sdi sdo sv dd 50 i outp i outn fsadj refio 50 10k 2000 bd ckp/n gnd dv dd33 dv dd18 av dd33 av dd18 gain adjust clock sync clk receiver delay adjust dckop/n dckip/n dbp/n[15:0] dap/n[15:0] clk divider 2 or 4 ref spi pattern generator junction temperature 16-bit dac refio: reference voltage input or output. the 1.25v internal reference is available at the pin through a 10k internal resistor. may be overdriven with an external refer - ence voltage between 1.1v and 1.4v. sck: serial interface clock input. maximum frequency is 50mhz. sdi: serial interface data input. data on sdi is clocked in on the rising edge of sck. sdo: serial interface data output. data is clocked out onto sdo by the falling edge of sck. sdo is high impedance when cs is high. sv dd : spi supply voltage input. 1.71v to 3.465v. tstp, tstn: test output pins. may be optionally used to measure internal temperature or timing of lvds inputs. see measuring internal junction temperature and mea - suring l vds input timing skew sections in applications information. use spi internal registers 0 x18 and 0 x19 to control tstp/n. connect to gnd if not used. note: for pin locations, refer to the pin locations section of this data sheet. ltc 2000 2000f for more information www.linear.com/ltc2000
18 o peration t iming diagrams sdi sdo cs sck t 2 t 13 t 10 t 5 hi-z hi-z t 7 t 6 t 1 t 3 t 4 1 2 3 15 16 2000 f01 dap/n, dbp/n t 12 dcki t 11 2000 f02 t 12 t 11 dap/n, dbp/n t 11 dcki t 12 2000 f03 t 11 t 12 figure 1. serial interface timing figure 2. lvds interface timing (dcki_q = 0, dck_tadj = 000) figure 3. lvds interface timing (dcki_q = 1) introduction the ltc2000 is a family of 2.5 gsps current steering dacs. three resolutions (16-, 14-, 11- bit) are available in a 170- lead bga package. the ltc2000 features high output bandwidth and output current, while maintaining a clean output spectrum with low spurs, making it ideal for generating high frequency or broadband signals. the ltc2000 output current is nominally 40 ma and is a scaled (16x) replica of the current flowing out of the fsadj pin (nominally 2.5 ma). the high output current allows flexibility in the output impedance, and the high fsadj current and low scaling factor give excellent close- in phase noise performance. the ltc2000 has two 16-, 14-, 11-bit wide lvds or dhstl- compatible parallel data input ports ( dap/n, dbp/n). each data input port is capable of receiving twos complement data at up to 1.25 gbps using a double data rate (ddr) data input clock ( dckip/n) at up to 625 mhz. the ddr data input clock may be either in quadrature or in phase with the data arriving on the data input ports. ltc 2000 2000f for more information www.linear.com/ltc2000
19 o peration note that the sample clock ( ckp/n) frequency is always four times the ddr data input clock ( dckip/n) frequency in dual - port mode. for example, to use the dac at 2.5 gsps , apply a 2.5 ghz clock to ckp/n and a 625 mhz clock to dckip/n and send data into both ports a and b (dap/n, dbp/n) at 1.25gsps per port. latency is defined as the delay from the dckip /n transition that samples a dac code to the ckp/n rising transition which causes that sample to appear at the dac output i outp/n . in dual-port mode the latency from dap/n to i outp/n is 10 sample clock cycles and the latency from dbp/n to i outp/n is 11 cycles, starting from the ckp/n rising edge that immediately follows the dckip/n transi- tion that sampled the dac code (figure 4b). single -port mode in single-port mode, data is written to port b ( dbp/n) only, allowing dac output sampling rates of up to 1.25gsps. figures 4 c and 4 d show a block diagram and sample waveforms representing single- port operation. samples are written to port b ( dbp/n) and sampled on both the falling and rising edges of the ddr data input clock ( dckip/n) by two groups of flip-flops. the contents of these flip-flops are then interleaved into a single data stream by the 2:1 mux and sampled by the dac sample clock ( ckp/n) at frequencies up to 1.25ghz. note that in single- port mode the sample clock ( ckp /n ) fre - quency is always twice the ddr data input clock ( dckip /n) frequency. for example, to use the dac at 1.25 gsps, apply a 1.25 ghz clock to ckp/n and a 625 mhz clock to dckip/n and send data into port b ( dbp/n) at 1.25 gsps. in single- port mode, port a ( dap/n) should be grounded. due to the design of the internal clock synchronizer in single port mode, there is a half cycle shift in the single port latency. the latency from dbp/n to i outp/n in single-port mode is 7.5 sample clock cycles, starting from the ckp/n falling edge that immediately follows the dckip/n transition that sampled the dac code (figure 4d). after incoming data is sampled by dckip/n, an internal multiplexer interleaves the data for resampling by the dac sample clock (ckp /n). see figures 4 a and 4 b. after a pipeline delay ( latency) of up to 11 dac sample clock cycles, the rising edges of ckp/n update the dac code and a proportional differential output current is steered between the two outputs (i outp/n ). note it takes about 3ns ( aperature delay) from the ckp/n rising edge that updates a dac code to the actual i outp/n transition for that dac code. an internal clock synchronizer monitors the incoming phase of dckip/n and chooses the appropriate phase for the multiplexer control signals to ensure that the data is sampled correctly by ckp/n. the ltc2000 also generates an lvds clock output ( dckop/n) by dividing the sample clock frequency to simplify clocking of the host fpga or asic. additional features such as pattern generation, lvds loopout, and junction temperature sensing simplify system development and testing. the serial peripheral interface ( spi) port allows configura - tion and read back of the internal registers which control the above functions. dual-port mode in dual-port mode, data is written to both ports a and b simultaneously and then subsequently interleaved inside the ltc2000, allowing dac output sampling rates of up to 2.5gsps . figures 4 a and 4 b show a simplified block diagram and sample waveforms for dual-port operation. the lvds data input ports a and b are sampled on both the falling and rising edges of the ddr data input clock (dckip/n) by four groups of flip-flops. the contents of these flip-flops are then interleaved by the 4:1 mux and sampled by the dac sample clock ( ckp/n) at frequencies up to 2.5 ghz, with data from port a ( dap/n) preceding data from port b (dbp/n) at the dac output. ltc 2000 2000f for more information www.linear.com/ltc2000
20 o peration 16-bit dac 4:1 mux n+3 n+2 n+1 n 50 i outp i outn 50 2000 f04a clock sync dbp/n[15:0] dap/n[15:0] dckip/n ckp/n dap/n[15:0] n n+2 n+4 n+6 n+8 n+10 dbp/n[15:0] dckip/n ckp/n i outp/n n+1 n+3 1 2 3 4 5 10 cycle latency 6 7 8 9 10 11 n n+1 2000 f04b n+5 n+7 n+9 n+11 11 cycle latency figure 4a. simplified block diagram C dual-port operation figure 4b. sample waveforms C dual-port operation ltc 2000 2000f for more information www.linear.com/ltc2000
21 o peration 16-bit dac 2:1 mux n+1 n 50 i outp i outn 50 2000 f04c clock sync dbp/n[15:0] dckip/n ckp/n dbp/n[15:0] dckip/n ckp/n i outp/n n n+1 0.5 1.5 7.5 cycle latency 2.5 3.5 4.5 5.5 6.5 7.5 n 2000 f04b n+2 n+3 n+4 n+5 n+6 n+6 n+7 figure 4c. simplified block diagram C single-port operation figure 4d. sample waveforms C single-port operation ltc 2000 2000f for more information www.linear.com/ltc2000
22 o peration r/w read/write register address command byte a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 data byte 2000 f05 figure 5. spi command and data input serial peripheral interface (spi) the ltc2000 uses an spi/ microwire- compatible 3-wire serial interface to configure and read back internal registers. the sv dd pin is the power supply for the spi interface (nominally 1.8 v or 3.3 v). the cs input is level triggered. when this input is taken low, it acts as a chip- select signal, enabling the sdi and sck buffers and the spi input register. after the falling edge of cs , the first data byte clocked into sdi by the rising edges of sck is the command byte. the first bit of the command byte signifies a read ( r/w = 1) or write (r/w = 0) operation. the next seven bits contain the register address, which completes the command byte. the next byte transferred after the command byte is the data byte. for write operations, the data byte is written to the spi register specified by the register address set in the command byte. during read operations, the data byte is ignored, and the contents of the selected spi register are clocked out onto the sdo pin by the falling edges of sck. during write operations, sdo will be low. when cs goes high, sdo is high impedance. figure 5 shows the spi command and data input. users wishing to transfer multiple bytes of data at once may do so, with the address for each subsequent byte automatically incremented internally. the address will continue to increment until cs goes high or until address bits a[4:0] reach 0 x1f, after which subsequent bytes will continue to be written to the same address. reserved address and bit locations should not be written with any value other than zero. table 11 contains a full description of all internal spi registers and can be found in the spi register summary section. power-on reset the internal power-on reset circuit will reset the ltc2000 upon power up and clear the output to mid-scale when power is first applied, making system initialization con- sistent and repeatable. all internal registers are reset to 0x00, with the exception of register address 0 x08, which resets to 0 x08. a software reset can also be applied by using the spi interface to load 0 x01 into register address 0x01, setting sw_rst to 1 ( see table 1). note that the sw_rst bit is automatically cleared when cs returns high. it is recommended that users perform a software reset once all power supplies are stable. power down users wishing to save power when the dac is not being used may reduce the supply current to less than 440 a by pulling the pd pin to gnd or by writing to register 0x01 to set full_pd = 1. alternatively, users may power down unused portions of the chip individually using dac_pd, ck_pd, dcko_dis, dcki_en, da_en, and db_en in registers 0x01, 0x02, 0x03, and 0x04 (see table 1). reference operation the ltc2000 has a 1.25 v internal bandgap voltage refer- ence that drives the refio pin through a 10 k internal resistor, and should be buffered if driving any additional external load. for noise performance, a 0.1 f capacitor to gnd is recommended on the refio pin, but is not required for stability. in the case where an external reference would be preferred, the external reference is simply applied to the refio pin and overdrives the internal reference. the acceptable external reference range is 1.1v to 1.4v. ltc 2000 2000f for more information www.linear.com/ltc2000
23 setting the full-scale current the full-scale dac output current (i outfs ) is nominally 40ma, but can be adjusted as low as 10 ma or as high as 60ma. the full-scale current is set by placing an external resistor (r fsadj ) between the fsadj pin and gnd. an internal reference control loop amplifier sets the current flowing through r fsadj such that the voltage at fsadj is equal to the voltage at refio, which is typically 1.25v. i outfs is set as a scaled replica of the current flowing out of the fsadj pin (i fsadj ): i fsadj = v refio r fsadj i outfs = 16 ? i fsadj ? 256 256 + gain_ adj where gain_ adj is a 6-bit two s complement number from C32 to 31 (nominally 0) which can be programmed using spi register 0 x09 as shown in table 2. for example, for r fsadj = 500, v refio = 1.25 v, and gain_adj = 0 x00, the control loop will force 1.25 v at the fsadj pin, causing 2.5ma to flow through r fsadj . i outfs will then be set to 16 ? 2.5ma = 40ma. o peration changing gain_adj to 0x1f (+31) will decrease the cur- rent by 10.8% to 35.7 ma. changing gain_adj to 0x20 (C32) will increase the current by 14.3% to 45.7ma. note that gain_adj appears in the denominator of the equation for i outfs , so the adjustment resolution varies from 0.5% to 0.3% per step. the circuit shown in figure 6 may be used to vary the full-scale output current beyond the range of the gain_adj register. dac linearity and harmonic distortion may be degraded when using full-scale currents other than 40 ma. the full- scale current must not exceed 60 ma, and is recommended to be at least 10ma. table 1. power-on reset and power-down spi registers address bit name description 0x01 0 sw_rst software reset. set sw_rst = 1 to restore all registers to their power-on reset state. sw_rst is automatically cleared when cs returns high. all registers reset to 0x00, except address 0x08 which resets to 0x08. 1 dac_pd dac power down. set dac_pd = 1 to power down the dac and fsadj bias circuits. 2 full_pd full power down. set full_pd = 1 to power down all active circuits on the chip and reduce the supply current to less than 100a. 0x02 0 ck_pd ckp/n clock receiver power down. ckp/n clock receiver is powered down when ck_pd = 1. 4 dcko_dis dckop/n output disable. set dcko_dis = 1 to power down the dcko lvds transmitter. for dcko_dis = 1, dckop/n are high impedance. 0x03 0 dcki_en dckip/n clock receiver enable. set dcki_en = 1 to enable the dcki clock receiver. 0x04 0 da_en dac data port a lvds receiver enable. set da_en = 1 to enable port a (dap/n) lvds receivers. for da_en = 0, port a lvds receivers are powered down and port a data will be zeroes. 1 db _en dac data port b lvds receiver enable. set db_en = 1 to enable port b (dbp/n) lvds receivers. for db_en = 0, port b lvds receivers are powered down and port b data will be zeroes. note: registers 0x01 to 0x04 reset to 0x00 (default). figure 6. ltc2000 full-scale adjust from 20ma to 60ma ? + ref ltc2000 refio 1.25v 10k 2000 f06 1k 500 0v to 2.5v ltc2630-lm12 fsadj ltc 2000 2000f for more information www.linear.com/ltc2000
24 o peration table 2. full-scale gain adjustment address bit name description 0x09 [5:0] gain_adj gain_adj (hex) gain_adj (decimal) gain adjustment full-scale current (r fsadj = 500, v refio = 1.25v) 0x1f +31 89.2% 35.68ma 0x1e +30 89.5% 35.80ma 0x01 +1 99.6% 39.84ma 0x00 0 100.0% 40.00ma 0x3f C1 100.4% 40.16ma 0x21 C31 113.8% 45.51ma 0x20 C32 114.3% 45.71ma note: register 0x09 resets to 0x00 (default). dac transfer function the ltc2000 contains an array of current sources that are steered through differential switches to either i outp or i outn , depending on the dac code programmed through the lvds parallel interface. the ltc2000 uses a 16 - /1 4 - /1 1 - bi t twos complement dac code. the complementary current outputs, i outp and i outn , source current from 0 ma to i outfs . for i outfs = 40ma ( nominal), i outp swings from 0ma ( for zero-scale dac code) to 40ma ( for full-scale dac code). i outn is complementary to i outp . when the dac code is set to mid-scale ( all zeros), i outfs is evenly divided between i outp and i outn . i outp and i outn are given by the following formulas: ltc2000-16: i outp = i outfs ? (code + 32768)/65536 + i outcm i outn = i outfs ? (32768 C code C 1)/65536 + i outcm ltc2000-14: i outp = i outfs ? (code + 8192)/16384 + i outcm i outn = i outfs ? (8192 C code C 1/4)/16384 + i outcm ltc2000-11: i outp = i outfs ? (code + 1024)/2048 + i outcm i outn = i outfs ? (1024 C code C 1/32)/2048 + i outcm the dac code ranges from C2 n-1 to 2 n-1 C 1, with n being the dac resolution (16/14/11). i outcm is a small, constant common-mode output current that is equal to approximately 0.2% full-scale, or 80 a for i outfs = 40ma. the ltc2000 differential output currents typically drive a resistive load either directly or drive an equivalent resistive load through a transformer ( see the output configurations section). the voltage outputs generated by the i outp and i outn outputs currents are then: v outp = i outp ? r load v outn = i outn ? r load v diff = v outp C v outn = (i outp -i outn ) ? r load substituting the values above gives: ltc2000-16: v diff = v refio ? ( r load /r fsadj ) ? (2 ? code + 1)/4096 ltc2000-14: v diff = v refio ? ( r load /r fsadj ) ? (2 ? code + 1/4)/1024 ltc2000-11: v diff = v refio ? ( r load /r fsadj ) ? (2 ? code + 1/32)/128 note that the gain of the dac depends on the ratio of r load to r fsadj , and the gain error tempco is affected by the temperature tracking of r load with r fsadj . analog outputs (i outp/n ) the two complementary analog outputs (i outp /n ) have low output capacitance that, with appropriate r load values, can achieve high output bandwidths of 2.1 ghz. the analog outputs also have an internal impedance of 50 to gnd that will affect the calculation of r load and the output ltc 2000 2000f for more information www.linear.com/ltc2000
25 o peration table 3. dac sample clock, and divided clock output spi registers address bit name description 0x02 0 ck_pd ckp/n clock receiver power down when ck_pd = 1 1 ck_ok ckp/n clock present indicator. when ck_ok = 1, clock is present at ckp/n pins and f dac > 50mhz. when ck_ok = 0, dac output is forced to mid-scale. ck_ok is read only. 4 dcko _dis dckop/n output disable. set dcko_dis = 1 to power down the dcko lvds transmitter. for dcko_dis = 1, dckop/n are high impedance. 5 dcko_div dckop/n divide select. when dcko_div = 0, f dckop/n = f dac /4. when dcko_div = 1, fdckop/n = f dac /2. 6 dcko_isel dckop/n output current select. when dcko_isel = 0, output current is 3.5ma. when dcko_isel = 1, output current is 7ma. 7 dcko_trm dckop/n internal termination on. when dcko_trm = 0, there is no internal termination at dckop/n. when dcko_trm = 1, there is 100 between dckop and dckon. note: register 0x02 resets to 0x00 (default). voltage swing of the dac. for example, loading both i outp and i outn with external 50 resistors to gnd will cause r load to equal 25. assuming an i outfs of 40 ma, v diff will swing between 1v and C1v. the specified output compliance voltage range is 1v. above 1 v, the differential current steering switches will start to approach the transition from saturation to linear region and degrade dac linearity. below C1 v protection diodes will limit the swing of the dac. small voltage swings and low common-mode voltages typically result in the best distortion performance. dac sample clock (ckp/n) the dac sample clock ( ckp/n) is used to update the ltc2000 outputs at rates of up to 2.5 gsps. provide a clean, low jitter differential clock at up to 2.5 ghz on pins ckp/n ( see generating the dac sample clock section). the dc bias point of ckp/n is set internally through a 5k impedance. a 0 dbm dac sample clock should be sufficient to obtain the performance shown in the typical performance characteristics section. for best jitter and phase noise, ac couple a differential clock onto ckp /n with balanced duty cycle and the highest possible amplitude and slew rate. use spi register 0 x02 to control the dac sample clock receiver (table 3). the ltc2000 contains a clock detector which sets ck_ok = 1 if the dac sample clock is present and f dac > 50 mhz. when the sample clock is not present (ck_ok = 0), the dac output is forced to mid-scale and the internal data path is held at reset. set ck_pd = 1 to power down the clock receiver and save power when the dac is not being used. note that at power-on reset, the dac sample clock receiver is on by default. divided clock output (dckop/n) the ltc2000 contains a programmable clock divider and lvds transmitter which provide a divided version (either f dac /4 or f dac /2) of the dac sample clock for use by the host fpga or asic. use spi register 0 x02 to control dckop/n ( table 3). at power-on reset, the lvds trans - mitter will provide a clock signal at f dac /4 with a 3.5 ma differential output current. if desired, set dcko_div = 1 to change the divided clock output frequency to f dac /2. the output current can be increased to 7 ma by setting dcko_isel = 1, and an internal 100 differential termination can be enabled by setting dcko_trm = 1. set dcko_dis = 1 to disable the lvds transmitter and save power when not in use. lvds data clock input (dckip/n) the dac code data written to the ltc2000 is captured on both the rising and falling edges of dckip/n . for single-port operation, provide a ddr clock at half the dac sample clock frequency (f dcki = f dac /2). to use a 1.25ghz sample clock in single-port mode, provide a 625mhz clock on dckip/n. for dual-port operation, provide a ddr clock at one quarter the dac sample clock frequency (f dcki = f dac /4). to use a 2.5 ghz sample clock in dual-port mode, provide a 625mhz clock on dckip/n. ltc 2000 2000f for more information www.linear.com/ltc2000
26 o peration table 4. lvds clock spi registers address bit name description 0x03 0 dcki_en dckip/n clock receiver enable. dcki_en = 1 enables lvds clock receiver. 1 dcki_ok dckip/n clock present indicator. when dcki_ok = 1, clock is present at dckip/n pins and f dckip/n > 25mhz. when dcki_ok = 0, dac output is forced to mid-scale unless pattern generator is enabled (pgen_en = 1). dcki_ok is read only. 2 dcki _q dckip/n quadrature phase select. for dcki_q = 0, dckip/n should be in phase with dap/n and dbp/n. set dcki_q = 1 to use dcki in quadrature with dap/n and dbp/n. [6:4] dcki_t adj dckip/n delay adjust. use with dcki_q = 0 to adjust delay of dckip/n relative to dap/n and dbp/n. for dcki_q = 1, dckip/n delay matches dap/n and dbp/n and is unaffected by dcki_tadj. dcki_t adj nominal dckip/n delay dcki_q = 1 dcki_q = 0 110 0ps 230ps 111 0ps 315ps 000 0ps 400ps (default) 001 0ps 485ps 010 0ps 570ps note: register 0x03 resets to 0x00 (default). use spi register 0 x03 to control the lvds data clock input (see table 4). setting dcki_en=1 will enable the lvds receiver at dckip /n . the ltc2000 contains a clock detector which sets dcki_ok=1 if the data input clock is present and has a frequency greater than 25mhz (f dcki > 25mhz). when the data clock is not present (dcki_ok ?= ?0), the dac output is forced to mid-scale and the internal data path is held at reset. for maximum setup/hold margin, set dcki_q = 1 and provide dckip/n in quadrature (90 out of phase) with the data on dap/n and dbp/n (figure 3 in the timing diagrams section). for dcki_q = 1, the internal delays on dckip/n, dap/n, and dbp/n are nominally matched. alternatively, it is possible to leave dcki_q = 0 and provide the clock at dckip/n in phase with the data on dap/n and dbp/n ( see figure 2 of the timing diagram section). in this case, an internal 400 ps delay on dckip/n is used to provide setup/hold margin. note that for dcki_q = 0, supply and temperature variation may reduce the setup/ hold margin on the bus by up to 150 ps. if desired, users may use the dcki_tadj bits in register 0 x03 to adjust the 400 ps internal dckip/n delay with a typical resolu - tion of 85ps. board trace lengths on dckip/n, dap/n, and dbp/n must be carefully matched to ensure that phase alignment is maintained on all inputs. if desired during development, users may observe the relative timing of neighboring lvds inputs on the tstp/n pins ( refer to the measuring lvds input timing skew section). lvds data input ports (dap/n, dbp/n) the ltc2000-16/ltc2000-14/ltc2000-11 allow for dac code data to be applied through one or two parallel 16-/14-/11-bit l vds ports ( dap/n, dbp/n). each port can run up to 1.25 gbps using a double-data-rate ( ddr) lvds data clock ( dckip/n) at frequencies up to 625 mhz. the data input format is twos complement. there are two modes of operation for applying the dac code to the ltc2000 single-port mode and dual-port mode. single port operation uses only lvds port b ( dbp /n) and allows sample rates of up to 1.25 gsps. dual port operation uses both lvds ports ( dap/n and dbp/n) and allows sample rates up to 2.5gsps. use spi register 0 x04 to control the lvds data input ports ( see table 5). after the clocks have stabilized and the synchronizer has initialized itself, set data_en = 1 to allow the data from ports a and b to be used to update the dac code. clear data_en = 0 to mute the dac and force the dac code to mid-scale as desired. ltc 2000 2000f for more information www.linear.com/ltc2000
27 o peration for single port operation, set data_sp = 1, da_en = 0, db_en = 1 and provide data to lvds port b ( dbp/n) only. for dual port operation leave data_sp = 0, set da_en = 1 and db_en = 1, and provide interleaved data to lvds ports a and b ( dap/n, dbp/n). the data on port a will precede the data on port b at the dac output. table 5. lvds data input spi registers address bit name description 0x04 0 da_en dac data port a lvds receiver enable. da_en = 1 enables port a receivers. for da_en = 0, receivers are powered down and port a data is 0x0000. 1 db_en dac data port b lvds receiver enable. db_en = 1 enables port b receivers. for db_en = 0, receivers are powered down and port b data is 0x0000. 2 data_sp dac data single port mode select. data_sp = 1 sets single port mode and only port b data is used to update the dac code. data_sp = 0 sets dual-port mode and data from both ports a and b are used. 3 data_en dac data enable. data_en = 0 mutes the dac output by forcing the dac code to mid-scale. data_en = 1 allows data from data ports a and b to be used to update the dac code. note: register 0x04 resets to 0x00 (default). clock synchronizer figure 7 shows a simplified block diagram of the internal clock synchronizer. the synchronizer monitors the in - coming phase of dckip/n using a pair of internal phase comparators. the synchronizer then automatically adjusts 4:1 mux 50 i outp i outn 50 2000 f07 4 0 90 180 270 dbp/n[15:0] dap/n[15:0] dckip/n ckp/n sync_ps sync_ph[7:4] sync_ph[3:0] logic phase cmp phase cmp 16-bit dac figure 7. simplified block diagram clock synchronizer in dual-port mode ltc 2000 2000f for more information www.linear.com/ltc2000
28 o peration table 6. clock synchronizer spi registers address bit name description 0x05 [1:0] sync_ps synchronizer phase select. selects phase of internal data multiplexer. sync_ps is read-only when sync_msyn = 0. 2 sync_msyn synchronizer manual mode select. when sync_msyn = 0, sync_ps is set automatically by the clock synchronizer based upon sync_ph. when sync_msyn = 1, sync_ps must be set by the user. 0x06 [7:0] sync_ph synchronizer phase comparator outputs. sync_ph indicates the phase of the lvds data clock (dckip/n) relative to the dac sample clock (ckp/n) divider used to control the data multiplexer. sync_ph is read only. sync_ph optimal sync_ps setting dual-port mode single-port mode 0x03 10 00 0x04 10 00 0x05 10 00 0x15 10 00 0x25 10 00 0x35 00 10 0x45 00 10 0x55 00 10 0x54 00 10 0x53 00 10 0x52 01 10 0x51 01 10 0x50 01 10 0x40 01 10 0x30 01 10 0x20 11 00 0x10 11 00 0x00 11 00 0x01 11 00 0x02 11 00 note: registers 0x05 and 0x06 reset to 0x00 (default). the phase of the mux control signals as needed to track any slow drift in the phase between the dckip/n and ckp/n due to supply and temperature variation. this ensures that data is sampled correctly by ckp/n. use spi registers 0 x05 and 0 x06 (table 6) to observe and control the operation of the synchronizer. upon power-up, apply clocks to ckp/n and dckip/n and set dcki_en =?1 (register 0 x03) to enable the lvds data clock receiver. allow at least 1 ms after the clocks have stabilized for the synchronizer to initialize, after which the ltc2000 is ready to accept lvds input data. the synchronizer uses phase comparators to monitor the phase of the data input clock relative to the sample clock divider which controls the mux. the outputs of these phase comparators ( sync_ ph) may be observed in register 0 x 06. the sync_ps bits control the phase of the data multi- plexer. for sync_msyn = 0, the sync_ps bits are read- only and are automatically adjusted by the synchronizer as needed, based upon the phase of dckip/n indicated by sync_ph. users may choose to override the automatic synchronizer by setting sync_msyn = 1 and writing values manually to sync_ps to set the phase of the internal multiplex- er. when using sync_msyn = 1, users must monitor sync_ph and adjust sync_ps as needed according to table 6. for further details see the synchronizing multiple ltc2000s section. ltc 2000 2000f for more information www.linear.com/ltc2000
29 o peration minimizing harmonic distortion the ltc2000 contains proprietary dynamic linearization circuitry which dramatically reduces 3 rd order harmonic distortion in the dac output. spi registers 0 x07 and 0x08 are used to control these circuits ( see table 7). optimal performance is normally achieved by setting lin_ vmx and lin_vmn (register 0 x08) to correspond to the maximum and minimum voltages expected at i outp/n . at power-on reset the default values are 0 b1000 and 0 b0000, which are appropriate for i outp/n swinging between 500 mv and gnd. if an application requires a different voltage swing, lin_vmx and lin_vmn can be programmed by writing to register 0x08 ( see table 7). for applications in which i outp/n swing below gnd, use lin_vmn = 0b0000. in some applications where 2-tone intermodulation distortion ( imd) is a critical specification, it may be desired to vary the amount of 3 rd order harmonic correction. for high sampling frequencies (f dac > 2 gsps), adjusting lin_gn in register 0x07 ( see table 7) can improve 2-tone intermodulation distortion at the expense of higher 3rd order harmonic distortion. for best imd performance at high sampling frequencies, users may also choose to disable dynamic linearization by setting lin _ dis = 1. sfdr and imd curves in the typical performance characteristics section show more detail regarding this effect. note that for f dac < 2 gsps, it is recommended to leave the dynamic linearization enabled. measuring lvds input timing skew it is important to ensure that the lvds inputs (dckip/n, dap/n, dbp/n) are well aligned. skew between clock and data lines, for example due to board trace length mismatch or output timing mismatch inside the host fpga or asic, will degrade the setup and hold margin of the incoming data. the ltc2000 includes an internal test multiplexer which may be used during development to verify timing alignment by comparing the timing of lvds inputs one pair at a time through the tstp/n pins. use spi register 0 x18 to control this test multiplexer (see table?8). be sure tdio_en = 0 in register 0x19 and then set lmx_en = 1 to enable the test multiplexer output. the signal from the lvds data input will be driven onto tstp/n by an nmos differential pair steering a 6.6 ma sink current onto an external load. connect a pair of 50 resistors from tstp/n to 3.3 v and observe tstp/n on a high speed oscilloscope. apply clocks to ckp/n and dckip/n and apply the pattern shown in figure 8 to port b for single-port mode or ports a and b for dual-port mode. this pattern is designed to simplify comparison of rising-to-rising and falling-to- falling edge timing for each input pair. set lmx_adr to select a pair of lvds inputs for timing comparison. set lmx_msel = 0 to observe the first signal at tstp/n. set lmx_msel = 1 to observe the second signal with inverted output polarity. for example, to compare db15p/n to dckip/n, first write 0x60 to register 0 x18 to set lmx_en = 1, lmx_adr = 10000, and lmx_sel = 0. the signal from db15p/n will be driven onto tstp/n. write 0 x61 to register 0 x18 to set lmx_sel = 1 and cause dckip/n to appear at tstp/n with inverted polarity. record the skew between the two signals and repeat this measurement for each pair of inputs. after all pairs have been measured, add the skews to calculate the total skew from dckip/n to each data input ( dap/n, dbp/n). in this way the skew of all lvds data inputs ( dap/n, dbp/n) relative to dckip/n can be accurately measured to within 100ps. note that due to internal delays inside the test multiplexer, it is only valid to compare timing between neighboring lvds pairs using the same lmx_adr setting. similarly, the multiplexer itself contains up to 400ps of skew between rising and falling edges, so it is only valid to compare the timing of a rising edge at tstp/n to another rising edge, and a falling edge to another falling edge. note that figure 8 shows the suggested input pattern for the ltc2000-16. ltc2000-14 users should apply codes 0x1555 and 0 x2aaa, and ltc2000-11 users should apply codes 0 x 555 and 0 x2 aa. also note that for the ltc2000 - 14 and ltc2000-11 in dual-port mode, the timing skew of lvds port a ( dap/n) cannot be compared to that of the lvds clock ( dckip/n) and lvds port b ( dbp/n), as there is no single test multiplexer address ( lmx_adr) that enables a timing comparison between signals da0n/p and dckip/n ( see table 8). it is recommended to keep lmx_en?=?0 during normal operation. ltc 2000 2000f for more information www.linear.com/ltc2000
30 o peration table 7. dynamic linearization spi registers address bit name description 0x07 0 lin_dis dynamic linearization disable. disabled when lin_dis = 1. [3:1] lin_gn dynamic linearization gain select. changing lin_gn varies the amount of 3rd order harmonic correction applied to the dac output. lin_gn = 000 is normally optimal. lin_gn linearization percentage 110 50% 111 63% 000 75% (default) 001 88% 010 100% 011 113% 100 125% 101 138% 0x08 [3:0] lin_vmx dynamic linearization max i outp/n voltage select. for optimal 3rd order harmonic performance, set lin_vmx to correspond to the maximum voltage expected at i outp/n . reset state is lin_vmx = 1000, which corresponds to 0.51v. lin_vmx must be greater than ln_vmn. [7:4] lin_vmn dynamic linearization min i outp/n voltage select. for optimal 3rd order harmonic performance, set lin_vmn to correspond to the minimum voltage expected at i outp/n . reset state is lin_vmn = 0000, which corresponds to 0.0v. lin_vmn must be less than ln_vmx. lin_vmx/n max/min voltage expected at ioutp/n 0000 0.00v (default for lin_vmn) 0001 0.16v 0010 0.19v 0011 0.22v 0100 0.25v 0101 0.31v 0110 0.38v 0111 0.44v 1000 0.51v (default for lin_vmx) 1001 0.63v 1010 0.75v 1011 0.87v 1100 1.00v note: register 0x07 resets to 0x00 (default). register 0x08 resets to 0x08 (default ). ltc 2000 2000f for more information www.linear.com/ltc2000
31 o peration table 8. spi registers for measuring lvds input timing skew address bit name description 0x18 0 lmx_msel lvds test mux select. set lmx_msel high or low to select between a pair of neighboring lvds signals for comparison at tstp/n. [5:1] lmx_adr lvds test mux address. use lmx_adr to select which pair of lvds signals will be compared at tstp/n (see below). 6 lmx_en lvds test mux enable. set lmx_en=1 to compare timing of neighboring signals at tstp/n. ensure tdio_en = 0 when lmx_en = 1. lmx_adr ltc2000-16 ltc2000-14 ltc2000-11 lmx_msel = 0 lmx_msel = 1 (inver ted) lmx_msel = 0 lmx_msel = 1 (inverted) lmx_msel = 0 lmx_msel = 1 (inverted) 00000 da14p/n da15n/p da12p/n da13n/p da9p/n da10n/p 0000101001 da[13:5]p/n da[14:6]n/p da[11:3]p/n da[12:4]n/p da[8:0]p/n da[9:1]n/p 01010 da4p/n da5n/p da2p/n da3n/p da0n/p 01011 da3p/n da4n/p da1p/n da2n/p 01100 da2p/n da3n/p da0p/n da1n/p 01101 da1p/n da2n/p da0n/p 01110 da0p/n da1n/p 01111 dckip/n da0n/p dckip/n dckip /n 10000 db15p/n dckin/p db13p/n dckin/p db10p/n dckin/p 10001 db14p/n db15n/p db12p/n db13n/p db9p/n db10n/p 1001011010 db[13:5]p/n db[14:6]n/p db[11:3]p/n db[12:4]n/p db[8:0]p/n db[9:1]n/p 11011 db4p/n db5n/p db2p/n db3n/p db0n/p 11100 db3p/n db4n/p db1p/n db2n/p 11101 db2p/n db3n/p db0p/n db1n/p 11110 db1p/n db2n/p db0n/p 11111 db0p/n db1n/p note: register 0x18 resets to 0x00 (default). dap/n[15:0] 0xaaaa 0xaaaa 0xaaaa 2000 f08 0xaaaa 0x5555 0x5555 0x5555 0x5555 dbp/n[15:0] dcki figure 8. sample pattern for measuring lvds input timing skew (ltc2000-16) ltc 2000 2000f for more information www.linear.com/ltc2000
32 o peration measuring internal junction temperature (t j ) the ltc2000 test multiplexer may also be used to connect internal junction temperature measurment diodes to the tstp/n pins. ensure lmx_en = 0 ( register address 0x18) and use spi register 0 x19 to set tdio_en = 1 to enable this function (table 9). there are two methods the user can choose from to measure internal junction temperature (t j ). for tdio_sel = 0, an unbiased npn transistor is diode-connected between the tstp/n pins. this diode is suitable for use with external temperature sensors such as the ltc2991 or ltc2997. if such a temperature sensor is not available, set tdio_ sel ?= ?1 to directly observe a temperature dependent voltage between tstp and tstn. the typical expected voltage at tstp is v tstp = 2.02v C 5.5mv/c ? ( t j C 25c ). the junction temperature can be calculated as t j = 25c + (2.02v C v tstp )/(5.5mv/c). for best accuracy with tdio_sel?=?1, use tstn to sense gnd at the bottom of the diode and calibrate the voltage at a known tempera - ture. typical uncalibrated accuracy is 5c. pattern generator a 64 sample deep pattern generator is included in the ltc2000 to simplify system development and debug. the pattern generator allows the user to send a repeating 64 sample pattern to the dac, completely independent of the presence or absence of valid signals on dckip/n, dap/n, and dbp/n. table 9. internal junction temperature spi registers address bit name description 0x19 0 tdio_en tstp/n junction temperature diode enable. set tdio_en = 1 to measure internal junction temperature (t j ) at tstp/n. ensure lmx_en = 0 when tdio_en = 1. 1 tdio_sel selects which internal temperature diode is observable at tstp/n. for tdio_sel = 1, the typical voltage at tstp with respect to tstn is v tstp = 2.02v C 5.5mv/c ? (t j C 25oc). junction temperature can be calculated as t j = 25c + (2.02v C v tstp )/(5.5mv/c). typical accuracy is 5c. for tdio_sel = 0, an unbiased diode is connected b/w tstp/n for use with external temperature sensors. note: register 0x19 resets to 0x00 (default). to use this feature, do the following: 1. set dcko_div = 0 in register 0 x02, data_sp = 0 and data_en = 0 in register 0 x04, and pgen_en = 0 in register 0x1e. 2. write 128 bytes of pattern data to address 0 x1f ( pgen _d) to fill the pattern generator with 64 samples. data is writ - ten msb first, and will be applied to the dac in the order written. data may be written one byte at a time or in larger multi- byte words. for the ltc2000 - 14 and ltc2000-11, data should be left justified with zeros filling the remaining two ( ltc2000-14) or five ( ltc2000-11) bits . 3. set pgen_en = 1 to start the pattern generator. 4. wait at least 1 ms to ensure that the synchronizer has initialized. 5. set data_en = 1 in register 0 x04. the dac will then begin to output the 64 sample pattern. the pattern generator will send the repeating 64 sample pattern to the dac until the user writes pgen_en = 0 or data_en = 0. to read back the pattern, set data_ en = 0 and pgen_ en = 0 and then read 128 bytes from address 0 x1f . note that the starting point of the pattern may have changed while the pattern was running. to modify the pattern, set data_ en = 0 and pgen_ en = 0 and write a new 64 sample pattern to address 0 x1f . ensure pgen_ en = 0 when reading or writing to address 0 x1f , and always read or write an entire 64 sample pattern prior to setting pgen_ en = 1. see table 10. table 10 C pattern generator spi registers address bit name description 0x1e 0 pgen_en pattern generator enable. set pgen_en = 1 to use the internal 64 sample pattern generator to provide data to the dac. set data_sp = 0, dcko_div = 0, and data_en = 1 when pgen_en = 1. 0x1f [7:0] pgen_d pattern generator data. write 128 bytes of data to this address to fill the pattern generator with 64 samples. data is written msb first. reading this location causes the pattern generator data to be shifted out through sdo. ensure pgen_en = 0 when reading or writing to address 0x1f. read or write an even number of bytes to address 0x1f prior to setting pgen_en = 1 to avoid corrupting the data inside the pattern generator. note : registers 0x1e and 0x1f reset to 0x00 (default). ltc 2000 2000f for more information www.linear.com/ltc2000
33 spi r egister s ummary address bit name description reset value r/w 0x00 [7:0] reserved reserved 0x01 0 sw_rst software reset. sw_rst = 1 resets all registers. 0 r/w 1 dac_pd dac power down. dac_pd = 1 to power down dac core. 0 r/w 2 full_pd full power down. full_pd = 1 to power down ltc2000. 0 r/w 3 reserved reserved [5:4] dac_res dac resolution indicator. dac_res = 00 for ltc2000-16. dac_res = 01 for ltc2000-14. dac_res = 11 for ltc2000-11. note that for pd = gnd or full_pd = 1, dac_res = 00. dac_res is read only. 00-16b 01-14b 11-11b r [7:6] reser ved reserved 0x02 0 ck_pd ckp/n clock receiver power down. ck_pd = 1 disables 0 r/w 1 ck_ok ckp/n clock present indicator. ck_ok = 1 clock present 0 r [3:2] reserved reserved 4 dcko_dis dckop/n output disable. dcko_dis = 1 disables 0 r/w 5 dcko_div dckop/n divide select. (0 = f dac /4, 1 = f dac /2). 0 r/w 6 dcko_isel dckop/n output current select. (0=3.5ma, 1 = 7ma) 0 r/w 7 dcko_trm dckop/n internal termination on. dcko_trm = 1 enables internal 100 termination 0 r/w 0x03 0 dcki_en dckip/n clock receiver enable. dcki_en = 1 enables. 0 r/w 1 dcki_ok dckip/n clock present indicator. dcki_ok = 1 indicates clock present 0 r 2 dcki_q dckip/n quadrature phase select. (0 = in phase, 1 = quadrature) 0 r/w 3 reser ved reserved [6:4] dcki_tadj dckip/n delay adjust. (see table 4) 000 r/w 7 reserved reserved 0x04 0 da_en port a lvds receiver enable. da_en = 1 to enable 0 r/w 1 db_en port b lvds receiver enable. db_en = 1 to enable 0 r/w 2 data_sp port mode select. (0 = dual port, 1 = single port) 0 r/w 3 data_en dac data enable. data_en = 0 forces dac output to mid-scale. 0 r/w [7:4] reserved reserved 0x05 [1:0] sync_ps clock synchronizer phase select. 00 r/w 2 sync_msyn clock synchronizer manual mode select. sync_msyn = 0: sync_ps is set automatically. sync_msyn = 1: sync_ps is set by the user. 0 r/w [7:3] reserved reserved 0x06 [7:0] sync_ph clock phase comparator outputs. (see table 6) 0x00 r 0x07 0 lin_dis dynamic linearization disable. lin_dis = 1 disables. 0 r/w [3:1] lin_gn dynamic linearization gain select. (see table 7) 000 r/w [7:4] reserved reserved 0x08 [3:0] lin_vmx dynamic linearization max i outp/n voltage select. (see table 7) 1000 r/w [7:4] lin_vmn dynamic linearization min i outp/n voltage select. (see table 7) 0000 r/w table 11. spi register list ltc 2000 2000f for more information www.linear.com/ltc2000
34 spi r egister s ummary address bit name description reset value r/w 0x09 [5:0] gain_adj dac gain adjustment. (see table 2) 0x00 r/w [7:6] reserved reserved 0x0a thru 0x17 [7:0] reserved reserved 0x18 0 lmx_msel lvds test mux select. (see table 8) 0 r/w [5:1] lmx_adr lvds test mux address select. (see table 8) 0x00 r/w 6 lmx_en lvds test mux enable. lmx_en = 1 enables lvds text mux. ensure tdio_en = 0 when lmx_en = 1. 7 reserved reserved 0x19 0 tdio_en tstp/n junction temperature diode enable. tdio_en = 1 enables temperature (t j ) measurement. ensure lmx_en = 0 when tdio_en = 1. 0 r /w 1 tdio_sel junction temperature select. tdio_sel = 0 uses a diode-connected unbiased npn transistor. tdio_sel = 1 outputs a voltage to calculate internal die temperature using: t j = 25c + (2.02v C v tstp )/(5.5mv/c). (see table 9) 0 r/w [7:2] reserved reserved 0x1a thru 0x1d [7:0] reserved reserved 0x1e 0 pgen_en pattern generator enable. pgen_en = 1 enables. 0 r/w [7:1] reserved reserved 0x1f [7:0] pgen_d pattern generator data. 0x00 r/w 0x20 thru 0x7f [7:0] reserved reserved table 11. spi register list (cont) a pplications i n f ormation sample start-up sequence the following is an example of a common start- up sequence. 1. apply valid supply voltages to av dd33 , dv dd33 , av dd18 , d vdd18 and sv dd . 2. write 0 x01 to address 0 x01 to perform a software reset. 3. apply a clock to ckp/n at the desired f dac frequency. the ltc2000 will generate a clock at dckop/n at f dac /4. 4. apply a clock to dckip/n at f dac /4 for dual-port mode or f dac /2 for single-port mode. 5. apply zeroes to ports a and b ( dap/n, dbp/n) for dual- port mode, or only to port b for single- port mode. 6. write to address 0 x03 to enable the dckip/n lvds receiver. set address 0 x03 to 0 x01 if the lvds clock ( dcki) and data ( da, db) are in phase with each other. set address 0x03 to 0x05 if they are in quadrature. 7. write 0 x06 to address 0 x04 for dual-port mode, or write 0 x04 to address 0 x04 for single-port mode to enable the dap/n and dbp/n lvds receivers. 8. wait at least 1 ms for the synchronizer to finish initializing. 9. write 0 x0b to address 0 x04 for dual -port mode, or write 0 x0e to address 0 x04 for single-port mode to set data_en = 1. ltc 2000 2000f for more information www.linear.com/ltc2000
35 a pplications i n f ormation 10.) apply desired data pattern to ports a and b (dap/n, dbp/n) for dual-port mode, or only to port b for single-port mode. port a samples will precede port?b samples at the dac output when using dual-port mode. output configurations the ltc2000s complementary current outputs (i outp/n ) source current into an external load referenced to gnd. output load configuration, component selection, and layout are critical to the performance of the ltc2000. for best ac performance, the output stages should be configured for differential (or balanced) operation. a differential resistor loaded output is a very simple output stage. well matched resistors are connected between gnd and i outp/n , with the resistance values setting both the output swing and non-zero output common-mode voltage (figure 9). while it is economical, this type of output stage can drive only differential loads with impedance levels and amplitudes appropriate for the dac outputs. differential transformer-coupled output configurations usually give the best ac performance and provide excel- lent rejection of common mode distortion and noise over a broad frequency range. figure 10 shows a transformer output configuration that uses a mini-circuits tc1-1-13m and a jtx -2-10t rf transformer for differential to single- ended conversion. i outp r r 2000 f09 ltc2000 i outn figure 9. differential resistor output load figure 10. transformer-based output configuration for differential to single-ended conversion i outp 2000 f10 ltc2000 mini-circuits tc1-1-13m mini-circuits jtx-2-10t ?? i outn ? ? for any output configuration, any imbalances in the output impedance between the i outp and i outn pins results in asymmetrical signal swings that lead to distortion (mostly even order). careful consideration is needed to select the best output configuration for a given application. generating the dac sample clock for best ac performance, it is important that the dac sample clock waveforms be clean, with low phase noise and good jitter performance, as the phase noise and spu- rious content of the clock source will appear directly in the dac output spectrum. a differential clock should be ac coupled onto the ckp/n pins, since the dc bias point of ckp/n is set internally to 1v through a 5 k impedance. figure 11 shows the dac sample clock receiver input and common-mode voltage control. while the differential input voltage range of the clock receiver spans from 300 mv to 1.8 v, a signal with the highest possible slew rate and amplitude and a bal - anced duty cycle is recommended. traces that carry the differential clock signal need to have accurately controlled impedance and accurate termination as close to the ckp/n pins of the ltc2000 as possible. there are several ways to generate the dac sample clock. for lab evaluation and testing, a high quality rf signal generator can provide a clean high frequency sine wave that is converted to the dac sample clock with a 1:1 rf transformer or balun (see figure 12). figure 11. dac sample clock receiver 5k av dd18 1v ltc2000 5k ckp ckn gnd 2000 f11 ltc 2000 2000f for more information www.linear.com/ltc2000
36 a pplications i n f ormation a more integrated clock source is one based on a low phase noise, low jitter pll. figure 13 shows how the dac sample clock can be generated from the ltc6946, a high performance pll with an internal vco that can provide output frequencies from 0.37 ghz to 5.7 ghz. see the ltc6946 data sheet for details. synchronizing multiple ltc2000s in dual-port mode in some applications, it is necessary to synchronize mul - tiple ltc 2000s to each other such that related samples arrive at all dac outputs simultaneously. figures 14 and 15a show a block diagram and sample waveforms for such a system in which two dacs ( x and y) are to be synchronized in dual-port mode. note that in this example a small timing skew between the two data signals at the dckip/n pins of dacs x and y has caused the dckip/n rising edges to arrive on op - posite sides of a dac sample clock (ckp/n) rising edge, and thus within different ckp/n clock cycles. as a result the default behavior is for the output of dac y to update with sample n one cycle earlier than the output of dac x. it is possible to correct this misalignment and synchro- nize dacs x and y by adjusting the clock synchronizer settings to subtract one cycle of latency from dac x, as shown in the adjusted waveform at the bottom of figure 15a. see the clock synchronizer section and figure 7 for more details on the operation of the clock synchronizer. in order to synchronize multiple dacs as shown in fig - ures?14 and 15 a, distribute the dac sample clock carefully with matched delays so that it arrives at the ckp/n pins of all dacs simultaneously. any remaining timing mismatch between sample clocks will appear directly as mismatch in the dac output timing. ensure that the timing mismatch between lvds data clock signals at the dckip/n pins of all dacs is less than 0.4 cycles of the dac sample clock, mi - nus any timing mismatch between the dac sample clocks. be sure to maintain sufficient matching between the timing of the lvds data inputs ( dap/n, dbp/n) and dckip/n for each dac to meet the setup and hold time specifications (t 11 , t 12 ) in the timing characteristics section. for example, let us consider a system using multiple dacs at 2.5 gsps in which the sample clock is designed to arrive at the ckp/n pins of all dacs within 30 ps of one another. the sample clock period is 400 ps, so the maximum allow - able timing mismatch between the data clock signals at the dckip/n pins of all dacs will be (0.4 ? 400 ps) C 30ps = 130 ps. for a system using multiple dacs at 1.25gsps, the allowable mismatch between dckip/n pins will be (0.4 ? 800 ps) C 30ps = 290 ps. in both cases, once the dacs n = 250 o = 1 n_div r = 10 f pfd ref (f ref ) f ref * 100pf + + 100pf l1 68nh ltc6946 k pfd f vco k vco i cp = 11.2ma v rf + cp loop filter lf(s) 2000 f13 tune r z 453 50 50 100pf c i 0.022f r_div o_div rf *crystek cvhd-950-100.000 100mhz oscillator rf + rf ? (f rf ) 25 15 c p 2700pf l2 68nh + ckp ckn ltc2000 figure 13. dac sample clock generation with the ltc6946 figure 12. dac sample clock generation with an rf signal generator and a 1:1 balun + 50 ?? 50 100pf ltc2000 f12 + + 1nf 1nf 50 ltc2000 mini-circuits tc1-1-13m rf signal generator ckp ckn ltc 2000 2000f for more information www.linear.com/ltc2000
37 a pplications i n f ormation are synchronized the mismatch in the dac output timing will be limited to 30ps. once all the dac sample clocks and lvds data clocks are aligned, determine whether any dacs are being updated one cycle late (such as dac x in figure 15a ) by determining whether dckip/n is arriving at the dacs within the same ckp/n clock cycle. to do this in dual-port mode, first use the phase comparator outputs sync_ph and table? 12 to determine the delay from the dckip/n rising edge to the next ckp/n rising edge for each dac ( measured in sample clock cycles). recall that the dckip/n timing mismatch must be kept below 0.4 cycles of the sample clock. if dckip/n ar- rives at both dacs within the same sample clock cycle, the difference in dckip/n to ckp/n delays indicated by sync_ph will equal the actual dckip/n timing mismatch, and thus will be less than 0.4 cycles. if dckip/n arrives at the dacs within different cycles, as in figure 15 a, the difference in the delays indicated by sync_ph will equal 1 cycle minus the actual dckip/n timing mismatch, and thus will be greater than 0.4 cycles. thus if the difference between the delays indicated by sync_ph is greater than ckp/n dac x ltc2000 dckip/n lvds data lvds clk matched delays matched delays dap/n dbp/n ckp/n dac y ltc2000 dckip/n 2000 f14 lvds data lvds clk dap/n dbp/n clock source fpga dap/n[15:0] n n+2 n+4 n+6 n+8 n+10 dbp/n[15:0] dac x dckip/n dac x i outp/n dac x i outp/n (adjusted) dac y i outp/n dac y dckip/n ckp/n n+1 n+3 0.9 cycles 0.1 cycles 10 cycles n 2000 f15a n+5 n+7 n+9 n+11 n n+1 n n+1 9 cycles 10 cycles figure 14. system with multiple ltc2000 dacs synchronized figure 15a. sample waveforms synchronizing multiple ltc2000s in dual port mode ltc 2000 2000f for more information www.linear.com/ltc2000
38 a pplications i n f ormation 0.4 cycles, the dckip/n rising edges are arriving in dif- ferent sample clock cycles. for the example in figure 15 a, we might read 0 x25 for sync_ph on dac x and 0 x52 on dac y. table 12 tells us that the dckip/n to ckp/n delay is greater than 0.8 cycles for dac x and less than 0.2 cycles for dac y, and thus the difference between them is at least 0.6 cycles. we conclude that the dckip/n rising edge of dac x must fall within a later sample clock cycle than that of dac y, and thus that dac x is being updated one cycle later than dac y. to correct any such misalignment and synchronize the dacs, consult table 12 and adjust the sync_ps settings for those dacs which are being updated one cycle late (dac x in the above example) by setting the synchronizer to manual mode (sync_msyn = 1) and overwriting the sync_ps value. in this example, reading register 0 x06 of dac x shows sync_ph = 0 x25 and that the sync_ps setting needs to change from the default (10) to the desired adjusted value (00), subtracting one cycle from the latency of dac x ( refer to table 12). write 0 x04 to register 0 x05 of dac x to set sync_msyn = 1 and sync_ps = 00. the outputs of dac x should now align with dac y as shown in figure?15a. see table 6 for details regarding the synchronizer registers 0x05 and 0 x06. sample verilog code implementing the synchronization of multiple ltc2000s using tables 12 and 13 can be found at: http://www.linear.com/docs/44845 synchronizing multiple ltc2000s in single-port mode figure 15 b shows sample waveforms for synchronizing two ltc2000 s in single port mode. synchronizing multiple ltc2000s in single port mode is essentially the same table 12. adjusting latency in dual-port mode phase comparator outputs sync_ph (reg 0x06) delay from dckip/n rising edge to next ckp/n rising edge (ckp/n cycles) sync_ps setting (default) (adjusted to reduce latency by 1 cycle)* 0x03 0 to 0.2 10 n/a 0x04 0.2 to 0.4 10 n/a 0x05 0.4 to 0.6 10 n/a 0x15 0.6 to 0.8 10 00 0x25 0.8 to 1.0 10 00 0x35 0 to 0.2 00 n/a 0x45 0.2 to 0.4 00 n/a 0x55 0.4 to 0.6 00 n/a 0x54 0.6 to 0.8 00 01 0x53 0.8 to 1.0 00 01 0x52 0 to 0.2 01 n/a 0x51 0.2 to 0.4 01 n/a 0x50 0.4 to 0.6 01 n/a 0x40 0.6 to 0.8 01 11 0x30 0.8 to 1.0 01 11 0x20 0 to 0.2 11 n/a 0x10 0.2 to 0.4 11 n/a 0x00 0.4 to 0.6 11 n/a 0x01 0.6 to 0.8 11 10 0x02 0.8 to 1.0 11 10 *n/a indicate sync_ph values that should not occur if the timing mismatch requirements described above are met. if such a case occurs, keep sync_ps as the default value. ltc 2000 2000f for more information www.linear.com/ltc2000
39 a pplications i n f ormation procedure as when operating in dual port modedac sample clocks must all be aligned to arrive at the ckp/n pins of all dacs simultaneously and timing mismatch between lvds data clock signals at the dckip/n pins of all dacs must be less than 0.4 cycles of the dac sample clock, minus any timing mismatch between the dac sample clocks. to determine whether any dacs are being updated one cycle late in single port mode, first use the phase comparator outputs sync_ph and table 13 to determine the delay from the dckip/n rising edge to the next ckp/n falling edge ( as opposed to rising edge in dual port mode) for each dac. if the difference between the delays indicated by sync_ph is greater than 0.4 cycles, the dckip/n ris - ing edges are arriving in different sample clock cycles. for the example in figure 15 b, we might read 0 x15 for sync_ph on dac x and 0 x20 on dac y. table 13 shows that the dckip/n to ckp/n delay is greater than 0.8 cycles for dac x and less than 0.1 cycles for dac y, and thus the difference between them is at least 0.7 cycles. this indicates that dac x is being updated one cycle later than dac y. consult table 13 and use the same procedure described above in the dual-port mode case to correct the sync_ps settings for those dacs that are updating one cycle late. in this single port example, writing 0 x06 to register 0x05 of dac x would set sync_msyn = 1 and sync_ps = 10, reducing the latency of dac x by one cycle and aligning its output with dac y, as shown in figure 15b. note that variations in system temperature or supply voltage may cause the phase of the data clock (dckip/n) and sample clock ( ckp/n) to vary with time. when using the ltc2000 with sync_msyn = 1, it is recommended that users monitor sync_ph and adjust sync_ps using tables 12 or 13 as needed to maintain proper alignment. the synchronization procedures described above also work for systems with more than two dacs. simply determine the minimum dckip/n to ckp/n delay of all dacs by reading sync_ph, and then adjust the sync_ps settings to subtract one cycle of latency to those dacs whose dckip/n to ckp/n delays are at least 0.4 cycles more than the minimum . sample verilog code implementing the synchronization of multiple ltc2000s using tables?12 and 13 can be found at: http://www.linear.com/docs/44845 dbp/n[15:0] dac x dckip/n dac x i outp/n dac x i outp/n (adjusted) dac y i outp/n dac y dckip/n ckp/n n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 0.8 cycles 0.1 cycles 7.5 cycles n 2000 f15b n n+2 n+1 n n+2 n+1 n+1 6.5 cycles 7.5 cycles figure 15b. sample waveforms synchronizing multiple ltc2000s in single port mode ltc 2000 2000f for more information www.linear.com/ltc2000
40 a pplications i n f ormation table 13. adjusting latency in single-port mode phase comparator outputs sync_ph (reg 0x06) delay from dckip/n rising edge to next ckp/n falling edge (ckp/n cycles) sync_ps setting (default) (adjusted to reduce latency by 1 cycle)* 0x03 0.5 to 0.6 00 n/a 0x04 0.6 to 0.7 00 10 0x05 0.7 to 0.8 00 10 0x15 0.8 to 0.9 00 10 0x25 0.9 to 1.0 00 10 0x35 0 to 0.1 10 n/a 0x45 0.1 to 0.2 10 n/a 0x55 0.2 to 0.3 10 n/a 0x54 0.3 to 0.4 10 n/a 0x53 0.4 to 0.5 10 n/a 0x52 0.5 to 0.6 10 n/a 0x51 0.6 to 0.7 10 00 0x50 0.7 to 0.8 10 00 0x40 0.8 to 0.9 10 00 0x30 0.9 to 1.0 10 00 0x20 0 to 0.1 00 n/a 0x10 0.1 to 0.2 00 n/a 0x00 0.2 to 0.3 00 n/a 0x01 0.3 to 0.4 00 n/a 0x02 0.4 to 0.5 00 n/a *n/a indicate sync_ph values that should not occur if the timing mismatch requirements described above are met. if such a case occurs, keep sync_ps as the default value. pcb layout considerations the close proximity of high frequency digital data lines and high dynamic range, wideband analog signals make clean printed circuit board design and layout an absolute necessity. figures 16 and 17 show a schematic and pcb layers for an evaluation circuit for the ltc2000. a single, solid ground plane should be used, while separate supply planes for av dd18 , dv dd18 , av dd33 , and dv dd33 should be kept all the way to the individual supply or ldo. all lvds input ( dckip/n, dap/n, dbp/n) board traces must be carefully matched to ensure proper phase alignment. these lvds inputs should be kept far away from both the i outp/n and ckp/n traces to avoid any data dependent coupling into the analog output and dac sample clock. the ckp/n traces should be routed either over the analog ground plane or over their own section on the ground plane. these traces also need to have accurately controlled im - pedance and should be well terminated near the ltc2000. the i outp/n traces should also be carefully matched to each other, routed over the ground plane, away from the lvds inputs and ckp/n signals. bypass capacitors are required on av dd18 , dv dd18 , av dd33 , and dv dd33 , and should all be connected to the analog ground plane . 2.2 f ceramic capacitors with low esr are recommended to be placed close to the ltc2000 with minimum trace lengths. a sample pcb layout and schematic can be found below. ltc 2000 2000f for more information www.linear.com/ltc2000
41 a pplications i n f ormation dap[15:0] dan[15:0] dckip dckin dbp[15:0] dbn[15:0] sv dd av dd33 dv dd33 av dd18 dv dd18 dckop dckon ckp r29 50 r26 50 ckn tstp tstn i outp i outn s1 s2 s3 s4 s5 r4 r3 refio fsadj 2000 f16 m1 m2 h1 j1 pd cs sdo sdi sck j10 matched lvds data and clock lines from fpga spi ports j8 k8 k7 3.3v 1.8v 47f 47f ltc2000 gnd c43 0.01f c66 1pf c42 100pf 6 1 2 3 5 gnd gnd in 4 c41 100pf t1 anaren b0430j50100ahf c47 10pf l6 1nh clock source r40 50 r46 50 r45 500 c40 10f r47 50 r48 50 figure 16 layer 2 layer 1 ltc 2000 2000f for more information www.linear.com/ltc2000
42 a pplications i n f ormation layer 3 layer 4 ltc 2000 2000f for more information www.linear.com/ltc2000
43 a pplications i n f ormation layer 6 layer 5 ltc 2000 2000f for more information www.linear.com/ltc2000
44 layer 7 layer 8 a pplications i n f ormation ltc 2000 2000f for more information www.linear.com/ltc2000
45 p in l ocations ( ltc 2000-16) ltc2000-16 bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 gnd b1 gnd c1 av dd18 d1 av dd18 e1 av dd18 f1 gnd a2 ckn b2 gnd c2 av dd18 d2 av dd18 e2 av dd18 f2 gnd a3 ckp b3 gnd c3 av dd18 d3 av dd18 e3 dv dd18 f3 gnd a4 gnd b4 gnd c4 av dd18 d4 dv dd18 e4 dv dd18 f4 gnd a5 dv dd18 b5 dv dd18 c5 dv dd18 d5 dv dd18 e5 dv dd18 f5 gnd a6 gnd b6 gnd c6 gnd d6 gnd e6 gnd f6 gnd a7 dan15 b7 dan14 c7 dan13 d7 dan12 e7 dan11 f7 dan10 a8 dap15 b8 dap14 c8 dap13 d8 dap12 e8 dap11 f8 dap10 a9 dbn15 b9 dbn14 c9 dbn13 d9 dbn12 e9 dbn11 f9 dbn10 a10 dbp15 b10 dbp14 c10 dbp13 d10 dbp12 e10 dbp11 f10 dbp10 pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 i outp j1 i outn k1 gnd l1 gnd m1 refio g2 gnd h2 gnd j2 gnd k2 gnd l2 gnd m2 fsadj g3 gnd h3 gnd j3 gnd k3 gnd l3 gnd m3 gnd g4 gnd h4 gnd j4 gnd k4 gnd l4 gnd m4 av dd33 g5 gnd h5 gnd j5 gnd k5 gnd l5 gnd m5 dv dd33 g6 gnd h6 gnd j6 gnd k6 gnd l6 gnd m6 gnd g7 dan9 h7 dan8 j7 dckon k7 dan7 l7 dan6 m7 dan5 g8 dap9 h8 dap8 j8 dckop k8 dap7 l8 dap6 m8 dap5 g9 dbn9 h9 dbn8 j9 dckin k9 dbn7 l9 dbn6 m9 dbn5 g10 dbp9 h10 dbp8 j10 dckip k10 dbp7 l10 dbp6 m10 dbp5 pin id function pin id function pin id function pin id function pin id function n1 gnd p1 av dd33 q1 av dd33 r1 gnd s1 pd n2 gnd p2 av dd33 q2 av dd33 r2 gnd s2 cs n3 gnd p3 av dd33 q3 av dd33 r3 tstn s3 sdo n4 av dd33 p4 av dd33 q4 av dd33 r4 tstp s4 sdi n5 dv dd33 p5 dv dd33 q5 dv dd33 r5 gnd s5 sck n6 gnd p6 gnd q6 gnd r6 gnd s6 sv dd n7 dan4 p7 dan3 q7 dan2 r7 dan1 s7 dan0 n8 dap4 p8 dap3 q8 dap2 r8 dap1 s8 dap0 n9 dbn4 p9 dbn3 q9 dbn2 r9 dbn1 s9 dbn0 n10 dbp4 p10 dbp3 q10 dbp2 r10 dbp1 s10 dbpo ltc 2000 2000f for more information www.linear.com/ltc2000
46 p in l ocations ( ltc 2000-16) 1 s r q p n m l k j h dv dd33 av dd33 gnd gnd gnd gnd refio fsadj pd cs gnd ckn ckp gnd gnd dan2 dap2 dbn2 dbp2 dan3 dap3 dbn3 dbp3 dan4 dap4 dbn4 dbp4 dan5 dap5 dbn5 dbp5 dan6 dap6 dbn6 dbp6 dan7 dap7 dbn7 dbp7 dckon dckop i outn i outp dckip dckin dan8 dap8 dbn8 dbp8 dan9 dap9 dbn9 dbp9 dan10 dap10 dbn10 dbp10 dan11 dap11 dbn11 dbp11 dan12 dap12 dbn12 dbp12 dan13 dap13 dbn13 dbp13 dan14 dap14 dbn14 dbp14 dan15 dap15 dbn15 dbp15 tstn tstp dan1 dap1 dbn1 dbp1 sdo sdi sck sv dd dan0 dap0 dbn0 dbp0 g f e d c b a 2 3 4 5 6 7 8 9 10 top view av dd18 dv dd18 ltc 2000 2000f for more information www.linear.com/ltc2000
47 pi n l ocations ( ltc 2000-14) ltc2000-14 bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 gnd b1 gnd c1 av dd18 d1 av dd18 e1 av dd18 f1 gnd a2 ckn b2 gnd c2 av dd18 d2 av dd18 e2 av dd18 f2 gnd a3 ckp b3 gnd c3 av dd18 d3 av dd18 e3 dv dd18 f3 gnd a4 gnd b4 gnd c4 av dd18 d4 dv dd18 e4 dv dd18 f4 gnd a5 dv dd18 b5 dv dd18 c5 dv dd18 d5 dv dd18 e5 dv dd18 f5 gnd a6 gnd b6 gnd c6 gnd d6 gnd e6 gnd f6 gnd a7 dan13 b7 dan12 c7 dan11 d7 dan10 e7 dan9 f7 dan8 a8 dap13 b8 dap12 c8 dap11 d8 dap10 e8 dap9 f8 dap8 a9 dbn13 b9 dbn12 c9 dbn11 d9 dbn10 e9 dbn9 f9 dbn8 a10 dbp13 b10 dbp12 c10 dbp11 d10 dbp10 e10 dbp9 f10 dbp8 pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 i outp j1 i outn k1 gnd l1 gnd m1 refio g2 gnd h2 gnd j2 gnd k2 gnd l2 gnd m2 fsadj g3 gnd h3 gnd j3 gnd k3 gnd l3 gnd m3 gnd g4 gnd h4 gnd j4 gnd k4 gnd l4 gnd m4 av dd33 g5 gnd h5 gnd j5 gnd k5 gnd l5 gnd m5 dv dd33 g6 gnd h6 gnd j6 gnd k6 gnd l6 gnd m6 gnd g7 dan7 h7 dan6 j7 dckon k7 dan5 l7 dan4 m7 dan3 g8 dap7 h8 dap6 j8 dckop k8 dap5 l8 dap4 m8 dap3 g9 dbn7 h9 dbn6 j9 dckin k9 dbn5 l9 dbn4 m9 dbn3 g10 dbp7 h10 dbp6 j10 dckip k10 dbp5 l10 dbp4 m10 dbp3 pin id function pin id function pin id function pin id function pin id function n1 gnd p1 av dd33 q1 av dd33 r1 gnd s1 pd n2 gnd p2 av dd33 q2 av dd33 r2 gnd s2 cs n3 gnd p3 av dd33 q3 av dd33 r3 tstn s3 sdo n4 av dd33 p4 av dd33 q4 av dd33 r4 tstp s4 sdi n5 dv dd33 p5 dv dd33 q5 dv dd33 r5 gnd s5 sck n6 gnd p6 gnd q6 gnd r6 gnd s6 sv dd n7 dan2 p7 dan1 q7 dan0 r7 gnd s7 gnd n8 dap2 p8 dap1 q8 dap0 r8 gnd s8 gnd n9 dbn2 p9 dbn1 q9 dbn0 r9 gnd s9 gnd n10 dbp2 p10 dbp1 q10 dbp0 r10 gnd s10 gnd ltc 2000 2000f for more information www.linear.com/ltc2000
48 p in l ocations ( ltc 2000-14) 1 s r q p n m l k j h gnd av dd33 dv dd33 tstn tstp pd cs sdo sdi sck sv dd gnd dan0 dap0 dbn0 dbp0 dan1 dap1 dbn1 dbp1 dan2 dap2 dbn2 dbp2 dan3 dap3 dbn3 dbp3 dan4 dap4 dbn4 dbp4 dan5 dap5 dbn5 dbp5 dckon dckop dckin dckip dan6 dap6 dbn6 dbp6 dan7 dap7 dbn7 dbp7 dan8 dap8 dbn8 dbp8 dan9 dap9 dbn9 dbp9 dan10 dap10 dbn10 dbp10 dan11 dap11 dbn11 dbp11 dan12 dap12 dbn12 dbp12 dan13 dap13 dbn13 dbp13 gnd gnd gnd av dd18 i outp i outn refio fsadj dv dd18 ckn ckp g f e d c b a 2 3 4 5 6 7 8 9 10 top view ltc 2000 2000f for more information www.linear.com/ltc2000
49 p in l ocations ( ltc 2000-11) ltc2000-11 bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 gnd b1 gnd c1 av dd18 d1 av dd18 e1 av dd18 f1 gnd a2 ckn b2 gnd c2 av dd18 d2 av dd18 e2 av dd18 f2 gnd a3 ckp b3 gnd c3 av dd18 d3 av dd18 e3 dv dd18 f3 gnd a4 gnd b4 gnd c4 av dd18 d4 dv dd18 e4 dv dd18 f4 gnd a5 dv dd18 b5 dv dd18 c5 dv dd18 d5 dv dd18 e5 dv dd18 f5 gnd a6 gnd b6 gnd c6 gnd d6 gnd e6 gnd f6 gnd a7 dan10 b7 dan9 c7 dan8 d7 dan7 e7 dan6 f7 dan5 a8 dap10 b8 dap9 c8 dap8 d8 dap7 e8 dap6 f8 dap5 a9 dbn10 b9 dbn9 c9 dbn8 d9 dbn7 e9 dbn6 f9 dbn5 a10 dbp10 b10 dbp9 c10 dbp8 d10 dbp7 e10 dbp6 f10 dbp5 pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 i outp j1 i outn k1 gnd l1 gnd m1 refio g2 gnd h2 gnd j2 gnd k2 gnd l2 gnd m2 fsadj g3 gnd h3 gnd j3 gnd k3 gnd l3 gnd m3 gnd g4 gnd h4 gnd j4 gnd k4 gnd l4 gnd m4 av dd33 g5 gnd h5 gnd j5 gnd k5 gnd l5 gnd m5 dv dd33 g6 gnd h6 gnd j6 gnd k6 gnd l6 gnd m6 gnd g7 dan4 h7 dan3 j7 dckon k7 dan2 l7 dan1 m7 dan0 g8 dap4 h8 dap3 j8 dckop k8 dap2 l8 dap1 m8 dap0 g9 dbn4 h9 dbn3 j9 dckin k9 dbn2 l9 dbn1 m9 dbn0 g10 dbp4 h10 dbp3 j10 dckip k10 dbp2 l10 dbp1 m10 dbp0 pin id function pin id function pin id function pin id function pin id function n1 gnd p1 av dd33 q1 av dd33 r1 gnd s1 pd n2 gnd p2 av dd33 q2 av dd33 r2 gnd s2 cs n3 gnd p3 av dd33 q3 av dd33 r3 tstn s3 sdo n4 av dd33 p4 av dd33 q4 av dd33 r4 tstp s4 sdi n5 dv dd33 p5 dv dd33 q5 dv dd33 r5 gnd s5 sck n6 gnd p6 gnd q6 gnd r6 gnd s6 sv dd n7 gnd p7 gnd q7 gnd r7 gnd s7 gnd n8 gnd p8 gnd q8 gnd r8 gnd s8 gnd n9 gnd p9 gnd q9 gnd r9 gnd s9 gnd n10 gnd p10 gnd q10 gnd r10 gnd s10 gnd ltc 2000 2000f for more information www.linear.com/ltc2000
50 p in l ocations ( ltc 2000-11) 1 s r q p n m l k j h g f e d c b a 2 3 4 5 6 7 8 9 10 top view gnd pd cs sdo sdi tstn tstp sck sv dd gnd dano dapo dbno dbpo dan1 dap1 dbn1 dbp1 dan2 dap2 dbn2 dbp2 dan3 dap3 dbn3 dbp3 dan4 dap4 dbn4 dbp4 dan5 dap5 dbn5 dbp5 dan6 dap6 dbn6 dbp6 dan7 dap7 dbn7 dbp7 dan8 dap8 dbn8 dbp8 dan9 dap9 dbn9 dbp9 dan10 dap10 dbn10 dbp10 dckon dckop dckin dckip gnd av dd33 dv dd18 av dd18 dv dd33 gnd i outp i outn refio fsadj gnd ckn ckp ltc 2000 2000f for more information www.linear.com/ltc2000
51 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage description s r q p n m l k j h g f e d c b a 123456 10 9 8 7 package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes pin 1 bga package 170-lead (15.00mm 9.00mm 1.54mm) (reference ltc dwg# 05-08-1890 rev b) bga 170 1112 rev b tray pin 1 bevel package in tray loading orientation component pin ?a1? notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (170 places) detail b substrate a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 1.39 0.35 1.04 0.45 0.35 0.39 0.65 nom 1.54 0.40 1.14 0.50 0.40 15.00 9.00 0.80 12.80 7.20 0.44 0.70 max 1.69 0.45 1.24 0.55 0.45 0.49 0.75 0.15 0.10 0.12 0.15 0.08 notes dimensions total number of balls: 170 a2 d e e e b f g suggested pcb layout top view 0.00 3.20 3.20 6.40 4.00 4.00 4.80 4.80 5.60 5.60 6.40 0.80 0.80 1.60 1.60 2.40 2.40 3.60 2.80 2.00 2.80 1.20 0.40 2.00 1.20 0.40 3.60 0.00 5.35 5.85 ltxxxxxx // bbb z z h2 h1 b 5. primary datum -z- is seating plane 6. solder ball composition can be 96.5% sn/3.0% ag/0.5% cu or sn pb eutectic 0.40 0.025 ? 170x 3.05 2.55 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc 2000 2000f for more information www.linear.com/ltc2000
52 ? linear technology corporation 2014 lt 0714 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2000 r elate d p arts t ypical a pplication part number description comments ltc1666/ltc1667/ ltc1668 12-/14-/16-bit 50msps dacs with 10ma full scale v cc = 5v, C1v to 1v output compliance, 28-pin ssop package ltc2153/ltc2158 single/dual 14-/12-bit 310msps adcs 88db sfdr, 1.25ghz bandwidth sample-and-hold ltc2630 single 12-/10-/8-bit rail-to-rail dacs with internal reference v cc = 2.7v to 5.5v, sc70 package ltc2991 octal i 2 c voltage, current, and temperature monitor v cc = 3v to 5.5v, 16-lead msop package ltc2997 remote/internal temperature sensor v cc = 2.v to 5.5v, 170a, 6-lead 2mm 3mm dfn package lt ? 5521 very high linearity active mixer 10mhz to 3.7ghz, 24.2dbm oip3 at 1.95ghz lt5579 high linearity upconverting mixer 1.5ghz to 3.8ghz, 27.3dbm oip3 at 2.14ghz lt5578 high linearity upconverting mixer 400mhz to 2.7ghz, 24.3dbm iip3 at 1.95ghz ltc6406 3ghz, low noise, rail-to-rail input differential amplifier/driver low noise: 1.6nv/ hz rti , 18ma at 3v, low distortion ltc6430-15 high linearity differential rf/if amplifier 20mhz to 2ghz bandwidth, 50dbm oip3 at 240mhz, 15.2db gain ltc6946 ultralow noise and spurious integer-n synthesizer with integrated vco 0.37ghz to 5.7ghz, C226dbc/hz normalized in-band phase noise, C274dbc/hz normalized in-band 1/f noise ltc2000 high speed dac driving lt5579 mixer as an upconverting transmitter with low noise power supply solution dap[15:0] dan[15:0] dckip dckin dbp[15:0] dbn[15:0] sv dd av dd18 dv dd18 dckop dckon ckp r29 50 r26 50 ckn tstp tstn i outn i outp s1 s2 s3 s4 s5 r4 r3 s6 refio fsadj 2000 ta01 m1 m2 h1 j1 pd cs sdo sdi sck j10 matched lvds data and clock lines from fpga spi ports j8 a3 a2 k8 k7 3.3v ltc2000y-16 av dd33 lt1763cs8-3.3 lt1763cs8-3.3 dv dd33 gnd c43 0.01f c66 1pf c42 100pf 6 1 2 3 5 gnd gnd in 4 c41 100pf t1 anaren b0430j50100ahf c65 10pf l6 1nh clock source r52 20 c66 47pf l9 2.7nh l8 2.7nh l11 1.5nh 4 3 1 2 1 2 1 2 1 2 22 15 l10 1.5nh l12 1.8nh lo input rf output c65 47pf r50 0 r49 0 c25 0.1f c26 0.1f r51 20 1k 7.15k r45 500 c40 10f r53 11.5 r54 11.5 c68 82pf c67 82pf c68 22pf c69 1.2pf c74 10f c73 1f c72 100pf c71 10pf shdn in gnd gnd gnd out sen byp 1 2 5 8 3 6 7 4 0.01f 47f 1f 5v shdn in gnd gnd gnd out sen byp 1 2 5 8 3 6 7 4 0.01f 47f 1f 5v shdn v in gnd gnd outf outs gnd gnd 7 6 8 5 1 2 3 4 10f 3.24k 4.7f 1f 1f 5v 47f 1f 3.3v if ? lt5579 0.1db chebychev, bw = 535mhz v cc 3.3v gnd if + lo rf ltc6655ch ms8-2.048 v out v out v out pad set 7 8 5 3 2 1 9 v in v in v ctrl lt3080edd 3.3v 3.24k 4.7f 5v 47f v out v out v out pad set 7 8 5 3 2 1 9 v in v in v ctrl lt3080edd 3.3v ltc 2000 2000f for more information www.linear.com/ltc2000

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