process CP329V small signal transistor npn- silicon darlington transistor chip princip al device types cmpta29 czta29 mpsa29 geometry process details r0 (20 -january 2006) process epitaxial planar die size 27 x 27 mils die thickness 7.1 mils base bonding pad area 4.2 x 4.2 mils emitter bonding pad area 4.3 x 4.3 mils top side metalization al - 30,000? back side metalization au - 13,000? 145 adams avenue hauppauge, ny 11788 usa tel: (631) 435-1110 fax: (631) 435-1824 www.centralsemi.com gross die per 4 inch w afer 15,980
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