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may 2015 ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 FAN6230A secondary-side synchronous rectification controller for flyback converters FAN6230A secondary-side synchronous rectification controller for flyback converters features ? secondary-side sr controller for flyback ? seamless transition between dcm and ccm ? shunt regulator integrated (1.25 v reference) ? charge pump circuit integrated for low output voltage in cc m ode ? output cable compensation circuit integrated ? pwm frequency tracking using secondary side winding voltage ? ultra low v dd operating voltage for 5 v , 9 v, 12 v output application ? ultra low green m ode operating current (typical: 0. 5 ma) ? boost entire efficiency and green-m ode operation for less power consumption at no load condition ? 16 -p in mlp33 package ? res dropping protection (enter green m ode ) ? lpc falling detect protection (disable gate drive) ? causal period protection (disable gate drive) description the FAN6230A is a secondary-side synchronous rectifier (sr) mosfet controller for high efficiency applications. it has internal shunt regulator with low bias current and internal charge pump circuit to reduce external part counts, total cost and overall system power consumption. with the internal charge pump circuit, the FAN6230A guarantees stable operation of sr switching even with lo w bias voltage in cc regulation. the FAN6230A also features internally adjustable cable compensation that helps maintain precise constant voltage regulations at the end of cable. unlike the traditional sr current sensing method s, which measure the sr mosfet drain voltage that is sensitive to the noise introduced by poor pcb layout. t he FAN6230A utilizes a novel linear-prediction timing control (lpc) circuit to estimate the sr current zero crossing instant without additional current sensing circuitry. while running in green mode, the FAN6230A shuts off the sr mosfet and lowers its bias supply current to 5 00 ? a, so overall power consumption of the system is further reduced. applications ? adaptive chargers for cellular phones, cordless phones, tablets, pdas, digital cameras, and power tools . ordering information part number operating temperature range package packing method FAN6230Ampx - 40 c to +125c 16 -lead, molded leadless package, (mlp) quad. jedec mo-220, 3 x 3 tape & reel ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 2 FAN6230A secondary-side synchronous rectification controller for flyback converters application diagram vin res cathode pgnd lpc v out FAN6230A r 1 r 2 r 5 q 1 gate q 2 i sr v det v lpc n : 1 vclamp vdd cp cn r 3 r 4 vref r 6 v ref opto comrl comrh v in lm i m r 7 r 8 c 1 c 2 c 3 c 4 c 5 c 6 r 9 r 10 t primary side pgnd primary side pgnd secondary side pgnd secondary side pgnd v res agnd c 9 c 10 figure 1. typical application circuit internal block diagram 9 + - v dd-on /v dd-off internal bias 1a/v v ct vdd 2 lpc enable 0.445a/v sr qq 10 11 c t i chr i dischr pgnd gate gate driver pwm block v lpc-en green mode t green-on / t green-off line detection function period detect causal function reset 0.6v/1.25v 16 14 1 vref cathode 13 comrl calculate v lpc-en + - + - reset + - 1.25v cable comp. s s s s s res 5 6 7 8 vin vclamp cp cn 15 comrh 4,12 agnd vclamp charge pump x 2 figure 2. functional block diagram ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 3 FAN6230A secondary-side synchronous rectification controller for flyback converters marking information f zxytt 6230 atm 1 4 5 8 9 12 13 16 figure 3. top marking information pin configuration lpc cathode vdd vref comrl gate res nc agnd cn cp vclamp vin pgnd agnd comrh exposed dap figure 4. pin assignments pin definitions pin # name description 1 cathode cathode of internal shunt regulator (open drain) 2 lpc sr mosfet drain voltage detection. this pin is used to detect the v oltage on the secondary winding during the on time period of the primary fet 3 nc not connected. it is recommended to solder to pcb 4 agnd analog ground 5 cn charg e pump cn 6 cp charg e pump cp 7 vclamp clamp voltage on vin voltage. the clamped voltage is fed to the charge pump circuit. need 1 f ceramic bypass capacitor to pgnd 8 vin input voltage for the charge pump, typically connected to the ou tput voltage of the power converter. 9 vdd sr gate driver voltage source and bias supply for internal control circuitry . 10 gate gate driver output. totem-pole output to drive the external sr mosfet. 11 pgnd power ground 12 agnd analog ground 13 comrl input for internal cable compensation circuit. tie a resistor fr om this pin to agnd to program the cable compensation function for low line operation 14 comrh input for internal cable compensation circuit. tie a resistor fr om this pin to agnd to program cable compensation function for high line operation 15 res reset control of the linear predict circuit. an internal current source, idisch r is modulated by the voltage level on the res pin. 16 vref reference for the internal shunt regulator. exposed dap analog ground must be soldered to pcb ground plane : fairchild l ogo z: plant code x: year code y: week code tt: die run code t : package type (mp=mlp) m : manufacture flow c ode ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 4 FAN6230A secondary-side synchronous rectification controller for flyback converters absolute maximum ratings stresses exceeding the absolute maximum ratings may dama ge the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the reco mmended operating conditions may affect device reliability . th e absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v in charge pump supply voltage 20 v v cathode cathode p in input voltage 20 v v vdd vdd p in input voltage -0.3 6.5 v v vref vref p in input voltage -0.3 7 .0 v v res res p in input voltage -0.3 7 .0 v v lpc lpc p in input voltage -0.3 7 .0 v v comrh comrh p in input voltage -0.3 6.5 v v comrl comrl p in input voltage -0.3 6.5 v v gate gate p in input voltage -0.3 6.5 v v cp cp p in input voltage -0.3 6.5 v v cn cn p in input voltage -0.3 6.5 v v vclamp vclamp p in input voltage -0.3 6.5 v p d power dissipation (t a =25c) 0.85 w ja th ermal resistance (junction- to -ambient thermal) 14 7 c /w jt thermal resistance (junction- to -top thermal) 12 c /w t j operating junction temperature - 40 15 0 c t stg storage temperature range - 40 150 c t l lead temperature (soldering) 10 seconds 260 c esd electrostatic discharge capability human body model, ansi / esda / jedec js-001-2012 2.5 kv charged device model, jesd22-c101 1.5 notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 2. all voltage values, except differential voltages, are given with res pect to agnd pin , (agnd=pgnd). ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 5 FAN6230A secondary-side synchronous rectification controller for flyback converters electrical characteristics v in =5 v~12 v , lpc=1.5 v, lpc width=2 ? s, res=1.5 v, t j =- 40 c to 105 c , f lpc =100 khz; unless otherwise specified. symbol parameter conditions min. typ. max. unit vin section (charge pump) v in v in continuously operating voltage 1.9 16 v i in - op operating current at 5 v in v in =5 v, c vclamp =c pn =c vdd =1 ? f, f lpc =140 khz,c l =3300 pf (including charge pump) 12 16 ma i in - op - 12v operating current at 12 v in v in = 12 v, c vclamp =c pn =c vdd =1 ? f, f lpc =140 khz,c l =3300 pf ( no charge pump) 6 8 ma i in -green operating current in green mode v in =5 v, c vclamp =c pn =c vdd =1 ? f 500 700 ? a v od output voltage for internal v dd supply c vclamp =c pn =c vdd =1 ? f, v in >2.5 v, f lpc =140 khz, c l =3300 pf, 1.9 ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 7 FAN6230A secondary-side synchronous rectification controller for flyback converters electrical characteristics v in =5 v~12 v , lpc=1.5 v, lpc width=2 ? s, res=1.5 v, t j =- 40 c to 105 c , f lpc =100 khz; unless otherwise specified. symbol parameter conditions min. typ. max. unit v lpc-high- l- 9v sr enabled threshold voltage at low- line , v in = 9 v v lpc-high-l- 9v =v lpc- th -l-9v / 0.875 0.81 0.88 0.95 v v lpc- th -l- 9v threshold voltage on lpc rising edge at low- line , v in = 9 v (4) spec.=0.45+0.03 ? v in , v in =9 v 0.72 0.77 0.82 v v lpc-high- l- 12v sr enabled threshold voltage at low- line , v in = 12 v v lpc-high-l- 12v =v lpc- th -l-12v / 0.875 0.95 1.02 1.09 v v lpc- th -l- 12v threshold voltage on lpc rising edge at low- line , v in = 12 v (4) spec.=0.45+0.03 ? v in , v in =12 v 0.85 0.90 0.95 v v lpc- th - trig threshold voltage on lpc falling edge at trigger 40 70 100 mv v line-h- 5v low -to high-line threshold voltage on lpc pin , v in = 5 v spec.=[0.80+0.023 ? v in ]*2; v in =5 v 1.7 1. 8 1. 9 v v line-l- 5v high-to low-line threshold voltage on lpc pin , v in =5 v spec.=[0.75+0.023 ? v in ]*2; v in = 5 v 1. 6 1 .7 1. 8 v v line-h- 9v low -to high-line threshold voltage on lpc pin , v in =9 v spec.=[0.80+0.023 ? v in ]*2; v in = 9 v 1. 87 1.97 2.07 v v line-l- 9v high-to low-line threshold voltage on lpc pin , v in =9 v spec.=[0.75+0.023 ? v in ]*2; v in = 9 v 1.77 1.87 1.97 v v line-h- 12v low -to high-line threshold voltage on lpc pin , v in = 12 v spec.=[0.80+0.023 ? v in ]*2; v i = 12 v 1.99 2.09 2.19 v v line-l- 12v high-to low-line threshold voltage on lpc pin , v in = 12 v spec.=[0.75+0.023 ? v in ]*2; v in = 12 v 1.89 1.99 2.09 v v lpc- clamp-h higher clamp voltage 5.4 6.2 7.0 v v lpc-dis lpc threshold voltage to disable sr gate switching v dd =5 v, lpc=3 v 4.50 4.75 5.00 v t lpc- lh - debounce line change debounce from low-line to high-line 12 18 24 ms t lpc- hl - debounce line change debounce from high-line to low- line (4) 15 ? s internal timing section ? ratio lpc lpc transfer ratio to i lpc (4) 1 ? a/v ? ratio res v res transfer ratio to i res (4) 0.445 ? a/v ? ratio lpc- res ratio between v lpc and v res v lpc =1.5 v, v res =1.5 v, lpc width=4 ? s 2.05 2.25 2.45 t lpc- en -h minimum lpc time to enable the sr gate at high-line, v lpc-high >v lpc-high-h v dd 5 v, v lpc =3 v, v res =1.5 v 80 18 0 28 0 ns ? t lpc- en -l minimum lpc time to enable the sr gate at low-line, v lpc-high >v lpc-high-l v dd 5 v, v lpc =1.5 v, v res =1.5 v 600 700 800 ns ? t min minimum gate width (4) v lpc =1.5 v, v res =1.5 v 0.35 0.50 0.65 ? s ? t gate-limit t on - sr (n+1)- t on - sr (n) < t gate-limit 500 ns ? green section ? t green- on minimum lpc non-switching period to enter green mode each lpc cluster to cluster 260 330 400 ? s ? continued on the following page ? ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 8 FAN6230A secondary-side synchronous rectification controller for flyback converters electrical characteristics v in =5 v~12 v , lpc=1.5 v, lpc width=2 ? s, res=1.5 v, t j =- 40 c to 105 c , f lpc =100 khz; unless otherwise specified. symbol parameter conditions min. typ. max. unit t green-off maximum lpc non-switching period to exit green mode each lpc cluster to cluster 100 150 200 ? s ? n green-off continuous lpc switching cycles to exit green mode 256 cycles ? comr section v dis-comr -h threshold voltage of comrh to disable cable compensation v dd >3.5 v 2.0 2.5 3.0 v v dis-comr -l threshold voltage of comrl to disable cable compensation v dd >3.5 v 2.0 2.5 3.0 v v ref- comrh cable compensation at high- line r comrh =100 k, c comrh =100 nf, v dd =5 v, res=1.5 v, lpc high =3 v, gate width=5 ? s, (v ref =v cathode , i cathode =5 ma) 1.37 1.40 1.43 v v ref- comrl cable compensation at low- line r comrl =100 k, c comrl =100 nf, v dd =5 v, res=1.5 v, lpc high=1.5 v, gate width=5 ? s (v ref =v cathode i cathode =5 ma) 1.37 1.40 1.43 v notes : 3. v dd >v dd_on : enable cathode pin (disable to pull high cathode pin). 4. guarantee by design ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 9 FAN6230A secondary-side synchronous rectification controller for flyback converters typical performance characteristics figure 5. operating current (i in - op ) vs. temperature figure 6. operation current in green mode (i in -green ) vs. temperature figure 7. turn-on threshold voltage (v dd - on ) vs. temperature figure 8. turn-off threshold voltage (v dd -off ) vs. temperature figure 9. maximum period (t max-period ) vs. temperature figure 10. sr turn-off dead time by causal function at low line (t dead-causal2 ) vs. temperature ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 10 FAN6230A secondary-side synchronous rectification controller for flyback converters typical performance characteristics figure 11. reference voltage (v ref ) vs. temperature figure 12. threshold voltage on lpc rising edge at low-l ine (v lpc- th -l- 5v ) vs. temperature figure 13. threshold voltage on lpc rising edge at low-l ine (v lpc- th -l- 9v ) vs. temperature figure 14. threshold voltage on lpc rising edge at low-l ine (v lpc- th -l- 12 v ) vs. temperature figure 15. low-to hi gh -line threshold voltage on lpc p in (v line-h- 5v ) vs. temperature figure 16. low-to hi gh -line threshold voltage on lpc p in (v line-h- 9v ) vs. temperature ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 11 FAN6230A secondary-side synchronous rectification controller for flyback converters typical performance characteristics figure 17. low-to hi gh -line threshold voltage on lpc p in (v line-h- 12v )vs. temperature figure 18. minimum lpc time to enable sr gate at high- line (t lpc- en -h ) vs. temperature figure 19. minimum lpc time to enable sr gate at low-line (t lpc- en -l ) vs. temperature figure 20. minimum lpc non-switching period to enter green mode (t green- on ) vs. temperature figure 21. minimum lpc non-switching period to exit green mode (t green-off ) vs. temperature figure 22. cable compensation at high- line (v ref-comrh ) vs. temperature ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 12 FAN6230A secondary-side synchronous rectification controller for flyback converters theory of operation of sr control synchronous rectification is widely used for low -voltage and high-current power converter applications to maximize efficiency. by replacing the rectifier diode wi th a mosfet operat ing as a synchronous rectifier (sr), the equivalent forward-voltage drop can be lowered and consequently the conduction loss can be reduced. unlike buck-derived topologies, the control of synchronous rectification of a flyback converter is challenging since it is a current-fed capacitor-loaded circuit structure. for this kind of circuit, the polarity of the voltage on the transformer secondary winding can change only after the synchronous rectifier (sr) is turned off. this is because the voltage on the seconda ry winding is clamped to the output voltage while the sr is conducting. thus, the sr current zero crossing instant should be predicted to properly turn off the sr gate before the sr current reaches zero, which allows the sr body diode to naturally turn off blocking reverse current flow. figure 23 shows a simplified flyback converter with a synchronous rectification and its key waveforms. when the switch qp is turned on, the input voltage is applied to the primary side magnetizing inductor of the transformer and the magnetizing inductor current ramps up . when the qp is turned off, the reflected output voltage is applied across the primary side magnetizing inductor and the magnetizing inductor current ramps down. depending on whether the converter operates in continuous conduction mode (ccm) or discontinuous conduction mode (dcm), the sr current zero crossing instant is determined differently. when operating in dcm, the sr current zero crossing instant changes according to the duty cycle of the primary side gate drive signal. whereas, the sr current zero crossing instant in ccm operation is when the primary side switch is turned on. thus, two different methods (linear pr edict and causal predict) are used in FAN6230A to anticipate the sr current zero crossing instant for both ccm and dcm operation. v sec i m i sr steady state in dcm steady state in ccm l m i m i m i sr n:1 vo ts v in ts v gs.pr v gs.sr v gs.pr v gs.pr v gs.sr v gs.sr q p q sr i sr figure 23. flyback converter and key waveforms for each operating m ode 1. linear predict control (lpc) figure 24 shows the conceptual circuit of linear pr edict control and its related waveforms. in dcm operation, the transformer current (magnetizing inductor current) always ramps up from zero when a new switching cycle start s. this current ramps down to zero before the next switching cycle starts. since the slope of the magn etizing current is determined by the voltage applied across the magnetizing inductor, the voltage second balance equation shows when the magnetizing current returns to its initial value after one switching cycle. in out on dis mm v nv tt ll ? (1) even in ccm operation, the voltage-second balance equation (1) is satisfied as long as the converter operates in steady state. the basic idea of the linear predict method is to predi ct the instant when the magnetizing current of the transformer goes back to its initial condition after completing one switching cycle by emulating the operation of the magnetizing inductor current. inductor current can be emulated by taking the transformer winding voltage which is converted to a current and then injected into a timing capacitor. the timing capacitor voltage emulates the inductor current and therefore the sr current zero crossing instant can be predicted for proper sr gate drive. v ct + - c t voltage controlled current source v lpc- th turn off sr gate turn on sr gate at the falling edge v lpc sr gate v sec + zcd v sec- v sec i m i d steady state in dcm steady state in ccm same area v sec i m i d same area v in /n v o v in /n v o v ct v ct t on t dis t on t dis on trig off trig logic block figure 24. conceptual circuit of linear predict control ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 13 FAN6230A secondary-side synchronous rectification controller for flyback converters 2. causal predict control (cpc) even though the linear predict method anticipates the sr current zero crossing instant very effectively in dcm operation, it has limitations for ccm operation. this is because the magnetizing current does not go back to its initial condition at the end of the switching cycle when the converter goes through a transient in ccm as illustrated in figure 25. thus, the linear predict method results in late termination of the sr gate, which can cause shoot-through since both primary side and secondary side switches are on at the same. to guarantee reliable sr control over all operating modes, ano ther sr control method - causal predict control is also employed in the FAN6230A. v sec i m i d transient in ccm not same v in /n v o sr current zero crossing instant predicted by linear predict v ct figure 25. magnetizing current waveform during transient in ccm causal predict control anticipates the sr current zero crossing instant based on the switching period of the previous switching cycle as illustrated in figure 26 . basically the causal predictive sr control is based on the assumption that the switching frequency does not change much between two consecutive switching cycles. thus, this method predicts the switching instant of the current switching cycle according to the switching pattern of the previous switching cycle. as can be seen in figure 26, cpc anticipates the sr current to cross zero later than the actual zero crossing in dcm. however, lpc predicts the sr current zero crossing instant properly in dcm. for ccm operation, lpc anticipates the sr current to cross zero later than the actual zero crossing. whereas, cpc predicts the sr current zero crossing instant properly in ccm. FAN6230A uses the zero crossing anticipation signals from lpc and cpc and among the two signals, the signal introduced first triggers the turn-off of the sr switch. one limitation of cpc is that it requires a relatively large dead time when the primary side pwm controller has variable frequency operation for output regulation or frequency modulation for emi reduction. this is to cover the possible switching period variation between two consecutive switching cycles determined by the primary side pwm controller. v lpc v gs.sr v ct v gs.pr vth v lpc.pk (n) i m anticipated zero crossing by lpc t period (n) t period (n+1) t priod (n-1) t priod (n) anticipated zero crossing by cpc figure 26. operation of causal predict control ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 14 FAN6230A secondary-side synchronous rectification controller for flyback converters functional description circuit operations 3. sr turn- on trigger by lpc pin voltage the most important signal that FAN6230A uses for sr control is the lpc pin voltage since it is used to detect the turn-on and turn-off instants of the primary side switch. figure 28 shows the typical operation together with the lpc voltage waveforms for dcm and ccm operation. the issue is that oscillation occurs on the lpc signal when both the primary side mosfet and the sr mosfet are off in dcm operation. to maintain proper sr control, it is essential to distinguish the oscillation from the actual pwm switching. the lpc voltage must meet two conditions in order to be recognized as a valid lpc voltage generated by pwm switching. ? the lpc voltage should rise above 90% of sampled lpc voltage of the previous switching cycle. the 90% of the lpc sampling voltage should be also higher than v lpc- th . in other words, the lpc voltage sampling voltage should be higher than v lpc- th /0.9 (v lpc-high ). ? in addition, lpc voltage should remain above the threshold longer than the lpc enable time (t lpc- en ). th e lpc enable time is adaptively changed according to the o per ating condition as t l pc - en -h = 180 ns for high line and t lpc- en -l =700 ns for low line , respectively. once the lpc voltage is recognized as valid, the lpc voltage sampling takes place when t lpc- en expires. the sampled lpc voltage is used to generate the threshold to validate lpc voltage next time and also utilized to drive the voltage controlled current source for linear predict control. when the lpc voltage that is recognized as valid lpc signal drops below v lpc- th , the sr mosfet is turned on. for several v in voltage applications , modulations of v lpc- th -l as a function of v in voltage are necessary, shows in figure 27, and table 1 shows detailed v lpc- th - l and v lpc- th -h for low line and high line condition, respectively. to prevent miss-trigger of sr in dcm operation , FAN6230A has an lpc falling detect protection, the lpc voltage should drop fast passing two detect thresholds within trigger time. even when the lpc voltage drops fast satisfying the conditions listed above, it is ignored when it happens within t inhibit (1.4 s) inhibit time after the sr turn-off instant. table 1. detailed parameter by lpc pin with low line and high line condition parameter condition value (typ.) unit t lpc- en -h high l ine 180 ns t lpc- en -l low l ine 700 ns v lpc-high-h high l ine 1.5 v v lpc-high-l- 5v low line, 5 v output 0.68 v v lpc-high-l-9v low line, 9 v output 0.88 v v lpc-high-l-12v low line, 12 v output 1.02 v v lpc- th -h high l ine 1.25 v v lpc- th -l- 5v low line, 5 v output 0.60 v v lpc- th -l-9v low line, 9 v output 0.77 v v lpc- th -l- 12 v low line, 12 v output 0.90 v v lpc- th -trig 70 mv v l p c _ t h _ l v i n 0 . 6 v 0 . 8 5 v 5 v 1 2 v figure 27. modulation of v lpc- th -l as a function of v in p in voltage ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 15 FAN6230A secondary-side synchronous rectification controller for flyback converters v out i m v in /n primary mosfet v gs synchr onous rectifier mosfet v ct v lpc v in /n+v out body diode of sr mosfet body diode of sr mosfet primary mosfet v out i m v in /n primary mosfet v gs synchr onous rectifier mosfet v ct v lpc v in /n+v out body diode of sr mosfet body diode of sr mosfet v lpc-th i m,min v lpc-th t lpc-en v ds.sr t lpc-en ignored recognized recognized v ds.sr t inhibit t inhibit 90% of v lpc pk of previous cycle v lpc-high v lpc-high 90% of v lpc pk of previous cycle figure 28. typical waveforms of linear-predict timing control in dcm and ccm operation 4. low / high line detection with lpc voltage according to the lpc sampling voltage, the low line and high line conditions are detected, which adjusts severa l key parameters according to the line voltage. the threshold voltages for line voltage detection are listed below. table 2. threshold voltages for line voltage detection 5. sr turn-o ff trigger by linear predict figure 29 shows the linear predict control block diagram. the basic idea of the linear predict method is to estimate the instant when the magnetizing current of the transformer goes back to its initial condition after completing one switching cycle by emulating the operation of the magnetizing inductor current. two voltage controlled current sources and an internal timing capacitor are used to emulate the charging and discharging of the magnetizing inductor. v sec n:1 vo v in q sr 1.0a/v v ct s/h 0.445a/v + - c t i chr i dischr v lpc-th turn off sr gate sr gate r 1 r 2 r 3 r 4 zcd lpc res + - 70mv q q set clr d 180 ns figure 29. linear-predict control block parameter condition value (t yp .) unit v line-h- 5v h igh l ine detect 1.80 v v line-l- 5v low l ine detect 1.70 v v line-h- 9v h igh l ine detect 1.97 v v line-l- 9v low l ine detect 1.87 v v line-h- 12v h igh l ine detect 2.27 v v line-l- 12v low l ine detect 2.09 v t lpc- lh -debounce from low to h igh l ine 18 ms t lpc- hl -debounce from high to low l ine 15 s ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 16 FAN6230A secondary-side synchronous rectification controller for flyback converters the current which charges the internal capacitor ct while lpc voltage is high is given as: 2 66 4 1 1 2 3 4 () 1 10 0.445 10 in o o ct v vr vr n i r r r r ?? ? ? ? ? ? ? ? ?? (2) whereas, the current discharging the internal capacitor ct while lpc voltage is low is given as 6 4 2 34 0.445 10 ct o r iv rr ? ? ? ? ? (3) the current-second balance of the capacitor which is equivalent to voltage second balance of the inductor is given as: 24 . 1 2 3 4 4 . 34 1.0 0.445 [( ) ] 0.445 [] in o o on pwm o on sr v rr v v t n r r r r r vt rr ?? ? ? ? ?? ? ?? ? (4) by introducing a voltage divider ratio which is defined as 4 1 2 3 4 2 r r r r r r ? ?? ? k , equation (4) can be simplified as : .. 2.25 [ ( ) ] in out out on pwm out on sr v v v t v t kn ? ? ? ? ? ? (5) by setting k=2 .2 5 , the voltage-second balance equation is obtained from (4) as : .. in on pwm o on sr v t v t n ? ? ? (6) as shown in equation (6), the ct voltage zero crossing occurs when the sr current crosses zero. considering the tolerance of the resistor dividers and internal circuit, the coefficient k should be slightly larger than 2 .2 5 to guarantee that the sr gate is turned off before the sr current reaches zero . due to the allowable voltage ranges of the internal circuitry of the lpc and res pins, there are several requirements for the lpc and res voltage dividers. ? si nce the minimum lpc sampling voltage allowing sr gate drive operation is v lpc-high , the minimum lpc sampling voltage should be higher than v lpc- high as : . 2 12 () in min lpc high l out v r vv r r n ?? ?? ? (7) ? to ensure the linear operation range of voltage controlled current source for lpc, the lpc voltage should be between 0.5 v and 4 v as: . 2 12 0.5 ( ) in min out v r vv r r n ?? ? (8) . 2 12 ( ) 4 in max out v r vv r r n ?? ? (9) ? to ensure the linear operation range of voltage controlled current source for res pin , the res voltage should be between 0.4 v and 4 .2 v as : 4 34 0.4 4.2 out r v v v rr ?? ? ( 10 ) ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 17 FAN6230A secondary-side synchronous rectification controller for flyback converters 6. sr turn-o ff trigger by causal predict to ensure the proper operation of secondary side synchronous rectification, it is critical to turn off the sr mosfet just before the turn on of next switching of primary side switch so that the two switches are not turned on at the same time. table 3 shows the dead time introduced to the causal predict control. table 3. dead time introduced to the causal predict control parameter condition value (t yp .) unit t dead-causal1 cv regulation, high line 79 0 ns t dead-causal2 cv regulation, low l ine 570 ns t dead-causal3 cc regulation, low l ine 85 0 ns v lpc v gs.sr v gs.pr vth v lpc.pk (n) t period (n) t period (n+1) t priod (n-1) t priod (n) t dead-causal t dead-causal figure 30. operation of causal predict control 7 . sr gate expansion limit protection gate expansion limit protection controls the on -time expansion of the sr mosfet. once the discharge time of the internal timing capacitor (t dis.ct ) is longer than 500ns plus previous on-time of the sr mosfet (t on - sr (n-1)); t on - sr (n) is limited to 500ns plus t on - sr (n-1 ) as shown in figure 31. when output load changes rapidly from light load to heavy load, voltage-second balance theorem may not be applied. in this transient state, gate expand limit protection is activated to prevent overlap between the sr gate and the pwm gate. when the FAN6230A detects through the lpc pin voltage that the operating condition has changed between high line and low line, sr gate is reduced to its minimum (500 ns) and then recovers with sr gate limit function. when the FAN6230A starts up or exits green mode, sr gate limit function is also incorporated resulting in soft- start of sr gate. t on-sr (n-1) v lpc sr_gate v ct sr-gate is turned off by gate limit protection t on-sr (n) =t on-sr (n-1)+500ns t dis.ct [n] t dis.ct [n-1] figure 31. operation of gate limit function 8. res pin operation the output voltage of the flyback converter is sensed on the res pin using a voltage divider. the output voltage information is used for the following functions. ? linear predict control: the res voltage is used to drive the voltage controlled current source for linear predict control. ? output short protection: when the res voltage drops below 0.2 v, sr is disabled. when res voltage drops more than 10% compared to the res voltage of the previous switching cycle, sr switching is also disabled (entering green mode). table 4. parameters related to res p in parameter condition value (t yp .) unit v res- en 0.2 v k res-drop 90 % 9. green mode operation to improve the system efficiency of the power supply under light load conditions the FAN6230A provides green mode operation . once the FAN6230A enters green mode, the major control functions including sr gate drive are disabled and the operating current is reduced from 12 ma to 500 a. the conditions to enter and exit green mode are as follows. ? enter green m ode when the non-switching duration in burst mode (non-switching time between two burst switching bundles) is longer than 330 s. ? exit green mode when the non-switching duration in burst mode is shorter than 1 50 s or normal switching continues for longer than 256 consecutive switching cycles. ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 18 FAN6230A secondary-side synchronous rectification controller for flyback converters table 5. green mode definition parameter value (t yp .) unit t green- on 330 s t green-off 150 s n green-off 256 cycle v lpc t green-off load increasing slowly ? ? ? ? ? ? sr gate load decreasing slowly n green-off v lpc sr gate light load heavy load t green-off t green-on t green-on t green-off t green-off load step change (175s) (350s) (256 cycles) figure 32. entering and exiting green m ode additionally, there are three more transient condition s that force FAN6230A into green mode to prevent any abnormal condition. after the FAN6230A enters green mode during the following transient, the switching will resume after 256 switching cycles. ? the lpc voltage should rise above 90% of sampled lpc voltage of the previous switching cycle. if the 90% of the lpc sampling voltage less than v lpc_th , the FAN6230A enters into green mode instant. ? when the res voltage drops more than 10% compared to the res voltage of the previous switching cycle, the FAN6230A enters into green mode. 10 . charge pump operation to ensure its normal operation even with low supply voltage in cc operation in charger application, the FAN6230A has an integrated charge pump circuit. the internal charge pump circuits can be divided into two main stages. the front is the voltage clamping stage which is an ldo which provides power for the charge pump circuit. the charge pump stage has a voltage doubling mode and bypass mode, the selection of which is determined by to the voltage on the vin pin as shown in figure 33. when the vin pin voltage is below 8 v, the charge pump is in voltage doubling mode. then, the voltage clamping stage regulates its output around 2.6 v so that the charge pump can provide 5.2 v at the vdd pin. when the charge pump stage is in bypass mode , the voltage clamping circuit regulates v clamp at 5.5 v , which is directly connected to vdd bypassing the charge pump. for 5 v output charger applicati on s , the charge pump stage is in voltage doubling mode most of the time to maintain a stable 5.2 v vdd supply voltage . to reduce the power consumption of the FAN6230A, the charge pump stage is in bypass mode in green mode with constant voltage regulation . to stabilize the operation of the clamping stage, a 1 f ceramic capacitor is typically used for v clamp and cpn, respectively. for the vdd capacitor, 1-2 f is recommended since too large of a capacitor can slow down the startup of the FAN6230A. vin 8v/7v charge pump x2 green dis & bypass vclamp vdd cp cn + - vdd uvlo ( bg ) cc _mode s 0 mux 1 2.6v 5.5v figure 33. internal charge pump control circuit v clamp c vdd c pn s1 s4 s3 s2 vdd dis & bypass s1 oscillator s1 s2 s3 s4 s2 s3 s4 dis & bypass cp cn figure 34. charge pump circuit and timing diagram ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 19 FAN6230A secondary-side synchronous rectification controller for flyback converters figure 35 shows the circuit for the power on sequence and the internal signals that connect to the reset pin of d flip flop disabling the sr gate drive signal. detailed description of each signal is summarized in table 6. table 6. detailed description of each signal signals to disable sr description green green mode res_short res pin voltage is below 0.2 v vdd_ovp vdd pin voltage is higher than 7 v max_period lpc voltage rising above v lpc_th is not detected longer than 24 s and 50 s for cv mode and cc mode, respectively. pow_on vdd is higher than 3.35 v en_32ms 32 ms after vdd rises above 3.35 v lpc_rdy lpc pin voltage is higher than v lpcth . 500 s power up delay is also incorporated. 10 11 vdd drv d clk rst q d f/f en32ms t_inhibit turn off trigger vdd ovp res_short max_period pow_on lpc_rdy green causal predict control linear predict control gate limit lpc detect + - 32ms delay vdd 3.35v/3v en32ms pow_on figure 35. conditions to disables sr switching figure 36 shows the corresponding startup and shutdown waveforms. 1v 2.6v vin v clamp 2.6v 5.5v vdd 2.6v 5.2v charge pump off and bypass 8v 7v 5.2v charge pump on 3.35v power on 3v sr switching 32ms 5.5v figure 36. power on sequence waveform ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 20 FAN6230A secondary-side synchronous rectification controller for flyback converters 11 . cable compensation the FAN6230A has a built-in cable compensation circuit to provide regulated constant voltage at the end of the cable over the entire load range in cv mode. t he voltage drop across the load cable is compensated by adjusting the reference voltage of the internal shunt regulator as shown in figure 37. 11 pgnd 16 14 1 vref cathode 13 comrl + - cable comp. comrh 3,4,12 agnd 1.25v vo r ref1 r ref2 figure 37. cable compensation the cathode pin of the FAN6230A is typically connected to an opto-coupler to implement feedback to the primary side controller. based on the control mechanism as addressed above, the setup of the cable compensation circuit can be described as follows: 2 0.8 period t ?? ?? ? ? ? ? ? ? ? ?? ?? ?? ?? ?? sr_on ref1 ref2 out comr ref2 t rr v 1.25v r r ( 11 ) it is typical to connect a 1 nf bypass capacitor in parallel with the resistors for comrh/l when the cable compensation function is used. since the output current is estimated based on the conduction time of sr mosfet, the cable compensation gain should be adjusted if the operation mode (ccm or dcm) changes with line voltage. thus, FAN6230A has two pins for cable compensation gain setting (comrh and comrl) for high line and low line, respectively. when the compensation gain doesn t have to be adjusted with line voltage, connect comrl pin to vdd. then, the cable compensation gain for low line and high line is solel y determined by the resistor on comrh pin. the comrh and comrl pin can be also shorted to ground if no cable compensation is required; the comr pin application is expressed in the table below: table 7. comr controller method comrh comrl pins of cable compensation vcomrh vcomrl vcomrh & vcomrl program h/l line cable compensation vcomrh v dd vcomrh program h/l line cable compensation v dd 10 nf default cable compensation 0 0 no cable compensation 12 . res dropping protection res voltage is sampled and held as a reference voltage, v res , during the rising edge of the v lpc and through t lpc- en . once v res drops below 90% of the previous sampled and held, the green mode function could be trigger. then sr gate drive signal is turned off immediately, as shown in figure 38. when the output voltage drops rapidly, voltage-second balance on the primary-side magnetizing inductor, l m , may not be satisfied. the res-dropping protection activates to prevent driving signals overlapping. + - + - r 9r smp_2 res_drop c smp_2 res v smp_2 = 0.9*res smp lpc t lpc_en smp_2 v smp_2 sr_gate res res_drop enter green mode v smp_2 = 0.9*res figure 38. v res dropping protection 13. under-voltage lockout (uvlo) v dd can serve as uvlo protection. the on and off thresholds of v dd are 3.35 v and 3 v, respectively. with ultra-low v dd thresholds , the FAN6230A can be used in low output voltage applications. ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 21 FAN6230A secondary-side synchronous rectification controller for flyback converters 14. causal period protection ( cp p) when the causal function fails in ccm operation, such as the first period is long er than next period of switching cycle, the sr will have an overlap issue . to prevent the sr gate from faulty triggering until next pwm rising, an internal causal period protection is integrated . if the second period (t period (n+1)) is more than first period (t period (n )) of 150%, meaning t period (n+1) > t period (n)150%, sr gate pulse is disabled in the next period of switching cycle, shown in figure 39. v lpc v gs.sr smp t lpc-en t lpc-en one cycle skipping t lpc-en t period (n) t period (n+1) [ t p e r i o d ( n + 1 ) > t p e r i o d ( n ) x 1 5 0 % ] n o s r g a t e a t n e x t c y c l e n o s r g a t e figure 39. causal period protection ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 22 FAN6230A secondary-side synchronous rectification controller for flyback converters layout guidelines vin res cathode pgnd lpc v out FAN6230A r 1 r 2 r 5 q 1 gate q 2 i sr v det v lpc n : 1 vclamp vdd cp cn r 3 r 4 vref r 6 v ref opto comrl comrh v in lm i m r 7 r 8 c 1 c 2 c 3 c 4 c 5 c 6 r 9 r 10 t primary side pgnd primary side pgnd secondary side pgnd secondary side pgnd v res agnd 1 2 3 4 5 c 9 c 12 figure 40. simplified typical application circuit layout plays a critical role to ensure normal operation of the FAN6230A . using a simplified application circuit as an example illustrat es the issues to consider while laying out the pcb. as shown in figure 40 , c 1 and c 2 are the input and output capacitor, respectively. t is the flyback transformer. q 1 is the primary side main switch. q 2 is the secondary side sr mosfet controlled by the FAN6230A. the main current flows through the transformer secondary side winding, c 2 and q 2 . so , the loop formed by the transformer secondary side winding, c 2 and q 2 should be kept as small as possible. the power ground 1 should be connected to power ground 2 first and then to the pgnd pin. since the charge pump output provides the supply voltage to drive the mosfet gate, the loop from the gate pin to the gate of q 2 and from q 2 source to the ground of c 6 should be kept as small as possible. therefore, connect the power ground 3, 4 and 5 together first and then to the pgnd pin of the FAN6230A . the resistors r 5 and r 6 sense the output voltage. so the ground of r 6 can be connected to the converter output capacitors or at the load side after the cable to get good voltage regulation. and the ground of r 6 should return to agnd of the ic directly to minimize noise. resistor r 9 and r 10 are used for cable compensation. the grounds of both resistors should be connected together first and then tied to the agnd of the ic. finally, the agnd and pgnd of the ic should be connected together with a single trace on the pcb as shown by the orange arrow. it is important to make the ground traces width as larger as possible for better noise immunity. ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 23 FAN6230A secondary-side synchronous rectification controller for flyback converters quick setup example for lpc and res voltage divider s design specifications ? m ax imum i nput voltage: 375 v dc ( 265 v ac ) ? m in imum input voltage : 80 v dc (90 v ac with 10 v dc ripple) ? output voltage : 5 v ? cable drop compensation: 0.4 v ? transformer turns ratio : n= 13 (np/ns) ? maximum sr drain voltage: 375/ 13 +(5+0.4)=34.24 v ? m in imum sr drain voltage : 80/ 13 +(5+0.4)=11.55 v . 2 2 2 5 ( .) 1 2 1 2 1 2 1 ( ) (11.55 ) 0.74 15.61 in min out lpc high l v max v r r r v v v v r r n r r r r ? ? ? ? ? ? ? ? ? ? ? ? ? . 2 2 2 1 2 1 2 1 2 1 ( ) 1 (34.24 ) 4.2 8.15 in max out dd v r r r v v v v r r n r r r r ? ? ? ? ? ? ? ? ? ? ? 12 2 8.15 15.61 rr r ? ? ? ? 4 4 4 ( in.) 3 4 3 4 3 4 1 ( ) (5.4 ) 0.4 13.5 out res m r r r v v v v r r r r r r ? ? ? ? ? ? ? ? ? 4 4 4 3 4 3 4 3 4 1 ( ) 1 (5.4 ) 4.2 1.28 out dd r r r v v v v r r r r r r ? ? ? ? ? ? ? ? ? ? 34 4 1.28 13.5 rr r ? ? ? ? t he scale-down ratio (lpc/res ratio) should be larger than 2.25 to gu arantee that sr gate is turned off before the secondary side diode current reaches zero. selecting 12 2 12.12 rr r ? ? and considering exceed 20% margin on lpc/res ratio, 34 12 42 /(2.25 1.2) 4.4 rr rr rr ? ? ? ? ? v sec n:1 vo v in q sr v ct lpc + - c t i chr i dischr v lpc-th v lpc sr gate r 1 r 2 r 3 r 4 res zcd on trig off trig logic block v ds-sr (det) v out i m v in /n primary mosfet v gs synchronous rectifier mosfet v ct v lpc v in /n+v out body diode of sr mosfet sr dead time v lpc-th v lpc-en i m,min v ds.sr figure 41. simplified linear-predict block ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 24 FAN6230A secondary-side synchronous rectification controller for flyback converters when flyback converter operates in dcm, the primary side mosfet voltage (v ds.pri ) oscillates when the secondary side diode current reaches zero, which is caused by the resonance between the effective output capacitor of the mosfet and magnetizing inductance of the transformer. this also causes oscillation on the sr mosfet voltage (v ds. sr ) as illustrated below where the peak to peak amplitude of the sr drain voltage is twice the output voltage. as input voltage drops causing the oscillation amplitude ( 2v o ) to be larger than the nominal sr drain voltage (v in /n+v o ), the oscillation on the lpc voltage can cause shrink of sr gate in next cycle since the oscillation is clamped at the peak. to avoid an abnormal condition, it is recommend ed to design the proper turn ratio of the transformer such that sr gate voltage does not shrink if sr mosfet voltage of 90% (0.9 v ds.sr.pk ) is higher than 2v o and v in is equal to the average of maximum dc voltage plus minimum dc voltage for consideration . refer to the following calculation: _ _ _ _ _ _ ( ) 0.9 () 0.9 : 0.5 ( ) 2 in in det resonance tr det resonance tr in dc avg dc max dc min det resonance o vv vo v n v n vo when v v v v when v v ? ? ? ? ? ? ? ? ? ?? with the design example, v ac =90 v, v o = 12 v, i o =1.56 a, c in =44 f; 112 7.63 24 ( ) 12 0.9 tr tr nn ? ? ? ? v ds.sr 0.9 v ds.sr.pk v in /n+v o v o v o v ds.pri v in nv o nv o v in +nv o 0.9 v lpc.pk v lpc.pk= v ds.sr /r lpc v lpc v i n > n v o v ds.sr 0.9 v ds.sr.pk v in /n+v o v o v o v ds.pri v in nv o nv o v in +nv o 0.9 v lpc.pk v lpc.pk v lpc v ds.sr.pk t lpc.en can cause shrink of sr gate v i n < n v o figure 42. condition that can cause sr miss-trigger by the resonance of lpc voltage it is recommended that a series 20 resistor is added to the gate of FAN6230A to protect the ga te pin from big negative voltage spike that could happen in power supply appli cation. ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 25 FAN6230A secondary-side synchronous rectification controller for flyback converters typical application circuit (flyback charger) application fairchild devices input voltage range output adaptive charger fan5 01 , FAN6230A 90~265 v ac 5 v / 2.5 a features ? ultra-low standby power consumption ? high efficiency vo (+) ns u2 fod817 a cy 100pf vo (-) q2 fdmc86520l cathode r12 10 r31 20 r20 11k r32 910 r33 3k r30 24k c23 1nf c14 100nf c11 390f/6.3v gate fb cs vdd vs comp sd sgnd hv pgnd d1~d4 ffm107 ac in u1 fan501 np na f1 2a/250v l1 470h r1 56k r2 300k c3 470pf/1kv r3 10 r6 0 r5 100 r9 56.2k c7 27pf c4 22f r7 0 d5 1n4148 rs1 4.3 c6 470pf r24 34k c1 12f/ 400v c2 12f/ 400v d6 ffm107 r23 17.4k 1 23 4 5 67 8 9 10 rs 1.3 ref cn res comrh comrl cp vclamp vin agnd vdd cathode lpc nc gate pgnd r34 27.4k r41 8.66k c5 1f 82 10 3 56 7 9 12 11 13 14 1 16 15 4 c8 1f c18 1f u3 fan6230_mlp c13 470pf c15 6.8nf q1 fcu900n60z r19a 274k r19 221k agnd c19 390f/6.3v r14 32.4k r10 110k r13 82k r11 100k r8 10 cl 0 u2 fod817 a c12 47nf c9 47nf 21 76 45 figure 43. schematic of typical application circuit figure 44. standby power and measured efficiency ? 20 14 fairchild semiconductor corporation www.fairchildsemi.com FAN6230A ? rev. 1.1 26 FAN6230A secondary-side synchronous rectification controller for flyback converters transformer specification ? core: epc -1716 pc95 ? bobbin: epc -1716 1 4 auxilliary winding secondary winding b o b b i n primary winding 2 3 3 5 primary winding 5 copper shielding 6 7 s e s e s e s e e s e figure 45. transformer table 8. transformer winding specifications no. terminal wire turns isolation layer turns start pin end pin w1 (pri. winding) 1 3 2uew 0.27*1 26 2 w2 (aux. winding) 4 5 2uew 0.20*2 8 2 5 x 2uew 0.20*2 8 w3 (sec. winding) 7 6 2uew 0.60*2 4 2 w4 (shielding) 5 x co pper shielding 1 2 w5 (pri. winding) 3 2 2uew 0.27*1 26 3 core shielding copper 5 co pper shielding 1 2 pin specification remark primary-side inductance 1-2 540 ? h ? 5% 80 khz, 1 v primary-side effective leakage inductance 1-2 30 ? h ? 5% 80 khz, 1 v , short o ne secondary winding 1 4 5 8 9 12 13 16 0.10 c a b 0.05 c ? ; ? ; ? 0.50 (0.25) bottom view front view ? ? ? 0.08 c 0.10 c 3.0 3.0 0.05 c pin#1 ident 0.05 c recommended land pattern top view a b 0.50 0.32(16x) 0.50(16x) 1.85 2.30 3.30 3.30 2.30 1.85 (0.23) 2x 2x c seating plane ? ? pin#1 ident (0.25) ? notes: a. conforms to jedec registration, mo-220. variation weed-4. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 2009. d. land pattern recommendation is for reference only, it may need to be adjusted to match your smt process capabilities. e. drawing filename: mkt-mlp16mrev2. please see note "d" www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductors product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. typical parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including typic als must be validated for each customer application by customers technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your localsales representative ? semiconductor components industries, llc |
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