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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad8012 * dual 350 mhz low power amplifier * protected under u.s. patent number 5,537,079. features low power 1.7 ma/amplifier supply current fully specified for 5 v and +5 v supplies high output current, 125 ma high speed 350 mhz, ? db bandwidth (g = +1) 150 mhz, ? db bandwidth (g = +2) 2,250 v/ s slew rate 20 ns settling time to 0.1% low distortion ?2 dbc worst harmonic @ 500 khz, r l = 100 ?6 dbc worst harmonic @ 5 mhz, r l = 1 k good video specifications (r l = 1 k , g = +2) 0.02% differential gain error 0.06 differential phase error gain flatness 0.1 db to 40 mhz 60 ns overdrive recovery low offset voltage, 1.5 mv low voltage noise, 2.5 nv/ hz available in 8-lead soic and 8-lead msop applications xdsl, hdsl line drivers adc buffers professional cameras ccd imaging systems ultrasound equipment digital cameras functional block diagram 8 7 6 5 1 2 3 4 out1 ?n1 +in1 +v s out2 ?n2 +in2 ? s ad8012 product description the ad8012 is a dual, low power, current feedback amplifier capable of providing 350 mhz bandwidth while using only 1.7 ma per amplifier. it is intended for use in high frequency, wide dynamic range systems where low distortion and high speed are essential and low power is critical. with only 1.7 ma of supply current, the ad8012 also offers exceptional ac specifications such as 20 ns settling time and 2,250 v/ s slew rate. the video specifications are 0.02% differ- ential gain and 0.06 degree differential phase, excellent for such a low power amplifier. in addition, the ad8012 has a low offset of 1.5 mv. the ad8012 is well suited for any application that requires high performance with minimal power. the product is available in standard 8-lead soic or msop packages and operates over the industrial temperature range C 40 c to +85 c. r l ? ?0 ?0 10 1k 100 distortion ?dbc ?0 ?0 ?0 ?0 g = +2 v out = 2v p-p r f = 750 third second figure 1. distortion vs. load resistance, v s = 5v, frequency = 500 khz amp 1 v in v ref r2 r1 r l = 100 or 135 v out np:ns transformer line power in db +v s + ? s + figure 2. differential drive circuit for xdsl applications
important links for the ad8012 * last content update 08/18/2013 06:36 pm parametric selection tables find similar products by operating parameters documentation an-356: user's guide to applying and measuring operational amplifier specifications mt-057: high speed current feedback op amps mt-051: current feedback op amp noise considerations mt-034: current feedback (cfb) op amps mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to-voltage converters a stress-free method for choosing high-speed op amps ug-129: evaluation board user guide ug-128: universal evaluation board for dual high speed op amps in soic packages current feedback amplifiers part 1: ask the applications engineer-22 current feedback amplifiers part 2: ask the applications engineer-23 two-stage current-feedback amplifier design tools, models, drivers & software analog filter wizard 2.0 ad8012 spice macro model evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad8012 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
rev. b ? ad8012?pecifications parameter conditions min typ max unit dynamic performance C 3 db small signal bandwidth g = +1, v out < 0.4 v p-p, r l = 1 k ? 270 350 mhz g=+2, v out < 0.4 v p-p, r l = 1 k ? 95 150 mhz g=+2, v out < 0.4 v p-p, r l = 100 ? 90 mhz 0.1 db bandwidth v out < 0.4 v p-p, r l = 1 k ? /100 ? 40/23 mhz large signal bandwidth v out = 4 v p-p 75 mhz slew rate v out = 4 v p-p 2,250 v/ s rise and fall time v out = 2 v p-p 3 ns settling time 0.1%, v out = 2 v p-p 20 ns 0.02%, v out = 2 v p-p 35 ns overdrive recovery 2 overdrive 60 ns noise/harmonic performance distortion v out = 2 v p-p, g = +2 second harmonic 500 khz, r l = 1 k ? /100 ? C 89/ C 73 dbc 5 mhz, r l = 1 k ? /100 ? C 78/ C 62 dbc third harmonic 500 khz, r l = 1 k ? /100 ? C 84/ C 72 dbc 5 mhz, r l = 1 k ? /100 ? C 66/ C 52 dbc output ip3 500 khz, ? f = 10 khz, r l = 1 k ? /100 ? 30/40 dbm imd 500 khz, ? f = 10 khz, r l = 1 k ? /100 ? C 79/ C 77 dbc crosstalk 5 mhz, r l = 100 ? C 70 db input voltage noise f = 10 khz 2.5 nv/ hz input current noise f = 10 khz, +input, C input 15 pa/ hz differential gain f = 3.58 mhz, r l = 150 ? /1 k ? , g = +2 0.02/0.02 % differential phase f = 3.58 mhz, r l = 150 ? /1 k ? , g = +2 0.3/0.06 degrees dc performance input offset voltage 1.5 4mv t min C t max 5mv open-loop transimpedance v out = 2 v, r l = 100 ? 240 500 k ? t min C t max 200 k ? input characteristics input resistance +input 450 k ? input capacitance +input 2.3 pf input bias current +input, C input 3 12 a +input, C input, t min C t max 15 a common-mode rejection ratio v cm = 2.5 v C 56 C 60 db input common-mode voltage range 3.8 4.1 v output characteristics output resistance g = +2 0.1 ? output voltage swing 3.85 4v output current t min C t max 70 125 ma short-circuit current 500 ma power supply supply current/amp 1.7 1.8 ma t min C t max 1.9 ma operating range dual supply 1.5 6.0 v power supply rejection ratio C 58 C 60 db specifications subject to change without notice. dual supply (@ t a = 25 c, v s = 5 v, g = +2, r l = 100 , r f = r g = 750 , unless otherwise noted.)
rev. b ad8012 ? single supply parameter conditions min typ max unit dynamic performance C 3 db small signal bandwidth g = +1, v out < 0.4 v p-p, r l = 1 k ? 220 300 mhz g=+2, v out < 0.4 v p-p, r l = 1 k ? 90 140 mhz g=+2, v out < 0.4 v p-p, r l = 100 ? 85 mhz 0.1 db bandwidth v out < 0.4 v p-p, r l = 1 k ? /100 ? 43/24 mhz large signal bandwidth v out = 2 v p-p 60 mhz slew rate v out = 3 v p-p 1,200 v/ s rise and fall time v out = 2 v p-p 2 ns settling time 0.1%, v out = 2 v p-p 25 ns 0.02%, v out = 2 v p-p 40 ns overdrive recovery 2 overdrive 60 ns noise/harmonic performance distortion v out = 2 v p-p, g = +2 second harmonic 500 khz, r l = 1 k ? /100 ? C 87/ C 71 dbc 5 mhz, r l = 1 k ? /100 ? C 77/ C 61 dbc third harmonic 500 khz, r l = 1 k ? /100 ? C 89/ C 72 dbc 5 mhz, r l = 1 k ? /100 ? C 78/ C 52 dbc output ip3 500 khz, r l = 1 k ? /100 ? 30/40 dbm imd 500 khz, r l = 1 k ? /100 ? C 77/ C 80 dbc crosstalk 5 mhz, r l = 100 ? C 70 db input voltage noise f = 10 khz 2.5 nv/ hz input current noise f = 10 khz, +input, C input 15 pa/ hz black level clamped to +2 v, f = 3.58 mhz differential gain r l = 150 ? /1 k ? 0.03/0.03 % differential phase r l = 150 ? /1 k ? 0.4/0.08 degrees dc performance input offset voltage 1 3mv t min C t max 4mv open-loop transimpedance v out = 2 v p-p, r l = 100 ? 200 400 k ? t min C t max 150 k ? input characteristics input resistance +input 450 k ? input capacitance +input 2.3 pf input bias current +input, C input 3 12 a +input, C input, t min C t max 15 a common-mode rejection ratio v cm = 1.5 v to 3.5 v C 56 C 60 db input common-mode voltage range 1.5 to 3.5 1.2 to 3.8 v output characteristics output resistance g = +2 0.1 ? output voltage swing 1 to 4 0.9 to 4.2 v output current t min C t max 50 100 ma short-circuit current 500 ma power supply supply current/amp 1.55 1.75 ma t min C t max 1.85 ma operating range single supply 3 12 v power supply rejection ratio C 58 C 60 db specifications subject to change without notice. (@ t a = 25 c, v s = +5 v, g = +2, r l = 100 , r f = r g = 750 , unless otherwise noted.)
rev. b ? ad8012 maximum power dissipation t he maximum power that can be safely dissipated by the ad8012 is limited by the associated rise in junction temperature. the m axi- mum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction t emperature of +175 c for an extended period can result in de vice failure. the output stage of the ad8012 is designed for maximum load current capability. as a result, shorting the output to common can cause the ad8012 to source or sink 500 ma. to ensure proper operation, it is necessary to observe the maximum power derating curves. direct connection of the output to either power supply rail can destroy the device. ambient temperature ? c ?0 0 t j = 150 c 2.0 1.5 1.0 maximum power dissipation ?w 8-lead soic package ?0 ?0 010203 040506 070 8090 8-lead msop 0.5 ?0 ?0 figure 3. plot of maximum power dissipation vs. temperature for ad8012 0.1 f 0.1 f 10 f 10 f r l v in v out 750 750 49.9 +v s ? s + + test circuit 1. gain = +2 0.1 f 0.1 f 10 f 10 f r l v in v out 750 750 53.6 +v s ? s + + test circuit 2. gain = ? t est circuits
rev. b ad8012 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8012 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v internal power dissipation 2 soic package (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 w msop package (rm) . . . . . . . . . . . . . . . . . . . . . . . . 0.6 w input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 v output short-circuit duration . . . . . . . . . . . . . . . . . .o bserve power derating curves storage temperature range rm, r . . . . . . C 65 c to +125 c operating temperature range (a grade) . . . C 40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air at +25 c. 8-lead soic package: ja = 155 c/w 8-lead msop package: ja = 200 c/w ordering guide model temperature range package description package options branding ad8012ar C 40 c to +85 c 8-lead soic r-8 ad8012ar-reel C 40 c to +85 c13 tape and reel r-8 ad8012ar-reel7 C 40 c to +85 c7 tape and reel r-8 ad8012arm C 40 c to +85 c 8-lead msop rm-08 h6a ad8012arm-reel C 40 c to +85 c13 tape and reel rm-08 h6a ad8012arm-reel7 C 40 c to +85 c7 tape and reel rm-08 h6a ad8012armz * C 40 c to +85 c 8-lead msop rm-08 h6a AD8012ARMZ-REEL * C 40 c to +85 c13 tape and reel rm-08 h6a AD8012ARMZ-REEL7 * C 40 c to +85 c7 tape and reel rm-08 h6a * z = pb-free product.
rev. b ? ad8012?ypical performance characteristics 20mv 5ns tpc 1. 100 mv step response; g = +2, v s = 2.5 v or 5 v, r l = 1 k ? * 1v 10ns tpc 2. 4 v step response; g = +2, v s = 5 v, r l = 1 k ? 20mv 5ns tpc 3. 100 mv step response; g = ?, v s = 2.5 v or 5 v, r l = 1 k ? * 1v 10ns tpc 4. 4 v step response; g = ?, v s = 5 v, r l = 1 k ? 20mv 5ns tpc 5. 100 mv step response; g = +2, v s = 2.5 v or 5 v, r l = 100 ? * 500mv 10ns tpc 6. 2 v step response; g = +2, v s = 2.5 v, r l = 100 ? * v s = 2 .5 v operation is identical to v s = +5 v single-supply operation.
rev. b ad8012 ? 1v 10ns tpc 7. 4 v step response; g = +2, v s = 5 v, r l = 100 ? 20mv 5ns tpc 8. 100 mv step response; g = ?, v s = 2.5 v or 5 v, r l = 100 ? * 500mv 10ns tpc 9. 2 v step response; g = ?, v s = 2.5 v, r l = 100 ? 1v 10ns tpc 10. 4 v step response; g = ?, v s = 5 v, r l = 100 ? r l ? ?0 ?0 10 1k 100 distortion ?dbc ?0 ?0 ?0 ?0 g = +2 v out = 2v p-p r f = 750 third second tpc 11. distortion vs. load resistance; v s = 5 v, frequency = 500 khz third r l = 1k frequency mhz distortion dbc 1 10 20 second r l = 1k third r l = 100 second r l = 100 ?0 ?0 ?0 ?00 g = +2 v out = 2v p-p r f = 750 tpc 12. distortion vs. frequency; v s = 5 v
rev. b ? ad8012 frequency mhz 0.1 10 100 g = +2 v o = 0.3v p-p r f = 750 r l = 100 v s = 5v 1 0.3 ?.3 0.2 ?.1 0.1 0 ?.2 ?.4 ?.5 0.4 0.5 normalized gain db tpc 13. gain flatness; v s = 5 v r l ? ?0 ?0 10 1k 100 distortion ?dbc ?0 ?0 ?0 ?0 g = +2 v out = 2v p-p r f = 750 second third tpc 14. distortion vs. load resistance; v s = +5 v, frequency = 500 khz ?0 ?00 10 20 distortion ?dbc ?0 ?0 g = +2 v out = 2v p-p r f = 750 frequency ?mhz 1 third r l = 1k second r l = 1k third r l = 100 second r l = 100 tpc 15. distortion vs. frequency; v s = +5 v frequency mhz 0.1 10 100 g = +2 v o = 0.3v p-p r f = 750 r l = 100 v s = +5v 1 0.3 ?.3 0.2 ?.1 0.1 0 ?.2 ?.4 ?.5 0.4 0.5 normalized gain db tpc 16. gain flatness; v s = +5 v frequency mhz 3 ? 100 500 2 ? v o = 0.3v p-p r f = 750 r l = 100 v s = 5v 1 0 ? ? 4 5 g = +10 g = +2 g = +1 ? 10 1 normalized gain db tpc 17. frequency response; v s = 5 v frequency mhz 3 ?5 100 500 0 ? g = +2 r f = 750 r l = 100 v s = 5v ? ? ?2 ?8 6 9 ?1 10 1 output voltage dbv 1v rms tpc 18. output voltage vs. frequency; v s = 5 v, g = +2, r l = 100 ?
rev. b ad8012 ? frequency ?mhz ?0 ?0 100 500 ?0 ?0 v in = 0.2v p-p v s = 5v, +5v ?0 ?0 ?0 ?0 ?0 0 1 0.03 0.1 10 cmrr db ?00 tpc 19. cmrr vs. frequency; v s = 5 v, +5 v frequency ?mhz normalized gain db 3 ? 100 500 2 ? v o = 0.3v p-p r f = 750 r l = 100 v s = +5v 1 0 ? ? 4 5 g = +10 g = +2 g = +1 ? 10 1 tpc 20. frequency response; v s = +5 v frequency mhz output voltage dbv ? ?1 100 500 ? ?5 g = +2 r f = 750 r l = 100 v s = +5v ? ?2 ?8 ?4 0 3 ?7 10 1 1vrms tpc 21. output voltage vs. frequency; v s = +5 v, g = +2, r l = 100 ? 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100k 1m 10m 100m 500m frequency ?hz ?0 ?0 ?00 psrr ?db v s = +5v or 5v g = +2 r f = 750 ?srr +psrr tpc 22. psrr vs. frequency; v s = 5 v, +5 v frequency ?mhz output resistance 100 0.1 100 500 1 10 1k 0.01 1 0.03 0.1 10 v s = 5v v s = +5v g = +2 r f = 750 tpc 23. output resistance vs. frequency 135 115 95 75 55 15 ? frequency hz 35 t z db 0 phase ?degrees ?0 ?0 ?20 ?60 ?00 ?40 ?80 t z (s) phase 1k 10k 100k 1m 10m 100m 1g tpc 24. open-loop transimpedance and phase vs. frequency
rev. b ?0 ad8012 load ? 10 1k 10k 100 7 1 6 3 5 4 2 0 8 9 swing v p-p +5v 5v tpc 25. output swing vs. load frequency ?hz 100 10k 1k 3.6 2.4 3.4 2.8 3.2 3.0 2.6 2.2 2.0 3.8 4.0 current noise +in/?n voltage noise 26 14 24 18 22 20 16 12 10 28 30 input current noise ?pa/ hz 100k input voltage noise nv/ hz tpc 26. noise vs. frequency 9 8 7 6 5 4 3 2 3 4 5 6 7 8 9 10 11 1 0 f = 5mhz g = 2 r f = 750 r l = 100 r l = 1k total supply voltage v peak-to-peak output at 5mhz ( 1% thd) v tpc 27. output swing vs. supply 0.1% 5ns g = +2 r f = 750 r l = 100 2v step t = 0 output voltage error ?0.1%/div tpc 28. settling time, v s = 5 v frequency ?mhz 3 ? 100 500 2 ? v o = 0.3v p-p r f = 750 r l = 1k 1 0 ? ? 4 5 g = +10 g = +2 g = +1 ? 10 1 normalized gain db tpc 29. frequency response; v s = 5 v 0.3 ?.3 0.2 ?.1 v o = 0.3v p-p g = +2 r f = 750 r l = 1k 0.1 0 ?.2 ?.4 0.4 0.5 ?.5 frequency ?mhz 0.1 10 1 100 normalized gain ?db tpc 30. gain flatness; v s = 5 v
rev. b ad8012 ?1 frequency ?mhz input referred error db ?0 ?00 100 500 ?0 ?0 ?0 ?0 ?0 ?10 ?0 ?0 ?20 1 0.03 0.1 10 side 1 side 2 driver v o = 2v p-p r l = 100 tpc 31. crosstalk vs. frequency frequency ?mhz 3 ? 100 500 2 ? v o = 0.3v p-p r f = 750 r l = 1k 1 0 ? ? 4 5 g = +10 g = +2 g = +1 ? 10 1 normalized gain db tpc 32. frequency response; v s = +5 v normalized gain ?db 0.3 ?.3 0.2 ?.1 v o = 0.3v p-p r f = 750 r l = 1k 0.1 0 ?.2 ?.4 0.4 0.5 ?.5 frequency ?mhz 0.1 10 1 100 tpc 33. gain flatness; v s = +5 v v out , 2v/div 20ns +3v 0v 0v v out v out v in v in 0v 0v ?v tpc 34. overdrive recovery; v s = 5 v, g = +2, r f = 750 ? , r l = 100 ? , v in = 3 v p-p (t = 1 s)
rev. b ?2 ad8012 theory of operation the ad8012 is a dual, high speed cf amplifier that attains new levels of bandwidth (bw), power, distortion, and signal swing capability. its wide dynamic performance (including noise) is the result of both a new complementary high speed bipolar process and a new and unique architectural design. the ad8012 uses a two-gain stage complementary design approach versus the traditional single-stage complementary mirror structure sometimes referred to as the nelson amplifier. though twin stages have been tried before, they typically consumed high power since they were of a folded cascade design, similar to that of the ad9617. this design allows for the standing or quiescent current to add to the high signal or slew current-induced stages. in the time domain, the large signal output rise/fall time and slew rate is typically controlled by the small signal bw of the amplifier and the input signal step amplitude, respectively, and not the dc quiescent current of the gain stages (with the excep- tion of input level shift diodes q1/q2). using two stages versus one also allows for a higher overall gain bandwidth product (gbwp) for the same power, resulting in lower signal distortion and the ability to drive heavier external loads. in addition, the second-gain stage also isolates (divides down) a3 s input reflected load drive and the nonlinearities created, resulting in relatively lower distortion and higher open-loop gain. overall, when high external load drive and low ac distortion is a requirement, a twin-gain stage integrating amplifier like the ad8012 will provide excellent results for lower power over the traditional single stage complementary devices. in addition, because the ad8012 is a cf amplifier, closed-loop bw varia tions versus external gain variations (varying rn) will be much lower compared to a vf op amp, where the bw varies inversely with gain. another key attribute of this amplifier is its ability to run on a single 5 v supply partially because of its wide common-mode input and output voltage range capability. for 5 v supply op eration, the device consumes half the quiescent power (vs. 10 v supply) with little degradation in its ac and dc perfor- mance characteristics. see data sheet comparisons. dc gain characteristics gain stages a1/a1b and a2/a2b combined provide negative feedforward transresistance gain as shown in figure 4. stage a3 is a unity-gain buffer that provides external load isolation to a2. each stage uses a symmetrical complementary design (a3 is also complementary though not explicitly shown). this is done to reduce both second-order signal distortion and overall quiescent power as previously described. in the quasi dc to low frequency region, the closed-loop gain relationship can be approximated as: these basic relationships are common to all traditional opera- tional amplifiers. v p q1 q2 ipp ipn inp ipn v n a1 a1 z i iq1 q3 q4 ie c p 1 c p 1 z2 a2 c l r n icq ?io r f v o c d icq + io iq1 ad8012 a2 c p 2 z1 = r1 || c1 z1 c d a3 r l z1 ? i ? i ir ?ifc ir + ifc v o i figure 4. simplified block diagram g= +r r g=?r r fn fn 1/ / noninverting operation inverting operation
rev. b ad8012 ?3 applications line driving for hdsl high bitrate digital subscriber line (hdsl) is becoming popular as a means of providing full duplex data communication at rates up to 1.544 mbps or 2.048 mbps over moderate distances via conventional telephone twisted pair wires. traditional t1 (e1 in europe) requires repeaters every 3,000 feet to 6,000 feet to boost the signal strength and allow transmission over distances of up to 12,000 feet. in order to achieve repeaterless transmission over this distance, an hdsl modem requires a transmitted power level of 13.5 dbm (assuming a line impedance of 135 ? ). hdsl uses the two binary/one quaternary line code (2b1q). a sample 2b1q waveform is shown in figure 5. the digital bit stream is broken up into groups of two bits. four analog volt- ages (called quaternary symbols) are used to represent the four possible combinations of two bits. these symbols are assigned the arbitrary names +3, +1, C 1, and C 3. the corresponding voltage levels are produced by a dac that is usually part of an analog front end circuit (afec). before being applied to the line, the dac output is low-pass filtered and acquires the sinu- soidal form shown in figure 5. finally, the filtered signal is applied to the line driver. the line voltages that correspond to the quaternary symbols +3, +1, C 1, and C 3 are 2.64 v, 0.88 v, C 0.88 v, and C 2.64 v. this gives a peak-to-peak line voltage of 5.28 v. voltage +3 2.64v +1 0.88v ? ?.88v ? ?.64v symbol name dac output filtered output to line driver ? 01 +3 10 +1 11 ? 00 ? 00 +1 11 +3 10 ? 00 ? 01 ? 01 +1 11 ? 01 ? 00 figure 5. time domain representation of an hdsl signal many of the elements of a classic differential line driver are shown in the hdsl line driver in figure 6. a 6 v peak-to-peak differential signal is applied to the input. the differential gain of the amplifier (1+2 r f /r g ) is set to +2, so the resulting differen- tial output signal is 12 v p-p. as is normal in telephony applications, a transformer galvani- cally isolates the differential amplifier from the line. in this case, a 1:1 turns ratio is used. in order to correctly terminate the line, it is necessary to set the output impedance of the amplifier to be equal to the impedance of the line being driven (135 ? in this case). because the transformer has a turns ratio of 1:1, the impedance reflected from the line is equal to the line impedance of 135 ? (r refl = r line /turns ratio 2 ). as a result, two 66.5 ? resistors correctly terminate the line. 6v p-p 12v p-p 1:1 +5v ?v r f 750 r f 750 r g 1.5k 1/2 ad8012 1/2 ad8012 0.1 f 0.1 f 66.5 66.5 6v p-p 1:1 135 to receiver circuitry to receiver circuitry gain = +2 up to 12,000 feet + figure 6. differential for hdsl applications the immediate effect of back-termination is that the signal from the amplifier is halved before being applied to the line. this doubles the power the amplifier must deliver. however, the back-termination resistors also play an important second role. full-duplex data transmission systems like hdsl simulta- neously transmit data in both directions. as a result, the signal on the line and across the back termination resistors is the com posite of the transmitted and received signal. the termina- tion resistors are used to tap off this signal and feed it to the receive circuitry. because the receive circuitry knows what is being transmitted, the transmitted data can be subtracted from the digitized composite signal to reveal the received data. driving a line with a differential signal offers a number of ad vantages compared to a single-ended drive. because the two outputs are always 180 degrees out of phase relative to one another, the differential signal output is double the output am plitude of either of the op amps. as a result, the differential amplifier can have a peak-to-peak swing of 16 v (each op amp can swing to 4 v), even though the power supply is 5 v. in addition, even-order harmonics (second, fourth, sixth, and so on.) of the two single-ended outputs tend to cancel out one another, so the total harmonic distortion (quadratic sum of all harmonics) decreases compared to the single-ended case, even as the signal amplitude is doubled. this is particularly advan- tageous in the case of the second harmonic. because it is very close to the fundamental, filtering becomes difficult. in this application, the thd is dominated by the third harmonic, which is 65 db below the carrier (i.e., spurious-free dynamic range = C 65 dbc). differential line driving also helps to preserve the integrity of the transmitted signal in the presence of electromagnetic interfer- ence (emi). emi tends to induce itself equally onto both the positive and negative signal lines. as a result, a receiver with good common-mode rejection will amplify the original signal while rejecting induced (common-mode) emi.
rev. b ?4 ad8012 choosing the appropriate turns ratio for the transformer increasing the peak-to-peak output signal of the amplifier in the previous example and adding a variation in the turns ratio of the transformer can yield further enhancements to the circuit. the output signal swing of the ad8012 can be increased to about 3.9 v before clipping occurs. this increases the peak-to-peak output of the differential amplifier to 15.6 v. because the signal applied to the primary winding is now bigger, the transformer turns ratio of 1:1 can be replaced with a (step-down) turns ratio of about 1.3:1 (from amplifier to line). this steps the 7.8 v peak-to-peak primary voltage down to 6 v. this is the same secondary voltage of the earlier examples, so the resulting power delivered to the line is the same. the received signal, which is small relative to the transmitted signal, will, however, be stepped up by a factor of 1.3. amplifying the received signal in this manner enhances its signal-to-noise ratio and is useful when the received signal is small compared to the to-be-transmitted signal. the impedance reflected from the 135 ? line now becomes 228 ? (1.3 2 135 ? ). with a correctly terminated line, the amplifier must now drive a total load of 456 ? (114 ? + 114 ? + 228 ? ), considerably more than the original 270 ? load. this reduces the drive current from the op amps by about 40%. more significant, however, is the reduction in dynamic power consumption that is, the power the amplifier must consume in order to deliver the load power. increasing the output signal so that it is as close as possible to the power rails minimizes the power consumed in the amplifier. there is, however, a price to pay in terms of increased signal distortion. increasing the output signal of each op amp from the original 3 v to 3.9 v reduces the spurious-free dynamic range (s fdr) from C 65 db to C 50 db (measured at 500 khz), even though the overall load impedance has increased from 270 ? to 456 ? . layout considerations the specified high speed performance of the ad8012 requires careful attention to board layout and component selection. table i shows recommended component values for the ad8012 and figures 8 C 13 show recommended layouts for the 8-lead soic and msop packages for a positive gain. proper rf design techniques and low parasitic component selections are mandatory. the pcb should have a ground plane covering all unused por tions of the component side of the board to provide a low impedance ground path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply bypassing (see figure 7). one end should be connected to the ground plane and the other within 1/8 inch of each power pin. an additional (4.7 f to 10 f) tantalum electrolytic capacitor should be connected in parallel. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance greater than 1.5 pf at the inverting input will significantly affect high speed performance when operating at low noninverting gains. stripline design techniques should be used for long signal traces (greater than about 1 inch). they should be designed with the proper system characteristic impedance and be properly termi- nated at each end. 0.1 f inverting configuration v out r f 10 f noninverting configuration v out r g r f r t 0.1 f 10 f r t v in r g v in * r o chosen for characteristic impedance. +v s + + ? s r o * r o * * r o chosen for characteristic impedance. figure 7. inverting and noninverting configurations table i. typical bandwidth vs. gain setting resistors small signal C 3 db bw (mhz), gain r f r g r t v s = 5 v, r l = 1 k C 1 750 ? 750 ? 53.6 ? 110 +1 750 ? 49.9 ? 350 +2 750 ? 750 ? 49.9 ? 150 +10 750 ? 82.5 ? 49.9 ? 40 r t chosen for 50 ? characteristic input impedance.
rev. b ad8012 ?5 figure 8. universal soic noninverter top silkscreen figure 9. universal soic noninverter top figure 10. universal soic noninverter bottom figure 11. universal msop noninverter top silkscreen figure 12. universal msop noninverter top figure 13. universal msop noninverter bottom
rev. b c01049??2/03(b) ?6 ad8012 outline dimensions 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa revision history location page 12/03 data sheet changed from rev. a to rev. b. renumbered figures and tpcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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