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| 1. general description the TEA19162T and tea19161t are combined controller (combo) ics for resonant topologies including pfc. they provide high efficiency at all power levels. together with the tea1995t dual llc resonant sr controller, a cost-effective resonant power supply can be built. this power supply meets the ef ficiency regulations of energy star, the department of energy (doe), the eco-desi gn directive of the european union, the european code of conduct, and other guidelines. the TEA19162T is a power factor correction (pfc) controller. the ic communicates with thetea19161t on start-up sequence and pr otections. it also enables a fast latch reset mechanism. to maximize the overall system efficiency, the tea19161t allows setting the TEA19162T pfc to burst mode at a low output power level. using the tea19161t and TEA19162T combo together with the tea1995t secondary synchronous rectifier controller, a highly efficient and reliable power supply can be designed with a minimum of external compo nents. the target output power is between 90 w and 500 w. the system provides a very low no-load inpu t power (< 75 mw; total system including the tea19161t/TEA19162T combo and the tea1995t) and high efficiency from minimum to maximum load. so, no additional low-power supply is required. TEA19162T pfc controller rev. 1 ? 10 march 2016 product data sheet
TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 2 of 30 nxp semiconductors TEA19162T pfc controller 2. features and benefits 2.1 distinctive features ? complete functionality as tea19161t/TEA19162T combo ? integrated x-capacitor discharge without additional external components ? universal mains supply operat ion (70 v (ac) to 276 v (ac)) ? integrated soft start and soft stop ? accurate boost voltage regulation 2.2 green features ? valley/zero voltage switching for minimum switching losses ? frequency limitation to reduce switching losses ? reduced supply current (200 ? a) when in burst mode 2.3 protection features ? safe restart mode for system fault conditions ? continuous mode protection with demagnetization detection ? accurate overvoltage protection (ovp) ? open-loop protection (olp) ? short-circuit protection (scp) ? internal and external ic overtemperature protection (otp) ? low and adjustable overcurrent protection (ocp) trip level ? adjustable brownin/brownout protection ? supply undervoltage protection (uvp) 3. applications ? desktop and all-in-one pcs ? lcd television ? notebook adapter ? printers ? gaming console power supplies 4. ordering information 5. block diagram table 1. ordering information type number package name description version TEA19162T so8 plastic small outline packa ge; 8 leads; body width 3.9 mm sot96-1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 3 of 30 nxp semiconductors TEA19162T pfc controller fig 1. block diagram ; & $ 3 ' , 6 & + $ 5 * ( & 2 1 7 5 2 / u h v h w 9 9 ' ( 0 $ * 1 ( 7 , = $ 7 , 2 1 $ 1 ' 9 $ / / ( < ' ( 7 ( & 7 , 2 1 6 8 3 3 / < 7 ( $ 7 7 , 0 ( 5 ? v 7 , 0 ( 5 p v 8 9 3 0 d l q v 6 w d u w 0 d l q v 6 w d u w ; & d s ' l v 0 $ , 1 6 & 8 5 5 ( 1 7 7 5 $ & . , 1 * ' ( / $ < ? v f x u u h q w f r p s d u d w r u 7 , 0 ( 5 p v 7 , 0 ( 5 p v * $ 7 ( 6 ( 1 6 , 1 * 6 ( 1 6 ( 5 ( 6 , 6 7 2 5 6 ( 1 6 , 1 * ' 5 , 9 ( 5 * d w h 3 i f 7 , 0 ( 5 ? v 9 $ / / ( < ' ( 7 ( & 7 , 2 1 = ( 5 2 & 8 5 5 ( 1 7 6 , * 1 $ / , 1 7 ( 5 1 $ / 6 8 3 3 / , ( 6 6 5 g 4 6 5 g 4 0 $ , 1 6 6 ( 1 6 , 1 * & 2 1 7 5 2 / 2 9 3 f r q w u r o 7 ( 0 3 ( 5 $ 7 8 5 ( 6 ( 1 6 , 1 * 3 ) & 2 6 & , / / $ 7 2 5 * d w h 3 i f g h p d j ( [ w 2 7 3 1 7 & 0 h d v x u h ( [ w 2 7 3 0 $ , 1 6 6 ( 1 6 , 1 * p 9 9 9 6 1 6 $ 8 ; 6 8 3 , & 6 1 6 0 $ , 1 6 d d d ? $ ? $ * p d p s o l i l h u ? $ 9 2 9 % r r v w 6 r i w 6 w r s v r i w v w r s 9 2 / 3 9 6 1 6 % 2 2 6 7 ? $ 5 h v h w ) d v w / d w f k % 2 2 6 7 9 2 / 7 $ * ( 6 ( 1 6 , 1 * 2 1 7 , 0 ( & 2 1 7 5 2 / ( q g ) d v w / d w f k 9 9 3 u r w $ f w l y h 6 r i w 6 w r s 1 7 & p h d v x u h ? $ ? $ 9 6 w d u w 6 8 3 , & 6 w d u w 0 d l q v 3 u r w $ f w l y h 6 1 6 & 8 5 * $ 7 ( 3 ) & 2 & 3 9 & 4 q ' 4 5 5 h v h w ) d v w / d w f k ( q d e o h 3 i f 3 u r w $ f w l y h , q w 2 7 3 8 9 3 6 8 3 , & 6 w d u w 6 8 3 , & 2 9 3 ( q g ) d v w / d w f k 3 u r w $ f w l y h 6 w d u w 0 d l q v ( q d e o h 3 i f ( q d e o h 3 i f 7 2 q 3 d v v h g 2 & 3 8 9 3 p d l q v , q w ( [ w 2 7 3 2 / 3 9 8 9 3 6 8 3 , & 9 $ q d 9 ' l j 9 3 5 2 7 ( & 7 , 2 1 6 & 8 5 5 ( 1 7 6 ( 1 6 , 1 * * $ 7 ( & 2 1 7 5 2 / 6 7 $ 5 7 8 3 & 2 1 7 5 2 / 2 7 3 ; & $ 3 ' , 6 & + $ 5 * ( p d l q v f r p s h q v d w l r q 9 * d w h 3 i f 7 2 q 3 d v v h g 2 9 3 2 9 % r r v w 9 h q d e o h 3 ) & 9 9 9 3 ) & & 2 0 3 * 1 ' ? $ p 9 p 9 6 1 6 & 8 5 TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 4 of 30 nxp semiconductors TEA19162T pfc controller 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration , & * $ 7 ( 3 ) & 6 1 6 $ 8 ; * 1 ' 3 ) & & 2 0 3 6 1 6 & 8 5 6 1 6 0 $ , 1 6 6 8 3 , & 6 1 6 % 2 2 6 7 d d d table 2. pin description symbol pin description gatepfc 1 gate driver output for pfc gnd 2 ground snscur 3 programmable current sense input for pfc supic 4 supply voltage snsboost 5 sense input for pfc output voltage snsmains 6 sense input for mains voltage pfccomp 7 frequency compensation pin for pfc snsaux 8 input from auxiliary winding for demagnetization timing and valley detection for pfc TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 5 of 30 nxp semiconductors TEA19162T pfc controller 7. functional description 7.1 general control the TEA19162T is a controller for a power factor correction circuit. figure 3 shows a typical configuration. 7.2 supply voltage and start-up when using the TEA19162T (pfc) together with the tea19161t (llc), connect the supic pin of the TEA19162T to the supic pin of the tea19161t. the llc controller then supplies the pfc either via the high-voltage supply pin of the tea19161t (suphv) or via the primary auxiliary winding. to enable the pfc, the supic voltage must exceed the v start(supic) level (13 v typical). although the v start(supic) level of the llc is higher than the v start(supic) level of the pfc, the system ensures that both converters (pfc and llc) start up at the same time. therefore, the llc initially pulls down th e snsboost pin, disabling the pfc until the supic voltage reaches the v start(supic) level of the llc. when both conditions are met and the snsmai ns is above the brownin level, the pfc starts up via an internal soft start (see figure 4 ). fig 3. TEA19162T typical configuration d d d 7 ( $ u h v r q d q w f r q y h u w h u 7 ( $ 6 1 6 $ 8 ; * $ 7 ( 3 ) & 6 1 6 0 $ , 1 6 6 1 6 & 8 5 6 8 3 , & 9 p d l q v / 9 p d l q v 1 5 p d l q v * 1 ' 6 1 6 % 2 2 6 7 9 e r r v w & e r r v w 3 ) & & 2 0 3 5 d x [ 5 6 1 6 & 8 5 5 v h q v h 5 6 1 6 % 2 2 6 7 0 & 6 8 3 , & TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 6 of 30 nxp semiconductors TEA19162T pfc controller the exact start-up sequence of the pfc depends on the availab ility of start-up conditions (brownin level, v start(supic) of the pfc, and i en(pfc) ). before t1, the supic voltage is below the uvp level of the pfc and llc. when the llc reaches a minimum supply voltage level (t1), the llc pulls down the snsboost pin to disable the pfc. at t2, the supic voltage reaches the start le vel of the pfc converter. however, as the llc pulls low the snsboost to be low the pfc short protection level, the pfc is still off. when the mains voltage exceeds the brownin level, the pfc resets its latched protection by pulling v snsboost to the v pu(rst)snsboost level (t3). however, th e llc returns it to the protection mode. when at t4 the supic voltage reaches the start level of the llc, the snsboost is released. the snsboost voltage increases because of the resistive divider which is connected to the pfc bus voltage. to ensure that this voltage is representative of the v boost voltage before the system actually starts to switch, an additional delay (t d(start) ; 3.62 ms) is active before the pfc starts switching (t5). another important condition for the pfc start is a precharge of the compensation circuitry connected to the pfccomp pin. this cond ition is met when the current out of the pfccomp pin < |i en(pfccomp) |. when at t6 the snsboost voltage reaches the start level of the llc (v start(snsboost) ), the llc converter starts to switch. fig 4. start-up of the pfc and llc w w w w d d d w g v w d u w 9 6 1 6 % 2 2 6 7 9 6 8 3 , & / / & 3 ) & 9 e r r v w 9 v w d u w 6 1 6 % 2 2 6 7 9 9 u h j 6 1 6 % 2 2 6 7 9 9 s x u v w 6 1 6 % 2 2 6 7 9 9 v f s v w r s 9 9 x y s 6 8 3 , & 9 9 v w d u w 6 8 3 , & 9 9 u v w 6 8 3 , & 9 9 x y s 6 8 3 , & 9 9 v w d u w k \ v 6 8 3 , & 9 9 v w d u w 6 8 3 , & 9 9 * $ 7 ( 3 ) & 8 9 3 6 & 3 2 1 z d l w 3 ) & p r g h r i r s h u d w l r q w w TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 7 of 30 nxp semiconductors TEA19162T pfc controller when v supic TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 8 of 30 nxp semiconductors TEA19162T pfc controller 7.3.2 brownin/brownout and external overtemperature protection on the TEA19162T, the mains measurement and external temperature are combined at the snsmains pin (see figure 5 ). at t1, the voltage at the snsmains pin is internally regulated to v regd(snsmains) (250 mv). the current into the snsmains pin is a meas ure of the system input mains voltage. the TEA19162T continuously measures the snsmains current and waits until it detects a peak in the measured current (t2). this peak current value is internally stored and used as an input for the brownout/brownin detection and the mains compensation. when, at t3, the current into the snsmains pin is well below the brownin level (< i en(ntc) ), the controller starts to measure the va lue of the external ntc. the external ntc is measured by sourcing a current (i o(snsmains) ) out of the snsmains pin. when, after a maximum measuring time of t det(ntc)max (1 ms), the voltage remains below v det(snsmains) during four consecutive ntc measurements, the otp protection is triggered (t5). to prevent the pfc from operating at very low mains input voltages, the pfc stops switching when the measured peak current drops to below i bo . when the measured current exceeds i bi , the pfc restarts with a soft start. 7.3.3 soft stop overvoltage protection (snsboost pin) when the snsboost voltage is between the v det(l)snsboost and v det(h)snsboost , the TEA19162T stops switching via a soft stop. t he tea19161t uses this function to force the TEA19162T to operate in burst mode with a specific duty cycle (see section 7.5.2 ). audible noise is avoided because at the end of a switching period, the pfc stops via a soft stop. after an ovp event, the system always starts via a soft start. fig 5. mains and external otp measurement d d d w w w w w p d l q v / p d l q v 1 9 6 1 6 0 $ , 1 6 9 p 9 , 6 1 6 0 $ , 1 6 ? $ TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 9 of 30 nxp semiconductors TEA19162T pfc controller 7.3.4 overvoltage protection (snsboost pin) to prevent output overvoltage during load steps and mains transients, an overvoltage protection circuit is built in. when the voltage on the snsboost pin exceeds the v ovp(stop) level and is outside the v det(l)snsboost and v det(h)snsboost window for a minimum period of t d(ovp) (100 ? s), switching of the power factor correction circuit is inhibited. when the snsboost pin voltage drops to below the v ovp(start) (v ovp(stop) ? v hys(ovp) ) level again, the switching of the pfc recommences. the ic always restarts with a soft start (see section 7.4.1 ). 7.3.5 pfc open-loop protection (vosense pin) the pfc does not start switching until the voltage on the snsboost pin exceeds v scp(start) . this function acts as short circuit protection for the boost voltage (scp-snsboost; see ta b l e 3 ). 7.3.6 overcurrent protection (pfcsense pin) sensing the voltage across an external sense resistor, r sense , on the source of the external mosfet, limits the maximum peak current cycle-by-cycle. the voltage is measured via the snscur pin. 7.3.7 fast latch reset the restart of the system after a protection is triggered depends on the type of protection. in a safe restart protection (only applicable fo r the llc), the system typically restarts after the restart delay time (1 sec). it is different for latched protections. typica lly, in a latched protec tion, the supic must reach the undervoltage protection level to rele ase the protection mode and to restart the system. the release/restart can only be achieved by disconnecting the mains. in the protection mode, the tea19161t/tea19161ct regulates the voltage of the supic pin to its start level. the pfc output capacitor supplies the supic pin via the suphv pin of the tea19161t/tea19161ct. so it takes a long time before the voltage of the supic pin drops below its undervoltage level after the mains is disconnected. to prevent this delay, a special fast latch reset function is implemented in the TEA19162T, which also releases the protection mode when the mains is reconnected. TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 10 of 30 nxp semiconductors TEA19162T pfc controller before t1, the llc (and/or pfc) is in a (latched) protection and pulls down the snsboost pin, which also disables the pfc. when the mains voltage drops to below the brownout level (i bo ) and the time t d(det)bo (50 ms) expires (t1), the pfc enters the brownout protection mode. when, in the brownout protection mode, the mains voltag e increases again and exceeds the brownin level (i bi ; t2), the pfc pulls up the snsboost voltage to the v pu(rst)snsboost level (see figure 6 ). because the v pu(rst)snsboost level of the pfc exceeds the v uvp(snsboost) level of the llc, the llc converter resets the protection mo de. however, switching is still inhibited as the snsboost voltage remains below the start level (v start(snsboost) ) of the llc. the supic voltage is still regulated to the v start(supic) level of the llc converter. to ensure that the voltage at the snsboost pin accurately reflects the output voltage of the pfc, the pfc converter starts after a delay time (t d(start) ) (t3). the start of the pfc converter is followed by a start-up of the llc converter (t4). 7.4 power factor co rrection regulation the power factor correction circuit oper ates in quasi-resonant or discontinuous conduction mode with valley switching. the next primary stroke is only started when the previous secondary stroke has ended and the voltage across the pfc mosfet has reached a minimum value. to detect tran sformer demagnetization and the minimum voltage across the external pfc mosfet switch, the voltage on the snsaux pin is used. fig 6. fast latch reset d d d w g v w d u w w g p d l q e r / / & 9 v w d u w 6 8 3 , & 9 9 v w d u w k \ v 6 8 3 , & 9 9 6 8 3 , & 9 6 1 6 % 2 2 6 7 3 ) & r i i z d l w s u r w h f w l r q r q 8 9 3 6 1 6 % 2 2 6 7 3 ) & / / & 9 r x w w w w p d l q v e u r z q r x w r q e u r z q l q e u r z q r x w w 9 u h j 6 1 6 % 2 2 6 7 9 9 v f s v w r s 9 9 s x u v w 6 1 6 % 2 2 6 7 9 9 v w d u w 6 1 6 % 2 2 6 7 9 9 x y s 6 1 6 % 2 2 6 7 9 TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 11 of 30 nxp semiconductors TEA19162T pfc controller 7.4.1 soft start (pfcsense pin) to prevent audible transformer noise at start-up or during hiccup, the soft start function slowly increases the transformer peak current (see figure 7 ). at t1, all conditions to start up the pf c are fulfilled. the ma ximum voltage on the snscur pin is limited to v start(soft)init (125 mv). when the pfc starts switching, the maximum snscur voltage is increased to v reg(oc) within a time period of t start(soft) (3.62 ms) or until the t on regulation limits the on-time of the pfc external mosfet. 7.4.2 t on control the power factor correction circuit is operated in t on control. the resulting mains harmonic reduction of a typical application is well within the class-d requirements. the following circuits determine the on-time of the external pfc mosfet: ? the error amplifier and the loop compensation which define the voltage on the pfccomp pin. at v tonzero(pfccomp) (3.5 v), the on-time is reduced to zero. at v tonmax(pfccomp) (1.93 v), the on-time is at a maximum. ? mains compensation which uses the current through the snsmains pin to represent the mains input voltage level. fig 7. pfc start-up 6 1 6 % 2 2 6 7 9 v w d u w v r i w l q l w * $ 7 ( 3 ) & 9 u h j r f 6 1 6 & 8 5 w w w d d d w v w d u w v r i w TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 12 of 30 nxp semiconductors TEA19162T pfc controller 7.4.3 pfc error amplifier (pfccomp and snsboost pins) the boost voltage is divided using a high-ohm ic resistive divider and is supplied to the snsboost pin. the transconductance error amplifier, which compares the snsboost voltage with an accurate trimmed reference voltage (v reg(snsboost) ) is connected to this pin. the external loop compensation network on the pfccomp pin filters the output current. in a typical application, a resistor and two capacitors set the regulation loop bandwidth. the transconductance of the error amplifier is not constant. to avoid triggering the ovp during start-up and during a converter transient response, the transconductance is increased to a level of i gm(high) starting at v gm(high)start (see figure 8 ). 7.4.4 valley switching and demagnetization (pfcaux pin) to ensure that the TEA19162T operates in discontinuous or quasi-resonant mode, the pfc mosfet is switched on after the transf ormer is demagnetized. to reduce switching losses and electromagnetic interference (emi), the next stroke is started when the pfc mosfet drain-source voltage is at its mini mum (valley switching) . the demagnetization and valley detection are measured via the snsaux pin. if no demagnetization signal is detected on the snsaux pin, the controller generates a demagnetization signal (t to(demag) ; 44.5 ? s typical) after the external mosfet is switched off. if no valley signal is detected on the pfcaux pin, the controller generates a valley signal (t to(vrec) ; 3.8 ? s typical) after demagnet ization is detected. to protect the internal circuitry, for example during lightning events, connect a 5 k ? series resistor (r aux ; see figure 13 ) to the pfcaux pin. also connect a 1 k ? (typical) external sense resistor (r snscur ; see figure 13 ) to the snscur pin. to prevent incorrect switching due to external disturbance, place the resistors close to the ic. fig 8. transconductance of the pfc error amplifier d d d j p j p k l j k p 9 p 9 9 j p k l j k v w d u w 9 r y s v w r s o 3 ) & & 2 0 3 ? $ 9 6 1 6 % 2 2 6 7 9 o v l q n 3 ) & & 2 0 3 TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 13 of 30 nxp semiconductors TEA19162T pfc controller 7.4.5 frequency limitation to optimize the transformer and minimize s witching losses, the s witching frequency is limited to f sw(pfc)max . if the frequency for quasi-resonant operation exceeds the f sw(pfc)max limit, the system enters discontinuous conduc tion mode (dcm). when the system is in dcm, the pfc mosfet switches on at a mi nimum voltage across the switch (valley switching). to ensure correct control of the pfc mosf et under all circumstances, the minimum off-time is limited at t off(pfc)min . 7.4.6 mains voltage compensation (snsmains pin) the equation for the transfer function of a power factor corrector contains the square of the mains input voltage. in a typical application, the result is a low bandwidth for low mains input voltages. at high mains input voltages, the mains harmonic reduction (mhr) requirements may be hard to meet. to compensate for the mains input voltage influence, the TEA19162T contains a correction circuit. the input voltage is measured via the snsmains pin (see section 7.3.2 ) and the information is fed to an internal mains compensation circuit (see figure 1 ). with this compensation, it is po ssible to keep the regulation loop bandwidth constant over the full mains input range. the result is that a mains voltage independent transient response on load steps is yielded, while still complying with class-d mhr requirements. in a typical application, an external circuitry at the pfccomp pin (see section 7.4.3 ) sets the bandwidth of the regulation loop. 7.4.7 active x-capacitor discharge the TEA19162T provides an active x-capacitor discharge after the mains voltage is disconnected. when the mains input voltage (and so also the measured current into the snsmains pin) increases (see figure 9 , t2 ? t1), the system assume s the presence of a mains voltage. when the mains voltage does not increase for a minimum period of t d(dch) , the active x-capacitor discharge is activated (t3). when the active x-capacitor discharge function is activated, the x-capacitor is discharged via the external pfc mosfet (see figure 10 ). to avoid any increase of the pfc output voltage, the external pfc mosfet is slowly tu rned on until a small current is detected via the snscur pin (see figure 9 , t4). a slow increase of the gatepfc voltage is achieved via a current source (i ch(gatepfc) ) that slowly charges the external gate-source capacitance of the external mosfet. when the voltage at the snscur exceeds v ch(stop)snscur level (10.5 mv), the voltage at the gatepfc pin slowly decreases by activating a current sink (i dch(gatepfc) ). as a result, the gate-source capacitance of the external mosfet is discharged. when the voltage on the gatepfc pin drops to below v dch(stop)gatepfc level (0.7 v), the current sink is switched off. the charge/disch arge cycle is repeated after the period t off(dch) (t5). as for a typical power mosfet the duration of charge/discharge pulses on the gatepfc pin is shorter than 2 ms, t p (4 ms typical) defines the pulse repetition time. TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 14 of 30 nxp semiconductors TEA19162T pfc controller when the voltage on the gatepfc pin exceeds v dch(gatepfc) while the voltage on the snscur pin is still below v ch(stop)snscur , the system assumes a full discharge of the x-capacitor. it starts to ramp down th e gatepfc voltage. unless the mains is reconnected, the next active x-capaci tor discharge cycle is started after t d(dch) . reconnecting the mains is detected via a positive di/dt at the snsmains pin. while the gatepfc pin discharges the x-capacitor, the mains can be reconnected. in that case, the current through the external mosfet increases rapidly. if the voltage on the snscur pin exceeds v dch(snscur) , the internal driver stage rapidly turns off the gatepfc pin. when the mains is discon nected again (measured via the snsmains pin), the next active x-capacitor discharge cycle starts, followed by a delay of t d(dch) . fig 9. TEA19162T active x-capacitor discharge d d d w w w w w g g f k w r i i g f k 7 s 9 g f k v w r s * $ 7 ( 3 ) & 9 f k v w r s 6 1 6 & 8 5 p d l q v / p d l q v 1 , f k * $ 7 ( 3 ) & , * $ 7 ( 3 ) & , g f k * $ 7 ( 3 ) & 9 * $ 7 ( 3 ) & 9 6 1 6 & 8 5 w TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 15 of 30 nxp semiconductors TEA19162T pfc controller 7.5 pfc-llc communication protocol the TEA19162T (pfc controller) is designed to cooperate with the tea19161t (llc controller) in one system. both controllers can be seen as a combo ic, split up into two packages. all required functionality between the TEA19162T and tea19161t is arranged via the combined supic and snsboost pins. both controllers are supplied via the supic pin (see section 7.2 ). the snsboost pin is used to communicate about the protection states of both controllers. the tea19161t forces the TEA19162T to enter burst mode also using the snsboost pin. fig 10. TEA19162T active x-capacitor discharge block diagram d d d * $ 7 ( 3 ) & f k d u j h & e r r v w 5 v h q v h 9 g l v g f k * $ 7 ( 3 ) & , f k * $ 7 ( 3 ) & , g f k * $ 7 ( 3 ) & 9 g f k v w r s * $ 7 ( 3 ) & ; & $ 3 $ & , 7 2 5 ' , 6 & + $ 5 * ( & 2 1 7 5 2 / h q d e o h w u l v w d w h * d w h ' l j 8 9 3 6 8 3 , & p d l q v / p d l q v 1 g u l y h u 7 , 0 ( 5 w g g f k , & 7 , 0 ( 5 w r i i g f k u h v h w 9 f k v w r s 6 1 6 & 8 5 9 g l v g f k 6 1 6 & 8 5 6 1 6 & 8 5 TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 16 of 30 nxp semiconductors TEA19162T pfc controller 7.5.1 protections when a protection is triggered in the pfc or the llc, it can also disable the other converter. for example, if an ovp is detected at the llc, both converters are stopped. also, at initial start-up, the pfc disables t he llc converter until the brownin level of the mains voltage is detected. the snsboost pin is used for the communica tion about such protection states. by pulling down the snsboost pin below the v uvp(snsboost) level of the llc converter, the pfc can disable the llc converter. similarl y, by pulling down the snsboost pin below the short protection level v scp(stop) of the pfc converter, the llc can disable the pfc. ta b l e 3 in section 7.3 gives an overview of all protections in the pfc converter. the pfc protections that also disable the llc are listed in the llc-column. when the mains voltage initially drops to below the brownout level and then increases to above the brownin level, all protections of the pfc and the llc are reset. a reset of all protections is also communicated via th e snsboost pin by pulling it up to the v pu(rst)snsboost level (see section 7.3.7 ). the ic starts and remains in the protection mo de until the mains brownin level is reached. the ic current consumption is then at power-saving level. 7.5.2 pfc burst mode based on the output power level of the llc converter, the llc determines when the pfc enters burst mode. during the burst mode, the llc converter disables the pfc by increasing the snsboost voltage to between v det(l)snsboost and v det(h)snsboost (see figure 11 ). it ensures a soft start and a soft stop at the start and the end of a switching period, respectively . this increase in the voltage on the snsboost pin is achieved by an additional current out of the llc converter towards the snsboost pin. the additional current creates a positive volt age shift because of the external resistive network at the snsboost pin. TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 17 of 30 nxp semiconductors TEA19162T pfc controller at t1, the current out of the llc snsboost pin (i stop(burst) ) is activated and the voltage on the snsboost pin increases. when a 100 k ? external resistor r snsboost between the snsboost pin and gnd pin is used (see figure 11 ), the snsboost voltage increase is about 640 mv (= i stop(burst)snsboost *r snsboost ). as due to this increase the snsboost voltage is between v det(l)snsboost and v det(h)snsboost levels (t2), the soft stop of the pfc converter is started. in th e soft stop state, the current out of the pfccomp pin (i ch(stop)soft ) is activated. at the end of the soft stop, the pfc enters the energy safe state and stops switching (t3). the voltage at the pfccomp pin is clamped at v tonzero(pfccomp) (3.5 v). it remains at this level du ring the energy safe state. as the llc converter operates continuously, even when the pfc is stopped, the pfc output capacitor discharges. when the pfc boost capacitor is discharged so much that the voltage on the snsboost pin drops by 100 mv ( ? v off(burst) ; t4), the internal current source in the llc converter is switched off. because of the negative voltage drop at the snsboost pin, the snsboost voltage drops below the regulation level (v reg(snsboost ); t5). the pfc starts switching again (t6). when v snsboost exceeds the llc v on(burst)max level (2.37 v) again, the internal current is reactivated and the pfc stops switching again. a. block diagram b. timing diagram fig 11. pfc burst mode d d d * 0 $ 0 3 / , ) , ( 5 v r i w v w r s 3 ) & / / & 6 1 6 % 2 2 6 7 3 ) & e x u v w p r g h 9 6 1 6 % 2 2 6 7 ! 9 n ? v ' ( / $ < 9 9 9 9 2 9 3 3 ) & & 2 0 3 , r i i e x u v w ? $ , f k v w r s v r i w ? $ 9 r i i e x u v w t 5 ( 6 ( 7 0 $ ; 9 $ / 8 ( v u 9 r i i e x u v w p 9 9 r q e x u v w p d [ 9 , r i i e x u v w d d d 2 ) ) 2 ) ) 2 1 2 1 9 g h w + 6 1 6 % 2 2 6 7 9 3 ) & / / & 9 g h w / 6 1 6 % 2 2 6 7 9 9 r y s v w r s 9 9 u h j 6 1 6 % 2 2 6 7 9 9 f o d p s 3 ) & & 2 0 3 9 9 w r q ] h u r 3 ) & & 2 0 3 9 9 6 1 6 % 2 2 6 7 w 9 3 ) & & 2 0 3 w w w 9 * $ 7 ( 3 ) & w w TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 18 of 30 nxp semiconductors TEA19162T pfc controller the TEA19162T current consumption in the burst mode depends on whether the ic is switching or not. during burst mode on-time and burst mode off-time, the current consumption is at operating level and power-saving level, respectively. 7.5.3 soft stop a soft stop always precedes the pfc burst mode. it reduces audible noise of the converter. the internal current source activated in the llc converter (see figure 11 ) pulls up the voltage at the pfc snsboost pin. when the snsboost pin voltage is between v det(l)snsboost (2.8 v) and v det(h)snsboost (3.23 v), the pfc soft stop begins. then, a pfc internal cu rrent source i ch(stop)soft is activated and the transconductance error amplifier in the pfc contro l loop is switched off (see figure 11 ). the activated current source provides a current of 32 ? a (i ch(stop)soft ) out of the pfccomp pin. this current slowly increases the volt age of the pfccomp pin, gradually reducing the converter switching on-time. when the zero on-time is reached, the soft stop ends. the zero on-time corresponds with the pfccomp pin voltage of v tonzero(pfccomp) (3.5 v). the detection of the overvoltage on the snsboost pin at the normal ovp level (v ovp(stop) ) is delayed for the time t d(ovp) (100 ? s). this additional delay is required to verify if the system should stop immediately be cause of an ovp or via a soft stop when activating the burst mode. 7.6 driver (pin gatepfc) the driver circuit to the gate of the power mosfet has a current so urcing capability of 600 ma and a current sink capa bility of 1.4 a typical. thes e capabilities allow a fast turn-on and turn-off of the power mosfet, ensuring efficient operation. when the supic voltage is below its start level, the internal keep-off circuitry of the pfc driver pulls down the gatepfc pin. the pullin g down of the gatepfc pin prevents that an external power mosfet is activated when the ic power supply is absent or when the v supic TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 20 of 30 nxp semiconductors TEA19162T pfc controller 10. characteristics table 6. characteristics t amb =25 ? c; v supic = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit supply (supic pin) v start(supic) start voltage on pin supic 12.35 13 13.65 v v uvp(supic) undervoltage protection voltage on pin supic 8.55 9 9.45 v i cc supply current operating mode; f sw = 100 khz; pin gatepfc = floating; v snsboost =2.2v - - 0.80 ma power-save mode; pin pfccomp = floating; v snsboost =2.7v - - 0.20 ma gate driver output (gatepfc pin) i source(gatepfc) source current on pin gatepfc v gatepfc =2v; v supic ? 13 v - ? 0.6 - a i sink(gatepfc) sink current on pin gatepfc v gatepfc =2v; v supic ? 13 v - 0.6 - a v gatepfc = 10 v; vsupic ? 13 v - 1.4 - a v o(max)gatepfc maximum output voltage on pin gatepfc 10.0 11.0 12.0 v mains voltage sensing (snsmains pin) i bi brownin current 5.35 5.75 6.15 ? a i bo brownout current 4.65 5.00 5.35 ? a i bo(hys) hysteresis of brownout current i bi ? i bo 640 750 820 na t d(det)bo brownout detection delay time 45.2 50 55.5 ms v regd(snsmains) regulated voltage on pin snsmains mains detection period; no current at snsmains; c max(snsmains) =100pf 230 250 270 mv x-capacitor discharge (snscur and gatepfc pins) t d(dch) discharge delay time x-capacitor discharge 109 118 128 ms i ch(gatepfc) charge current on pin gatepfc x-capacitor discharge ? 29 ? 26 ? 23 ? a i dch(gatepfc) discharge current on pin gatepfc x-capacitor discharge 23 26 29 ? a v ch(stop)snscur stop charge voltage on pin snscur x-capacitor discharge; stop of external most gate charge; dv/dt = 0 8.00 10.50 12.50 mv v dch(stop)gatepfc stop discharge voltage on pin gatepfc x-capacitor discharge; stop of external most gate discharge 0.3 0.7 1.1 v t off(dch) discharge off-time x-capa citor; time between discharge/charge pulses; gatepfc pin 1.88 - 6.40 ms TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 21 of 30 nxp semiconductors TEA19162T pfc controller t p pulse period x-capacitor discharge; pulseduration<2ms (typical); gatepfc pin 3.76 4.00 4.27 ms v dis(dch)gatepfc disable discharge voltage on pin gatepfc x-capacitor discharge 9.00 9.45 9.90 v v dis(dch)snscur disable discharge voltage on pin snscur x-capacitor discharge 44 50 56 mv output voltage sensing, regulation and co mpensation (snsboost and pfccomp pins) v reg(snsboost) regulation voltage on pin snsboost i pfccomp = 0 a 2.475 2.500 2.525 v g m transconductance error amplifier; v snsboost to i pfccomp ; |v snsboost ? v intregd(snsboost) |<40mv ? 90 ? 75 ? 60 ? a/v i sink(pfccomp) sink current on pin pfccomp v snsboost =2v; v pfccomp = 2.75 v 30.0 35.5 41.0 ? a g m(high) high transconductance error amplifier; v snsboost to i pfccomp ; v start(gm)high ? v snsboost TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 23 of 30 nxp semiconductors TEA19162T pfc controller v scp(stop) stop short-circuit protection voltage 0.35 0.40 0.45 v v scp(start) start short-circuit protection voltage 0.45 0.50 0.55 v t d(start) start delay time after short-circui t protection removed 3.30 3.62 4.00 ms i pu(rst)snsboost reset pull-up current on pin snsboost fast latch reset; v snsboost =1.5v ? 245 ? 210 ? 175 ? a v pu(rst)snsboost reset pull-up voltage on pin snsboost fast latch reset 1.94 2.00 2.06 v i prot(snsboost) protection current on open pin snsboost pin snsboost = open - 35 - na v ovp(stop) stop overvoltage protection voltage 2.59 2.63 2.67 v v ovp(start) start overvoltage protection voltage 2.47 2.53 2.59 v v hys(ovp) overvoltage protection hysteresis voltage on pin snsboost v stop(ovp) ? v start(ovp) 0.07 0.10 0.13 v soft start (pin snscur) t start(soft) soft start time 3.30 3.62 4.00 ms v start(soft)init initial soft start voltage 100 125 155 mv soft stop (pins sn sboost and pfccomp) v det(l)snsboost low-level detection voltage on pin snsboost soft stop 2.74 2.80 2.86 v v det(h)snsboost high-level detection voltage on pin snsboost soft stop 3.17 3.23 3.29 v i ch(stop)soft soft stop charge current pin pfccomp ? 36 ? 32 ? 28 ? a t d(ovp) overvoltage protection delay time pin snsboost 80 100 120 ? s external and internal overtemperature measurement i en(ntc) ntc enable current pin snsmains; ntc measurement; mains measurement period; falling slope 2.0 2.5 3.0 ? a i o(snsmains) output current on pin snsmains ? 214 ? 200 ? 186 ? a table 6. characteristics ?continued t amb =25 ? c; v supic = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 24 of 30 nxp semiconductors TEA19162T pfc controller t det(ntc)max maximum ntc detection time 0.92 1.00 1.08 ms v det(snsmains) detection voltage on pin snsmains ntc measurement; i snsmains = ? 200 a 1.95 2.00 2.05 v t pl(ic) ic protection level temperature 130 150 160 ?c table 6. characteristics ?continued t amb =25 ? c; v supic = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 25 of 30 nxp semiconductors TEA19162T pfc controller 11. application information capacitor c supic filters the ic supply voltage, whic h must be supplied externally. sense resistor r sense converts the current through the mosfet m1 to a voltage on the snscur pin. the r sense value determines the maximum primary peak current in mosfet m1. to limit the current into the snscur pin due to negative voltage spikes across the sense resistor, resistor r snscur is added. to protect the ic from damage during lightning events, resistor r aux is added. fig 13. application diagram d d d 7 ( $ u h v r q d q w f r q y h u w h u 7 ( $ 6 1 6 $ 8 ; * $ 7 ( 3 ) & 6 1 6 0 $ , 1 6 6 1 6 & 8 5 6 8 3 , & 9 p d l q v / 9 p d l q v 1 5 p d l q v * 1 ' 6 1 6 % 2 2 6 7 9 e r r v w & e r r v w 3 ) & & 2 0 3 5 d x [ 5 6 1 6 & 8 5 5 v h q v h 5 6 1 6 % 2 2 6 7 0 & 6 8 3 , & TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 26 of 30 nxp semiconductors TEA19162T pfc controller 12. package outline fig 14. package outline sot096-1 (so8) 8 1 , 7 $ p d [ $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5 ( ) ( 5 ( 1 & ( 6 2 8 7 / , 1 ( 9 ( 5 6 , 2 1 ( 8 5 2 3 ( $ 1 3 5 2 - ( & 7 , 2 1 , 6 6 8 ( ' $ 7 ( , ( & - ( ' ( & - ( , 7 $ p p l q f k h v r r ' , 0 ( 1 6 , 2 1 6 l q f k g l p h q v l r q v d u h g h u l y h g i u r p w k h r u l j l q d o p p g l p h q v l r q v 1 r w h v 3 o d v w l f r u p h w d o s u r w u x v l r q v r i p p l q f k p d [ l p x p s h u v l g h d u h q r w l q f o x g h g 3 o d v w l f r u p h w d o s u r w u x v l r q v r i p p l q f k p d [ l p x p s h u v l g h d u h q r w l q f o x g h g 6 2 7 ; z 0 $ $ $ e s ' + ( / s 4 g h w d l o ; ( = h f / y 0 $ $ $ s l q l q g h [ \ ( 0 6 p p v f d o h 6 2 s o d v w l f v p d o o r x w o l q h s d f n d j h o h d g v e r g \ z l g w k p p 6 2 7 TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 27 of 30 nxp semiconductors TEA19162T pfc controller 13. revision history table 7. revision history document id release date data sheet status change notice supersedes TEA19162T v.1 20160310 product data sheet - - TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 28 of 30 nxp semiconductors TEA19162T pfc controller 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. 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[3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 14.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? 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TEA19162T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 29 of 30 nxp semiconductors TEA19162T pfc controller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. greenchip ? is a trademark of nxp b.v. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors TEA19162T pfc controller ? nxp semiconductors n.v. 2016. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 march 2016 document identifier: TEA19162T please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 distinctive features . . . . . . . . . . . . . . . . . . . . . . 2 2.2 green features . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 protection features . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 general control . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 supply voltage and start-up . . . . . . . . . . . . . . . 5 7.3 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3.1 internal overtemperature protection (otp). . . 7 7.3.2 brownin/brownout and external overtemperature protection . . . . . . . . . . . . . . . 8 7.3.3 soft stop over voltage protection (snsboost pin) . . . . . . . . . . . . . . . . . . . . . . . 8 7.3.4 overvoltage protection (snsboost pin) . . . . 9 7.3.5 pfc open-loop protection (vosense pin) . . . 9 7.3.6 overcurrent protection (pfcsense pin) . . . . . 9 7.3.7 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.4 power factor correction regulation . . . . . . . . . 10 7.4.1 soft start (pfcsense pin). . . . . . . . . . . . . . . 11 7.4.2 t on control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4.3 pfc error amplifier (pfccomp and snsboost pins) . . . . . . . . . . . . . . . . . . 12 7.4.4 valley switchin g and demagnetization (pfcaux pin) . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4.5 frequency limitation . . . . . . . . . . . . . . . . . . . . 13 7.4.6 mains voltage compensation (snsmains pin). . . . . . . . . . . . . . . . . . . . . . . 13 7.4.7 active x-capacitor discharge . . . . . . . . . . . . . 13 7.5 pfc-llc communication protocol . . . . . . . . . 15 7.5.1 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.2 pfc burst mode . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.3 soft stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6 driver (pin gatepfc) . . . . . . . . . . . . . . . . . . 18 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 9 thermal characteristics . . . . . . . . . . . . . . . . . 19 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 application information. . . . . . . . . . . . . . . . . . 25 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 14 legal information . . . . . . . . . . . . . . . . . . . . . . 28 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15 contact information . . . . . . . . . . . . . . . . . . . . 29 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 |
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