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TPS720 sbvs100e ? june 2008 ? revised september 2015 TPS720 350 ma, ultra-low v in , rf low-dropout linear regulator with bias pin the TPS720 supports a novel feature in which the 1 features output of the ldo regulates under light loads when 1 ? 350-ma high-performance ldo the in pin is left floating. the light-load drive current ? low quiescent current: 38 a is sourced from v bias under this condition. this feature is particularly useful in power-saving ? excellent load transient response: applications where the dc-dc converter connected 15 mv for i load = 0 ma to 350 ma in 1 s to the in pin is disabled but the ldo is still required ? excellent line transient response: to regulate the voltage to a light load. v out = 2 mv for v bias = 600 mv in 1 s the TPS720 is stable with ceramic capacitors and v out = 200 v for v in = 400 mv in 1 s uses an advanced bicmos fabrication process that ? low noise: 48 v rms (10 hz to 100 khz) yields a dropout of 110 mv at a 350-ma output load. ? 80 db v in psrr (10 hz to 10 khz) the TPS720 has the unique feature of providing a monotonic v out rise (overshoot limited to 3%) with ? 70 db v bias psrr (10 hz to 10 khz) v in inrush current limited to 100 ma + i load with an ? fast start-up time: 140 s output capacitor of 2.2 f. ? built-in soft-start with monotonic v out rise and the TPS720 uses a precision voltage reference and start-up current limited to 100 ma + i load feedback loop to achieve overall accuracy of 2% over ? overcurrent and thermal protection load, line, process, and temperature extremes. an ? low dropout: 110 mv at i load = 350 ma ultra-small dsbga package makes the TPS720 ideal for handheld applications. the TPS720 is also ? stable with 2.2- f output capacitor available in a son-8 package. this family of devices ? available in 1.33 mm 0.96 mm dsbga-5 and 2 is fully specified over the temperature range of mm 2 mm son-6 packages t j = ? 40 c to 125 c. 2 applications device information (1) ? digital cameras part number package body size (nom) ? cellular camera phones dsbga (5) 1.36 mm 0.96 mm TPS720 son (6) 2.00 mm 2.00 mm ? wireless lan ? handheld products (1) for all available packages, see the orderable addendum at the end of the data sheet. 3 description simplified schematic the TPS720 family of dual rail, low-dropout linear regulators (ldos) offers outstanding ac performance (psrr, load and line transient response), while consuming a very low quiescent current of 38 a. the v bias rail that powers the control circuit of the ldo draws very low current (on the order of the quiescent current of the ldo) and can be connected to any power supply that is equal to or greater than 1.4 v above the output voltage. the main power path is through v in , which can be a lower voltage than v bias ; it can be as low as v out + v do , increasing the efficiency of the solution in many power-sensitive applications. for example, v in can be an output of a high-efficiency, dc-dc step-down regulator. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TPS720xx v en v batt inen out gnd v core 1.3 v 1.8 v standalone dc/dc converter or pmu bias c bias c out c in productfolder sample &buy technical documents tools & software support &community referencedesign
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com table of contents 8.1 application information ............................................ 14 1 features .................................................................. 1 8.2 typical application .................................................. 15 2 applications ........................................................... 1 9 power supply recommendations ...................... 17 3 description ............................................................. 1 10 layout ................................................................... 17 4 revision history ..................................................... 2 10.1 layout guidelines ................................................. 17 5 pin configuration and functions ......................... 3 10.2 layout example .................................................... 17 6 specifications ......................................................... 3 10.3 thermal considerations ........................................ 17 6.1 absolute maximum ratings ...................................... 3 10.4 power dissipation ................................................. 18 6.2 esd ratings .............................................................. 4 11 device and documentation support ................. 19 6.3 recommended operating conditions ....................... 4 11.1 device support .................................................... 19 6.4 thermal information .................................................. 4 11.2 documentation support ........................................ 19 6.5 electrical characteristics ........................................... 5 11.3 community resources .......................................... 19 6.6 typical characteristics .............................................. 7 11.4 trademarks ........................................................... 19 7 detailed description ............................................ 12 11.5 electrostatic discharge caution ............................ 19 7.1 overview ................................................................. 12 11.6 glossary ................................................................ 19 7.2 functional block diagram ....................................... 12 12 mechanical, packaging, and orderable 7.3 feature description ................................................. 12 information ........................................................... 20 7.4 device functional modes ........................................ 13 12.1 package mounting ................................................ 20 8 application and implementation ........................ 14 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision d (august 2009) to revision e page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ................................................................................................. 1 changes from revision c (september, 2008) to revision d page ? added electrical specifications for drv package ................................................................................................................... 5 ? noted electrical specifications for yzu package .................................................................................................................... 5 2 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 5 pin configuration and functions drv package yzu package 6-pin son with exposed thermal pad 5-pin dsbga top view top view (1) ti recommends connecting the son (drv) package thermal pad to ground. pin functions pin i/o description name drv yzu output pin. a 2.2- f ceramic capacitor is connected from this pin to ground, for stability and to provide out 1 a3 o load transients. see input and output capacitor requirements . nc 2 ? ? no connection. enable pin. a logic high signal on this pin turns the device on and regulates the voltage from in to en 3 c3 i out. a logic low on this pin turns off the device. bias supply pin. ti recommends bypassing this input with a ceramic capacitor to ground for better bias 4 c1 i transient performance. see input and output capacitor requirements . gnd 5 b2 ? ground pin. input pin. this pin can be a maximum of 4.5 v; v in must not exceed v bias . bypass this input with a in 6 a1 i ceramic capacitor to ground. see input and output capacitor requirements . 6 specifications 6.1 absolute maximum ratings at t j = ? 40 c to 125 c (unless otherwise noted). all voltages are with respect to gnd. (1) min max unit v in (2) input voltage (steady-state) ? 0.3 v bias or 5 (3) v v in_peak (4) peak transient input 5.5 v v bias bias voltage ? 0.3 6 v v en enable voltage ? 0.3 6 v v out output voltage ? 0.3 5 v i out peak output current internally limited output short circuit duration indefinite p diss total continuous power dissipation see thermal information t j operating junction temperature ? 55 125 c t stg storage temperature ? 55 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) to ensure proper operation of the device it is necessary that v in v bias under all conditions. (3) whichever is less. (4) for durations no longer than 1ms each, for a total of no more than 1000 occurrences over the lifetime of the device. copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: TPS720 bias in en gnd out c3 b2 a3 c1 a1 ingnd bias 65 4 out nc en 12 3 thermal pad (1)
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com 6.2 esd ratings value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 charged-device model (cdm), per jedec specification jesd22- v (esd) electrostatic discharge 500 v c101 (2) machine model (mm) 100 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating junction-air temperature range (unless otherwise noted) min nom max unit v in input voltage (steady-state) 1.1 v bias or 4.5 (1) v v bias bias voltage 2.5 or or vout + 1.4 (2) 5.5 v v out output voltage 0.9 3.6 v i out peak output current 0 350 ma c in input capacitance 1 f c bias bias capacitance 0.1 f c out (3) output capacitance 2.2 f (1) whichever is less (2) whichever is greater (3) maximum esr should be less than 250 m . 6.4 thermal information TPS720 thermal metric (1) drv (son) yzu (wscp) unit 6 pins 5 pins r ja junction-to-ambient thermal resistance 66.5 144.9 c/w r jc(top) junction-to-case (top) thermal resistance 86.2 1.1 c/w r jb junction-to-board thermal resistance 36.1 27.5 c/w jt junction-to-top characterization parameter 1.7 4.1 c/w jb junction-to-board characterization parameter 36.6 27.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance 7.4 n/a c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 4 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 6.5 electrical characteristics over operating temperature range (t j = ? 40 c to 125 c), v bias = (v out + 1.4 v ) or 2.5 v (whichever is greater); v in v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = 25 c. parameter test conditions min typ max unit v bias or v in input voltage 1.1 (1) v 4.5 (2) v bias bias voltage 2.5 5.5 v output voltage (4) 0.9 3.6 v nominal t j = 25 c ? 3 3 mv v out + 1.4 v v bias 5.5 v, over v bias , v in , i out , v out + 0.5 v v in 4.5 v, ? 2% 2% t j = ? 40 c to 125 c 0 ma i out 350 ma drv package only: v out + 1.4 v v bias 5.5 v, over v bias , v in , i out , v out + 0.5 v v in 4.5 v, ? 25 25 mv t j = ? 40 c to 125 c v out (3) output 0 ma i out 350 ma, accuracy v out < 1.2 v yzu package only: v out + 1.4 v v bias 5.5 v, over v bias , v in , i out , v out + 0.5 v v in 4.5 v, ? 1% 1% t j = ? 10 c to 85 c 0 ma i out 350 ma 1.6 v v out 3.3 v v out + 1.4 v v bias 5.5 v, v in floating 1% 0 a i out 500 a v out / v in v in line regulation v in = (v out + 0.5 v) to 4.5 v, i out = 1 ma 16 v/v v bias = (v out + 1.4 v) or 2.5 v (whichever is v out / v bias v bias line regulation 16 v/v greater) to 5.5 v, i out = 1 ma v in line transient v in = 400 mv, t rise = t fall = 1 s 200 v v bias line transient v bias = 600 mv, t rise = t fall = 1 s 0.8 mv v out / i out load regulation 0 ma i out 350 ma (no load to full load) ? 15 v/ma load transient 0 ma i out 350 ma, t rise = t fall = 1 s 15 mv v in = v out(nom) ? 0.1 v, v do_in v in dropout voltage (5) (v bias ? v out(nom) ) = 1.4 v, 110 200 mv i out = 350 ma v do_bias v bias dropout voltage (6) v in = v out(nom) + 0.3 v, i out = 350 ma 1.09 1.4 v i cl output current limit v out = 0.9 v out(nom) 420 525 800 ma i out = 100 a 38 i gnd ground pin current a i out = 0 ma to 350 ma 54 80 i shdn shutdown current (i gnd ) v en 0.4 v, t j = ? 40 c to 85 c 0.5 2 a f = 10 hz 85 f = 100 hz 85 v in ? v out 0.5 v, f = 1 khz 85 psrr v in power-supply rejection ratio v bias = v out + 1.4 v, db f = 10 khz 80 i out = 350 ma f = 100 khz 70 f = 1 mhz 50 (1) performance specifications are ensured up to a minimum v in = v out + 0.5 v. (2) whichever is less. (3) minimum v bias = (v out + 1.4 v) or 2.5 v (whichever is greater) and v in = v out + 0.5 v. (4) v o nominal value is factory programmable through the onchip eeprom. (5) measured for devices with v out(nom) 1.2 v. (6) v bias ? v out with v out = v out(nom) ? 0.1 v. measured for devices with v out(nom) 1.8 v. copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: TPS720
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com electrical characteristics (continued) over operating temperature range (t j = ? 40 c to 125 c), v bias = (v out + 1.4 v ) or 2.5 v (whichever is greater); v in v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = 25 c. parameter test conditions min typ max unit f = 10 hz 80 f = 100 hz 80 v in ? v out 0.5 v, f = 1 khz 75 psrr v bias power-supply rejection ratio v bias = v out + 1.4 v, db f = 10 khz 65 i out = 350 ma f = 100 khz 55 f = 1 mhz 35 bw = 10 hz to 100 khz, v bias 2.5 v, v n output noise voltage 48 v rms v in = v out + 0.5 v v bias = (v out +1.4 v) or 2.5 v (whichever is 100 + i vin_inrush inrush current on v in ma greater), v in = v out + 0.5 v i load v out = 95% v out(nom) , i out = 350 ma, t str start-up time 140 s c out = 2.2 f v en(hi) enable pin high (enabled) 1.1 v v en(lo) enable pin low (disabled) 0 0.4 v i en enable pin current v en = 5.5 v , v in = 4.5 v, v bias = 5.5 v 1 a undervoltage lockout v bias rising 2.41 2.45 2.49 v uvlo hysteresis v bias falling 150 mv shutdown, temperature increasing 160 t sd thermal shutdown temperature c reset, temperature decreasing 140 t j operating junction temperature ? 40 125 c 6 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 6.6 typical characteristics over operating temperature range (t j = ? 40 c to 125 c), v bias = (v out + 1.4 v) or 2.5 v (whichever is greater); v in = v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = 25 c. i out = 0 ma i out = 350 ma figure 1. v in line regulation (TPS72013yzu) figure 2. v in line regulation (TPS72013yzu) i out = 0 ma i out = 350 ma figure 3. v bias line regulation (TPS72013yzu) figure 4. v bias line regulation (TPS72013yzu) figure 5. load regulation under light loads figure 6. load regulation (TPS72013yzu) (TPS72013yzu) copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: TPS720 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 0 50 100 150 200 250 300 350 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 4.5 v (v) in +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 4.5 v (v) in +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 0 1 2 3 4 5 6 7 8 9 10 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com typical characteristics (continued) over operating temperature range (t j = ? 40 c to 125 c), v bias = (v out + 1.4 v) or 2.5 v (whichever is greater); v in = v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = 25 c. figure 8. load regulation with v in floating (TPS72013yzu) figure 7. load regulation with v in floating (TPS72013yzu) figure 9. vin dropout voltage vs output current figure 10. vbias dropout voltage vs temperature (TPS72013yzu) (TPS72033yzu) figure 11. output voltage vs temperature (TPS72013yzu) figure 12. ground pin current vs vbias input voltage (TPS72013yzu) 8 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720 1.3451.325 1.305 1.285 1.265 1.245 v (v) out - 40 - 25 - 10 125 95 80 65 50 20 35 5 110 t (c) j i = 350ma out i = 0ma out i = 1ma out 5045 40 35 30 25 20 15 10 50 i gnd ( m a) 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c i = 1ma out +105 c +85 c +25 c - 10 c - 40 c 160140 120 100 8060 40 20 0 v (mv) do_in 0 50 100 150 200 250 300 350 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 1.151.14 1.13 1.12 1.11 1.10 1.09 1.08 1.07 1.06 1.05 1.04 v = v - v do_bias bias out (v) - 40 - 25 - 10 125 95 80 65 50 20 35 5 110 t j (c) v = v - out out(nom) 0.1 i out = 350ma 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (ma) out 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i (ma) out v = 2.7v bias v = 3.5v bias v = 4.5v bias v = 5.5v bias v = 3.0v bias v = 4.0v bias v = 5.0v bias t = +25 c j 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 i (ma) out 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out v = 2.7v bias t = -40c j t = +25c j t = +85c j t = +105c j t = +125c j t = 0c j
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 typical characteristics (continued) over operating temperature range (t j = ? 40 c to 125 c), v bias = (v out + 1.4 v) or 2.5 v (whichever is greater); v in = v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = 25 c. figure 13. ground pin current vs output current figure 14. ground pin current vs temperature (TPS72013yzu) (TPS72013yzu) figure 15. shutdown current vs vbias input voltage figure 16. current limit vs vbias input voltage (TPS72013yzu) (TPS72013yzu) figure 17. current limit vs vin input voltage figure 18. vin power-supply ripple rejection vs frequency (TPS72013yzu) (TPS72015yzu) copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: TPS720 675650 625 600 575 550 i (ma) cl 2.5 3.0 3.5 4.0 4.5 v (v) in +125 c - 10 c +25 c - 40 c +85 c +105 c 120100 8060 40 20 0 psrr (db) 10 100 1k 1m 10k 100k 10m frequency (hz) i = 0ma out i = 350ma out i = 50ma out (v v - in out ) = 0.5v (v v - bias out ) = 1.4v 3.02.5 2.0 1.5 1.0 0.5 0 i shdn ( m a) 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c +105 c +85 c - 10 c +25 c - 40 c 675650 625 600 575 550 i (ma) cl 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125c -10c +25c -40c +85c +105c 7060 50 40 30 20 10 0 i ( a) m gnd 0 50 100 150 200 250 300 350 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 6050 40 30 20 10 0 i ( a) m gnd - 40 - 25 - 10 125 95 80 65 50 20 35 5 110 t ( c) j i = 350ma out
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com typical characteristics (continued) over operating temperature range (t j = ? 40 c to 125 c), v bias = (v out + 1.4 v) or 2.5 v (whichever is greater); v in = v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = 25 c. figure 19. vin power-supply ripple rejection figure 20. vbias power-supply ripple rejection vs frequency (TPS72015yzu) vs frequency (TPS72015yzu) v in = 1.8 v v out = 1.3 v v bias = 2.7 v i out = 0 ma figure 21. output spectral noise density vs frequency figure 22. v in inrush current (TPS72015yzu) v in = 1.6 to 2 v v out = 1.3 v v bias = 2.7 v v in = 1.8 v v out = 1.3 v v bias = 2.7 v v in slew rate = 1 v/ s i out = 350 ma i out = 350 ma figure 24. v in line transient response figure 23. v in inrush current 10 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720 100 8060 40 20 0 psrr (db) 10 100 1k 1m 10k 100k 10m frequency (hz) i = 1ma out i = 350ma out (v v in out - ) = 0.5v (v v bias out - ) = 1.4v 500mv/div v out i in en 200ma/div200mv/div 20 s/div m v = 1.3v out i = 400ma in-peak 1mv/div v out v in 200mv/div 100 s/div m 1.6v 2.0v 10 1 0.1 0.01 output spectral noise density ( m v/ ? )hz 100 1k 10k 100k frequency (hz) 500mv/div v out i in en 50ma/div 200mv/div 20 s/div m v = 1.3v out i = 110ma in-peak 100 8060 40 20 0 psrr (db) 10 100 1k 1m 10k 100k 10m frequency (hz) i = 350ma out (v v - in out ) = 350mv (v v in out - ) = 300mv (v v in out - ) = 250mv
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 typical characteristics (continued) over operating temperature range (t j = ? 40 c to 125 c), v bias = (v out + 1.4 v) or 2.5 v (whichever is greater); v in = v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = 25 c. v in = 1.8 v v out = 1.3 v v bias = 2.7 v to 3.3 v v in = 1.8 v v out = 1.3 v v bias = 2.7 v v bias slew rate = 600 m/ s i out = 350 ma t rise = 1 s figure 25. v bias line transient response figure 26. load transient response copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: TPS720 10mv/div v out i out 100ma/div 100 s/div m 0ma 300ma 1mv/div v out v bias 200mv/div 100 s/div m 2.7v 3.3v
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com 7 detailed description 7.1 overview the TPS720 belongs to a family of new generation ldo regulators that use innovative circuitry to achieve ultra- wide bandwidth and high loop gain, resulting in extremely high psrr (up to 1 mhz) at very low headroom (v in ? v out ). the implementation of the bias pin on the TPS720 vastly improves efficiency of low v out applications by allowing the use of a preregulated, low-voltage input supply. the TPS720 supports a novel feature in which the output of the ldo regulates under light loads ( < 500 a) when the in pin is left floating. the light-load drive current is sourced from v bias under this condition. this feature is particularly useful in power-saving applications where the dc-dc converter connected to the in pin is disabled but the ldo is still required to regulate the voltage to a light load. these features, combined with low noise, low ground pin current, and ultra-small packaging, make this device ideal for portable applications. this family of regulators offers sub-bandgap output voltages, current limit and thermal protection, and is fully specified from ? 40 c to 125 c. 7.2 functional block diagram 7.3 feature description 7.3.1 internal current limit the TPS720 internal current limits help protect the regulator during fault conditions. during current limit, the output sources a fixed amount of current that is largely independent of output voltage. in such a case, the output voltage is not regulated, and is v out = i limit r load . the nmos pass transistor dissipates (v in ? v out ) i limit until thermal shut down is triggered and the device is turned off. as the device cools down, it is turned on by the internal thermal shutdown circuit. if the fault condition continues, the device cycles between current limit and thermal shutdown. see the thermal considerations section for more details. the nmos pass element in the TPS720 has a built-in body diode that conducts current when the voltage at out exceeds the voltage at in. this current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current is recommended. 7.3.2 inrush current limit the TPS720 family of ldo regulators implement a novel inrush current limit circuit architecture: the current drawn through the in pin is limited to a finite value. this i inrushlimit charges the output to its final voltage. all the current drawn through v in goes to charge the output capacitance when the load is disconnected. the following equation shows the inrush current limit performed by the circuit: i inrushlimit (a) = c out ( f) 0.0454545 (v/ s) + i load (a) (1) 12 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720 thermal shutdown current limit uvlo bandgap in en out bias
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 feature description (continued) assuming a c out of 2.2 f with the load disconnected (that is, i load = 0) the i inrushlimit is calculated to be 100 ma. the inrush current charges the ldo output capacitor. if the output of the ldo regulates to 1.3 v, then the ldo charges the output capacitor to the final output value in approximately 28.6 s. another consideration is when a load is connected to the output of an ldo. the connected load tries to steer a portion of the current away from v out . the TPS720 inrush current limit circuit employs a new technique that supplies not only the i inrushlimit , but also the additional current needed by the load. if i load = 350 ma, then the i inrushlimit calculates to be approximately 450 ma (from equation 1 ). 7.3.3 shutdown the enable pin (en) is active high and is compatible with standard and low voltage, ttl-cmos levels. when shutdown capability is not required, en can be connected to the in pin. 7.3.4 undervoltage lockout (uvlo) the TPS720 uses an undervoltage lock-out circuit on the bias pin to keep the output shut off until the internal circuitry is operating properly. the uvlo circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are less than 50- s duration. 7.4 device functional modes driving the en pin over 1.1 v turns on the regulator. driving the en pin below 0.4 v causes the regulator to enter shutdown mode. in shutdown, the current consumption of the device is reduced to 500 na, typically. copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: TPS720
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information 8.1.1 input and output capacitor requirements although an input capacitor is not required for stability on the in pin, it is good analog design practice to connect a 0.1- f to 1- f low equivalent series resistance (esr) capacitor across the in pin input supply near the regulator. this capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. a higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is located close to the power source. if source impedance is not sufficiently low, a 0.1- f input capacitor may be necessary to ensure stability. the bias pin does not require an input capacitor because it does not source high currents. however, if source impedance is not sufficiently low, then ti recommends a small 0.1- f bypass capacitor. the TPS720 is designed to be stable with standard ceramic capacitors with values of 2.2 f or larger at the output. x5r- and x7r-type capacitors are best because they have minimal variation in value and esr over temperature. maximum esr should be less than 250 m ? . 8.1.2 output regulation with in pin floating the TPS720 supports a novel feature in which the output of the ldo regulates under light loads when the in pin is left floating. under normal conditions, when the in pin is connected to a power source, the bias pin draws only tens of milliamperes. however, when the in pin is floating, an innovative circuit is used that allows a maximum current of 500 a to be drawn by the load through the bias pin, while maintaining the output in regulation. this feature is particularly useful in power-saving applications where a dc-dc converter connected to the in pin is disabled, but the ldo is required to regulate the output voltage to a light load. figure 27 shows an application example where a microcontroller is not turned off (to maintain the state of the internal memory), but where the regulated supply (shown as the tps62xxx) is turned off to reduce power. in this case, the TPS720 bias pin provides sufficient load current to maintain a regulated voltage to the microcontroller. figure 27. example of floating in pin regulation 14 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720 microcontroller TPS720xx tps62xxx vin en sw fb in out bias en gnd 2.2 m f 10 m f 10 m h 2.5v to 5.5v control to turn on/off the dc/dc output of dc/dc is floating whenthe tps62xxx en pin is low gnd
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 application information (continued) 8.1.3 dropout voltage the TPS720 uses a nmos pass transistor to achieve low dropout. when (v in ? v out ) is less than the dropout voltage (v do ), the nmos pass device is in the linear region of operation and the input-to-output resistance is the r ds(on) of the nmos pass element. v do approximately scales with output current because the nmos device behaves as a resistor in dropout. as with any linear regulator, psrr and transient response are degraded as (v in ? v out ) approaches dropout. this effect is shown in figure 19 . 8.1.4 transient response as with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response. 8.1.5 minimum load the TPS720 is stable with no output load. traditional ldos suffer from low loop gain at very light output loads. the TPS720 employs an innovative, low-current mode circuit under very light or no-load conditions, resulting in improved output voltage regulation performance reduced to zero output current. 8.2 typical application figure 28. typical application schematic 8.2.1 design requirements table 1 shows the parameters for this design example. table 1. design parameters design parameter example value v in 1.8 v v bias 2.7 v v out 1.3 v i out 10-ma typical, 350-ma peak copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: TPS720 TPS720xx v en v batt inen out gnd v core 1.3 v 1.8 v standalone dc/dc converter or pmu bias c bias c out c in
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com 8.2.2 detailed design procedures a small-size solution is desired, so select the minimum recommended component size. set c in = 1 f, c bias = 100 nf, c out = 2.2 f. 8.2.3 application curves i out = 350 ma figure 29. v in line regulation (TPS72013yzu) figure 30. load regulation (TPS72013yzu) v in = 1.6 to 2 v v out = 1.3 v v bias = 2.7 v v in = 1.8 v v out = 1.3 v v bias = 2.7 v v in slew rate = 1 v/ s i out = 350 ma i out = 350 ma figure 32. v in line transient response figure 31. v in inrush current 16 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 0 50 100 150 200 250 300 350 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 4.5 v (v) in +125 c +105 c +85 c - 10 c +25 c - 40 c 500mv/div v out i in en 200ma/div200mv/div 20 s/div m v = 1.3v out i = 400ma in-peak 1mv/div v out v in 200mv/div 100 s/div m 1.6v 2.0v
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 9 power supply recommendations the input supply and bias supply for the ldo must be within its recommended operating conditions and provide adequate headroom for the device to have a regulated output. the minimum capacitor requirements must be met, and if the input supply is noisy, then additional input capacitors with low esr can help improve transient performance. 10 layout 10.1 layout guidelines to improve ac performance such as psrr, output noise, and transient response, ti recommends designing the board with separate ground planes for v in and v out , with the ground plane connected only at the gnd pin of the device. in addition, the ground connection for the output capacitor should be connected directly to the gnd pin of the device. high equivalent series resistance (esr) capacitors may degrade psrr. the bias pin draws very little current and can be routed as a signal (make sure to shield it from high-frequency coupling). 10.2 layout example figure 33. recommended layout 10.3 thermal considerations thermal protection disables the output when the junction temperature rises to approximately 160 c, allowing the device to cool. when the junction temperature cools to approximately 140 c, the output circuitry is again enabled. depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. this cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: TPS720 out nc en in gnd bias thermal pad 1 2 3 6 5 4 c out c in c bias to bias supply to input supply to load to enable signal ground plane ground plane
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com thermal considerations (continued) any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. for reliable operation, junction temperature should be limited to 125 c maximum. to estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. for good reliability, thermal protection should trigger at least 35 c above the maximum expected ambient condition of the particular application. this configuration produces a worst-case junction temperature of 125 c at the highest expected ambient temperature and worst-case load. the internal protection circuitry of the TPS720 has been designed to protect against overload conditions. it was not intended to replace proper heatsinking. continuously running the TPS720 into thermal shutdown degrades device reliability. 10.4 power dissipation the ability to remove heat from the die is different for each package type, presenting different considerations in the printed-circuit-board (pcb) layout. the pcb area around the device that is free of other components moves the heat from the device to the ambient air. performance data for jedec low- and high-k boards are given in the thermal information table. using heavier copper increases the effectiveness in removing heat from the device. the addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. power dissipation depends on input voltage and load conditions. power dissipation (p d ) is equal to the product of the output current times the voltage drop across the output pass element (v in to v out ), as shown in equation 2 : p d = (v in ? v out ) i out (2) 18 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720
TPS720 www.ti.com sbvs100e ? june 2008 ? revised september 2015 11 device and documentation support 11.1 device support 11.1.1 development support 11.1.1.1 evaluation module an evaluation module (evm) is available to assist in the initial circuit performance evaluation using the TPS720. the TPS720xxdrvevm evaluation module (and related user guide ) can be requested at the texas instruments website through the product folders or purchased directly from the ti estore . 11.1.2 device nomenclature table 2. device nomenclature (1) (2) product v out xx(x) is the nominal output voltage. for output voltages with a resolution of 100 mv, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 v; 125 = 1.25 v). TPS720 xx(x) yyy is the package designator. z is the package quantity. r is for reel (3000 pieces), t is for tape (250 pieces). (1) for the most current package and ordering information see the package option addendum at the end of this document, or visit the device product folder on www.ti.com . (2) output voltages from 0.9 v to 3.6 v in 50-mv increments are available. contact the factory for details and availability. 11.2 documentation support 11.2.1 related documentation for related documentation see the following: ? TPS720xxdrvevm evaluation module , sbvu024 ? using new thermal metrics , sbva025 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. copyright ? 2008 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: TPS720
TPS720 sbvs100e ? june 2008 ? revised september 2015 www.ti.com 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 12.1 package mounting solder pad footprint recommendations for the TPS720 are available from the texas instruments website at www.ti.com . figure 34. yzu wafer chip-scale package dimensions (in mm) 20 submit documentation feedback copyright ? 2008 ? 2015, texas instruments incorporated product folder links: TPS720 n tes: o 1,3621,302 1. all linear dimen eters. sions are in millim 2. this drawing is sub out notice. ject to change with 0,9940,934
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples hpa01044drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dab TPS72009yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 g3 TPS72009yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 g3 TPS720105drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 odc TPS720105drvt active wson drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 odc TPS720105yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nm TPS720105yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nm TPS72010drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 daa TPS72010drvt active wson drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 daa TPS720115drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 shp TPS720115drvt active wson drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 shp TPS72011drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 par TPS72011drvt active wson drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 par TPS72011yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 bq TPS72011yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 bq TPS72012drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dab TPS72012drvt active wson drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dab
package option addendum www.ti.com 15-apr-2017 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS72012yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nn TPS72012yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nn TPS72013yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 fs TPS72013yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 fs TPS72015drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dac TPS72015drvt active wson drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dac TPS72015yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 ft TPS72015yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 ft TPS72017yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gc TPS72017yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gc TPS72018drvr active wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dad TPS72018drvt active wson drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dad TPS72018yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gd TPS72018yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gd (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 15-apr-2017 addendum-page 3 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of TPS720 : ? automotive: TPS720-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS72009yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72009yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS720105drvr wson drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS720105drvt wson drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS720105yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS720105yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72010drvr wson drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72010drvt wson drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS720115drvr wson drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS720115drvt wson drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72011drvr wson drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72011drvt wson drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72011yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72011yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72012drvr wson drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72012drvt wson drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72012yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72012yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 package materials information www.ti.com 13-oct-2016 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS72013yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72013yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72015drvr wson drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72015drvt wson drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72015yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72015yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72017yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72017yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72018drvr wson drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72018drvt wson drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TPS72018yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 TPS72018yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS72009yzur dsbga yzu 5 3000 182.0 182.0 20.0 TPS72009yzut dsbga yzu 5 250 182.0 182.0 20.0 TPS720105drvr wson drv 6 3000 203.0 203.0 35.0 TPS720105drvt wson drv 6 250 203.0 203.0 35.0 TPS720105yzur dsbga yzu 5 3000 182.0 182.0 20.0 package materials information www.ti.com 13-oct-2016 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) TPS720105yzut dsbga yzu 5 250 182.0 182.0 20.0 TPS72010drvr wson drv 6 3000 203.0 203.0 35.0 TPS72010drvt wson drv 6 250 203.0 203.0 35.0 TPS720115drvr wson drv 6 3000 203.0 203.0 35.0 TPS720115drvt wson drv 6 250 203.0 203.0 35.0 TPS72011drvr wson drv 6 3000 203.0 203.0 35.0 TPS72011drvt wson drv 6 250 203.0 203.0 35.0 TPS72011yzur dsbga yzu 5 3000 182.0 182.0 20.0 TPS72011yzut dsbga yzu 5 250 182.0 182.0 20.0 TPS72012drvr wson drv 6 3000 203.0 203.0 35.0 TPS72012drvt wson drv 6 250 203.0 203.0 35.0 TPS72012yzur dsbga yzu 5 3000 182.0 182.0 20.0 TPS72012yzut dsbga yzu 5 250 182.0 182.0 20.0 TPS72013yzur dsbga yzu 5 3000 182.0 182.0 20.0 TPS72013yzut dsbga yzu 5 250 182.0 182.0 20.0 TPS72015drvr wson drv 6 3000 203.0 203.0 35.0 TPS72015drvt wson drv 6 250 203.0 203.0 35.0 TPS72015yzur dsbga yzu 5 3000 210.0 185.0 35.0 TPS72015yzut dsbga yzu 5 250 210.0 185.0 35.0 TPS72017yzur dsbga yzu 5 3000 210.0 185.0 35.0 TPS72017yzut dsbga yzu 5 250 210.0 185.0 35.0 TPS72018drvr wson drv 6 3000 203.0 203.0 35.0 TPS72018drvt wson drv 6 250 203.0 203.0 35.0 TPS72018yzur dsbga yzu 5 3000 210.0 185.0 35.0 TPS72018yzut dsbga yzu 5 250 210.0 185.0 35.0 package materials information www.ti.com 13-oct-2016 pack materials-page 3

www.ti.com package outline c 0.625 max 0.3 0.2 0.5 typ 5x 0.35 0.25 0.5 typ 0.433 b e a d 4222196/a 11/2015 dsbga - 0.625 mm max height yzu0005 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3 symm symm ball a1 corner seating plane ball typ 0.05 c c b a 1 2 0.015 c a b scale 10.000d: max = e: max = 1.362 mm, min = 0.994 mm, min = 1.302 mm0.934 mm
www.ti.com example board layout 5x ( )0.25 (0.5) typ (0.433) typ ( ) metal 0.25 0.05 max solder mask opening metal under solder mask ( ) solder mask opening 0.25 0.05 min 4222196/a 11/2015 dsbga - 0.625 mm max height yzu0005 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. refer to texas instruments literature no. snva009 (www.ti.com/lit/snva009). solder mask details not to scale 1 3 symm symm land pattern example scale:50x c 2 a b non-solder mask defined (preferred) solder mask defined
www.ti.com example stencil design (0.433) typ (0.5) typ 5x ( 0.25) (r ) typ0.05 metal typ 4222196/a 11/2015 dsbga - 0.625 mm max height yzu0005 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. c 1 2 a b 3 symm symm solder paste example based on 0.1 mm thick stencil scale:50x
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